Total No. of Questions—8] [Total No. of Printed Pages—2

Seat

No. [5559]-182

S.E. (Computer) (First Semester) EXAMINATION, 2019

DIGITAL ELECTRONICS AND LOGIC DESIGN

(2015 PATTERN)

Time : Two Hours Maximum Marks : 50

P.T.O.

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[5559]-182 2

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Total No. of Questions—8] [Total No. of Printed Pages—3

Seat

No. [5459]-182

S.E. (Computer Engineering) (I Sem.) EXAMINATION, 2018

DIGITAL ELECTRONICS AND LOGIC DESIGN

(2015 PATTERN)

Time : Two Hours Maximum Marks : 50

N.B. :— (i) Attempt Q. 1 or Q. 2, Q. 3 or Q. 4, Q. 5 or Q. 6,

Q. 7 or Q. 8.

(ii) Neat diagram must be drawn wherever necessary.

(iii) Assume suitable data, if necessary.

1. (a) How will you implement full-adder using half-adder ? Explain

the circuit diagram. [6]

(b) How lockout condition in counter is avoided ? [2]

(c) Draw and explain Ring counter using JK flip-flop (Timing Diagram

is expected). [4]

Or

2. (a) Design full Subtractor using multiplexer IC 74151. [4]

(b) Compare synchronous and asynchronous counter. [2]

(c) Simplify the following function using Qunie-McCluskey minimization

technique :

Y(A, B, C, D) = �m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14). [6]

P.T.O.

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[5459]-182 2

3. (a) Design an ASM chart for 2-bit UP counter using mode control

line. [6]

When M = I UP counting

When M = 0 remain in same state.

(b) Implement the following function using PAL :

F1(A, B, C, D) = �m (1, 3, 4, 6, 9, 12, 14)

F2(A, B, C, D) = �m (1, 2, 3, 7, 12, 15). [4]

(c) Define PLD. Mention different types of PLD. [2]

Or

4. (a) Write VHDL code full adder using behavioural style of

modeling. [4]

(b) Explain entity declaration for 4 : 1 multiplexer having enable

line. [2]

(c) Design BCD to Excess-3 code converter using PLA. [6]

5. (a) Draw three input standard TTL NAND gate and explain its

operation. [5]

(b) Explain the interfacing of TTL and CMOS : [8]

(i) CMOS driving TTL

(ii) TTL driving CMOS.

Or

6. (a) Draw and explain wired AND gate in detail. [5]

(b) Explain the characteristics of digital IC. [4]

(c) Explain with a neat diagram CMOS NOR gate. [4]

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[5459]-182 3 P.T.O.

7. (a) Explain addressing modes of 8051 with example (any three) : [6]

(b) List any eight applications of microcontroller 8051. [4]

(c) Explain the following pins of 8051 : [3]

(i) RXD

(ii) PSEN

(iii) EA .

Or

8. (a) State the registers used in Timer/counter operation. Explain

TMOD register. [5]

(b) Explain the following instructions with respective to microcontroller

8051 and give example of each : [8]

(i) MUL

(ii) L JUMP

(iii) SWAP

(iv) PUSH. CEGP0

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Seat

No.

( , , , ) (0, 2, 3, 6, 8, 9, 12, 14)f a b c d m� �

�

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[5252]-562 1 P.T.O.

Total No. of Questions—8] [Total No. of Printed Pages—3

Seat

No. [5252]-562

S.E. (Computer Engineering) (First Semester)

EXAMINATION, 2017

DIGITAL ELECTRONICS AND LOGIC DESIGN

(2015 PATTERN)

Time : Two Hours Maximum Marks : 50

N.B. :— (i) Attempt Q. 1 or Q. 2, Q. 3 or Q. 4, Q. 5 or Q. 6,

Q. 7 or Q. 8.

(ii) Neat diagrams must be drawn wherever necessary.

(iii) Assume suitable data, if necessary.

1. (a) Design and implement Binary to Gray code converter using

logic gate. [6]

(b) Explain look ahead carry generator in detail. [4]

(c) Draw basic internal structure of Decade counter IC 7490 and

explain its operation. [2]

Or

2. (a) Implement full adder using 8:1 Multiplexer and draw the

diagram. [6]

(b) Write a short note on Johnson counter. [4]

(c) Convert the following flip-flop : [2]

D-Flip-Flop to T-Flip-Flop

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[5252]-562 2

3. (a) Design the ASM chart for a 2-bit binary counter having one

enable line E such that when : [6]

E = l (count enabled) and

E = 0 (counting is disabled).

(b) A combinational Circuit is defined by the following

function : [6]

F1(A,B,C) = �m (0,1,3,7)

F2(A,B,C) = �m (1,2,5,6)

Implement this circuit with PLA.

Or

4. (a) Write VHDL code for full adder using structural style of

Modeling (Declare half adder as a component) and also draw

truth table and diagram of full adder. [6]

(b) Explain entity declaration for XOR gate [2]

(c) A combinational circuit is defined by the function : [4]

F1 = �m(0,1,3,4)

Implement this circuit with PAL.

Or

5. (a) Draw and explain the circuit diagram of CMOS Inverter.

[5]

(b) Define the following terms and mention the standard values

for TTL logic Family : [8]

1. Noise Margin

2. Fan Out

3. Power Dissipation

4. Propagation Delay.

Or

6. (a) Draw and explain 2-input NAND TTL logic gate with totem

pole output driver. [7]

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[5252]-562 3 P.T.O.

(b) 1. Give the classification of logic family [6]

2. Explain the advantage of open collector output.

7. (a) Explain the features of 8051 Microcontroller [4]

(b) What are the different addressing Modes in 8051 ? Give example

of each. [6]

(c) Explain the following pins of 8051 : [3]

1. ALE

2. XTAL

3. EA .

Or

8. (a) Describe different timer modes of 8051 Microcontroller. Draw

format of TMOD register. [7]

(b) Explain the following instructions with respective to 8051 and

give example of each : [6]

l. PUSH

2. MUL

3. CPL.

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Seat

No.

F(A, B, C, D) (1, 3, 5, 8, 9, 11, 15) (2, 13)m d� � �

F1 m (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)� �

F2 (1, 2, 8, 12, 13)� �