schem,mlb kepler,j45g - assistenza apple | … · 09/02/2012 sidle_j15 118 93 project specific...
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DRAWING
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
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Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
3
B
7
BRANCH
DRAWING NUMBER SIZE
D
SHEET
R
DATE
D
A
C
PAGE
A
C
3456
D
B
8 7 6 5 4 2 1
12APPDCK
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DRAWING TITLE
DESCRIPTION OF REVISIONREV ECN
REVISION
PROPRIETARY PROPERTY OF APPLE INC.
Schematic / PCB #’s
SCHEM,MLB_KEPLER,J45G 8/22/2013 DVT
1 OF 94
SCHEM,MLB,KEPLER,J45G
051-0675
2013-08-2200022656546 ENGINEERING RELEASED
1 OF 119
dvt
6.0.0
Debug Sensors04/26/2013
CLEAN_J454656
Load Side Voltage and Current Sensing04/26/2013
CLEAN_J454555
High Side Voltage and Current Sensing04/26/2013
CLEAN_J454454
SMBus Connections04/26/2013
CLEAN_J454353
SMC Project Support04/26/2013
CLEAN_J454252
SMC Shared Support04/26/2013
CLEAN_J454151
SMC04/26/2013
CLEAN_J454050
KEYBOARD/TRACKPAD (2 OF 2)04/26/2013
CLEAN_J453949
KEYBOARD/TRACKPAD (1 OF 2)04/26/2013
CLEAN_J453848
USB 3.0 CONNECTORS04/26/2013
CLEAN_J453746
Camera 2 of 204/26/2013
CLEAN_J453640
Camera 1 of 204/26/2013
CLEAN_J453539
SSD Connector04/26/2013
CLEAN_J453437
X29C CONNECTOR04/26/2013
CLEAN_J453335
Thunderbolt Connector B04/26/2013
CLEAN_J453233
Thunderbolt Connector A04/26/2013
CLEAN_J453132
Thunderbolt Mobile Support04/26/2013
CLEAN_J453030
Thunderbolt Host (2 of 2)04/26/2013
CLEAN_J452929
Thunderbolt Host (1 of 2)04/26/2013
CLEAN_J452828
DDR3 Termination04/26/2013
CLEAN_J452727
DDR3 SDRAM Bank B (2 OF 2)04/26/2013
CLEAN_J452626
DDR3 SDRAM Bank B (1 OF 2)04/26/2013
CLEAN_J452525
DDR3 SDRAM Bank A (2 OF 2)04/26/2013
CLEAN_J452424
DDR3 SDRAM Bank A (1 OF 2)04/26/2013
CLEAN_J452323
DDR3 VREF MARGINING04/26/2013
CLEAN_J452222
CPU Memory S3 Support04/26/2013
CLEAN_J452121
Project Chipset Support04/26/2013
CLEAN_J452020
Chipset Support04/26/2013
CLEAN_J451919
CPU & PCH XDP04/26/2013
CLEAN_J451818
PCH DECOUPLING04/26/2013
CLEAN_J451717
PCH Grounds04/26/2013
CLEAN_J451616
PCH Power04/26/2013
CLEAN_J451515
PCH GPIO/MISC/NCTF04/26/2013
CLEAN_J451414
PCH PCI-E/USB04/26/2013
CLEAN_J451313
PCH DMI/FDI/PM/GFX/PCI04/26/2013
CLEAN_J451212
PCH RTC/HDA/JTAG/SATA/CLK04/26/2013
CLEAN_J451111
CPU Decoupling05/02/2013
CLEAN_J151010
CPU Ground04/26/2013
CLEAN_J4599
CPU Power04/26/2013
CLEAN_J4588
CPU DDR3 Interfaces04/26/2013
CLEAN_J4577
CPU Clock/Misc/JTAG/CFG04/26/2013
CLEAN_J4566
CPU DMI/PEG/FDI/RSVD04/26/2013
CLEAN_J4555
PD Parts05/03/2013
CLEAN_J4544
BOM Configuration07/31/2012
J15_REFERENCE33
BOM Configuration07/31/2012
J15_REFERENCE22
119
GPU (Kepler) Constraints9409/02/2012
SIDLE_J15
118
Project Specific Constraints9304/26/2013
CLEAN_J45
117
SMC Constraints9204/26/2013
CLEAN_J45
116
Camera Constraints9104/26/2013
CLEAN_J45
115
Thunderbolt Constraints9004/26/2013
CLEAN_J45
114
Memory Constraints8904/26/2013
CLEAN_J45
113
PCH Constraints 28804/26/2013
CLEAN_J45
112
PCH Constraints 18704/26/2013
CLEAN_J45
111
CPU Constraints8604/26/2013
CLEAN_J45
110
PCB Rule Definitions8504/26/2013
CLEAN_J45
105
NC & No Test8404/26/2013
CLEAN_J45
104
Functional Test Points8304/26/2013
CLEAN_J45
102
Signal Aliases8204/26/2013
CLEAN_J45
100
Power Aliases8104/26/2013
CLEAN_J45
97
eDP Muxed Graphics Support8008/14/2012
CLEAN_D2
96
eDP Mux7907/31/2012
D2_MLB
95
RIO Connectors7804/26/2013
CLEAN_J45
93
GFX IMVP VCore Regulator7707/31/2012
D2_MLB
92
KEPLER PEX PWR/GNDS7607/31/2012
D2_MLB
91
KEPLER GPIOS,CLK & STRAPS7507/31/2012
D2_MLB
90
KEPLER EDP/DP/GPIO7407/31/2012
D2_MLB
89
GDDR5 Frame Buffer B7307/31/2012
D2_MLB
88
GDDR5 Frame Buffer A7207/31/2012
D2_MLB
87
1V05 GPU / 1V35 FB POWER SUPPLY7107/31/2012
D2_MLB
86
KEPLER FRAME BUFFER I/F7007/31/2012
D2_MLB
85
KEPLER CORE/FB POWER6907/31/2012
D2_MLB
84
KEPLER PCI-E6807/31/2012
D2_MLB
83
eDP Display Connector6704/26/2013
CLEAN_J45
82
Power Sequencing EG/PCH S06601/13/2012
D2_KEPLER
81
Power Control 1/ENABLE6506/23/2013
CLEAN_J45
80
Power FETs6404/26/2013
CLEAN_J45
78
Misc Power Supplies6304/26/2013
CLEAN_J45
77
LCD/KBD Backlight Driver6204/26/2013
CLEAN_J45
76
1V05V POWER SUPPLY6104/26/2013
CLEAN_J45
75
5V / 3.3V Power Supply6004/26/2013
CLEAN_J45
74
1.35V DDR3L SUPPLY5904/26/2013
CLEAN_J45
73
CPU VR12.5 VCC Power Stage5804/26/2013
CLEAN_J45
72
CPU VR12.5 VCC Regulator IC5704/26/2013
CLEAN_J45
71
PBus Supply & Battery Charger5604/26/2013
CLEAN_J45
70
DC-In & Battery Connectors5504/26/2013
CLEAN_J45
66
AUDIO: JACK TRANSLATORS5404/26/2013
CLEAN_J45
65
AUDIO: JACK5304/26/2013
CLEAN_J45
64
AUDIO: SPEAKER AMP5204/26/2013
CLEAN_J45
63
AUDIO:CODEC, DIGITAL5104/26/2013
CLEAN_J45
62
AUDIO:CODEC, ANALOG5004/26/2013
CLEAN_J45
61
SPI ROM / LPC+SPI Conn.4904/26/2013
CLEAN_J45
60
Fan Connectors4806/23/2013
CLEAN_J45
ContentsDate
Sync(.csa)
Page58
Thermal Sensors4704/26/2013
CLEAN_J45
820-3787 CRITICAL1 PCBPCBF,MLB_KEPLER,J45G
051-0675 CRITICALSCH1 SCHEM,MLB_KEPLER,J45G
ABBREV=ABBREVTITLE=MLB
LAST_MODIFIED=Thu Aug 22 12:19:14 2013
Table of ContentsMASTER
MASTER11
Contents(.csa)
PageDate
Sync
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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IV ALL RIGHTS RESERVED
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DSIZEDRAWING NUMBER
REVISION
BRANCH
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THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
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BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
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J45G BOM GroupsBOM Variants
->
->
Development/Base BOM
DRAM SPD Straps
Module Parts
PCBA,MLB,KEPLER,CRW_BEST,8G-MIC,VR-ELP,J45G639-5248 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600_S,FB_2G_ELPIDA
639-5256 PCBA,MLB,KEPLER,CRW_BEST,16G-ELP,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600,FB_2G_ELPIDA
639-5257 PCBA,MLB,KEPLER,CRW_CTO,8G-HYN,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600_S,FB_2G_HYNIX_A_DIE
PCBA,MLB,KEPLER,CRW_CTO,8G-MIC,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600_S,FB_2G_HYNIX_A_DIE639-5259
639-5488 PCBA,MLB,KEPLER,CRW_CTO,16G-MIC,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600,FB_4G_HYNIX
639-5487 BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600,FB_4G_HYNIXPCBA,MLB,KEPLER,CRW_CTO,16G-HYN,VR-4GHYN,J45G
639-5486 PCBA,MLB,KEPLER,CRW_CTO,8G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600_S,FB_4G_HYNIX
639-5485 PCBA,MLB,KEPLER,CRW_CTO,8G-MIC,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600_S,FB_4G_HYNIX
639-5484 BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600_S,FB_4G_HYNIXPCBA,MLB,KEPLER,CRW_CTO,8G-HYN,VR-4GHYN,J45G
639-5483 PCBA,MLB,KEPLER,CRW_BEST,16G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600,FB_4G_HYNIX
PCBA,MLB,KEPLER,CRW_BEST,16G-MIC,VR-4GHYN,J45G639-5482 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600,FB_4G_HYNIX
639-5480 PCBA,MLB,KEPLER,CRW_BEST,8G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600_S,FB_4G_HYNIX
PCBA,MLB,KEPLER,CRW_BEST,8G-MIC,VR-4GHYN,J45G639-5479 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600_S,FB_4G_HYNIX
639-5478 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600_S,FB_4G_HYNIXPCBA,MLB,KEPLER,CRW_BEST,8G-HYN,VR-4GHYN,J45G
PCBA,MLB,KEPLER,CRW_CTO,16G-ELP,VR-ELP,J45G639-5268 BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600,FB_2G_ELPIDA
333S0685 CRITICAL4 U8800,U8850,U8900,U8950 FB_4G_HYNIXIC,SDRAM,GDDR5,64MX3,HYNIX,H5GC4H24MFP-T2C
U8800,U8850,U8900,U89504 CRITICAL333S0734 FB_2G_HYNIX_29nmIC,SDRAM,GDDR5,64MX3,HYNIX,H5GC2H24BFR-T2C
CRITICALU8800,U8850,U8900,U89504333S0701 FB_2G_ELPIDA_29nmIC,SDRAM,GDDR5,2GBIT,5GBPS,170FBGA,EDW2032BBBG-6A-F
4 U8800,U8850,U8900,U8950 CRITICAL333S0695 FB_2G_ELPIDAIC,SDRAM,GDDR5,2GBIT,5GBPS,170FBGA
CRITICALIC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX333S0630 U8800,U8850,U8900,U8950 FB_2G_HYNIX_A_DIE4
BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600,FB_2G_HYNIX_A_DIE639-5267 PCBA,MLB,KEPLER,CRW_CTO,16G-ELP,VR-HYN,J45G
639-5266 BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600,FB_2G_ELPIDAPCBA,MLB,KEPLER,CRW_CTO,16G-MIC,VR-ELP,J45G
BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600,FB_2G_ELPIDAPCBA,MLB,KEPLER,CRW_CTO,16G-HYN,VR-ELP,J45G639-5264
639-5261 PCBA,MLB,KEPLER,CRW_CTO,8G-ELP,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600_S,FB_2G_HYNIX_A_DIE
CRITICAL333S0631 4 IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG FB_2G_SAMSUNGU8800,U8850,U8900,U8950
IC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA CRITICALU2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670333S0667 4Gb_HYNIX_160032
333S0660 U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U267032 4Gb_MICRON_1600CRITICALIC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA
IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG 4Gb_SAMSUNG_1600U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670 CRITICAL32333S0624
4Gb_HYNIX_1600_SIC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA333S0667 16 U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570 CRITICAL
BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600_S,FB_2G_ELPIDA639-5260 PCBA,MLB,KEPLER,CRW_CTO,8G-MIC,VR-ELP,J45G
BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600,FB_2G_HYNIX_A_DIE639-5263 PCBA,MLB,KEPLER,CRW_CTO,16G-HYN,VR-HYN,J45G
RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:HRAM:2Gb_SAMSUNG_1600
RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:LRAM:2Gb_HYNIX_1600
RAM:2Gb_ELPIDA_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
4Gb_HYNIX_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:LRAM:4Gb_HYNIX_1600_S
4Gb_SAMSUNG_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:HRAM:4Gb_SAMSUNG_1600_S
RAM:2Gb_MICRON_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
4Gb_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:LRAM:4Gb_ELPIDA_1600_S
4Gb_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:LRAM:4Gb_HYNIX_1600
4Gb_MICRON_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:HRAM:4Gb_MICRON_1600
4Gb_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:LRAM:4Gb_ELPIDA_1600
4Gb_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:HRAM:4Gb_SAMSUNG_1600
4Gb_MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAM:4Gb_MICRON_1600_S
BASE_BOMCRITICAL1 BASE685-0177 J45G MLB,KEPLER BASE BOM
J45G MLB,KEPLER, DEVEL BOM DEVEL1 CRITICAL DEVEL_BOM985-0181
IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA1 CRITICALU4000333S0700
333S0624 U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U257016 4Gb_SAMSUNG_1600_SCRITICALIC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG
333S0703 CRITICALU2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U257016 4Gb_ELPIDA_1600_SIC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P
IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA333S0660 CRITICALU2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570 4Gb_MICRON_1600_S16
IC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P 4Gb_ELPIDA_1600U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670 CRITICAL333S0703 32
CRITICALU84001 IC,GPU,GK107-GT A2,BGA908337S4256 GK107:GT
GK107:GXU84001337S4427 CRITICALIC,GPU,107GX,926MHZ,1.0375V,1.5V,FBGA908
CRITICAL1 U8400 GK107:GX2IC,GPU,CK107-762,A2,940MHz,5GBPS,1.2V,1.5V908BG337S4616
337S4599 U05001 CRITICAL CPU_CRW:BETTERIC,CPU,CRW,PRQ,C0,2.0,47W,4+3E,6M,BGA
XDP_DEBUG XDP_CONN,XDP_PCH
GFX_BM GK107:GX,DPMUX:HOCO
J45G_COMMON ALTERNATE,COMMON,J45G_COMMON1,J45G_COMMON2,J45G_PROGPARTS,GFX_BM,ACAPS:A2
J45G_COMMON1 CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,CPUPEG:X8X8,S2_PWR:S0
J45G_COMMON2 EDP:YES,LPCPLUS_CONN:YES,LPCPLUS_R:YES,XDP,RIO_PWR:1V5,SPI:DUAL_IO,SSD_PWR_EN:GPIO,CAM_WAKE:NO
J45G_PVT BKLT:PROD,SENSOR_NONPROD:N
J45G_PROGPARTS SMC_PROG:PROTO4,BOOTROM_PROG:PROTO4,TBTROM:PROG,TPAD_PSOC:PROG,GFX_PROGPARTS
DPMUXMCU:PROGGFX_PROGPARTS
J45G_DEVEL:ENG ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,DDRVREF_DAC,SENSOR_NONPROD:Y,BKLT:ENG,DBGLED,CAM_XTAL:YES,DPMUX_DEBUG
J45G_DEVEL:DVT ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,DBGLED
1 CRITICALIC,PCH,LPT-M, HM87,C2,SR199,PRQ,20x20mm,FCBGA U1100337S4542
CRITICALU2800338S1247 IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC, FCBGA2881
U3900 CRITICAL338S1186 1 IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA
U05001 CPU_CRW:CTO337S4624 IC,CPU,CRW,PRQ,C0,2.6,47W,4+3E,6M,BGA1364 CRITICAL
BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600_S,FB_2G_ELPIDA639-5258 PCBA,MLB,KEPLER,CRW_CTO,8G-HYN,VR-ELP,J45G
PCBA,MLB,KEPLER,CRW_BEST,16G-HYN,VR-ELP,J45G639-5252 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600,FB_2G_ELPIDA
639-5250 PCBA,MLB,KEPLER,CRW_BEST,8G-ELP,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600_S,FB_2G_ELPIDA
PCBA,MLB,KEPLER,CRW_BEST,8G-ELP,VR-HYN,J45G639-5249 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600_S,FB_2G_HYNIX_A_DIE
COMMON PARTS,MLB,KEPLER,J45685-0177
IC,CPU,CRW,PRQ,C0,2.3,47W,4+3E,6M,BGA1364337S4600 1 CRITICALU0500 CPU_CRW:BEST
639-5255 PCBA,MLB,KEPLER,CRW_BEST,16G-ELP,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600,FB_2G_HYNIX_A_DIE
PCBA,MLB,KEPLER,CRW_BEST,16G-MIC,VR-ELP,J45G639-5254 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600,FB_2G_ELPIDA
PCBA,MLB,KEPLER,CRW_BEST,16G-MIC,VR-HYN,J45G639-5253 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600,FB_2G_HYNIX_A_DIE
PCBA,MLB,KEPLER,CRW_BEST,16G-HYN,VR-HYN,J45G639-5251 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600,FB_2G_HYNIX_A_DIE
PCBA,MLB,KEPLER,CRW_BEST,8G-HYN,VR-ELP,J45G639-5246 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600_S,FB_2G_ELPIDA
DEV,MLB,KEPLER,J45985-0181
639-5489 PCBA,MLB,KEPLER,CRW_CTO,16G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600,FB_4G_HYNIX
639-5481 PCBA,MLB,KEPLER,CRW_BEST,16G-HYN,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600,FB_4G_HYNIX
639-5265 BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600,FB_2G_HYNIX_A_DIEPCBA,MLB,KEPLER,CRW_CTO,16G-MIC,VR-HYN,J45G
639-5262 PCBA,MLB,KEPLER,CRW_CTO,8G-ELP,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600_S,FB_2G_ELPIDA
PCBA,MLB,KEPLER,CRW_BSET,8G-MIC,VR-HYN,J45G639-5247 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600_S,FB_2G_HYNIX_A_DIE
PCBA,MLB,KEPLER,CRW_BEST,8G-HYN,VR-HYN,J45G639-5245 BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600_S,FB_2G_HYNIX_A_DIE
BOM ConfigurationSYNC_MASTER=J15_REFERENCE SYNC_DATE=07/31/2012
J45G_COMMON
J45G_DEVEL:DVT
dvt
051-0675
6.0.0
2 OF 119
2 OF 94
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
SMC
FROM J15
Programmables - All builds
EFI ROM
Alternate Parts
311S0649 ON alt to Toshiba (U2030,U7001)ALL311S0541
ALL197S0479 197S0478 Epson alt to NDK
ALL197S0464 Epson alt to NDK197S0466
ALL333S0704 333S0700 ELPIDA to HYNIX U4000
TI eDP MUXALL353S3528353S3526
Pericom eDP MUX353S3528 ALL353S3527
128S0264 ALL Kemet alt to Sanyo128S0364
138S0732 ALL138S0715 Romh Alt to Vishay
ALL Romh Alt to Vishay127S0162127S0164
Samsung Alt to Murata138S0811138S0846 ALL
333S0703333S0629 ALL Epida Alt die
138S0639 Samsung Alt to Murata138S0803 ALL
138S0674 Samsung Alt to MurataALL138S0843
Kemet alt to Sanyo128S0376 ALL128S0371
NXP alt to DiodesALL376S1089 376S1128
Taiyo Yuden alt to SamsungALL138S0638138S0681
ALL NXP alt to Diodes376S0855376S1129
Toshiba alt to DiodesALL376S0855376S1032
CRITICAL
BOOTROM_PROG:BLANK
CRITICAL
CRITICAL
CRITICAL
BOOTROM_PROG:PROTO1
BOOTROM_PROG:PROTO3
BOOTROM_PROG:PROTO4
335S0852
IC,EDP MUX-95C,(RENESAS) V3.2.8,DVB,D2 U9600 DPMUXMCU:PROGCRITICAL
IC,MCU,H8S/2113,9X9MM,TLP-145V
IC,TRKPD/KYBD CNTRLR,CU only,V225,J45
IC,TP PSOC,QFN,BLANK
1
337S4313 CRITICAL1 U9600 DPMUXMCU:BLANK
1 TPAD_PSOC:BLANKU4801 CRITICAL337S4587
1 SMC_PROG:BASEIC,SMC-A3,40MHZ/50DMIPS,SCPL FW,157BGA U5000
1 SMC_PROG:PVT341S3741 U5000IC,SMC-A3,SCPL,EXT,VXXXX,PVT,J15
341S3901 SMC_PROG:PROTO41 U5000IC,SMC-B1,SCPL,EXT,V2.16Q13,PROTO4,J45G
ALL EPSON Alt to NDK197S0481 197S0480
Diodes alt to FairchildALL376S1053
128S0329 NEC alt to SanyoALL128S0311
ALL155S0583155S0667 Panasonic alt to TDK
ALL376S0820376S1080 Diodes alt to On Semi
ALL152S0461 Cyntec alt to Vishay152S1645
ALL371S0713 DDS alt to ST371S0558
Samsung alt to Murata138S0706138S0739 ALL
U6100IC,SPI SRL 50MHZ FLASH,64MBIT,8SOP,FUSE,L1335S0807
U610064MBIT SPI SRL DUAL I/O FLSH,SOIC8,Z BOOTROM_PROG:BLANK21335S0812 CRITICAL
BOOTROM_PROG:PROTOIC,EFI ROM(V0008)PROTO 0,J15 U6100341S3712 1 CRITICAL
CRITICALU61001341S3890 IC,EFI ROM(V0100) PROTO 3-J45 & EVT-J45
CRITICALU9101 GPUROM:BLANK1 IC,GPUROM,D2,BLANK
IC,EFI ROM(V0106) PROTO 4,J45341S3904 CRITICAL1
341S3742 U6100IC,EFI ROM(V0013) PROTO 1,J151 CRITICAL
341S3856 U4801 CRITICAL TPAD_PSOC:PROG1
CRITICAL TBTROM:BLANKU2890335S0915 1 EEPROM,SPI FLASH ROM,4MBit,50MHZ,USON8
341S3565 1
TBTROM:PROGU2890 CRITICAL341S3920 IC,EEPROM,FALCON RIDGE (V13.1),J44/J45
SYNC_DATE=07/31/2012SYNC_MASTER=J15_REFERENCE
BOM Configuration
376S0604
U6100
338S1214
dvt
051-0675
6.0.0
3 OF 119
3 OF 94
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
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IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
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THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
--------------------------------------------------------
APN 806-2247
APN 860-1448
APN 806-6192
SMT GND TEST PONTS
CPU BOSS APN 860-2931APN 817-0688
APN 817-0741
APN 860-1327
J45 THERMAL MODULE STANDOFF
APN 860-1328
J45 STANDOFF
APN 870-2451
J45 POGO PINS
APN 806-9391
Thermal Module gaskets APN 875-9290--------------------------------------------------------
Frame Holes
PD parts
GPU BOSS APN 860-4772
APN 806-6194
APN 817-4517
STDOFF-4.5OD1.8H-SM
STDOFF-4.5OD1.9H-SM
2.8R2.3
POGO-2.3OD-5.5H-SM-LOW-FORCESM
SL-1.1X0.45-1.4x0.75
TH-NSP
SM
SHLD-MLB-USB-J45
POGO-2.3OD-5.5H-SM-LOW-FORCESM
POGO-2.3OD-5.5H-SM-LOW-FORCESM
POGO-2.3OD-5.5H-SM-LOW-FORCESM
POGO-2.3OD-5.5H-SM-LOW-FORCESM
POGO-2.3OD-5.5H-SM-LOW-FORCESM
SL-1.1X0.45-1.4x0.75
TH-NSP
SL-1.1X0.45-1.4x0.75
TH-NSP
TH-NSP
SL-1.1X0.45-1.4x0.75
TH-NSP
SL-1.1X0.45-1.4x0.75
SL-1.1X0.45-1.4x0.75
TH-NSP
SL-2.3X3.9-2.9X4.5
TH-NSP
2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM
SMT-PAD-NSP2.1SM2.0MM-CIR
SMT-PAD-NSP2.1SM2.0MM-CIR 2.1SM2.0MM-CIR
SMT-PAD-NSP
THMLB-MTG-BRKT-J5
SHLD-J45-CAN-FENCE2-MDP
SMSM
SHLD-J45-CAN-FENCE1-MDP
POGO-2.3OD-5.5H-SM-LOW-FORCESM
STDOFF-4.9OD2.38H-SM-2
2.9OD1.2ID-1.35H-SM 2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM 2.9OD1.2ID-1.35H-SM2.9OD1.2ID-1.35H-SM2.9OD1.2ID-1.35H-SM
4.5OD1.85ID-1.95H
4.5OD1.85ID-1.95H
4.5OD1.85ID-1.95H
2.9OD1.2ID-1.35H-SM
5.0OD1.85ID-2.35H
5.0OD1.85ID-2.35H
5.0OD1.85ID-2.35H
5.0OD1.85ID-2.35H
6.0OD3.9H-SM
OMIT
OMIT
6.0OD3.9H-SM
OMIT
6.0OD3.9H-SM
OMIT
6.0OD3.9H-SM
D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC1946-3819
SYNC_DATE=05/03/2013SYNC_MASTER=CLEAN_J45
PD Parts
GND_BATT_CHGND
GND_CHASSIS_MLBCAN2
GND_CHASSIS_MLBCAN3
GND_CHASSIS_MLBCAN4
GND_CHASSIS_MLBCAN6
GND_CHASSIS_MLBCAN1
GND_CHASSIS_FAN
GND_CHASSIS_MLBCAN5
EDGE_BOND CRITICAL
STDOFF-4.5OD1.8H-SM STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2
4.5OD1.85ID-1.95H-1
SH0425
1
SH0424
1
ZT04151
SH0423
1
SH0431
1
ZT04701
SH04501
SH0432
1
SH0433
1
SH0435
1
SH0436
1
SH0434
1
ZT04711
ZT04721
ZT04741
ZT04751
ZT04731
ZT04501
SH0442
1
2
SH0441
1
2
SH0443
1
2
SH0444
1
2
ZT0490
1
ZT0491
1
ZT0492
1
BR0401
1
SH04511
SH04521
SH0437
1
SH0446
1
SH0445
1
SH0460
1
2
SH0461
1
2
SH0462
1
2
SH0467
1
2
SH0466
1
2
SH0465
1
2
SH0428
1
SH0427
1
SH0430
1
SH0440
1
2
SH0420
1
SH0422
1
SH0426
1
SH0429
1
CG0400
1
CG0401
1
CG0402
1
CG0403
1
SH0421
1
dvt
051-0675
6.0.0
4 OF 119
4 OF 94
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYM 10 OF 12
EDP
DIGITAL DISPLAY INTERFACES
FDI
EDP_TXN0
DDIC_TXP2
FDI_TXP1
FDI_TXN1
FDI_TXP0
FDI_TXN0
EDP_DISP_UTIL
EDP_RCOMP
DDIB_TXN0
DDIC_TXN1
DDIC_TXP0
DDIC_TXN0
DDIB_TXN3
DDIB_TXP2
EDP_TXP1
EDP_TXP0
EDP_TXN1
EDP_AUXP
EDP_HPD
EDP_AUXN
DDID_TXP1
DDID_TXN1
DDID_TXP0
DDID_TXN0
DDID_TXP3
DDID_TXN3
DDID_TXP2
DDID_TXN2
DDIC_TXP1
DDIC_TXN2
DDIC_TXN3
DDIC_TXP3
DDIB_TXP0
DDIB_TXN1
DDIB_TXP1
DDIB_TXN2
DDIB_TXP3
RESERVEDSYM 12 OF 12
DAISY_CHAIN_NCTF
RSVD132
RSVD133
RSVD134
RSVD135
RSVD136
RSVD137
RSVD138
RSVD139
DAISY_CHAIN_NCTF
TP
TP
TP
TP
TP
TP
TP
TP
NCNCNCNCNCNCNCNC
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
SYM 1 OF 12
FDI
PCI EXPRESS BASED INTERFACE SIGNALS
DMI
PEG_TX15
PEG_TX14
PEG_TX13
PEG_TX12
PEG_TX11
PEG_TX10
PEG_TX9
PEG_TX8
PEG_TX7
PEG_TX6
PEG_TX5
PEG_TX4
PEG_TX3
PEG_TX2
PEG_TX1
PEG_TX0
PEG_RX15*
PEG_RX14*
PEG_RX13*
PEG_RX12*
PEG_RX11*
PEG_RX10*
PEG_RX9*
PEG_RX8*
PEG_RX7*
PEG_RX6*
PEG_RX5*
PEG_RX4*
PEG_RX3*
PEG_RX2*
PEG_RX1*
PEG_RX0*
PEG_TX15*
PEG_TX14*
PEG_TX13*
PEG_TX12*
PEG_TX11*
PEG_TX10*
PEG_TX9*
PEG_TX8*
PEG_TX7*
PEG_TX6*
PEG_TX5*
PEG_TX4*
PEG_TX3*
PEG_TX2*
PEG_TX1*
PEG_TX0*
PEG_RCOMP
DISP_INT
FDI_CSYNC
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
DMI_RX0*
DMI_RX1*
DMI_RX2*
DMI_RX3*
DMI_RX0
DMI_RX2
DMI_RX3
DMI_TX0*
DMI_TX1*
DMI_TX2*
DMI_TX3*
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
DMI_RX1
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
exist between both TP’s on each corner.daisy-chain fashion. Continuity should
Each corner of CPU has two testpoints.Other corner test signals connected in
to match Intel symbol.Port D pins out of order
NO_TEST NO_TEST
CPU Daisy-Chain Strategy:
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
HASWELL
OMIT_TABLE
BGA
1%1/16WMF-LF402
24.9
10k5%1/16WMF-LF402
HASWELL
OMIT_TABLE
BGA
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
12 86
12 84 86
12 84 86
12 84 86
12 84 86
12 84 86
12 86
12 84 86
12 86
12 86
12 84 86
12 84 86
12 84 86
12 84 86
12 84 86
12 84 86
402
1/16WMF-LF
1%24.9
12 86
12 86
HASWELL
OMIT_TABLE
BGA
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
CPU DMI/PEG/FDI/RSVDSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
TP_DP_IG_A_MLP<3>TP_DP_IG_A_MLN<3>TP_DP_IG_A_MLP<2>TP_DP_IG_A_MLN<2>
=PEG_D2R_N<2>
CPU_DC_BE53_BF53TRUE
TRUECPU_DC_A3_B3CPU_DC_A4
TP_DP_IG_B_MLP<0>
PPVCOMP_S0_CPU
TP_DP_IG_A_MLP<1>
CPU_DC_BC54
CPU_DC_A3_B3 TRUE
CPU_DC_BF51
TRUE CPU_DC_B54_C54
DMI_S2N_N<0>
=PEG_D2R_N<13>
=PEG_D2R_N<7>
CPU_EDP_RCOMP
TP_DP_IG_D_MLP<3>
PPVCCIO_S0_CPU
TP_DP_IG_A_AUXCHN
PPVCOMP_S0_CPU
=PEG_D2R_N<6>=PEG_D2R_N<5>
=PEG_R2D_C_P<9>
CPU_PEG_RCOMP
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
DMI_N2S_N<2>
DMI_N2S_P<1>
DMI_N2S_N<3>
DMI_N2S_N<0>DMI_N2S_N<1>
DMI_N2S_P<3>
DMI_S2N_P<2>
=PEG_D2R_N<0>
=PEG_D2R_N<9>
DMI_S2N_N<2>
FDI_INT
FDI_CSYNC
=PEG_R2D_C_P<15>=PEG_R2D_C_P<14>=PEG_R2D_C_P<13>=PEG_R2D_C_P<12>=PEG_R2D_C_P<11>=PEG_R2D_C_P<10>
=PEG_R2D_C_P<8>=PEG_R2D_C_P<7>=PEG_R2D_C_P<6>
=PEG_R2D_C_P<4>=PEG_R2D_C_P<3>
=PEG_R2D_C_P<1>=PEG_R2D_C_P<2>
=PEG_R2D_C_N<15>=PEG_R2D_C_N<14>=PEG_R2D_C_N<13>
=PEG_R2D_C_N<11>=PEG_R2D_C_N<10>
=PEG_R2D_C_N<8>=PEG_R2D_C_N<9>
=PEG_R2D_C_N<7>=PEG_R2D_C_N<6>=PEG_R2D_C_N<5>=PEG_R2D_C_N<4>=PEG_R2D_C_N<3>=PEG_R2D_C_N<2>=PEG_R2D_C_N<1>
=PEG_D2R_P<14>=PEG_D2R_P<15>
=PEG_D2R_P<12>=PEG_D2R_P<11>
=PEG_D2R_P<9>=PEG_D2R_P<10>
=PEG_D2R_P<7>=PEG_D2R_P<6>
=PEG_D2R_P<4>
=PEG_D2R_P<2>
=PEG_D2R_P<0>
=PEG_D2R_N<15>=PEG_D2R_N<14>
=PEG_D2R_N<12>
=PEG_D2R_N<10>=PEG_D2R_N<11>
=PEG_D2R_N<8>
=PEG_D2R_N<3>
=PEG_D2R_N<1>
DMI_S2N_P<1>DMI_S2N_P<0>
DMI_S2N_N<3>
DMI_S2N_N<1>
DMI_S2N_P<3>
=PEG_R2D_C_P<5>
=PEG_D2R_P<1>
DMI_N2S_P<0>
DMI_N2S_P<2>
=PEG_D2R_N<4>
TP_DP_IG_A_MLN<0>
TP_DP_IG_C_MLP<2>
TP_EDP_DISP_UTIL
TP_DP_IG_B_MLN<0>
TP_DP_IG_C_MLN<1>TP_DP_IG_C_MLP<0>TP_DP_IG_C_MLN<0>
TP_DP_IG_B_MLN<3>TP_DP_IG_B_MLP<2>
TP_DP_IG_A_MLP<0>
TP_DP_IG_A_MLN<1>
TP_DP_IG_D_MLN<1>TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<3>TP_DP_IG_D_MLP<2>TP_DP_IG_D_MLN<2>
TP_DP_IG_C_MLP<1>TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLN<3>TP_DP_IG_C_MLP<3>
TP_DP_IG_B_MLN<1>TP_DP_IG_B_MLP<1>TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<3>
TP_DP_IG_A_AUXCHP
=PEG_D2R_P<3>
=PEG_D2R_P<5>
=PEG_D2R_P<8>
=PEG_D2R_P<13>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<0>
=PEG_R2D_C_N<12>
DP_IG_A_HPD_L
TRUECPU_DC_A53_B53CPU_DC_A52_B52 TRUE
CPU_DC_B2_C3 TRUE
CPU_DC_A53_B53 TRUE
CPU_DC_A52_B52 TRUE
CPU_DC_BE3_BF3 TRUE
CPU_DC_BE2_BF2 TRUE
CPU_DC_BD54_BE54 TRUE
CPU_DC_BE2_BF2 TRUE
CPU_DC_BD1_BE1 TRUE
CPU_DC_BD54_BE54 TRUE
CPU_DC_BD1_BE1 TRUE
CPU_DC_B54_C54 TRUE
TRUE CPU_DC_BE52_BF52
TRUE CPU_DC_C1_C2TRUE CPU_DC_C1_C2TRUE CPU_DC_B2_C3
CPU_DC_BE52_BF52 TRUE
CPU_DC_BE3_BF3 TRUE
CPU_DC_D1
CPU_DC_D54
CPU_DC_A51
CPU_DC_BF4
CPU_DC_BC1
CPU_DC_BE53_BF53 TRUE
R05101
2
U0500
F12
AB2
AB3
AC3
AC1
AB1
AB4
AC4
AC2
AF2
AF4
AG4
AG2
AF1
AF3
AG3
AG1
F11
AH6
E10
C10
M2
V5
V4
V1
Y3
Y2
B10
E9
D9
B9
L5
L2
M4
L4
F10
D10
M1
Y5
V3
V2
Y4
Y1
A10
F9
C9
A9
M5
L1
M3
L3
B6
C5
T6
R6
R2
R4
T4
T1
E6
D4
G4
E3
J5
G3
J3
J2
C6
B5
T5
R5
R1
R3
T3
T2
D6
E4
G5
E2
J6
G2
J4
J1
U0500
C25
A25
C24
A24
D25
B25
D24
B24
C21
A21
C20
A20
D21
B21
D20
B20
C17
A17
C16
A16
D17
B17
D16
B16
F15
F14
E12
E14
AG6
C14
A12
D14
B12
C12
A14
D12
B14
R05301
2
R05311
2
U0500
A3
A4
A51
A52
A53
B2
B3
B52
B53
B54
BC1
BC54
BD1
BD54
BE1
BE2
BE3
BE52
BE53
BE54
BF2
BF3
BF4
BF51
BF52
BF53
C1
C2
C3
C54
D1
D54
AD45
AE9
AF9
AG45
AN35
AN37
G14
G17
TP0500 1
TP05011
TP05111
TP05311
TP0510 1
TP0520 1
TP0530 1
TP0521 1
5 OF 94
5 OF 119
6.0.0
051-0675
dvt
82
82
82
82
5
5
5 8
82
5 5
86
6 8 10 18 57
82
5 8
86
82
82
82
82
20
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
BI
BI
BI
BI
BI
IN
IN
OUT
BI
NC
OUT
BI
SYM 2 OF 12
CLOCK
JTAG
PWR
DDR3
THERMAL
THERMTRIP*
PM_SYNC
PWRGOOD
SM_DRAMPWROK
PLTRSTIN*
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST*
PRDY*
PREQ*
TCK
TMS
TRST*
TDI
TDO
DBR*
BPM0*
BPM1*
BPM3*
BPM2*
BPM4*
BPM5*
BPM6*
BPM7*
PECI
PROC_DETECT*
PROCHOT*
CATERR*
DPLL_REF_CLKN
DPLL_REF_CLKP
BCLKN
BCLKP
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
OUT
IN
IN
IN
IN
IN
IN
SYM 11 OF 12RESERVED
RSVD_TP28
RSVD_TP27
RSVD_TP39
RSVD_TP38
RSVD11
RSVD_TP1
RSVD_TP2
RSVD51
RSVD52
RSVD50
RSVD16
RSVD42
RSVD41
RSVD10
RSVD9
RSVD95
RSVD94
RSVD93
RSVD92
CFG_RCOMP
CFG16
CFG19
CFG18
CFG17
VSS_H54
VSS_H52
VSS_H51
VSS_H53
VCC_F22
VSS_G19
VSS_F52
VSS_F51
TESTLO_F21
CFG0
CFG1
CFG6
CFG5
CFG2
CFG3
CFG4
TESTLO_F20
CFG11
CFG10
CFG9
CFG8
CFG7
CFG12
CFG14
CFG13
CFG15
RSVD_TP17
RSVD_TP18
RSVD_TP37
RSVD_TP36
RSVD_TP35
RSVD_TP23
RSVD_TP3
RSVD_TP4
RSVD47
RSVD48
RSVD49
RSVD_TP26
RSVD_TP25
RSVD_TP24
NCNC
NCNC
NCNC
NCNC
NC
NC
NCNC
NC
IN
OUT
IN
IN
IN
OUT
ININ
INOUT
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
J1800 and only for debug accessThese can be placed close to
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
(IPU)
(IPU)
18 86
18 86
18 86
18 86
18 86
10K5%
1/16WMF-LF
402
PLACE_NEAR=U0500.F50:157mm
12 21 86
14 18 86
14 41 86
14 41 86
402MF-LF1/16W1%100
PLACE_NEAR=U0500.BB52:12.7mm
PLACE_NEAR=U0500.BB53:12.7mm
402MF-LF1/16W1%75
PLACE_NEAR=U0500.BB51:12.7mm
402MF-LF1/16W1%100
40 86 62
402MF-LF1/16W
5%
1/16W
56
5%
MF-LF402
40 41 57 86
OMIT_TABLE
HASWELLBGA
21
11 86
11 86
11 86
11 86
11 86
11 86
BGA
OMIT_TABLE
HASWELL
49.91%1/16W
402MF-LF
402MF-LF1/16W
1%49.9
402MF-LF1/16W
1%49.9
NOSTUFF
1/16W
1K5%
MF-LF402
1K
NOSTUFF
5%1/16W
402MF-LF
402MF-LF1/16W
5%1K
NOSTUFF
402MF-LF1/16W5%1K
NOSTUFF
402MF-LF1/16W
5%1K
NOSTUFFCPUCFG6_PD
402MF-LF1/16W
5%1K
CPUCFG5_PD
402MF-LF1/16W5%1K
1K
EDP:YES
5%1/16WMF-LF
402
NOSTUFF
1K5%1/16WMF-LF402
PLACE_NEAR=U0500.AP48:51.562mm
1%1/16WMF-LF
402
3.32K
NOSTUFF
1K5%
1/16WMF-LF
402
18 83 86
18 83 86
18 83 86
18 83 86
18 83 86
18 83 86
18 83 86
402MF-LF1/16W
1%
PLACE_NEAR=R0621.2:1mm
1.82K 12 86
1418 19 86
18 86
18 86
18 86
CPU Clock/Misc/JTAG/CFGSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
CPUPEG:X16
CPUCFG5_PDCPUPEG:X8X8
CPUCFG6_PD,CPUCFG5_PDCPUPEG:X8X4X4
=PP1V5R1V35_S0_CPU
PPVCCIO_S0_CPU
CPU_PROCHOT_L
CPU_CFG<9>CPU_CFG<3>
CPU_CFG<16>
CPU_CFG<1>CPU_CFG<0>
CPU_CFG<7>CPU_CFG<6>
CPU_RESET_L
CPU_PWRGD
CPU_CLK135M_DPLLREF_N
PM_THRMTRIP_L
TP_CPU_RSVD_TP17
CPU_CFG<18>
TP_CPU_RSVD_TP39TP_CPU_RSVD_TP38
TP_CPU_RSVD_TP25TP_CPU_RSVD_TP26
TP_CPU_RSVD_TP28TP_CPU_RSVD_TP27
CPU_CFG<19>
CPU_TESTLO_F20
CPU_CFG<0>
TP_CPU_RSVD_TP18
CPU_TESTLO_F21
TP_CPU_RSVD_TP47
TP_CPU_RSVD_TP23
TP_CPU_RSVD_TP3
CPU_CFG_RCOMP
CPU_CFG<5>CPU_CFG<4>
CPU_CFG<9>CPU_CFG<10>
CPU_CFG<2>
CPU_CFG<16>
CPU_CFG<17>
CPU_CFG<3>
XDP_CPU_PRDY_L
XDP_CPU_TMS
XDP_DBRESET_L
XDP_BPM_L<0>XDP_BPM_L<1>
XDP_BPM_L<3>XDP_BPM_L<2>
XDP_BPM_L<4>XDP_BPM_L<5>XDP_BPM_L<6>
XDP_CPU_TDOXDP_CPU_TDI
XDP_CPU_TRST_L
TP_CPU_RSVD_TP24
TP_CPU_RSVD_TP35
CPU_CFG<4>
CPU_CFG<1>CPU_CFG<2>
CPU_CFG<5>CPU_CFG<6>CPU_CFG<7>CPU_CFG<8>
CPU_CFG<11>CPU_CFG<12>
CPU_CFG<14>CPU_CFG<13>
CPU_CFG<15>
TP_CPU_RSVD_TP36
TP_CPU_RSVD_TP4
TP_CPU_RSVD_TP1
TP_CPU_RSVD_TP48TP_CPU_RSVD_TP49
TP_CPU_RSVD_TP37
=PPVCC_S0_CPU
CPU_SM_RCOMP<1>CPU_SM_RCOMP<0>
PM_SYNC
CPU_CLK135M_DPLLREF_P
CPU_CLK135M_DPLLSS_NCPU_CLK135M_DPLLSS_P
DMI_CLK100M_CPU_NDMI_CLK100M_CPU_P
CPU_PECI
TP_CPU_RSVD_TP2
CPU_CATERR_L
CPU_PROCHOT_R_L
XDP_CPU_TCK
XDP_CPU_PREQ_L
=MEM_RESET_L
CPU_SM_RCOMP<2>
XDP_BPM_L<7>
PM_MEM_PWRGD
R06201
2
R06111
2
R06141
2
R06131
2
R06121
2
R06011
2 R060312
U0500
AB6
AA6
R51
R50
P49
N50
R49
P53
U51
P51
G50
F53
AC6
AE6
G51
L54
D52
N53
N52
C51
E50
F50
AP48
BE51
BB51
BB53
BB52
V6
Y6
N54
N49
M49
D53
M51
M53
U0500
AG49
AD49
Y53
W53
U53
V54
R53
R52
Y52
Y51
V53
V52
AC49
AE49
Y50
AB49
V51
W51
Y49
Y54
R54
AH49
AL6
AM48
AU26
AU27
B50
BC4
BD4
E5
F16
F8
G53
H50
L49
L50 N51
A5
A6
BD3
BE4
E1
F1
F24
F25
F6
G10
G12
G21
G24
G6
L51
L52
L53
F20
F21
F22
F51
F52
G19
H51
H52
H53
H54
R06901
2
R06801
2
R06851
2
R06491
2
R06431
2
R06411
2
R06401
2
R06471
2
R06461
2
R06451
2
R06441
2
R06421
2
R06211
2
R06481
2
dvt
051-0675
6.0.0
6 OF 119
6 OF 94
810 21 81
5 8 10 18 57
6 18 86
6 18 83 86
6 18 86
6 18 86
6 18 86
6 18 86
6 18 86
18 86
18 86
618 86
6 18 86
6 18 86
618 86
18 86
6 18 86
6 18 86
18 86
618 83 86
618 86
618 86
618 86
618 86
618 86
618 86
18 86
18 86
18 86
18 86
18 86
18 86
810 81
86
86
86
OUT
OUT
OUT
NC
NC
NC
NC
NCNCNCNCNCNCNC NC
NC
NCNCNC
NCNC
NC
NC
NC
NCNCBI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYM 3 OF 12
MEMORY CHANNEL A
SA_DQ12
SA_DQ11
SA_DQ8
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_CKP3
SA_CKN3
SA_CKP2
SA_CKP1
SA_CKN1
SA_CKP0
SA_CKN0
SA_CKE1
SA_CS1*
SA_DQ20
SM_VREF
SA_DQSN7
SA_DQSN6
SA_DQSN5
SA_DQSN4
SA_DQSN3
SA_DQSN2
SA_DQSN1
SA_DQSN0
SA_DQS7
SA_DQS6
SA_DQS4
SA_DQS5
SA_DQS3
SA_DQS2
SA_DQS1
SA_DQS0
SA_MA13
SA_MA12
SA_MA11
SA_MA9
SA_MA8
SA_MA7
SA_MA5
SA_MA6
SA_MA4
SA_MA2
SA_MA3
SA_MA0
SA_MA1
SA_CAS*
SA_WE*
VSS_BC21
SA_RAS*
SA_BS1
SA_BS2
SA_ODT3
SA_BS0
SA_ODT2
SA_ODT1
SA_ODT0
SA_CS3*
SA_CS2*
SA_CS0*
SA_CKE3
SA_CKE2
SA_CKE0
SA_DQ30
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ9
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ61
SA_DQ62
SA_DQ63
SA_DQ4
SA_DQ3
SA_DQ10
SA_DQ7
SA_DQ5
SA_DQ6
SA_DQ47
SA_DQ46
SA_DQ45
SB_DIMM_VREFDQ
SA_DIMM_VREFDQ
RSVD25
RSVD162
RSVD165
RSVD168
SA_CKN2
SA_MA10
SA_MA14
SA_MA15
RSVD170
RSVD169
RSVD167
RSVD166
RSVD164
RSVD163
SA_DQ59
SA_DQ60RSVD161
RSVD160
SYM 4 OF 12
MEMORY CHANNEL B
SB_DQ29
SB_DQ28
RSVD171
SB_CKN0
SB_CKE0
RSVD181
RSVD180
RSVD179
RSVD178
RSVD177
RSVD176
RSVD175
RSVD174
RSVD173
RSVD172
SB_DQSN3
SB_DQSN6
SB_DQS0
SB_DQS1
SB_DQS5
SB_DQS3
SB_DQS4
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7 SB_CKE1
SB_DQ8
SB_DQ9
SB_DQ10SB_CKE2
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14 SB_CKE3
SB_DQ15
SB_DQ16 SB_CS0*
SB_DQ17 SB_CS1*
SB_DQ18 SB_CS2*
SB_DQ19 SB_CS3*
SB_DQ20SB_ODT0
SB_DQ21SB_ODT1
SB_DQ22SB_ODT2
SB_DQ23SB_ODT3
SB_DQ24
SB_DQ25 SB_BS0
SB_DQ26 SB_BS1
SB_DQ27
SB_DQ30SB_RAS*
SB_WE*
SB_CAS*
SB_MA0
SB_MA1SB_DQ36
SB_MA2SB_DQ37
SB_MA3SB_DQ38
SB_MA4SB_DQ39
SB_MA5SB_DQ40
SB_MA6SB_DQ41
SB_MA7SB_DQ42
SB_MA8SB_DQ43
SB_MA9SB_DQ44
SB_MA10SB_DQ45
SB_MA11SB_DQ46
SB_MA12SB_DQ47
SB_MA13SB_DQ48
SB_MA14SB_DQ49
SB_MA15SB_DQ50
SB_DQ51SB_DQSN0
SB_DQ52SB_DQSN1
SB_DQ53SB_DQSN2
SB_DQ54
SB_DQ55SB_DQSN4
SB_DQ56SB_DQSN5
SB_DQ57
SB_DQ58SB_DQSN7
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63SB_DQS2
SB_DQS6
SB_DQS7
SB_CKP0
SB_CKN1
SB_CKP1
SB_CKN2
SB_CKP2
SB_CKN3
SB_CKP3
SB_BS2
VSS_AU30
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NCNC
NCNC
NCNC
NCNCNC
NC
NCNC
NC
NCNCNC
NCNC
NCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
22 86
22 86
22
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
23 27 89
23 27 89
24 27 89
24 27 89
24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
OMIT_TABLE
HASWELLBGA
OMIT_TABLE
HASWELLBGA
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
24 27 89
23 27 89
24 27 89
23 27 89
23 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
25 27 89
25 27 89
25 27 89
26 27 89
26 27 89
26 27 89
25 27 89
25 26 27 89
25 26 27 89
26 27 89
25 27 89
26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
CPU DDR3 Interfaces
MEM_A_DQ<2>MEM_A_DQ<3>
MEM_A_CS_L<1>
MEM_A_DQ<45>
MEM_A_DQ<54>
MEM_A_DQ<51>
MEM_A_DQ<53>
MEM_A_DQ<0>MEM_A_DQ<1>
MEM_A_DQ<4>MEM_A_DQ<5>MEM_A_DQ<6>MEM_A_DQ<7>MEM_A_DQ<8>MEM_A_DQ<9>MEM_A_DQ<10>MEM_A_DQ<11>MEM_A_DQ<12>MEM_A_DQ<13>
MEM_A_DQ<15>MEM_A_DQ<16>
MEM_A_DQ<18>MEM_A_DQ<19>MEM_A_DQ<20>
MEM_A_DQ<22>MEM_A_DQ<21>
MEM_A_DQ<23>MEM_A_DQ<24>MEM_A_DQ<25>
MEM_A_DQ<27>MEM_A_DQ<26>
MEM_A_DQ<28>MEM_A_DQ<29>MEM_A_DQ<30>
MEM_A_DQ<32>MEM_A_DQ<31>
MEM_A_DQ<33>MEM_A_DQ<34>MEM_A_DQ<35>
MEM_A_DQ<37>MEM_A_DQ<36>
MEM_A_DQ<38>MEM_A_DQ<39>MEM_A_DQ<40>MEM_A_DQ<41>MEM_A_DQ<42>MEM_A_DQ<43>MEM_A_DQ<44>
MEM_A_DQ<46>MEM_A_DQ<47>MEM_A_DQ<48>MEM_A_DQ<49>MEM_A_DQ<50>
MEM_A_DQ<52>
MEM_A_DQ<55>MEM_A_DQ<56>
MEM_A_DQ<61>
MEM_A_DQ<63>MEM_A_DQ<62>
MEM_B_DQ<4>MEM_B_DQ<3>MEM_B_DQ<2>MEM_B_DQ<1>MEM_B_DQ<0>
MEM_B_DQ<9>MEM_B_DQ<8>MEM_B_DQ<7>MEM_B_DQ<6>MEM_B_DQ<5>
MEM_B_DQ<14>MEM_B_DQ<13>MEM_B_DQ<12>MEM_B_DQ<11>MEM_B_DQ<10>
MEM_B_DQ<19>
MEM_B_DQ<17>
MEM_B_DQ<15>
MEM_B_DQ<20>
MEM_B_DQ<24>MEM_B_DQ<23>MEM_B_DQ<22>MEM_B_DQ<21>
MEM_B_DQ<25>
MEM_B_DQ<30>MEM_B_DQ<29>MEM_B_DQ<28>MEM_B_DQ<27>MEM_B_DQ<26>
MEM_B_DQ<35>MEM_B_DQ<34>MEM_B_DQ<33>MEM_B_DQ<32>MEM_B_DQ<31>
MEM_B_DQ<40>MEM_B_DQ<39>MEM_B_DQ<38>MEM_B_DQ<37>MEM_B_DQ<36>
MEM_B_DQ<45>MEM_B_DQ<44>MEM_B_DQ<43>MEM_B_DQ<42>MEM_B_DQ<41>
MEM_B_DQ<50>MEM_B_DQ<49>MEM_B_DQ<48>MEM_B_DQ<47>MEM_B_DQ<46>
MEM_B_DQ<55>MEM_B_DQ<54>MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<60>MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<57>MEM_B_DQ<56>
MEM_B_DQ<61>
MEM_B_DQ<63>MEM_B_DQ<62>
MEM_A_DQ<60>
MEM_B_CLK_N<0>MEM_B_CLK_P<0>MEM_B_CKE<0>
MEM_B_CLK_N<1>MEM_B_CLK_P<1>MEM_B_CKE<1>
MEM_B_CS_L<0>MEM_B_CS_L<1>
MEM_B_ODT<0>MEM_B_ODT<1>
MEM_B_BA<0>MEM_B_BA<1>MEM_B_BA<2>
MEM_B_RAS_LMEM_B_WE_LMEM_B_CAS_L
MEM_B_A<0>MEM_B_A<1>MEM_B_A<2>MEM_B_A<3>MEM_B_A<4>MEM_B_A<5>MEM_B_A<6>MEM_B_A<7>MEM_B_A<8>MEM_B_A<9>MEM_B_A<10>MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>MEM_B_A<14>MEM_B_A<15>
MEM_A_CLK_N<0>MEM_A_CLK_P<0>MEM_A_CKE<0>
MEM_A_CLK_N<1>MEM_A_CLK_P<1>MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_ODT<0>MEM_A_ODT<1>
MEM_A_BA<0>MEM_A_BA<1>MEM_A_BA<2>
MEM_A_RAS_LMEM_A_WE_LMEM_A_CAS_L
MEM_A_A<0>MEM_A_A<1>MEM_A_A<2>MEM_A_A<3>MEM_A_A<4>MEM_A_A<5>MEM_A_A<6>MEM_A_A<7>MEM_A_A<8>MEM_A_A<9>MEM_A_A<10>MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>MEM_A_A<14>MEM_A_A<15>
MEM_B_DQS_N<7>MEM_B_DQS_N<6>MEM_B_DQS_N<5>MEM_B_DQS_N<4>MEM_B_DQS_N<3>MEM_B_DQS_N<2>MEM_B_DQS_N<1>MEM_B_DQS_N<0>
MEM_B_DQS_P<5>MEM_B_DQS_P<4>MEM_B_DQS_P<3>MEM_B_DQS_P<2>MEM_B_DQS_P<1>MEM_B_DQS_P<0>
MEM_A_DQS_N<7>
MEM_A_DQS_N<5>MEM_A_DQS_N<6>
MEM_A_DQS_N<4>MEM_A_DQS_N<3>MEM_A_DQS_N<2>MEM_A_DQS_N<1>MEM_A_DQS_N<0>
MEM_A_DQS_P<6>MEM_A_DQS_P<7>
MEM_A_DQS_P<5>MEM_A_DQS_P<4>MEM_A_DQS_P<3>MEM_A_DQS_P<2>MEM_A_DQS_P<1>MEM_A_DQS_P<0>
MEM_A_DQ<17>
MEM_A_DQ<14>
CPU_DIMMB_VREFDQ
CPU_DIMMA_VREFDQ
MEM_B_DQ<52>
MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>
MEM_B_DQS_P<7>MEM_B_DQS_P<6>
CPU_DIMM_VREFCA
MEM_B_DQ<16>
MEM_B_DQ<18>
U0500
AU39
AU40
AV39
AV40
AW39
AW40
AY39
AY40
BA39
BA40
BC53
BD31
BC20
BD21
BD32
BE21
BE34
BF34
BC34
BD34
BE25
BD25
BE23
BD23
BF25
BC25
BF23
BC23
BE16
BC17
BE17
BD16
AR6
AH54
AH52
AR51
AR53
AN53
AN51
AR52
AR54
AV52
AV53
AY52
AY51
AK51
AV51
AV54
AY54
AY53
AY47
AY49
BA47
BA45
AY45
AY43
AK54
BA49
BA43
BF14
BC14
BC11
BF11
BE14
BD14
BD11
BE11
AH53
BC9
BE9
BE6
BC6
BD9
BF9
BE5
BD6
BB4
BC2
AH51
AW3
AW2
BB3
BB2
AW4
AW1
AU3
AU1
AR1
AR4
AK52
AU2
AU4
AR2
AR3
AK53
AN54
AN52
AJ53
AP52
AW53
BA46
BE12
BD7
BA2
AT3
AJ52
AP53
AW52
AY46
BD12
BE7
BA3
AT2
BD28
BD27
BD20
BF31
BC31
BE20
BE32
BE31
BF28
BE28
BF32
BC27
BF27
BC28
BE27
BC32
BC16
BF16
BF17
BD17
BF20
BF21
AN6
AM6
BC21
U0500 AY36
BC37
BC39
BD37
BD38
BD39
BE37
BE38
BE39
BF37
BF39
AY23
BA23
BA36
AV20
AU36
AU35
AV35
AV36
AW27
AW26
BA26
BA27
AV27
AV26
AY26
AY27
BA20
AY19
AU19
AW20
AC54
AC52
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
AE51
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
AE54
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AC53
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10
AU8
BA8
AC51
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AE52
AM1
AM4
AK2
AK3
AE53
AU47
AU49
AD53
AV46
BE48
BE43
AW15
AW12
AW6
AL3
AD52
AU46
BD48
BD43
AW16
AW10
AW8
AL2
BA30
AW30
AU23
AY35
AW35
AU20
AW36
BA35
AY30
AV30
AW32
AY32
AT30
AV32
BA32
AU32
AY20
BA19
AV19
AW19
AV23
AW23
AU30
dvt
051-0675
6.0.0
7 OF 119
7 OF 947 OF 94
7 OF 119
6.0.0
051-0675
dvt
BI
OUT
IN
SYM 5 OF 12
RSVD68
VIDSOUT
VIDSCLK
VIDALERT*
RSVD79(VSS)
RSVD78
VSS_V50(RSVD)
VSS_AP50(RSVD)
VSS_AP49(RSVD)
VSS_AN49(RSVD)
VSS_AM50(RSVD)
IVR_ERROR
VSS_AK49(RSVD)
VSS_AJ49(RSVD)
VSS_AJ50(RSVD)
VSS_AG50(RSVD)
VSS_AD50(RSVD)
VSS_AB50(RSVD)
FC_F17
RSVD65
RSVD69
RSVD67
RSVD66
RSVD74
RSVD73
RSVD72
RSVD71
RSVD70
VCC_L6
VCC_M6
VCOMP_OUT
VCC_SENSE
VSS_B51
FC_D5
FC_D3
VDDQ
VCC
VCC
VCCIO_OUT
RSVD76
RSVD75
VSS_E52
PWR_DEBUG
RSVD64SYM 6 OF 12
POWER
VCC
VCC
IN
OUT
NCNCNCNC
NCNC
NCNCNCNC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Max load: 300mA
Connections would be requiredfor 2014 CPU support.
R0802.2:
R0800.2:
R0810.2:
Max load: 300mA
NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.
0
5%1/16WMF-LF402
57 86
110
PLACE_NEAR=U0500.J50:2.54mm
402
1/16W1%
MF-LF
0
402
5%
MF-LF1/16W
57 86
PLACE_NEAR=U0500.J53:38mm
5%
402MF-LF1/16W
4357 86
PLACE_NEAR=R0810.1:2.54mm
751%
1/16WMF-LF
402
OMIT_TABLE
HASWELLBGA
OMIT_TABLE
HASWELL
BGA
18
PLACE_NEAR=U0500.C50:50.8mm
PLACE_SIDE=BOTTOM
1001/16WMF-LF
402
5%
57 86
CPU PowerSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
PPVCCIO_S0_CPUMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V
CPU_VIDSOUT_R
CPU_VIDALERT_R_L
TP_CPU_IVR_ERROR
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V
PPVCOMP_S0_CPU
CPU_VIDALERT_L
TP_CPU_FC_VCCSTTP_CPU_FC_VCCST_PWRGD
CPU_VIDSOUT CPU_PWR_DEBUG
=PP1V5R1V35_S0_CPU
=PPVCC_S0_CPU
TP_CPU_RSVD_TP75TP_CPU_RSVD_TP76
TP_CPU_RSVD_TP78
CPU_VCCSENSE_P
=PPVCC_S0_CPU
CPU_VIDSCLK_RCPU_VIDSCLK
R08121 2
R08021
2
R08111 2
R08101 2
R08001
2
U0500
D3
D5
F17
AM49
F19
AH9
AN18
AN22
AN31
AN33
AR49
J12
J17
J21
J26
J31
U49
V49
W49
W9
A36
A38
A39
A42
A43
A45
A46
A48
AA46
AA47
AA8
AA9
B43
B45
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29
L6
M6
C50
D51
AK6
AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33
J53
J52
J50
AB50
AD50
AG50
AJ49
AJ50
AK49
AM50
AN49
AP49
AP50
B51
E52
V50
U0500
A27
A28
A31
A32
A34
AB45
AB46
AB8
AC46
AC47
AC8
AC9
AD46
AD8
AE46
AE47
AE8
AF8
AG46
AG8
AH46
AH47
AH8
AJ45
AJ46
AK46
AK47
AK8
AL45
AL46
AL8
AL9
AM46
AM47
AM8
AM9
AN10
AN12
AN13
AN14
AN15
AN16
AN17
AN19
AN20
AN21
AN23
AN24
AN25
AN26
AN27
AN29
AN30
AN32
AN34
AN36
AN38
AN39
AN40
AN41
AN42
AN43
AN44
AN45
AN46
AN8
AN9
AP10
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AP41
AP42
AP43
AP44
AP46
AP47
AP8
AP9
AR35
AR37
AR39
AR41
AR43
AR45
AR46
B27
B28
B31
B32
B34
B36
B38
B39
B42
H30
H31
H32
H33
H34
H36
H37
H38
H39
H40
H42
H43
H45
H46
H48
H8
H9
J10
J14
J19
J24
J29
J33
J36
J37
J38
J39
J40
J42
J43
J45
J46
J48
J8
J9
K38
K40
K43
K44
K45
K46
K48
K8
K9
L37
L38
L39
L40
L42
L43
L44
L46
L47
L8
M37
M38
M39
M40
M42
M43
M44
M45
M46
M8
M9
N37
N38
N39
N40
N42
N43
N44
N46
N47
N8
N9
P45
P46
P8
R46
R47
R8
R9
T45
T46
U46
U47
U8
U9
V45
V46
V8
W46
W47
W8
Y45
Y46
Y8
R08601
2
dvt
6.0.0
8 OF 119
8 OF 94
051-0675
5 6 10 18 57
5
610 21 81
6 8 10 81
6 8 10 81
SYM 7 OF 12GROUND
VSS VSS
SYM 8 OF 12GROUND
VSSVSS
SYM 9 OF 12 VSS_P9(RSVD)
VSS_G18(RSVD)
VSS_AR22(RSVD)
VSS_AB48(RSVD)
VSS_NCTF
VSS_SENSE
VSS
VSS
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
BGA
OMIT_TABLE
HASWELLBGA
OMIT_TABLE
HASWELL
BGA
OMIT_TABLE
HASWELL
57 86
1005%1/16WMF-LF402
PLACE_SIDE=BOTTOMPLACE_NEAR=U0500.D50:50.8mm
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
CPU Ground
CPU_VCCSENSE_N
U0500A11
A15
A19
A22
A26
A30
A33
A37
A40
A44
AA1
AA2
AA3
AA4
AA48
AA5
AA7
AB5
AB51
AB52
AB53
AB54
AB7
AB9
AC48
AC5
AC50
AC7
AD48
AD51
AD54
AD7
AD9
AE1
AE2
AE3
AE4
AE48
AE5
AE50
AE7
AF5
AF6
AF7
AG48
AG5
AG51
AG52
AG53
AG54
AG7
AG9
AH1
AH2
AH3
AH4
AH48
AH5
AH50
AH7
AJ48
AJ51
AJ54
AK48
AK5
AK50
AK7
AK9
AL1
AL4
AL48
AL5
AL7
AM5
AM51
AM52
AM53
AM54
AM7
AN1
AN2
AN3
AN4
AN48
AN5
AN50
AN7
AP51
AP54
AP7
AR12
AR14
AR16
AR18
AR20
AR24
AR26
AR48
AR5
AR50
AR7
AR8
AR9
AT1
AT10
AT12
AT15
AT16
AT18
AT20
AT22
AT25
AT26
AT29
AT33
AT35
AT37
AT39
AT4
U0500AT40
AT42
AT43
AT45
AT46
AT47
AT49
AT5
AT50
AT51
AT52
AT53
AT54
AT6
AT8
AT9
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42
AU5
AU9
AV1
AV13
AV18
AV2
AV22
AV25
AV29
AV3
AV33
AV4
AV42
AV5
AV50
AV9
AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49
AW5
AW50
AW51
AW54
AW9
AY13
AY22
AY25
AY29
AY33
AY37
AY42
AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9
U0500
AB48
AR22
BC10
BC12
BC15
BC18
BC22
BC26
BC3
BC30
BC33
BC36
BC38
BC41
BC43
BC46
BC48
BC5
BC50
BC52
BC7
BD10
BD15
BD18
BD36
BD41
BD46
BD5
BD51
BE10
BE15
BE36
BE41
BE46
BF10
BF12
BF15
BF18
BF22
BF26
BF30
BF33
BF36
BF38
BF41
BF43
BF46
BF48
BF7
C11
C15
C19
C22
C26
C30
C33
C37
C4
C40
C44
C49
C52
C8
D11
D15
D19
D22
D26
D30
D33
D37
D40
D44
D49
D8
E11
E15
E16
E17
E19
E20
E21
E22
E24
E25
E26
E30
E33
E37
E40
E44
E49
E51
E53
E8
F2
F26
F3
F30
F33
F37
F4
F40
F44
F49
F5
G11
G13
G16
G18
G20
G23
G25
G26
G30
G33
G37
G40
G44
G49
G52
G54
G7
G8
G9
H44
H49
H7
J44
J49
J51
J54
J7
K1
K2
K3
K4
K5
K6
K7
L48
L7
L9
M48
M50
M52
M54
M7
N48
N7
A49
A50
A8
B4
BA1
BA54
BB1
BB54
BD2
BD53
BF49
BF5
BF50
BF6
C53
D2
E54
F54
G1
P1
P2
P3
P4
P48
P5
P50
P52
P54
P6
P7
P9
R48
R7
D50
T48
U1
U2
U3
U4
U48
U5
U50
U52
U54
U6
U7
V48
V7
V9
W48
W50
W52
W54
W7
Y48
Y7
Y9
R09601
2
9 OF 94
9 OF 119
6.0.0
051-0675
dvt
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)
CAPS for Acoustic Control (C102E to C103F)
Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402
PLACEMENT_NOTE (C1046-C1067):
CPU VCORE Decoupling
PLACEMENT_NOTE (C1000-C1019):
PLACEMENT_NOTE (C1068-C1076:
PLACEMENT_NOTE (C1024-C1045):
PLACEMENT_NOTE (C1020-C1023):
PLACEMENT_NOTE (C1090-C1097):
Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)
NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.
Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)
CPU VCCIO Decoupling
(Z = 1.5mm, place on tall side next to CPU & under heat pipe)
PLACEMENT_NOTE (C1098-C1099):
PLACEMENT_NOTE (C1080-C1089):
Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402 Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402
CPU VDDQ Decoupling
CAPS for Acoustic Control (C109A to C102D)
0402
1UF
X6S-CERM10V10%
Place on bottom side of U0500
10V
0402
Place on bottom side of U0500
10%
X6S-CERM
1UF
X6S-CERM0402
Place on bottom side of U0500
10%10V
1UF
0402-2
4VX5R-CERM
20UF
CRITICAL
NO STUFFPlace near inductors on bottom side.
20%
10%10VX6S-CERM0402
Place on bottom side of U0500
1UF
0402
Place on bottom side of U0500
1UF
X6S-CERM10V10%
10V
0402
Place on bottom side of U0500
10%
X6S-CERM
1UF
0402
Place on bottom side of U0500
1UF
X6S-CERM10V10%
X6S-CERM0402
Place on bottom side of U0500
1UF10V10%
0402
Place on bottom side of U0500
10V10%1UF
X6S-CERMX6S-CERM0402
Place on bottom side of U0500
1UF10V10%
0402-2
4VX5R-CERM
20UF
NO STUFF
CRITICAL
Place near inductors on bottom side.
20%
0402-2
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side.NO STUFF
20%
0402-2
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side.NO STUFF
20%
0402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
0402-2
4VX5R-CERM
20UF
Place near U0500 on bottom side
NO STUFF
20%
0402-2
4VX5R-CERM
20UF
Place near U0500 on bottom side
20%
NO STUFF
0402-2
4VX5R-CERM
20UF
Place near U0500 on bottom side
20%
NO STUFF
0402-2
4VX5R-CERM
20UF20%
NO STUFFPlace near U0500 on bottom side
0402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
NO STUFF
20%
CRITICAL
0402-2
4VX5R-CERM
20UF
NO STUFF
CRITICAL
20%
0402-2
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20%
0402-2
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20%
0402-2
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20%
0402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20%
0402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
4VX5R-CERM
20UF
Place near inductors on bottom side.
20%
NO STUFF
CRITICAL
0402-20402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
20%
NO STUFF
CRITICAL
0402-2
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20%
0402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20%
0.01UF10%
X7R-CERM16V
0402
X6S-CERM
Place on bottom side of U0500
0402
10%10V
1UF1UF
X6S-CERM0402
Place on bottom side of U0500
10%10V
X6S-CERM0402
10%
Place on bottom side of U0500
10V
1UF1UF10V
0402
Place on bottom side of U0500
10%
X6S-CERM
1UF
X6S-CERM0402
Place on bottom side of U0500
10%10V
X6S-CERM0402
Place on bottom side of U0500
10%10V
1UF10V
0402
Place on bottom side of U0500
1UF
X6S-CERM
10%1UF
X6S-CERM0402
Place on bottom side of U0500
10V10%
0402
Place on bottom side of U100.
1UF
X6S-CERM10V10%
X6S-CERM0402
Place on bottom side of U0500
10%1UF10V
Place near U0500 on bottom side
20%10UF
0603X6S-CERM4V4V
20%
Place near U0500 on bottom side
10UF
0603X6S-CERMX6S-CERM
10UF20%4V
0603
Place near U0500 on bottom side
20%
Place near U0500 on bottom side
10UF
0603
4VX6S-CERM
20%
Place near U0500 on bottom side
10UF
0603X6S-CERM4V
20%
Place near U0500 on bottom side
10UF
X6S-CERM4V
06030603
20%
Place near U0500 on bottom side
10UF
X6S-CERM4V
Place near U0500 on bottom side
20%10UF
0603X6S-CERM4V
4V
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
X5R-CERM0402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
0402-2
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20%
0402-2X5R-CERM4V
0402-2
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20%
POLY-TANTD15T-ECGLT-COMBO2.0V
330UF-6MOHM
CRITICAL
20%
D15T-ECGLT-COMBO
CRITICAL
2.0V20%330UF-6MOHM
POLY-TANT
0402
Place on bottom side of U0500
10%10VX6S-CERM
1UF
0402
Place on bottom side of U0500
1UF
X6S-CERM10V10%
0402
Place on bottom side of U0500
1UF10V10%
X6S-CERM0402
Place on bottom side of U0500
10%10VX6S-CERM
1UF
X6S-CERM0402
Place on bottom side of U0500
10%10V
1UF
0402
Place on bottom side of U0500
1UF
X6S-CERM10V10%
0402
Place on bottom side of U0500
X6S-CERM
10%10V
1UF1UF10%10V
0402
Place on bottom side of U0500
X6S-CERMX6S-CERM0402
Place on bottom side of U0500
10%10V
1UF
X6S-CERM0402
Place on bottom side of U0500
10%10V
1UF
0402-2
20%20UF
X5R-CERM4V
CRITICAL
Place near inductors on bottom side.
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A1
0402-2
20%20UF4V
Place near inductors on bottom side.
CRITICAL
X5R-CERM0402-2
4V
Place near inductors on bottom side.
X5R-CERM
20%20UF
CRITICAL
0402-2
20%
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
20UF
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A2
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A2
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
0402-2
20%20UF
X5R-CERM4V
CRITICAL
Place near inductors on bottom side. NO STUFF
0402-2
20%20UF
X5R-CERM4V
CRITICAL
Place near inductors on bottom side.ACAPS:A2
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A1
0402-2
20%20UF
X5R-CERM4V
CRITICAL
Place near inductors on bottom side.ACAPS:A2
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A2
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A1
0402-2
20%20UF
X5R-CERM4V
CRITICAL
Place near inductors on bottom side. ACAPS:A1
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A2
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A1
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
NO STUFF
0402-2
20%20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
NO STUFF
0402-2
20%20UF
X5R-CERM4V
CRITICAL
NO STUFF
0402-2
20UF
X5R-CERM4V20%
CRITICAL
Place near inductors on bottom side.ACAPS:A2
0402-2
20UF
X5R-CERM4V20%
CRITICAL
NO STUFFPlace near inductors on bottom side.
0402-2
20UF
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
20%
0402-2
20%
X5R-CERM4V
Place near inductors on bottom side.
CRITICAL
20UF
ACAPS:A1
2.5VPOLY-TANTCASE-B2S
CRITICAL
20%210UF
CRITICAL
2.5V
210UF
POLY-TANTCASE-B2S
20%
POLY-TANTCASE-B2S
210UF
CRITICAL
2.5V20%
POLY-TANT
20%2.5V
CASE-B2S
210UF
CRITICAL
POLY-TANT2.5V
CASE-B2S
210UF
CRITICAL
20%
POLY-TANT2.5V
210UF
CRITICAL
20%
CASE-B2S CASE-B2S
20%
POLY-TANT2.5V
210UF
CRITICAL
POLY-TANT
CRITICAL
210UF2.5V20%
CASE-B2S
CRITICAL
CASE-B2SPOLY-TANT
20%2.5V
NO STUFF
210UF
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
Place near inductors on bottom side.
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A2
0402-2
4VX5R-CERM
20UF20%
CRITICAL
0402-2
4VX5R-CERM
20UF
NO STUFF
CRITICAL
20%
0402-2
4VX5R-CERM
20UF
CRITICAL
NO STUFF
20%
0402-2
4V20%
X5R-CERM
20UF
CRITICAL
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A2
0402-2
4VX5R-CERM
20UF20%
ACAPS:A1
CRITICAL
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A1
0402-2
4VX5R-CERM
20UF20%
CRITICAL
ACAPS:A2
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A1
0402-2
4V
20UF
CRITICAL
20%
ACAPS:A1
X5R-CERM0402-2
4VX5R-CERM
20UF
NO STUFF
20%
CRITICAL
0402-2
4V
20UF20%
CRITICAL
ACAPS:A2
X5R-CERM0402-2
4VX5R-CERM
20UF20%
CRITICAL
NO STUFF
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A2
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
0402-2
4VX5R-CERM
20UF20%
CRITICAL
NO STUFF
0402-2
20%
CRITICAL
20UF
X5R-CERM4V
0402-2
4VX5R-CERM
20UF20%
CRITICAL
ACAPS:A1
0402-2
4VX5R-CERM
20UF20%
CRITICAL
NO STUFF
0402-2
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A1
0402-2
4VX5R-CERM
NO STUFF
CRITICAL
20%20UF
CRITICAL
330UF-9MOHM
D15T-1
2.5VPOLY-TANT
20%
NO STUFF
SYNC_MASTER=CLEAN_J15 SYNC_DATE=05/02/2013
CPU Decoupling
=PP1V5R1V35_S0_CPU
PPVCCIO_S0_CPU
=PPVCC_S0_CPU
C10091
2
C10081
2
C10071
2
C10311
2
C10061
2
C10051
2
C10041
2
C10031
2
C10021
2
C10011
2
C10001
2
C10301
2
C10291
2
C10271
2
C10261
2
C10201
2
C10211
2
C10221
2
C10231
2
C10251
2
C10241
2
C10281
2
C10321
2
C10331
2
C10391
2
C10381
2
C10371
2
C10361
2
C10351
2
C10341
2
C10791
2
C10891
2
C10881
2
C10871
2
C10861
2
C10851
2
C10841
2
C10831
2
C10821
2
C10811
2
C10801
2
C10931
2
C10921
2
C10911
2
C10901
2
C10971
2
C10961
2
C10951
2
C10941
2
C10431
2
C10421
2
C10411
2
C10401
2
C10981
23
C10991
23
C10191
2
C10181
2
C10171
2
C10161
2
C10151
2
C10141
2
C10131
2
C10121
2
C10111
2
C10101
2
C10651
2
C10641
2
C10631
2
C10621
2
C10611
2
C10601
2
C10591
2
C10581
2
C10571
2
C10561
2
C10551
2
C10541
2
C10531
2
C10521
2
C10511
2
C10501
2
C10491
2
C10481
2
C10471
2
C10461
2
C10451
2
C10441
2
C10671
2
C10661
2
C10681
2
C10691
2
C10701
2
C10711
2
C10721
2
C10731
2
C10741
2
C10751
2
C10761
2
C103F1
2
C103E1
2
C103D1
2
C103C1
2
C103B1
2
C103A1
2
C102F1
2
C102E1
2
C101B1
2
C101A1
2
C109F1
2
C109E1
2
C109D1
2
C109C1
2
C109B1
2
C109A1
2
C102D1
2
C102C1
2
C102B1
2
C102A1
2
C101E1
2
C101D1
2
C101C1
2
C101F1
2
C10771
23
dvt
051-0675
6.0.0
10 OF 119
10 OF 94
6 8 21 81
5 6 8 18 57
6 8 81
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
HDA_SDI1
HDA_SDI2
TP25
TP22
HDA_DOCK_RST*/GPIO13
SATA_RXP0
SATA_RXP5/PERP2
SATA_RXN5/PERN2
TP8
SRTCRST*
RTCX1
RTCX2
HDA_BCLK
DOCKEN*/GPIO33
SATA_RCOMP
SATA_TXN0
SATA_TXP4/PETP1
SATA_TXP1
SATA_TXN4/PETN1
SATA_TXN1
SATA0GP/GPIO21
SATALED*
SPKR
JTAG_TDI
JTAG_TDO
JTAG_TMS
TP20
JTAG_TCK
INTRUDER*
HDA_SYNC
HDA_SDI3
HDA_SDO
SATA_RXP2
SATA_RXN2
SATA_TXN2
SATA_TXP2
SATA_RXN3
SATA_RXP3
SATA_TXN3
TP9
SATA_IREF
SATA1GP/GPIO19
SATA_TXP0
SATA_RXN1
SATA_RXP1
RTCRST*
INTVRMEN
SATA_RXN0
SATA_RXP4/PERP1
SATA_RXN4/PERN1
SATA_TXP3
SATA_TXP5/PETP2
SATA_TXN5/PETN2
HDA_SDI0
HDA_RST*
JTAG
(1 OF 11)
RTC
AZALIA SATA
CLOCKS
(2 OF 11)
PCIECLKRQ2*/GPIO20/SMI*
CLKOUT_33MHZ4
PCIECLKRQ5*/GPIO44
CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
PCIECLKRQ0*/GPIO73
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_PCIE_P6
CLKOUT_PCIE_N6
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
TP18
TP19
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ6*/GPIO45
CLKOUT_PCIE_P5
CLKOUT_PCIE_N5
PCIECLKRQ1*/GPIO18
CLKOUT_DPNS_N
CLKOUT_DPNS_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PEG_A_CLKRQ*/GPIO47
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_DP_P
CLKOUT_DP_N
CLKOUT_PCIE_P7
CLKOUT_PCIE_N7
XTAL25_OUT
XTAL25_IN
ICLK_IREF
DIFFCLK_BIASREF
CLKIN_GND_N
CLKIN_GND_P
CLKIN_DMI_P
CLKIN_DMI_N
CLKOUT_33MHZ2
CLKIN_SATA_P
CLKIN_SATA_N
CLKOUTFLEX0/GPIO64
CLKIN_33MHZLOOPBACK
CLKOUT_33MHZ0
CLKOUT_33MHZ1
CLKOUTFLEX2/GPIO66
CLKOUTFLEX1/GPIO65
CLKOUTFLEX3/GPIO67
CLKOUT_33MHZ3
REFCLK14IN
CLKIN_DOT96_P
CLKIN_DOT96_N
PCIECLKRQ3*/GPIO25
PEG_B_CLKRQ*/GPIO56
PCIECLKRQ4*/GPIO26
PCIECLKRQ7*/GPIO46
CLKOUT_PEG_B_P
CLKOUT_PEG_B_N
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
NCNC
NCNC
NCNCNC
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
If HDA = S0, must also ensure that signal cannot be high in S3.
(IPD)
(IPD-PLTRST#)
(IPU)
1.5V -> 1.1V
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPU-RSMRST#)
(IPU-RSMRST#)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
(IPU-PLTRST#)
(IPD)
(IPD)
Unused clock terminations for FCIM Mode
(IPD-boot)
(IPD-boot)
(IPU)
(IPD)
Unused
(if not combo w/SD Card)Reserved: Ethernet
SATA Port assignments:
PCIe:
Unused
Reserved: ODD
Primary HDD/SSD (SATA only)
Secondary HDD/SSD (SATA only)
NOTE: ENET pair only used if SD Card Reader is USB3.
(IPD)
(IPD-DOCKEN#?)
CLKOUT_PEG outputs can be used for those devices. If 2 or less devices are attached to PEG the while PCH-attached PCIe devices use the other set. PEG-attached (CPU) PCIe devices must use one set,NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.
19 87
51 88
MF201
5%1/20W
330K 1M
MF201
5%1/20W
20K
MF201
5%1/20W
20K
MF201
5%1/20W
1UF
X5R402
10%10V
1UF
X5R402
10%10V
PLACE_NEAR=U1100.AY5:2.54mm
7.5K
MF201
1%1/20W
11 82
18 83
18 83
18 83
18 83
1/16W1%
402MF-LF
340
MF201
1%1/20W
1K
19 87
18
18
33 88
33 88
36 88
18
36 88
11 34
11 35
11 28
6 86
6 86
6 86
6 86
19 88
11 82
28 88
28 88
4.7K2015% 1/20W MF
MF5% 1/20W 2014.7K
1/20W5% 201MF10K
1/20W5% 201MF10K
1/20W5% 201MF10K
1/20W5% 201MF10K
1/20W5% 201MF10K
1/20W5% 201MF10K
1/20W5% 201MF10K
5% 1/20W 201MF10K
10KMF 2015% 1/20W
10KMF 2015% 1/20W
5% 201MF10K
1/20W
10KMF 2015% 1/20W10KMF 2015% 1/20W
51 88
51 88
51 88
51 88
1/20W5% 201MF10K 1/20W5% 201MF10K
2011/20W5% MF10K 1/20W5% 201MF10K
1/20W5% 201MF10K 1/20W5% 201MF10K
1/20W5% 201MF10K
1/20W10K
MF 2015%
1/20W5% 201MF10K
FCBGAMOBILE
LYNXPOINT
OMIT_TABLE
FCBGA
OMIT_TABLE
LYNXPOINTMOBILE
6 86
6 86
84 86
84 86
331/20W5% 201MF
PLACE_NEAR=U1100.B25:1.27mm
MF33
1/20W5% 201PLACE_NEAR=U1100.A24:1.27mm
PLACE_NEAR=U1100.A22:1.27mm
33MF 2015% 1/20W
1/20W5% 201MF33
PLACE_NEAR=U1100.C24:1.27mm
19 88
19 88
19 88
84
84
84
84
84
84
18
7.5K
201
PLACE_NEAR=U1100.AN44:2.54mm 1%
MF1/20W
11 82
1/20W5% 201MF10K
34 88
34 88
11 82
84
84
84
84
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
PCH RTC/HDA/JTAG/SATA/CLK
ENET_CLKREQ_L
TP_PCIE_CLK100M_PEGBN
PCH_PEGCLKRQB_L_GPIO56
ENET_MEDIA_SENSE_RDIV
XDP_PCH_TCK
ENET_MEDIA_SENSE_RDIVDP_TBT_SEL
HDA_SDOUT
HDA_SDIN0
PCH_CLK96M_DOT_N
PCH_SPKRDP_TBT_SEL
PCH_SRTCRST_L
PCH_INTRUDER_L
HDA_SYNC_R
=PP1V5_S0_PCH_VCCVRM_BIAS
PCH_INTRUDER_LPCH_INTVRMEN_L
PCH_SRTCRST_L
RTC_RESET_L
=PPVRTC_G3_PCH
SYSCLK_CLK25M_SB
TP_HDA_SDIN3
TP_HDA_SDIN1
PCH_DIFFCLK_BIASREF
PCH_CLK14P3M_REFCLK
PCH_CLKIN_GNDNPCH_CLKIN_GNDP
PCH_CLK100M_SATA_P
TP_PCH_GPIO66_CLKOUTFLEX2TP_PCH_GPIO67_CLKOUTFLEX3
PCIE_CLK100M_PCH_NPCIE_CLK100M_PCH_P
DMI_CLK100M_CPU_N
TP_PCIE_CLK100M_ENETN
SYSCLK_CLK32K_RTC
HDA_BIT_CLK_R
HDA_RST_R_L
HDA_BIT_CLK
XDP_PCH_TMS
XDP_PCH_TDO
=PP1V5_S0_PCH_SATA
SSD_CLKREQ_L
TP_PCH_GPIO64_CLKOUTFLEX0
PCH_SATALED_L
ENETSD_CLKREQ_LAP_CLKREQ_L
PCH_CLKRQ5_L_GPIO44PEG_CLKREQ_LPCH_CLKRQ7_L_GPIO46
ENET_CLKREQ_L
HDA_SYNC
HDA_RST_L
PCH_INTVRMEN_L
RTC_RESET_L
PCH_SPKR
XDP_PCH_TDI
TP_PCH_GPIO65_CLKOUTFLEX1
PCH_CLK33M_PCIIN
SYSCLK_CLK25M_SB_R
PCH_CLK96M_DOT_PPCH_CLKRQ5_L_GPIO44
TP_PCIE_CLK100M_PE5N
TP_PCI_CLK33M_OUT3
PCH_CLKRQ7_L_GPIO46
TP_PCIE_CLK100M_SWNTP_PCIE_CLK100M_SWP
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_GPUN
TP_PCI_CLK33M_OUT2
TP_PCIE_CLK100M_GPUP
PCIE_CLK100M_SSD_PPCIE_CLK100M_SSD_N
PCIE_CLK100M_AP_NPCIE_CLK100M_AP_P
XDP_DD3_AP_CLKREQ_L
PCIE_CLK100M_CAMERA_NPCIE_CLK100M_CAMERA_P
CAMERA_CLKREQ_L
TBT_CLKREQ_L
PEG_CLKREQ_L
PCIE_CLK100M_TBT_NPCIE_CLK100M_TBT_P
ITPXDP_CLK100M_NITPXDP_CLK100M_P
LPC_CLK33M_SMC_RLPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIOUT
SATARDRVR_ENDP_AUXCH_ISOL_L
=PP1V5_S0_PCH_CLK
PCH_CLK100M_SATA_N
CPU_CLK135M_DPLLREF_PCPU_CLK135M_DPLLREF_N
CPU_CLK135M_DPLLSS_PCPU_CLK135M_DPLLSS_N
DMI_CLK100M_CPU_P
TP_PCIE_CLK100M_PEGBP
PCH_PEGCLKRQB_L_GPIO56
TP_PCIE_CLK100M_ENETP
CAMERA_CLKREQ_LTBT_CLKREQ_L
TP_HDA_SDIN2
HDA_SDOUT_R
TP_PCIE_ENET_R2D_CNTP_PCIE_ENET_R2D_CP
TP_SATA_F_D2RN
TP_PCIE_ENET_D2RPTP_PCIE_ENET_D2RN
TP_SATA_D_D2RN
TP_SATA_D_R2D_CP
TP_SATA_D_D2RPTP_SATA_D_R2D_CN
TP_SATA_F_R2D_CP
TP_SATA_F_D2RPTP_SATA_F_R2D_CN
XDP_DC0_DP_AUXCH_ISOL_LXDP_DC1_SATARDRVR_EN
TP_SATA_ODD_R2D_CPTP_SATA_ODD_R2D_CNTP_SATA_ODD_D2RPTP_SATA_ODD_D2RN
SATA_A_R2D_C_PSATA_A_R2D_C_NSATA_A_D2R_PSATA_A_D2R_N
SATA_B_D2R_NSATA_B_D2R_PSATA_B_R2D_C_NSATA_B_R2D_C_P
PCH_SATALED_L
PCH_SATA_RCOMP
SSD_CLKREQ_L
PCIE_CLK100M_ENETSD_NPCIE_CLK100M_ENETSD_P
XDP_DD2_ENETSD_CLKREQ_L
=PP3V3_SUS_PCH_GPIO=PP3V3_S0_PCH_GPIO
R11001
2
R11011
2
R11021
2
R11031
2
C11031
2
C1102 1
2
R11301
2
R11721 2
R11731
2R1177 1 2
R1178 1 2
R1134 1 2
R1142 1 2
R1169 1 2
R1144 1 2
R1145 1 2
R1147 1 2
R1114 2 1
R1115 1 2
R1143 1 2
R1133 1 2
R1179 1 2
R1146 1 2
R1148 1 2
R1191 1 2R1192 1 2
R1193 1 2R1194 1 2
R1195 1 2R1196 1 2
R1197 1 2
R1170 1 2R1171 1 2
U1100
B17
B25
C22
C24
L22
K22
G22
F22
A24
A22
A8
G10
AB3
AE2
AD3
AD1
D9
B5
B4
AT1
AU2
BD4
AY5
BC8
BC10
BB9
BC12
BD13
BC14
BE8
BE10
BD9
BE12
BB13
BE14
AW8
AV10
AY13
AR13
AV15
AP15
AY8
AW10
AW13
AT13
AW15
AR15
AP3
AL10
B9
AB6
C26
F8
BB2
BA2
U1100
D17
AY24
AW24
H33
G33
AR24
AT24
BE6
BC6
D44
E44
B42
F41
A40
AF39
AF40
AJ40
AJ39
AF35
AF36
AH43
AH45
Y43
AA44
AB43
AD43
AF43
AE44
AB40
AJ44
Y45
AA42
AB45
AD45
AF45
AE42
AB39
AJ42
AB35
AB36
Y39
Y38
C40
F38
F36
F39
AN44
AM45
AB1
AF1
AF3
T3
V3
AA2
AE4
Y3
AF6
U4
F45
AD38
AD39
AM43
AL44
R1110 1 2
R1113 1 2
R1111 1 2
R1112 1 2
R11902 1
R1176 1 2
11 OF 94
11 OF 119
6.0.0
051-0675
dvt
84
11
11 82
88
11
11 82
11 88
11 88
88
17
11 88
11 88
11 88
11
12 15 81
84
84
88
88
84
84
88
88
84
88
88
81
11 34
84
11
18
18 33
11
11 82
11
11 82
11 88
11
11
84
87
8811
84
84
11
84
84
84
82
20 84
82
18
18 82
81
88
84
11
84
11 35
11 28
84
19 88
84
84
84
84
84
84
84
84
84
84
84
84
11
87
12 13 14 81
12 14 20 29 81
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
DAC_IREF
VGA_IRTN
VGA_VSYNC
VGA_HSYNC
PIRQH*/GPIO5
PIRQG*/GPIO4
DDPC_AUXN
EDP_BKLTEN
EDP_VDDEN
GPIO54
GPIO51
GPIO55
GPIO53
DDPC_CTRLCLK
DDPB_CTRLDATA
DDPB_CTRLCLK
DDPC_CTRLDATA
EDP_BKLTCTL
PIRQF*/GPIO3
DDPC_HPD
DDPC_AUXP
DDPD_AUXP
DDPB_HPD
DDPD_HPD
PIRQE*/GPIO2
DDPD_CTRLDATA
DDPD_CTRLCLK
VGA_RED
PIRQA*
GPIO52
GPIO50
PIRQD*
PIRQC*
PIRQB*
PME*
PLTRST*
DDPB_AUXN
VGA_BLUE
VGA_GREEN
DDPB_AUXP
DDPD_AUXN
VGA_DDC_DATA
VGA_DDC_CLK
CRT
PCI
DISPLAY
(5 OF 11)
EDP
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
SYSTEM POWER
MANAGEMENT
(4 OF 11)
DMI
FDI
SUSACK*
RI*
DPWROK
BATLOW*/GPIO72
PWRBTN*
RSMRST*
DRAMPWROK
SLP_LAN*
SLP_A*
PWROK
SLP_SUS*
ACPRESENT/GPIO31
SLP_WLAN*/GPIO29
DSWVRMEN
SLP_S4*
DMI_TXN1
DMI_TXN3
DMI_TXN2
DMI_TXP1
DMI_TXP0
TP5
PMSYNCH
DMI_RXN0
TP15
TP16
TP13
TP17
DMI_RXN1
SYS_RESET*
FDI_RXP1
FDI_RXN1
FDI_RXP0
FDI_RXN0
APWROK
TP21
SUSWARN*/SUSPWRNACK/GPIO30
DMI_TXN0
FDI_RCOMP
DMI_TXP2
DMI_TXP3
DMI_IREF
TP12
DMI_RCOMP
TP7
WAKE*
SUS_STAT*/GPIO61
SUSCLK/GPIO62
SLP_S5*/GPIO63
DMI_RXP0
DMI_RXP3
DMI_RXP2
DMI_RXP1
TP10
SLP_S3*
CLKRUN*
SYS_PWROK
DMI_RXN2
FDI_IREF
FDI_INT
FDI_CSYNC
DMI_RXN3
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
NCNCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
OUT
OUT
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
VGA DAC Disabled per SB
Redundant to pull-up on audio page
Redundant to pull-up on audio page
(IPU-RSMRST#)
(IPD-PLTRST#)
(IPU)
(IPD-DeepSx)
(IPU-PWROK&PCIRST#)
(IPU)
(OD)
(IPD-PLTRST#)
(IPU)
(IPD-PLTRST#)
DG v1.0 (Table 12-18).
(IPD-DeepSx)
586
5 86
7.5K1%
PLACE_NEAR=U1100.AY17:12.7mm
MF1/20W
201
586
586
586
584 86
584 86
584 86
584 86
584 86
584 86
584 86
584 86
584 86
584 86
584 86
584 86
OMIT_TABLE
LYNXPOINTMOBILEFCBGA
330K
MF1/20W
201
5%
10K
MF1/20W
201
5%
12 65
100K
MF1/20W
201
5%
19 40 83 88
18 19 40 83 88
621 86
19 83 88
19 88
65 83 88
12 18 40 88
40 41
12 30 42
12 33 35 83 88
12 40 49 83
20 40 49 83
41
12 40 65
12 21 33 37 40 65 78 83
12 21 40 65 83
6 86
40 83 88
100KMF1/20W 2015%
1KMF1/20W 2015%
10KMF1/20W 2015%
100KMF1/20W 2015%
100KMF1/20W 2015%
100KMF1/20W 2015%
100KMF1/20W 2015%
100KMF1/20W 2015%
MOBILELYNXPOINT
FCBGA
OMIT_TABLE
12 82
12 82
84
5 86
1%7.5K
PLACE_NEAR=U1100.AR44:12.7mm
MF1/20W
201
10KMF1/20W 2015%
10KMF1/20W 2015%
10KMF1/20W 2015%
10KMF1/20W 2015%
10KNO STUFF
MF1/20W 2015%
10KMF1/20W 2015%
100KNO STUFF
MF1/20W 2015%
10KMF1/20W 2015%
100KMF1/20W 2015%10KMF1/20W 2015%
12 82
10KMF1/20W 2015%
12 82
12 29
12 82
18 20 21 83
5%0
0201
1/20WMF
12 82
12 82
10KMF1/20W 2015%
3.0KMF1/20W 2015%
42
12 82
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
PCH DMI/FDI/PM/GFX/PCI
=PP3V3_S0_PCH_GPIO
PM_SLP_S3_L
PM_SLP_S5_L
PM_SLP_SUS_L
PM_SYNC
=PP3V3_S5_PCH_GPIO
EDP_IG_PANEL_PWREDP_IG_BKL_ON
PM_SLP_SUS_L
PM_SLP_S4_L
PCIE_WAKE_L
AUD_I2C_INT_L
TBT_PWR_REQ_LAUD_IP_PERIPHERAL_DET
SDCONN_OC_L
BT_PWRRST_LAUD_IPHS_SWITCH_EN_PCHENET_LOW_PWR_PCH
PM_CLKRUN_L
PM_BATLOW_L
PM_PWRBTN_L
PCH_FDI_RCOMP
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PCH_STRP_TOPBLK_SWP_L
PM_PWRBTN_L
SMC_ADAPTER_EN
=PP3V3_S0_PCH_GPIO
TP_DP_IG_C_AUXCHP
TP_DP_IG_C_HPDTP_DP_IG_D_HPD
TBT_PWR_REQ_L
TP_DP_IG_C_DDC_DATA
=PP3V3_SUS_PCH_GPIO
PM_SYSRST_L
PM_RSMRST_L
PM_MEM_PWRGD
=PP1V5_S0_PCH_RCOMP
TP_DP_IG_B_AUXCHN
=PPVRTC_G3_PCH
PCH_DSWVRMEN
PM_DSW_PWRGD
TP_PCH_SLP_S0_L
PCH_RI_L
FDI_CSYNCFDI_INT
PM_SLP_S4_L
TP_PCH_STRP_BBS1
TP_DP_IG_B_DDC_DATATP_DP_IG_B_DDC_CLK
TP_DP_IG_C_DDC_CLK
TP_DP_IG_D_DDC_DATATP_DP_IG_D_DDC_CLK
TP_DP_IG_C_AUXCHNTP_DP_IG_D_AUXCHN
TP_DP_IG_B_AUXCHP
TP_DP_IG_D_AUXCHP
TP_DP_IG_B_HPD
AUD_IP_PERIPHERAL_DET
DMI_N2S_N<0>DMI_N2S_N<1>DMI_N2S_N<2>DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<2>DMI_N2S_P<1>
DMI_N2S_P<3>
DMI_S2N_N<0>
DMI_S2N_N<2>DMI_S2N_N<1>
DMI_S2N_N<3>
DMI_S2N_P<0>DMI_S2N_P<1>DMI_S2N_P<2>DMI_S2N_P<3>
PM_PCH_SYS_PWROK
PM_BATLOW_L
EDP_IG_BKL_PWM
EDP_IG_BKL_ON
EDP_IG_PANEL_PWR
PCI_INTB_LPCI_INTC_L
TP_PCH_SLP_LAN_L
PCIE_WAKE_L
PM_CLKRUN_L
TP_PCH_SLP_WLAN_L
PM_SLP_S3_L
TP_PM_SLP_A_L
TP_PCH_STRP_ESI_L
AUD_IPHS_SWITCH_EN_PCH
PCI_INTD_L
PCI_INTA_L
ENET_LOW_PWR_PCH
BT_PWRRST_L
PCH_DMI_RCOMP
PM_PCH_APWROK
PM_PCH_PWROK
PLT_RESET_L
TP_PCI_PME_L
AUD_I2C_INT_L
SDCONN_OC_L
PCH_SUSWARN_L
PCH_SUSACK_L
=PP1V5_S0_PCH_RCOMP
R12001
2
U1100
U40
H45
H43
R40
R39
K40
K43
K45
R35
R36
K38
J42
J44
N40
N38
H39
N36
K36
G36
A12
C10
B13
A10
C12
AL6
H20
L20
K17
M20
G17
F17
L15
M15
Y11
AD10
T45
M43
M45
U44
N42
U39
V45
N44
R12151
2
R12051
2
R12091
2
R1223 2 1
R1225 1 2
R1291 1 2
R1222 2 1
R1221 2 1
R1224 2 1
R1284 2 1
R1281 2 1
U1100
E6
AB7
K7
AN7
BE16
AY17
AW22
AR20
AP17
AV20
AY22
AP20
AR17
AW20
BD21
BE20
BD17
BE18
BB21
BC20
BB17
BC18
L13
H3
C8
AL39
AL40
AT45
AR44
AJ35
AL35
AJ36
AL36
AY3
K1
F10
N4
J2
F3
G5
H1
C6
Y7
F1
D2
U7
R6
Y6
J4
AD7
AM1
AW44
AW17
AU44
AV45
AV43
AU42
AB10
AY45
AV17
K3
R12101
2
R1261 1 2
R1263 1 2
R1262 1 2
R1260 1 2
R1233 1 2
R1231 1 2R1214 1 2
R1230 1 2
R1217 1 2
R1218 1 2
R1216 1 2
R12861
2
R1240 2 1
R1239 1 2
dvt
051-0675
6.0.0
12 OF 119
12 OF 94
11 12 14 20 29 81
12 21 40 65 83
12 40 65
14 81
12 82
12 82
12 65
12 21 33 37 40 65 78 83
12 33 35 83 88
12 82
12 29
12 82
12 82
12 82
12 82
12 82
12 40 49 83
12 30 42
12 18 40 88
11 12 14 20 29 81
82
82
82
11 13 14 81
12 13 81
82
11 15 81
88
82
82
82
82
84
82
84
82
84
12 13 81
BI
BI
BI
BI
IN
IN
OUT
IN
OUT
IN
BI
IN
OC1*/GPIO40
OC2*/GPIO41
OC5*/GPIO9
OC0*/GPIO59
OC3*/GPIO42
OC6*/GPIO10
OC4*/GPIO43
OC7*/GPIO14
USB2P6
USB2N6
USB2P5
USB2N7
USB2N5
USB2N13
USB2P0
USB2P4
USB2P10
USB2P2
USB2P3
USB2P8
PETN7
PETP6
PETN4
PETN3
PETN1_USB3TN3
PCIE_IREF
USB3TP6
USB3TN5
USB3TN1
PETN8
PETP8
PETN5
PCIE_RCOMP
USB3TN6
USB3TN2
USB3TP1
PETP7
PETN6
PETP1_USB3TP3
TP11
USB3TP5
USB3TP2
PETP5
TP6
USB2N0
USB2N4
USB2N10
PERN6
PERP3
PERP1_USB3RP3
PERP6
PERN5
PERN3
PERN1_USB3RN3
USB3RN5
USB3RN2
PERP5
USB3RP5
USB3RP2PERN7
PERP7
PERN4
PERN2_USB3RN4
PERP4
PERP2_USB3RP4
USB3RN6
USB3RN1
USB3RP6
USB3RP1
PERP8
PERN8
USB2N1
USB2N2
USB2N3
USB2N9
USB2P9
USB2N8
USB2P7
USB2N11
USB2P13
USB2P1
PETP4
USB2P11
PETP2_USB3TP4
PETN2_USB3TN4
PETP3
USB2N12
USB2P12
TP23
TP24
USBRBIAS*
USBRBIAS
(9 OF 11)
USB
PCI-E
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
SML0CLK
SML1ALERT*/PCHHOT*/GPIO74
LDRQ1*/GPIO23
LAD1
TP3
TP4
TP2
TP1
SPI_CS1*
SERIRQ
SPI_CS0*
SPI_IO2
SPI_IO3
SPI_CLK
SPI_CS2*
SPI_MISO
SPI_MOSI
LAD2
SML1DATA/GPIO75
CL_RST*
SML1CLK/GPIO58
LDRQ0*
TD_IREF
CL_CLK
CL_DATA
SMBALERT*/GPIO11
SMBCLK
SMBDATA
SML0ALERT*/GPIO60
LAD0
SML0DATA
LFRAME*
LAD3
SMBUS
LPC
(3 OF 11)
SPI
C-LINK
IN
BI
BI
OUT
BI
OUT
OUT
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
NCNC
NCNC
NCNC
NCNC
BI
BI
BI
BI
OUT
BI
IN
IN
OUT
OUT
BI
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Unused
PCIe Port Assignments:
(& Ethernet if combo)SD Card Reader
PCIe/USB3 Port Assignments:
USB3 Port Assignments:
SSD (Gumstick)
(PCIe-only)Or PCIe switch if TBT/SSD
Lane 1
Lane 0
(PCIe-only)
SSD (Gumstick)
Or PCIe switch if TBT/SSD
Or PCIe switch if TBT/SSD
Or PCIe switch if TBT/SSD
SSD (Gumstick)
SSD (Gumstick)
(PCIe-only)Lane 2
(PCIe-only)Lane 3
Camera
AirPort
(IPU/IPD)
(IPU/IPD)
(IPU)
(IPU)
(IPU-LDRQ1#?)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
(IPU)
(IPU)
Reserved: SD (HS)
Reserved: WiFi (HS)
Ext A (LS/FS/HS)
Ext C (LS/FS/HS)
USB Port Assignments:
Reserved: PSOC (Legacy Trackpad)
Unused
Unused
Unused
Ext D (LS/FS/HS)
Reserved: Camera
Ext A (SS)
Ext B (SS)
USB3 Port Assignments:
Ext D (SS)
IR
BT
Trackpad(IPD)
Ext C (SS)
Ext B (LS/FS/HS)
84
84
84
84
10KMF 2015% 1/20W
1/20W5% 201MF10K
5% 201MF1/20W10K
1/20W5% 201MF10K
5% 1/20W 201MF10K
1/20W5% 201MF10K
13 18
13 18
18
13 18
18
13 18
37 87
13 18
FCBGA
LYNXPOINTMOBILE
OMIT_TABLE
37 87
37 87
37 87
37 87
37 87
78 83 87
78 83 87
78 87
78 87
84
84
84
84
84
84
84
84
49 88
49 88
FCBGA
OMIT_TABLE
LYNXPOINTMOBILE
43 88
43 88
43 88
43 88
43 83 88
43 83 88
7.5K1%
MF201
1/20W
PLACE_NEAR=U1100.BD29:12.7mm
331/20W5% MF 201331/20W5% 201MF
MF1/20W33
5% 201
1/20W5%33
201MF
331/20W MF 2015%
13 20
13 40 49 83
10KMF 2015% 1/20W
40 49 79 83 88
40 49 79 83 88
40 49 79 83 88
40 49 79 83 88
40 49 79 83 88
1%
201
1/20WMF
8.2K
33 87
33 87
84
84
38 87
38 87
10KMF 2015% 1/20W
10KMF 2015% 1/20W
10KMF 2015% 1/20W
10KMF 2015% 1/20W10KMF 2015% 1/20W
49 88
49 88
13 49
13 49
18
1/20W5% 201MF10K
1KMF 2015% 1/20W
1KMF 2015% 1/20W
78 83 87
20
20
20
20
78 83 87
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
34 88
33 88
33 88
33 88
33 88
36 88
36 88
36 88
36 88
PLACE_NEAR=U1100.K24:11.4mm
22.6
MF201
1/20W1%
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
PCH PCI-E/USB
USB3RPCIE_SD_R2D_C_PUSB3RPCIE_SD_R2D_C_N
USB3RPCIE_SD_D2R_PUSB3RPCIE_SD_D2R_N
TP_USB3_SPARE_R2D_CNTP_USB3_SPARE_R2D_CP
TP_USB3_SPARE_D2RNTP_USB3_SPARE_D2RP
PCIE_CAMERA_D2R_N
PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_D2R_P
PCIE_CAMERA_R2D_C_N
PCIE_AP_R2D_C_PPCIE_AP_R2D_C_N
PCIE_AP_D2R_PPCIE_AP_D2R_N
PCIE_SSD_R2D_C_P<0>
PCIE_SSD_D2R_N<1>PCIE_SSD_D2R_P<1>
PCIE_SSD_R2D_C_P<1>PCIE_SSD_R2D_C_N<1>
PCIE_SSD_D2R_P<0>
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_N<2>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_D2R_P<2>
PCIE_SSD_R2D_C_N<3>PCIE_SSD_R2D_C_P<3>
PCIE_SSD_D2R_P<3>PCIE_SSD_D2R_N<3>
PCIE_SSD_R2D_C_P<2>
PCH_USB_RBIAS
LPC_AD_R<0>
SMBUS_PCH_DATA
SML_PCH_0_CLKSML_PCH_0_DATA
SML_PCH_1_CLKSML_PCH_1_DATA
PCH_SML0ALERT_L
SMBUS_PCH_CLK
PCH_SMBALERT_L
TP_CLINK_DATA
TP_CLINK_CLK
PCH_TD_IREF
TP_CLINK_RESET_L
SPI_MOSI_R
SPI_MISO
TP_SPI_CS2_L
SPI_CLK_R
SPI_IO<3>
SPI_IO<2>
SPI_CS0_R_L
LPC_SERIRQ
TP_SPI_CS1_L
TBT_PWR_EN_PCH
PCH_SML1ALERT_L
LPC_AD<0>
LPC_AD<2>LPC_AD<3>
LPC_AD<1>
LPC_FRAME_L
USB_EXTA_NUSB_EXTA_P
USB_EXTC_NUSB_EXTC_P
USB_EXTB_NUSB_EXTB_P
USB_EXTD_NUSB_EXTD_P
USB_BT_N
USB_IR_N
USB_BT_P
USB_TPAD_N
USB_IR_P
USB_TPAD_P
USB3_EXTA_D2R_PUSB3_EXTA_D2R_N
USB3_EXTA_R2D_C_N
USB3_EXTB_D2R_N
USB3_EXTA_R2D_C_P
USB3_EXTB_D2R_PUSB3_EXTB_R2D_C_N
USB3_EXTC_D2R_P
USB3_EXTC_R2D_C_P
USB3_EXTD_R2D_C_N
XDP_DA0_USB_EXTA_OC_LXDP_DA1_USB_EXTC_OC_L
XDP_DA3_CAMERA_PWR_ENXDP_DB0_USB_EXTB_OC_LXDP_DB1_USB_EXTD_OC_L
XDP_DB3_SDCONN_STATE_CHANGE_L
TP_USB_7P
TP_USB_WLANN
TP_USB_SDN
TP_USB_CAMERAN
TP_USB_4N
TP_USB_WLANP
TP_USB_SDP
TP_USB_4P
TP_USB_PSOCN
TP_USB_7N
TP_USB_PSOCP
TP_USB_6N
=PP1V5_S0_PCH_RCOMP
USB3_EXTD_D2R_NUSB3_EXTD_D2R_P
USB3_EXTD_R2D_C_P
XDP_DB2_SD_PWR_ENPCH_PCIE_RCOMP
TP_LPC_DREQ0_L
LPC_FRAME_R_L
LPC_AD_R<3>LPC_AD_R<2>LPC_AD_R<1>
USB3_EXTC_R2D_C_N
TP_USB_CAMERAP
TP_USB_6P
XDP_DA2_SSD_PWR_EN
USB3_EXTB_R2D_C_P
USB3_EXTC_D2R_N
PCH_SML1ALERT_LPCH_SML0ALERT_L
SPI_IO<2>SPI_IO<3>
PCH_SMBALERT_L
XDP_DB1_USB_EXTD_OC_LSD_PWR_EN
XDP_DB0_USB_EXTB_OC_L
SSD_PWR_EN
LPC_SERIRQ
TBT_PWR_EN_PCH
XDP_DA0_USB_EXTA_OC_LXDP_DA1_USB_EXTC_OC_L
=PP3V3_SUS_PCH_GPIO=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_S0_PCH
CAMERA_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE_L
=PP3V3_S3RS0_CAMPWREN=PP3V3_S3RS4_PCH_GPIO
R13701
2
R1367 2 1
R1368 1 2
R1361 1 2
R1362 1 2
R1360 1 2
R1369 1 2
U1100
P3
V1
U2
P1
M3
T1
N2
M1
BE30
BD29
AW31
AT31
AW33
AT33
AW36
AY38
AT40
AN38
AY31
AR31
AY33
AR33
AV36
AW38
AT39
AN39
BE32
BD33
BE34
BE36
BD37
BC38
BE40
BD42
BC32
BB33
BC34
BC36
BB37
BE38
BC40
BD41
BC30
L33
M33
BB29
B37
A38
B29
A28
G26
F24
A36
A34
B33
F31
K31
G29
A32
A30
D37
C38
D29
C28
F26
G24
C36
C34
D33
G31
L31
H29
C32
C30
AR26
AW26
AW29
AR29
AP26
AV26
AV29
AP29
BE24
BD25
BE26
BD27
BD23
BC24
BC26
BE28
K26
K24
U1100
AF11
AF10
AF7
A20
C20
A18
C18
D21
G20
B21
AL11
N7
R10
U11
N8
U8
R7
H6
K6
N11
AJ11
AJ7
AL7
AJ10
AJ4
AJ2
AH3
AH1
AY43
BA45
BC45
BE44
BE43
R13001
2
R1340 1 2
R1341 1 2
R1343 1 2R1342 1 2
R1344 1 2
R1350 1 2
R13801
2
R1355 1 2
R1354 1 2R1353 1 2
R1320 1 2
R1321 1 2
R1351 1 2
R1393 1 2R1392 1 2
dvt
051-0675
6.0.0
13 OF 119
13 OF 94
84
84
84
84
87
13
13
84
84
84
13
84
84
84
84
84
84
84
84
84
84
84
12 81
84
84
13
13
13 49
13 49
13
13 18
18 78 83
13 18
18 64
13 40 49 83
13 20
13 18
13 18
11 12 14 81
15 17 81
81
18 35
13 18
81
81
OUT
OUT
BI
IN
OUT
OUT
IN
BI
ININ
OUT
IN
OUT
GPIO24
GPIO57
GPIO27
TACH4/GPIO68
SCLOCK/GPIO22
THRMTRIP*
BMBUSY*/GPIO0
SLOAD/GPIO38
GPIO35/NMI*
GPIO34
SDATAOUT1/GPIO48
SDATAOUT0/GPIO39
SATA5GP/GPIO49
SATA3GP/GPIO37
GPIO28
GPIO15
SATA4GP/GPIO16
TACH0/GPIO17
VSS
GPIO8
PLTRST_PROC*
TP14
LAN_PHY_PWR_CTRL/GPIO12
TACH3/GPIO7
TACH2/GPIO6
TACH1/GPIO1
VSS
TACH7/GPIO71
TACH6/GPIO70
TACH5/GPIO69
PECI
PROCPWRGD
RCIN*
VSS
SATA2GP/GPIO36
CPU/MISC
(6 OF 11)
GPIO
OUT
OUT
BI
OUT
IN
OUT
BI
OUT
OUT
OUT
IN
IN
IN IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
NOTE: GPIO0 pull-up/down on project-specific page
NOTE: GPIO70 pull-up/down on project-specific page
Pull-up/down on chipset support page (depends on TBT controller)
Systems with chip-down memory should add pull-downs on another page and set straps per software.Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.
(IPU-Boot/SATA5GP?)
(IPU-Boot?)
(IPU-Boot?)
(IPU-Boot/SATA4GP?)
(IPU-DeepSx)
(IPU-RSMRST#)
(IPD)
Redwood Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.
(IPD-PLTRST#)
(IPD-PLTRST#)
6 18 86
21
14 49 83
14 82
14 20
18
14 20
14 49 83
6 41 86
RAMCFG3:H
10K
MF1/20W
201
5%10K
RAMCFG2:H
MF1/20W
201
5%
RAMCFG1:H
10K
MF1/20W
201
5%
RAMCFG0:H
10K
MF1/20W
201
5%
14 40
14 20
14 40
14 82
FCBGA
LYNXPOINTMOBILE
OMIT_TABLE
20KMF1/20W 2015%
100KMF1/20W 2015%
10KMF1/20W 2015%
10KMF1/20W 2015%
100KMF1/20W 2015%
10KMF1/20W 2015%
10KMF1/20W 2015%
100KMF1/20W 2015%
10KMF1/20W 2015%
10KMF1/20W 2015%
10KMF1/20W 2015%
29
18
10KMF1/20W 2015%
10KMF1/20W 2015%10KMF1/20W 2015%
43NO STUFF
MF1/20W201
5%
MF1/20W0201
05%
390MF
1/20W201
5%
6 41 86
14 82
20
18
14 82
6
10KMF1/20W 2015%10KMF1/20W 2015%
10KMF1/20W 2015%
14 82
10KMF1/20W 2015%
18
14 79 82
14 18
1K1/16WMF-LF402
NO STUFF
5%
18 20
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
PCH GPIO/MISC/NCTF
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAMCFG_SLOT
JTAG_ISP_TDO
=PP3V3_SUS_PCH_GPIO
XDP_DD0_SSD_PCIE_SEL_LMEM_VDD_SEL_1V5_L
LPCPLUS_GPIOJTAG_TBT_TMS_PCH
ODD_PWR_EN_LJTAG_ISP_TCK
JTAG_ISP_TDI
PCH_RCIN_L
=PP3V3_S5_PCH_GPIO
=PP3V3_S0_PCH_GPIO
SPIROM_USE_MLB
XDP_DD1_MLB_RAMCFG1
SD_SEL_PCIE_L_USB_H
JTAG_ISP_TDO
JTAG_ISP_TDI
SPIROM_USE_MLB
FW_PWR_EN_PCH
XDP_DC3_JTAG_ISP_TCK
XDP_DC2_ODD_PWR_EN_L
XDP_FC1_GPU_GOOD
XDP_DD0_SSD_PCIE_SEL_L
LPCPLUS_GPIO
MEM_VDD_SEL_1V5_L
XDP_FC0_HDD_PWR_EN
SMC_RUNTIME_SCI_L
DPMUX_UC_IRQ
FW_PME_L
PCH_RCIN_L
PCH_PROCPWRGD
PCH_PECI
PCH_A20GATE
CPU_RESET_L
PM_THRMTRIP_L
CPU_PWRGD
PM_THRMTRIP_L_R
CPU_PECI
MLB_RAMCFG0
MLB_RAMCFG3
=PP3V3_S0_PCH_GPIO
=PP1V05_S0_PCH_V_PROC_IO
PCH_A20GATE
FW_PME_L
SMC_RUNTIME_SCI_LDPMUX_UC_IRQ
WOL_EN
TBT_GO2SX_BIDIRSMC_WAKE_SCI_L
FW_PWR_EN_PCH
WOL_EN
=TBT_CIO_PLUG_EVENT_ISOL
ISOLATE_CPU_MEM_L
MLB_RAMCFG2
JTAG_TBT_TMS_PCH
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
TBT_POC_RESET_L
R14721
2
R14731
2
R14741
2
R14751
2
U1100AT8
AB11
Y10
R11
AD11
AN6
AP1
U12
Y1
K13
AY1
AU4
AV3
AT6
AT3
AK1
AN2
AK3
BB4
AM3
AN4
AT7
C14
F13
A14
G15
C16
D13
G13
H15
AV1
AN10
BE41
BE5
C45
A5
A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
N10
R1411 2 1
R1495 2 1
R1491 1 2R1492 1 2
R1493 1 2
R1494 1 2
R1484 1 2
R1490 1 2
R1496 1 2
R1485 1 2
R1412 2 1
R1498 2 1
R1450 1 2
R1455 1 2
R1470 1 2
R1440 1 2
R1456 1 2
R1486 1 2
R1499 1 2
R1413 2 1
R1489 1 2
R14571
2
14 OF 94
14 OF 119
6.0.0
051-0675
dvt
14 20
11 12 13 81
14 18
14 82
14 49 83
14 20
18
18 20
14 20
14 88
12 81
11 12 14 20 29 81
14 49 83
14 88
14
41 88
20
20
11 12 14 20 29 81
15 17 81
14
14 82
14 40
14 79 82
14 82
14 82
14 40
14 82
20
DCPSUS1
DCPSUSBYP
VCCADAC1_5
VSS
VCCVRM
VCCVRM
VCCVRM
VCCVRM
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCASW
VCC3_3
DCPSUS3
VCCSUS3_3
VCCADACBG3_3
VCC
CRT
USB3
CORE
PCIE/DMI
(7 OF 11)
FDI
HVCMOS
SATA
VCCMPHY
DCPSUS2
VCCUSBPLL
VCCSPI
DCPSST
VCCRTC
VSS
VCCVRM
VCCVRM
VCCIO
VCCCLK3_3
VCCCLK
VCCASW
VCC3_3
VCC3_3VCC3_3
VCC
VCC
V_PROC_IO
DCPRTC
VCCSUSHDA
VCCSUS3_3
VCCDSW3_3
VCCSUS3_3
VCCSUS3_3
VCCIO
VCCCLK
THERMAL
(8 OF 11)
GPIO/LPC
USB
HDA
RTC
CPU
SPI
CLK/MISC
NC
NCNC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Current data from LPT EDS (doc #486708, Rev 1.0).
??mA Max, ??mA Idle
??mA Max, ??mA Idle
VCCVRM: 183mA Max, 68mA Idle
VCCCLK: 306mA Max, 89mA Idle
VCCCLK: 306mA Max, 89mA Idle
VCCCLK: 306mA Max, 89mA Idle
VCCIO: 3629mA Max, 264mA Idle
VCC: 1.312 A Max, 130mA Idle
VCCCLK3_3: 55mA Max, 11mA Idle
VCCSUS3_3: 261mA Max, 6mA Idle
VCC3_3: 133mA Max, 3mA Idle
VCCASW: 670mA Max, 34mA Idle
Powered in DeepSx
VCCVRM: 183mA Max, 68mA Idle
VCCVRM: 183mA Max, 68mA Idle
VCCVRM: 183mA Max, 68mA Idle
VCCVRM: 183mA Max, 68mA Idle
VCCIO: 3629mA Max, 264mA Idle
VCCIO: 3629mA Max, 264mA Idle
NOTE: Pin name is VCC but really is 3.3V
??mA Max, ??mA Idle
VCC3_3: 133mA Max, 3mA Idle
VCCASW: 670mA Max, 34mA Idle
VCCSUS3_3: 261mA Max, 6mA Idle
4mA Max, 2mA Idle
22mA Max, 1mA Idle
VCCASW: 670mA Max, 34mA Idle
6uA Max (3.0V, room temperature)
VCC3_3: 133mA Max, 3mA Idle
15 mA Max, 1mA Idle
VCCSUS3_3: 261mA Max, 6mA Idle
VCCVRM: 183mA Max, 68mA Idle
VCCIO: 3629mA Max, 264mA Idle
VCC3_3: 133mA Max, 3mA Idle
DG v1.0 (Table 12-18).VGA DAC Disabled per SB
VCCSUS3_3: 261mA Max, 6mA Idle
10mA Max, 1mA Idle
20%10V
CERM402
0.1UF
BYPASS=U1100.A6:6.35mm
10%6.3VCERM402
1UF
BYPASS=U1100.A6:6.35mm
20%10V
CERM402
0.1UF
BYPASS=U1100.A6:6.35mm
OMIT_TABLE
LYNXPOINTMOBILE
CKPLUS_WAIVE=PwrTerm2Gnd
CKPLUS_WAIVE=PwrTerm2Gnd
FCBGA
MOBILEFCBGA
LYNXPOINT
OMIT_TABLE
402CERM
PLACE_NEAR=R1550.1:2.54mm
1UF6.3V10%
PLACE_NEAR=U1100.U14:2.54mm
201
5.11
1/20WMF-LF
1%
BYPASS=U1100.P14:6.35mm
0.1UF20%10VCERM402
BYPASS=U1100.AA14:6.35mm
10V20%
CERM402
0.1UF
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
PCH Power
=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PCH_VCCSUS_RTC
=PP1V05_S0_PCH_VCCIO_GPIO
=PP3V3_S5_PCH_VCCDSW
=PP1V05_S0M_PCH_VCCASW
=PP1V05_S0M_PCH_VCCASW
=PP1V5_S0_PCH_VCCVRM_THRM
=PP3V3_S0_PCH_VCC3_3_USB
PP1V05_S0_PCH_VCC_CLK_F
=PP1V5_S0_PCH_VCCVRM_CLK
=PP1V05_S0_PCH_VCCCLK_CLK135
PPVOUT_S5_PCH_DCPSUSBYP_RMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.05V
PPVOUT_S5_PCH_DCPSUSBYPMIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm
PPVOUT_S0_PCH_DCPSSTMIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm
=PP1V05_S0_PCH_VCCCLK_SSC100
=PP1V05_S0_PCH_VCCCLK_CLK100
=PP1V05_S0_PCH_VCCCLK_SSC
=PP3V3_S0_PCH_VCCCLK3_3
=PP3V3_S0_PCH_VCC3_3_THRM
=PP3V3_S0_PCH_VCC_FUSE
=PP1V05_S0_PCH_V_PROC_IO
PPVOUT_S0_PCH_DCPRTC
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_SUS_PCH_VCCSUS_USB
=PP1V05_S0M_PCH_VCCASW
=PP1V05_S0_PCH_VCC
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP1V05_S0_PCH_VCCIO
=PP1V5_S0_PCH_VCCVRM_USB3
=PP3V3_SUS_PCH_VCCSUS_USB3
=PPVRTC_G3_PCH
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP1V05_S0_PCH_VCCIO_FDI
=PP1V5_S0_PCH_VCCVRM_SATA
=PP1V5_S0_PCH_VCCVRM_PCIE
=PP1V5_S0_PCH_VCCVRM_FDI
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP1V05_S0_PCH_VCCIO_USB2
=PP1V05_S0_PCH_VCCUSBPLL
C1532 1
2
C15311
2
C1533 1
2
U1100
Y12
AJ26
AJ28
U14
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
Y26
AA24
R30
R32
AA26
AD20
AD22
AD24
AD26
AD28
P45
M31
Y18
Y20
Y22
AA18
U18
U20
U22
U24
V18
V20
V22
V24
AM22
AN34
AN35
AP22
AR22
AT22
AK18
AK20
AK22
AM18
AM20
AJ30
AJ32
AK26
AK28
AN11
BB44
BE22
P43
U1100
P14
P16
AA14
Y35
AJ12
AJ14
P18
P20
AP45
L24
AE14
AF12
AG14
AK30
AK32
L17
R18
Y32
AA30
AA32
AD34
L26
L29
M26
M29
U32
V32
AD35
AD36
AE30
AE32
AG30
AG32
A16
U30 U36
V28
V30
Y30
A6
AD12
K8
R20
R22
R24
R26
R28
U26
A26
U35
AF34
AW40
M24
C1550 1
2
R15501 2
C15901
2
C15801
2
dvt
051-0675
6.0.0
15 OF 119
15 OF 94
13 17 81
17 81
81
17 81
15 17 81
15 17 81
17
17 81
17
17
17 81
17 81
17 81
17 81
17 81
17 81
17 81
14 17 81
17 81
17 81
15 17 81
17 81
17 81
17 81
17
81
11 12 81
17 81
17 81
17
17
17
17 19 81
17 81
17 81
VSSVSS
VSS(10 OF 11)
VSSVSS
(11 OF 11)VSS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
FCBGA
LYNXPOINT
OMIT_TABLE
MOBILE
FCBGA
OMIT_TABLE
MOBILELYNXPOINT
PCH GroundsSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
U1100AL34
AL38
AN36
AN40
AN42
AN8
AP13
AP24
AP31
AP43
AR2
AK16
AL8
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38
D42
AV13
AM14
AV22
AV24
AV31
AV33
BB25
AV40
AV6
AW2
F43
AY10
AM24
AY15
AY20
AY26
AY29
AY7
B11
B15
K39
L2
L44
AM26
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
AM28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
AM30
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
AM32
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
AM16
Y40
Y8
U1100
AB8
AC2
AC44
AD14
AD16
AD18
AD30
AD32
AD40
AD6
AD8
AE16
AE28
AF38
AF8
AG16
AG2
AG26
AG28
AG44
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38
AJ6
AJ8
AK14
AK24
AK43
AK45
AL12
AL2
BC22
BB42
B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28
AA16
AA20
AA22
AA28
AA4
AB12
AB34
AB38
16 OF 94
16 OF 119
6.0.0
051-0675
dvt
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
(PCH 3.3V SUSPEND RTC PWR)
(PCH 3.3V SUSPEND USB PWR)
(PCH 3.3V FUSE PWR)
670mA Max, 34mA Idle
(PCH 3.3V/1.5V HDA PWR)
(PCH 3.3V DSW PWR)
PCH VCCIO BYPASS
PCH VCCDSW3_3 BYPASS
PCH VCCSUSHDA BYPASS(PCH 1.5V VCCVRM PWR)
PCH VCC3_3 BYPASS
(PCH 3.3V USB2 PWR)PCH VCC3_3 BYPASS
PCH VCC3_3 BYPASS
(PCH 3.3V CLK PWR)PCH VCCCLK3_3 BYPASS
PCH VCC3_3 BYPASS(PCH 3.3V HVCMOS PWR)
(PCH 3.3V GPIO/LPC PWR)
PCH VCCIO BYPASS(PCH 1.05V FDI PWR)
PCH VCCUSBPLL BYPASS
(PCH 1.05V CORE PWR)PCH VCC BYPASS
Not documented in EDS!
(PCH 1.05V USB2 PLL PWR)
(PCH 1.05V SSC PWR)PCH VCCCLK BYPASS
PCH VCCCLK BYPASS
(PCH 1.05V SSC100 PWR)
PCH VCCCLK BYPASS(PCH 1.05V DIFFCLK PWR)
PCH VCCCLK BYPASS
(PCH 1.05V CLK PLL PWR)PCH CLK VCC BYPASS
(PCH 1.05V DIFFCLK135 PWR)
(PCH 3.3V THERMAL PWR)
PCH VCCSPI BYPASS
(PCH 3.3V SUSPEND PWR)PCH VCCSUS3_3 BYPASS
(PCH 3.3V SPI PWR)
PCH VCCSUS3_3 BYPASS
PCH VCCSUS3_3 BYPASS
PCH VCCVRM BYPASS
PCH VCCIO BYPASS(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)
PCH VCCASW BYPASS(PCH 1.05V ME CORE PWR)
??mA Max, ??mA Idle
183mA Max, 68mA Idle
Current data from LPT EDS (doc #486708, Rev 1.0).
PCH VCC BYPASS
(PCH 1.05V USB2 PWR)
PCH V_PROC_IO BYPASS(PCH 1.05V CPU I/F PWR)
BYPASS=U1100.AG30:6.35mm
6.3VCERM402
1UF10%
BYPASS=U1100.AD35:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.AD34:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.AA30:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.AM18:6.35mm
1UF
CERM402
10%6.3V
1UF
CERM402
10%6.3V
PLACE_NEAR=U1100.V20:2.54mm
1UF
CERM402
10%6.3V
PLACE_NEAR=U1100.V20:2.54mm
6.3V22UF
20%
603X5R-CERM-1
PLACE_NEAR=U1100.V20:2.54mm
BYPASS=U1100.AE18:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.AK20:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.AD20:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.AG18:12.7mm
10UF
X5R603
20%6.3V
BYPASS=U1100.AA24:6.35mm
CERM402
1UF10%6.3V
BYPASS=U1100.AK22:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.AK18:6.35mm
6.3V10%
402CERM
1UF
BYPASS=U1100.AK18:12.7mm
6.3V20%
603X5R
10UF
BYPASS=U1100.AE30:6.35mm
6.3VCERM402
1UF10%
BYPASS=U1100.U35:6.35mm
6.3V
402CERM10%1UF
BYPASS=U1100.AN34:6.35mm
1UF
CERM402
10%6.3V
BYPASS=U1100.U30:6.35mm
0.1UF20%10V
402CERM
0.1UF
CERM
20%
402
10V
BYPASS=U1100.AJ12:6.35mm
BYPASS=U1100.AJ12:12.7mm
6.3V
402
1UF10%
CERM
BYPASS=U1100.AJ12:6.35mm
0.1UF20%
402CERM10V
BYPASS=U1100.U32:6.35mm
402CERM6.3V1UF10%
0.1UF20%
402CERM10V
BYPASS=U1100.R30:6.35mm
BYPASS=U1100.AE14:6.35mm
0.01UF
0402X7R-CERM
10%16V
0.1UF20%
CERM10V
402BYPASS=U1100.L24:6.35mm
0.1UF20%10V
402CERM
BYPASS=U1100.AK30:6.35mm
402CERM
1UF10%
6.3V
BYPASS=U1100.P18:6.35mm
BYPASS=U1100.AP45:6.35mm
1UF
X5R402
10%10V
NO STUFF
BYPASS=U1100.AP45:12.7mm
10UF
X5R603
20%6.3V
OMIT_TABLECRITICAL
4.7UH-170MA-0.321OHM
0603
MF-LF402
5%1/16W
1BYPASS=U1100.AF34:12.7mm
10UF
X5R603
20%6.3V
BYPASS=U1100.M29:6.35mm
CERM6.3V1UF10%
402402CERM6.3V1UF10%
BYPASS=U1100.L29:6.35mmBYPASS=U1100.L26:6.35mm
402CERM6.3V1UF10%
10V20%
CERM
0.1UF
402BYPASS=U1100.A16:6.35mm
0.1UF20%
BYPASS=U1100.R20:6.35mm402
10VCERM
1UF
CERM402
10%6.3V
BYPASS=U1100.AD12:6.35mm
BYPASS=U1100.K8:6.35mm
10%1UF6.3VCERM402
0.1UF20%10V
402CERM
BYPASS=U1100.R26:6.35mm
20%0.1UF
10V
402CERM
BYPASS=U1100.A26:6.35mm
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
PCH DECOUPLING
113S0022 1 RES,FF,0 OHM,(020OHM MAX),2A,0603 L1790
=PP3V3_SUS_PCH_VCCSUS_USB
=PP1V05_S0_PCH_V_PROC_IO
=PP3V3_S0_PCH_VCCCLK3_3
=PP1V05_S0_PCH_VCC_CLK
=PP1V05_S0_PCH_VCCIO_FDI
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S0_PCH_VCC_FUSE
=PP3V3_S0_PCH_VCC3_3_THRM
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP1V05_S0_PCH_VCCUSBPLL
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCC
=PP1V05_S0_PCH_VCCCLK_SSC100
=PP1V05_S0_PCH_VCCCLK_SSC
=PP1V05_S0_PCH_VCCCLK_CLK135
=PP1V05_S0_PCH_VCCCLK_CLK100
=PP3V3_S0_PCH_VCC3_3_USB
=PP3V3_S0_PCH_VCC3_3_GPIO=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PCH_VCCSUS_RTC
=PP1V05_S0M_PCH_VCCASW
PP1V05_S0_PCH_VCC_CLK_R
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MM
=PP1V5_S0_PCH_VCCVRM_USB3=PP1V5_S0_PCH_VCCVRM_PCIE=PP1V5_S0_PCH_VCCVRM_SATA=PP1V5_S0_PCH_VCCVRM_CLK=PP1V5_S0_PCH_VCCVRM_THRM
=PP1V5_S0_PCH_VCCVRM_FDI
=PP1V5_S0_PCH_VCCVRM
=PP1V5_S0_PCH_VCCVRM_BIAS
=PP1V05_S0_PCH_VCCIO_USB2
MIN_NECK_WIDTH=0.075 MM
PP1V05_S0_PCH_VCC_CLK_F
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 MM
C1777 1
2
C1778 1
2
C1780 1
2
C1782 1
2
C17641
2
C17521
2
C17511
2
C1750 1
2
C17581
2
C17631
2
C17571
2
C1755 1
2
C17561
2
C17621
2
C17611
2
C1760 1
2
C1776 1
2
C1770 1
2
C1772 1
2
C1774 1
2
C17871
2
C1785 1
2
C17861
2
C1723 1
2
C1726 1
2
C1728 1
2
C1730 1
2
C1732 1
2
C1734 1
2
C17911
2
C1790 1
2
L1790
1 2
R17901 2
C1740 1
2
C1722 1
2
C1721 1
2
C1720 1
2
C1700 1
2
C1704 1
2
C1702 1
2
C1708 1
2
C1706 1
2
C1710 1
2
17 OF 94
17 OF 119
6.0.0
051-0675
dvt
15 81
14 15 81
15 81
81
15 81
15 19 81
15 81
15 81
15 81
15 81
15 81
15 81
15 81
15 81
15 81
15 81
15 81
15 81
15 81 15 81
13 15 81
15 81
15 81
15
15
15
15
15
15
81
11
15 81
15
IN
OUT
IN
IN
IN
OUT
OUT IN
OUT
OUT
OUT
OUTIN
INOUT
OUT
OUT
IN
IN
IN
OUTIN
OUTIN
OUT IN
BI
BI
BI
BI
TP
TP
TP
TP
IN
OUT
OUT
G
D S
OUT
G
D S
NCNCGND
VCC
NCNC
YA
G
D SG
D S
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
OUT
NCNC
BI
IN
IN
IN
IN
IN
IN
IN
IN
TP
TP
TP
TP
TP
TP
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
BI
IN
OUT
IN
OUT
OUT
OUT
INOUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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8 7 6 5 4 3
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
ITPCLK/HOOK4
OBSFN_D1
OBSDATA_D1OBSDATA_D0
OBSDATA_C3
OBSDATA_C1
OBSFN_C0OBSFN_A1OBSFN_A0
OBSDATA_B1
OBSDATA_D2
XDP_PRESENT#
DBR#/HOOK7
OBSDATA_D3
ITPCLK#/HOOK5
RESET#/HOOK6VCC_OBS_CD
TMSTDITRSTnTDO
518S0847
PWRGD/HOOK0
OBSDATA_B2
HOOK3
HOOK1
HOOK2
SCLTCK1
SDA
CPU JTAG Isolation
Extra BPM Testpoints
VCC_OBS_AB
OBSDATA_B3
OBSDATA_B0
OBSDATA_A0OBSDATA_A1
OBSDATA_A2OBSDATA_A3
OBSFN_B0OBSFN_B1
R187x and R189x should be placed where
’Output’ PCH/XDP signals require pulls.
Unused PCH/XDP Signals
signal destination (to minimize stub).from PCH to J1850 and path to non-XDPsignal path needs to split between route
’Output’ non-XDP signals require pulls.
PCH/XDP Signal Isolation Notes:
Non-XDP Signals(All 10 R’s)PCH/XDP Signals
TDI and TMS are terminated in CPU.
TCK0
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
OBSFN_C1
OBSDATA_C2
OBSFN_D0
OBSDATA_C0
NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.
Merged (CPU/PCH) Micro2-XDP
20
11 82
201SHORT
OMIT
NONE NONENONE
201SHORT
NONE NONENONE
OMIT
201NONE
OMIT
NONE NONESHORT
13
201NONESHORT
NONE NONE
OMIT
11
11
11
201
OMIT
SHORTNONENONENONE
13 37
13 78 83
13
14 20
201SHORT
NONENONE NONE
OMIT
13 35 13
78 83 201NONE NONE NONE
SHORT
OMIT
13
201SHORT
OMIT
NONE NONE NONE11
11
14
11
11 33
13 64 13
1414
201SHORT
NONENONENONE
OMIT
14 34
13
13
14
14
TP-P6
TP-P6
TP-P6
TP-P6
6 18 83 86
6 18 83 86
6 83 86
5% 2011/20W MF51
XDP
PLACE_NEAR=U1100.AE2:28mm
5% 2011/20W MF
XDP51
PLACE_NEAR=U1100.AD3:28mm
5% 2011/20W MF
XDP51
PLACE_NEAR=U1100.AD1:28mm
5% 2011/20W MF
XDP51
PLACE_NEAR=U1100.AB3:28mm
PLACE_NEAR=J1800.55:28mm
CRITICALXDP
DMN5L06VK-7SOT-563
6 83 86 PLACE_NEAR=J1800.57:28mm
XDP
SOT-563DMN5L06VK-7
CRITICAL
5%
201
1/20WMF
330K
74LVC1G07GFSOT891
XDP
SOT-563DMN5L06VK-7
CRITICAL
PLACE_NEAR=J1800.51:28mm
CRITICALXDP
DMN5L06VK-7SOT-563
PLACE_NEAR=J1800.53:28mm
16V
0201X5R-CERM
0.1UF10%
19 40 65 83
5% 2011/20W MF51
XDP
PLACE_NEAR=U0500.M49:28mm
5% 2011/20W MF51
XDP
PLACE_NEAR=U0500.N54:28mm
6 86
6 86
6 86
6 86
6 86
6 86
6 86
6 86
6 86
5%150
402MF-LF1/16W
12 20 21 83
11 18 83
11 18 83
11 18 83
5% 2011/20W MFPLACE_NEAR=U0500.AG7:2.54mm
XDP1K
6 86
6 86
6 86
6 19 86
XDP
6.3VCERM-X5R0201
0.1UF10%
XDP
6.3VCERM-X5R0201
0.1UF10%
CRITICALXDP_CONN
DF40RC-60DP-0.4VM-ST-SM1
XDP
6.3VCERM-X5R
0201
0.1UF10%
683 86
683 86
686
686
686
683 86
686
686
686
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
686
686
686
686
686
686
XDP
6.3VCERM-X5R
0201
0.1UF10% 5%
1K
XDP
MF-LF402
1/16W
686
686
686
8
43
43
11 18 83
5% 2011/20W MFPLACE_NEAR=U0500.F50:2.54mm1K
XDP
5%0
02011/20W MF
XDP
PLACE_NEAR=U5000.J3:2.54mm
5%0
XDP
402MF-LF1/16W
614 86
12 40 88
12 19 40 83 88
618 83 86
5% 2011/20W MF51
XDP
PLACE_NEAR=U0500.M53:28mm
201
OMIT
NONENONENONESHORT
2014
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
CPU & PCH XDP
XDP_CPU_VCCST_PWRGDXDP_CPU_PWRBTN_L
XDP_SYS_PWROK
=SMBUS_XDP_SDA
XDP_CPU_TCK
=PP5V_S0_XDPJTAGISOL
CPU_PWRGD
=PP1V05_S0_CPU_JTAG
=PP1V05_S0_CPU_JTAG
XDP_PCH_TMS
XDP_CPU_TRST_L
XDP_CPU_TDO
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_PCH_TMS
XDP_PCH_TDO
XDP_PCH_TCK
XDP_PCH_TDI
XDP_CPU_TMS
XDP_JTAG_CPU_ISOL_L
=PP3V3_S5_XDPJTAGISOL
ALL_SYS_PWRGD
XDP_CPU_PRESENT_L
CPU_CFG<18>
CPU_CFG<12>CPU_CFG<13>
CPU_CFG<19>
CPU_PWR_DEBUG PLT_RESET_L
CPU_CFG<14>CPU_CFG<15>
XDP_DBRESET_L
CPU_CFG<1>
XDP_CPU_PREQ_L
CPU_CFG<0>
XDP_BPM_L<1>XDP_BPM_L<0>
CPU_CFG<4>CPU_CFG<5>
CPU_CFG<6>CPU_CFG<7>
XDP_PCH_TCK
CPU_CFG<3>
XDP_BPM_L<2>
XDP_BPM_L<6>
XDP_BPM_L<7>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
PM_PCH_SYS_PWROK
PM_PWRBTN_L
XDP_CPU_TCK
XDP_CPUPCH_TRST_LMAKE_BASE=TRUE
AP_CLKREQ_L
XDP_FC0_HDD_PWR_EN
XDP_DA1_USB_EXTC_OC_L
XDP_DB1_USB_EXTD_OC_L
XDP_FC1_GPU_GOOD
=SMBUS_XDP_SCL
XDP_CPU_PRDY_L
USB_EXTA_OC_L
CAMERA_PWR_ENSSD_PWR_EN
USB_EXTB_OC_L
SDCONN_STATE_CHANGE_LSD_PWR_EN
DP_AUXCH_ISOL_L
ODD_PWR_EN_LJTAG_ISP_TCKSSD_PCIE_SEL_L
XDP_DA0_USB_EXTA_OC_L
XDP_DA3_CAMERA_PWR_ENXDP_DA2_SSD_PWR_EN
XDP_DB0_USB_EXTB_OC_LXDP_DB2_SD_PWR_ENXDP_DB3_SDCONN_STATE_CHANGE_L
XDP_DC1_SATARDRVR_EN MAKE_BASE=TRUE
XDP_DC3_JTAG_ISP_TCKXDP_DC2_ODD_PWR_EN_L MAKE_BASE=TRUE
XDP_DD0_SSD_PCIE_SEL_L
ENETSD_CLKREQ_LMLB_RAMCFG1
SATARDRVR_EN
XDP_DD3_AP_CLKREQ_L
XDP_DD1_MLB_RAMCFG1 MAKE_BASE=TRUEXDP_DD2_ENETSD_CLKREQ_L MAKE_BASE=TRUE
XDP_DC0_DP_AUXCH_ISOL_L
=PP1V05_SUS_PCH_JTAG
XDP_PCH_TDI
XDP_TRST_LXDP_PCH_TDO
XDP_CPURST_L
PPVCCIO_S0_CPU
CPU_CFG<10>
CPU_CFG<9>
CPU_CFG<16>CPU_CFG<17>
CPU_CFG<2>
CPU_CFG<8>
CPU_CFG<11>
R1897 1 2R1896 1 2
R1872 1 2
R1875 1 2
R1890 1 2
R1893 1 2
R1894 1 2
R1879 1 2
R1895 1 2
TP18101
TP18111
TP18121
TP18131
R1861 2 1
R1860 2 1
R1862 2 1
R1866 2 1
Q1842
3
54
Q1842
6
21
R18451
2
U1845
2
3
1 5
6
4
Q1840
3
54
Q1840
6
21
C1845 1
2
R1820 1 2
R1823 2 1R18301
2
R1805 1 2
C18061
2
C18011
2
J1800
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
6162
6364
78
9
C1800 1
2
TP18021
TP18031
TP18041
TP18051
TP18061
TP18071
C1804 1
2
R18311
2
R1800 1 2
R1802 1 2
R1804 1 2
R1824 2 1
R1876 1 2
18 OF 119
18 OF 94
6.0.0
051-0675
dvt
81
18 81
18 81
618 83 86
618 83 86
11 18 83
11 18 83
11 18 83
81
618 83 86
81
11 18 83
5 6 8 10 57
IN
IN
OUT
OUT
IN
OUTIN
OUT
OUT
OUT
OUT
NCNC
IN
OUT
OUT
SD
G
S
D
G
OUT
OUT
OUTIN
IN
Y
A
B 08
Y
A
B 08
IN
32.768K
GND THRM
VOUT
X2
X1
25M_A
25M_B
25M_C
VIOE_25M_A
VIOE_25M_B
VIOE_25M_C
VG3HOT
NC
VDD
PAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PCH PWROK Generation
System RTC Power Source & 32kHz / 25MHz Clock Generator
NOTE: ALL_SYS_PWRGD must remain low until at
PCH Reset Button
WF: Do we need this?
least 5ms after all rails are valid.
PCH 33MHz Clocks
IPD = 9-50k
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
PCH ME Disable Strap
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.SMC controls strap enable to allow in-field control of strap setting.
For SB RTC Power
+V3.3A should be first
create VDD_RTC_OUT.internally ORed toVBAT and +V3.3A are
to reduce VBAT draw.available ~3.3V power
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell: VBAT (300-ohm & 10uF RC)No Coin-Cell: 3.42V G3Hot (no RC)
No bypass necessaryNo Coin-Cell: 3.3V S5Coin-Cell & No G3Hot: 3.3V S5
NOTE: 30 PPM crystal required
APN 197S0480
at least S4. Both issues to be complicates VDD_25M power, forcing 1.2V VDDIO. Redwood Ridge also edge on 25MHZ_B when powered fromNOTE: SLG3NB148A provides slow rising
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.
VDDIO_25M_B: Camera power rail for XTAL circuit.VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.
(SLG3NB148C). addressed in upcoming part
SB XTAL Power
GreenClk 25MHz Power
TBT XTAL PowerCamera XTAL Power
618 86
5%
0
MF-LF1/16W
402
XDP
PLACE_NEAR=U1100.E44:6.35mm
22
MF1/20W
201
5%
PLACE_NEAR=U1100.D44:6.35mm
22
MF1/20W
201
5%
11 88
49 83 88
40 88
11 88
11 88 22
PLACE_NEAR=U1100.A40:6.35mm
MF1/20W
201
5%
11 88
5%0
OMIT
1/16WMF-LF402
SILK_PART=SYS RESET
5%1/16W
402
4.7K
MF-LF
12 40 83 88
11 87
11 87
28 87
402CERM
10%6.3V
1UF
1UF
402-1
10V10%
X5R10V
402CERM
20%0.1UF 0.1UF
402CERM10V20%
402
1/16WMF-LF
1M
NO STUFF
5%
0.1UF20%10V
CERM402
1/16WMF-LF402
0
5%
0402
50VC0G-CERM
12PF
5%
C0G-CERM50V
12PF
0402
5%
40 41
1K
MF1/20W
201
5%
100K
MF1/20W
201
5%
11 88
36 87
SOT-563
DMN5L06VK-7
SOT-563DMN5L06VK-7
NO STUFF
MF0201
05%1/20W
12 88
12 83 88
1K
1/16WMF-LF402
5%
12 18 40 83 88 57
18 40 65 83
SOT833
PLACE_NEAR=U1100.AD7:7MM
CKPLUS_WAIVE=UNCONNECTED_PINS
CKPLUS_WAIVE=UNCONNECTED_PINS
74LVC2G08GT/S505
74LVC2G08GT/S505SOT833
2.0K1/16WMF-LF
402
5%
20%10VCERM402
0.1UF
BYPASS=U1950:5MM
29 30 40 41
MF1/20W
05%
0201
CRITICALTQFN
SLG3NB148CV
25.000MHZ-20PPM-12PF-85C3.2X2.5MM-SM
CRITICAL
Chipset SupportSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
=PP3V3_S0_SB_PM
=PP3V3_S0_SB_PM
PM_SYSRST_L
=PP3V42_G3H_PCHPWRGD
PM_PCH_PWROKMAKE_BASE=TRUE
XDP_DBRESET_L
PM_PCH_APWROK
PM_PCH_SYS_PWROKSYS_PWROK_RCPUVR_PGOOD
ALL_SYS_PWRGD
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
PCH_CLK33M_PCIIN
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIOUT
=PP5V_S0_PCH
=PP3V3R1V5_S0_PCH_VCCSUSHDA
HDA_SDOUT_R
SPI_DESCRIPTOR_OVERRIDE
SPI_DESCRIPTOR_OVERRIDE_L
SPI_DESCRIPTOR_OVERRIDE_LS5V
=PPVBAT_G3_SYSCLK
=PP3V3_S5_SYSCLK
=PPVRTC_G3_OUT
=PP3V3_S4_SYSCLK
=PPVDDIO_S0_SBCLK=PPVDDIO_S3RS0_CAMCLK=PPVDDIO_TBTLC_CLK
SYSCLK_CLK25M_X1
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_X2_R
SYSCLK_CLK25M_SBSYSCLK_CLK25M_CAMERASYSCLK_CLK25M_TBTSYSCLK_CLK25M_X2
SMC_DELAYED_PWRGD
PM_S0_PGOOD
R19961 2
R19561 2
R19551 2
R19591 2
R19971
2
R19951
2
C19101
2
C1902 1
2
C1920 1
2
C1922 1
2
R19061
2
C1924 1
2
R19051 2
C190512
C19061 2
R19211
2
R19201
2Q1920
3
54
Q1920 6
2 1
R19482
1
R19491 2U1950
5
6
4
8
3U1950
1
2
4
8
7
R19501
2
C19501
2
R19471
2
U1900
9
8
15
12
7 10
16
17
5 13
11
6
14
1
4
3
Y1905
24
13
dvt
051-0675
6.0.0
19 OF 119
19 OF 94
2
19 81
19 81
81
81
15 17 81
81
81
81
81
81
35
81
OUT
OUT
OUT
OUT
OUT
G
D S
G
D S
OUT
OUTIN
IN
IN OUT
OUT
IN
IN
OUT
OUT IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
GND
1Y
VCC
1A
3Y 3A
2A 2Y
Y
B
A
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN G
SYM_VER_1
D
S
OUT
IN
IN
08
Y1
Y2
GNDB2
VCC
A1B1A2
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
HDMI HPD pull-down
RR output is open-drain, no isolation necessary
TBTLC can be on when S0 is off, and vice-versa
Redwood Ridge JTAG Isolation
Redwood Ridge Support
Buffered
TBT_PWR_EN must be high for JTAG Programming
RAM Configuration Straps
GPIO Glitch Prevention
RIO SD Card Reader Support
GS3 Connector SupportDEVSLP not supported on LPT-H
PCH 33MHz Clock for DPMUX
Pull-up values TBD
To/From RR(Pull-ups on PCH page)
Unbuffered
Platform Reset ConnectionsLCD HPD Inverter(Pull-Up on CPU Page)
To/From PCH
U2060 supports I/O’s powered when VCC=0VIsolation ensures no leakage to RR or PCH
To/From PCH
From RIO Connector
Flexible I/O Aliases
Must pull signal correctly even if always USB or PCIeFlexible I/O Configuration Strap
SD Card Reader is always USB3 in this implementaton.
18
14
18
14
14
RAMCFG0:L
1K5%
1/20WMF201
1/20WMF
5%1K
RAMCFG1:L
201
1K5%
1/20WMF
RAMCFG2:L
201
RAMCFG3:L
1K5%
MF1/20W
201
DMN5L06VK-7SOT-563
SOT-563DMN5L06VK-7
10K
MF1/20W
5%
201
34
201
470K5%
1/20WMF
20 28 13
12 40 49 83
201MF
1/20W5%
10K
28 14
14
201
5%1/20W
MF
100K
13
13
13
13 78 83 88
78 83 88
78 83 88
78 83 88
14
14
14
28
201MF1/20W5%10K
28
28
201
10K5%1/20WMF
201MF
1/20W5%
10K
78 83
10%0.1UF
X5R-CERM16V
0201
201
100K5%
1/20WMF
78 79
CRITICAL
X2SONSN74AUP3G07DQER
CRITICAL
TC7SZ08FEAPESOT665
402
20%10V
CERM
0.1UF
7922
MF1/20W5%
201
PLACE_NEAR=U1100.B42:6.35MM
11 84
1/16WMF-LF402
5%
079
5%
402
100K1/16WMF-LF
CRITICAL
SC70-HFMC74VHC1G08
402
1/16WMF-LF
0
5%
0
1/16WMF-LF402
5%
MF-LF1/16W
0
402
5%
0
MF-LF1/16W
402
5%
10%0.1UF
0201CERM-X5R
6.3V
201
470K5%1/20WMF
12 18 21 83
0
1/16W5%
MF-LF402
5%
402
33
MF-LF1/16W
5%
402MF-LF1/16W
33
35
28
33
34
22
88
40
49 83
79 DMN32D2LFB4DFN1006H4-3
5
14 18
20 28
CRITICAL
74LVC2G08GT/S505
SOT833
16V
0201X5R-CERM
0.1UF10%
28
42
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
Project Chipset Support
SMC_PME_SDCONN_L
=PP3V3_S0_PCH_GPIO
DP_INT_IG_HPD
PLT_RESET_LMAKE_BASE=TRUE
DPMUX_LRESET_L
TBT_PCIE_RESET_L
CAM_PCIE_RESET_L
AP_RESET_L
SSD_RESET_LMAKE_BASE=TRUEPLT_RST_BUF_L
=PP3V3_S0_RSTBUF
LPC_PWRDWN_LTBT_PWR_EN_PCHJTAG_ISP_TCKTBT_PWR_EN JTAG_TBT_TCK
TBT_PWR_EN
MLB_RAMCFG0MLB_RAMCFG1MLB_RAMCFG2MLB_RAMCFG3
=PP3V3_S0_PCH_GPIO
SSD_DEVSLP
TP_PCI_CLK33M_OUT2
LPC_CLK33M_DPMUX_UC_RMAKE_BASE=TRUE
LPC_CLK33M_DPMUX_UC
MAKE_BASE=TRUETBT_CIO_PLUG_EVENT_L
HDMI_HPD
PP3V3_TBTLC
LPC_RESET_L
=PP3V3_S4_SMC
LPCPLUS_RESET_LMAKE_BASE=TRUE
PCA9557D_RESET_L
SMC_LRESET_L
DP_IG_A_HPD_L
SD_SEL_PCIE_L_USB_H
USB3RPCIE_SD_R2D_C_N
USB3RPCIE_SD_D2R_N
USB3RPCIE_SD_R2D_C_P
USB3_SD_R2D_C_NMAKE_BASE=TRUE
USB3_SD_D2R_PMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB3_SD_D2R_N
SMC_PME_SDCONN
=TBT_CIO_PLUG_EVENT_ISOL
JTAG_TBT_TDIJTAG_ISP_TDI
JTAG_TBT_TDOJTAG_ISP_TDO
JTAG_TBT_TMS_PCH
=PP3V3_S0_PCH_GPIO
JTAG_TBT_TMS
USB3RPCIE_SD_D2R_P
=PP3V3_S0_PCH_GPIO
USB3_SD_R2D_C_PMAKE_BASE=TRUE
SDCONN_STATE_CHANGE_L
=PP3V3_S3_SDBUF
RIO_SDCONN_STATE_CHANGE_L
Q2040
3
54
R20401
2
C2080 1
2
R20801
2
U2080
3
2
1
4
5
R20911 2
R20871 2
R20881 2
R20851 2
C2030 1
2
R20411
2
R20711 2
R20811 2
R20831 2
Q2010
3
1
2
U20001
5
2
6
4
8
7
3
C20131
2
R20021
2
R20111
2
R20121
2
R20131
2
Q2040
6
21
R20701
2
R20751
2
R20301
2
R20631
2
R20621
2
R20611
2
C2060 1
2
R20101
2
U2060
1
3
6
48
7
5
2
U2030
2
1
3
5
4
R20571 2
R20721 2
dvt
051-0675
6.0.0
20 OF 119
20 OF 94
11 12 14 20 29 81
81
11 12 14 20 29 81
28 29 81
41 42 81
11 12 14 20 29 81
11 12 14 20 29 81
81
IN IN
IN
OUT
OUT
OUT
IN
IN
IN
G
D
S
OUT
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
S
D
G
SD
G
S D
G
S
D
G
S
D
G
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
Ensures CKE signals are held low in S3MEMVTT Clamp
S0
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
60mW max power
toS3toS0
75mA max load @ 0.75V
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
0 1 1 1 1 1 CPU_MEM_RESET_L 1 1 1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 0 1 3 0 0 0 1 X 1 0 0
4 0 0 1 1 X 1 0 1 5 0 1 1 1 0 (*) 1 1 1 6 0 1 1 1 1 1 1 1 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
MEM S0 "PGOOD" for CPU
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_LCPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN
14 12 40 65 83
12 18 20 83
402
100K
MF-LF
5%1/16W
CPUMEM:S0
82
CPUMEM:S0
5%1/16W
402MF-LF
10K
CPUMEM:S0
402MF-LF1/16W
5%100K
23 24 25 26
1K5%1/16WMF-LF402
CPUMEM:S0
64
402MF-LF
5%10K1/16W
CPUMEM:S012 33 37 40 65 78 83
100K5%
402
1/16WMF-LF
CPUMEM:S0
59 82
MF-LF1/16W
100K
402
5%
CPUMEM:S0
402CERM
20%0.001UF
50V
NO STUFF
1/10W
603MF-LF
5%10
CPUMEM:S0
CPUMEM:S3
MF-LF1/16W5%
0
402
6
MF-LF
1%1/16W
43.2K
402
402
27.4K1/16WMF-LF
1%
CRITICAL
DMB53D0UVSOT-563
402
1/16WMF-LF
10K5%
DMB53D0UVSOT-563
CRITICAL
6 12 86
0402X5R-CERM
10%0.047UF
10V
20%
402CERM10V
CPUMEM:S0
0.1UF
NO STUFF
10%0.047UF
X5R6.3V
201
CRITICALCPUMEM:S0
DMN5L06VK-7SOT-563
SOT-563
CRITICALCPUMEM:S0
DMN5L06VK-7
DMN5L06VK-7
CPUMEM:S0CRITICAL
SOT-563
DMN5L06VK-7
CPUMEM:S0CRITICAL
SOT-563
CPUMEM:S0CRITICAL
SOT-563DMN5L06VK-7
SOT-563DMN5L06VK-7
CPUMEM:S0CRITICAL
CPUMEM:S0CRITICAL
SOT-563
DMN5L06VK-7
SOT-563
CPUMEM:S0CRITICAL
DMN5L06VK-7SOT-563
DMN5L06VK-7
CRITICALCPUMEM:S0
SOT-563DMN5L06VK-7
CRITICALCPUMEM:S0
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
CPU Memory S3 Support
MEMPWR_DIV
CPUVDDQ_EN_L
=PP3V3_S3_MEMRESET
PM_SLP_S3_L
=PP5V_S3_MEMRESET
VTTCLAMP_EN
VTTCLAMP_L
=DDRVTT_EN
MEMRESET_ISOL_LS5V_L
MEM_RESET_L
ISOLATE_CPU_MEM_L
CPU_MEM_RESET_LMAKE_BASE=TRUE
PLT_RESET_L
MEMVTT_EN_L
MEMVTT_EN
CPUVDDQ_ENPM_MEM_PWRGD_L
PM_MEM_PWRGD=PP3V3_S5_CPU_VCCDDR
PM_SLP_S4_L
=PP1V5_S3_MEMRESET
=MEM_RESET_L
=PPVTT_S0_VTTCLAMP
=PP5V_S3_MEMRESET
=PP1V5R1V35_S0_CPU
R21021
2
R21101
2
R21151
2
R21161
2
R21051
2
R21011
2
R21511
2
C2151 1
2
R21501
2
R21171 2
R21211
2
R21201
2Q21205
3
4
R21221
2
Q21206
2
1
C2120 1
2
C21161
2
C2117 1
2
Q2100 3
5 4
Q2100 6
2 1
Q2105 6
2 1
Q21053
54
Q2110 6
2 1
Q21103
54
Q2115
6
21
Q2115
3
54
Q2150 3
5 4
Q2150 6
2 1
dvt
051-0675
6.0.0
21 OF 119
21 OF 94
81
21 81
22
81
81
81
21 81
6 8 10 81
OUT
V-
V+
V-
V+
IN
IN
IN
G
DSG
DSG
DSG
DS
IN
G
DSG
DSG
DSG
DS
IN
RESET*
A0A1A2
SCLSDA
P0P1P2
P5P6P7
P3P4
THRM
VCC
GNDPAD
NC
NC
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTASCL
SDA
A0
A1
GND
IN
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Q2225 pin 6:
NOTE: CPU has single output for
NOTE: DDR3 assumes TPS51916 supply with 10.0k/49.9k divider
2.575mV / step @ output
+36uA - -36uA (- = sourced)
1.199V - 1.801V (+/- 301mV)
1.200V - 1.800V (+/- 300mV)
NOTE: CPU DAC output step sizes:
3.923mV / step @ output
+28uA - -29uA (- = sourced)
0.950V - 1.750V (+/- 400mV)
0.932V - 1.760V (+/- 414mV)
1.343V (DAC: 0x68 = 1.341V)1.500V (DAC: 0x74 = 1.495V) DDR3L assumes TPS51916 supply with 19.6k/57.6k divider
- DDRVREF_DAC - Stuffs DAC margining circuit.
- =PPDDR_S3_MEMVREF
0.000V - 3.004V (0x00 - 0xE9)
0.299V - 1.206V (+/- 453mV)
0.275V - 1.075V (+/- 400mV)
0.675V (DAC: 0x34 = 0.670mV)
0.000V - 2.707V (0x00 - 0xD2)
5
D
MEM VREGMEM B VREF CAMEM A VREF CAMEM B VREF DQMEM A VREF DQ
DDR3 (1.5V)0.750V (DAC: 0x3A = 0.747mV)
0.300V - 1.200V (+/- 450mV)
0.000V - 1.354V (0x00 - 0x69)
0.269V - 1.083V (+/- 406mV)
+811uA - -816uA (- = sourced)
7.67mV / step @ output 7.68mV / step @ output
0.000V - 1.508V (0x00 - 0x75)
+901uA - -911uA (- = sourced)
Margined range:
DAC range:
DDR3L (1.35V)4
C
DDR3L (1.35V)3
C
2
B
DDR3 (1.5V)
A
1PCA9557D Pin:
DAC Channel:
Nominal value
Margined target:
Addr=0x30(WR)/0x31(RD)
RST* on ’platform reset’ so that system
NOTE: Margining will be disabled across all
and disables margining after platform reset.
DAC-Based Margining
ISOLATE_CPU_MEM_L is low DAC margining VREFCA ensure margining support. When
VREFCA. Split into two
soft-resets and sleep/wake cycles.
watchdog will disable margining.
Q2265 pin 6:
of margining option.
VRef DividersAlways used, regardless
Power aliases required by this page:
Signal aliases required by this page:
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SDA- =I2C_PCA9557D_SCL
- =I2C_VREFDACS_SCL
BOM options provided by this page:
EN RC’s to avoid drain glitches
(All 4 R’s)
DAC sets voltage level, PCA9557 & FETs enable outputs
FETs for CPU isolation during S3
NOTE: MEMVREG and FRAMEBUF share
- =PP3V3_S3_VREFMRGN
to remove short due to CPU.
signals for independent DAC
DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step
(OD)
Addr=0x98(WR)/0x99(RD)
both at the same time!
Pins B1 & B4:
Page Notes
DAC step size:
VRef current:
CPU-Based Margining
R22x6 pin 2:
a DAC output, cannot enable
59
DDRVREF_DAC
6.3VCERM-X5R
0201
0.1UF10%
1%
33.2K
1/16WMF-LF402
DDRVREF_DAC
DDRVREF_DAC
MF1/20W
100K5%
201
DDRVREF_DAC
MF1/20W
100K5%
201
DDRVREF_DACCRITICAL
UCSPMAX4253
CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins
MAX4253
CRITICALDDRVREF_DAC
UCSP
OMIT
NONENONE
NONE
402
SHORT
786
786
21
DMN5L06VK-7
CRITICAL
SOT-563
MF
100K
DDRVREF_DAC
1/20W5%
201
DMN5L06VK-7
CRITICAL
SOT-563
DMN5L06VK-7
CRITICAL
SOT-563
CRITICAL
DMN5L06VK-7SOT-563
7
PLACE_NEAR=Q2220.6:2.54mm
SOT-563
DDRVREF_DAC
DMN5L06VK-7
CRITICAL
MF1/20W
5%100K
DDRVREF_DAC
201
DDRVREF_DAC
100K
402
5%
MF-LF1/16W
402CERM10V20%
DDRVREF_DAC
0.1UF
DMN5L06VK-7
CRITICALDDRVREF_DAC
SOT-563
PLACE_NEAR=Q2260.6:2.54mm
DDRVREF_DAC
20%10V
CERM402
0.1UF
100K
402
5%
MF-LF1/16W
DDRVREF_DAC
100K
DDRVREF_DAC
402
5%
MF-LF1/16W
DMN5L06VK-7
CRITICALDDRVREF_DAC
SOT-563DDRVREF_DAC
402CERM10V20%
0.1UF
DMN5L06VK-7
CRITICALDDRVREF_DAC
SOT-563DDRVREF_DAC
20%10V
CERM402
0.1UF
DDRVREF_DAC
MF1/20W
5%100K
201
100K
5%
DDRVREF_DAC
402MF-LF1/16W
DDRVREF_DAC
MF1/20W
5%100K
201
1%332DDRVREF_DAC
1/16W 402MF-LFPLACE_NEAR=Q2225.1:2.54mm
1%332
DDRVREF_DAC
1/16W 402MF-LF PLACE_NEAR=Q2225.4:2.54mm
1%332
DDRVREF_DAC
1/16W 402MF-LFPLACE_NEAR=Q2265.1:2.54mm
1%332
DDRVREF_DAC
1/16W 402MF-LF
PLACE_NEAR=Q2265.4:2.54mm
1M
DDRVREF_DAC
402MF-LF1/16W5%
PLACE_NEAR=Q2260.3:2mm
0201X5R-CERM
10%6.3V
0.022UF
0201X5R-CERM
10%6.3V
PLACE_NEAR=Q2220.3:2mm
0.022UF
0201X5R-CERM
10%6.3V
PLACE_NEAR=Q2260.6:2mm
0.022UF
MF1/20W
2
5%
PLACE_NEAR=C2280.1:2mm
201
1/20W
24.9
1%
MF201
1K
402MF-LF1/16W
1%
PLACE_NEAR=R2281.2:1mm
2
5%
MF1/20W
PLACE_NEAR=C2260.1:2mm
201
24.9
1%1/20WMF201
MF-LF1/16W
402
1%1K
PLACE_NEAR=R2283.2:1mm
PLACE_NEAR=R2261.2:1mm
1K
MF-LF402
1/16W1%
24.9
1%1/20WMF201
1%1K
MF-LF1/16W
402PLACE_NEAR=R2263.2:1mm
PLACE_NEAR=R2241.2:1mm
1/16W1%
MF-LF402
1K
0201X5R-CERM
10%6.3V
PLACE_NEAR=Q2220.6:2mm
0.022UF
PLACE_NEAR=C2240.1:2mm
MF1/20W
2
5%
201
MF1/20W5%
2
PLACE_NEAR=C2220.1:2mm
201
24.9
1%1/20WMF201
1%1K
MF-LF1/16W
402PLACE_NEAR=R2243.2:1mm
PLACE_NEAR=R2221.2:1mm
MF-LF402
1/16W1%1K
MF-LF1/16W
402
1%1K
PLACE_NEAR=R2223.2:1mm
20
CRITICALDDRVREF_DAC
PCA9557QFN
43
43
MSOP
DAC5574
DDRVREF_DACCRITICAL
43
43
DDRVREF_DAC
6.3VCERM-X5R0201
0.1UF10%
DDRVREF_DAC
2.2UF
402-LFCERM
20%6.3V
DDRVREF_DAC
6.3VCERM-X5R
0201
0.1UF10%
SYNC_MASTER=CLEAN_J45
DDR3 VREF MARGININGSYNC_DATE=04/26/2013
CPU_MEM_VREFCA_B_ISOL
VREFMRGN_DQ_A_RDIV
VREFMRGN_CA_B_EN_RC
CPU_MEM_VREFDQ_B_ISOL
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPPVREF_S3_MEM_VREFCA_B
CPU_MEM_VREFDQ_A_ISOL
PPVREF_S3_MEM_VREFDQ_AMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm
VREFMRGN_MEMVREG_BUF
VREFMRGN_MEMVREG_EN
VREFMRGN_MEMVREG_FBVREF
VREFMRGN_DQ_A_EN
VREFMRGN_CA_AB
VREFMRGN_DQ_B
PCA9557D_RESET_L
VREFMRGN_DQ_B_RDIV
=PPDDR_S3_MEMVREF
MEM_VREFDQ_A_RC
MEM_VREFDQ_B_RC
CPU_MEM_VREFCA_A_ISOL
MEM_VREFCA_A_RC
MEM_VREFCA_B_RC
VREFMRGN_CA_B_EN
VREFMRGN_DQ_A_EN_RC
VREFMRGN_DQ_B_EN
VREFMRGN_DQ_B_EN_RC
VREFMRGN_CA_A_EN_RC
VREFMRGN_FRAMEBUF_BUF
DDRREG_FB
=PP3V3_S3_VREFMRGN
VREFMRGN_CA_B_RDIV
VREFMRGN_CA_A_RDIV
VREFMRGN_DQ_A
CPU_DIMMA_VREFDQ
MEMRESET_ISOL_LS5V_L
CPU_DIMM_VREFCA
CPU_DIMMB_VREFDQ
=I2C_PCA9557D_SDA=I2C_PCA9557D_SCL
=I2C_VREFDACS_SDA
=I2C_VREFDACS_SCL
VREFMRGN_FRAMEBUF_EN
VREFMRGN_CA_A_EN
=PP3V3_S3_VREFMRGN
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPPVREF_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm
PPVREF_S3_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3 mmPP3V3_S3_VREFMRGNMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
U2201
3
4
5
8
6
7
9
10
11
12
13
14
15
1
2
17
16C2202 1
2
U2200
9
10
3
6
7
8
1
2
4
5
C22011
2
C2200 1
2
C2205 1
2R22141 2
R22131
2
R22151
2
U2204
A3
A2
A1
A4
B1
B4
U2204
C3
C2
C1
C4
B1
B4
R22181 2
Q2260
6
21
R22021
2Q2220
3
54
Q2260
3
54
Q2220
6
21
Q2225
6
21
R22011
2
R22251 2
C2225 1
2
Q2265
6
21
C2245 1
2
R22451 2
R22651 2
Q2225
3
54
C2265 1
2
Q2265
3
54
C2285 1
2
R22071
2
R22851 2
R22081
2
R2226 1 2
R2246 1 2
R2266 1 2
R2286 1 2
R22171
2
C22801
2
C22601
2
C22401
2
R22831 2
R22801 2
R22821
2
R22631 2
R22601 2 R22811
2
R22621
2
R22401 2 R22611
2
R22421
2
C22201
2
R22431 2
R22231 2
R22201 2 R22411
2
R22221
2
R22211
2
dvt
6.0.0
22 OF 94
22 OF 119
051-0675
25 26 82 86
23 24 82 86 89
81
22 81
22 81
23 24 82 86 89
25 26 82 86
NCNCNC
NCNCNC
NC
NCNC
NC
NC NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NCNC NC
NC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQSVREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
20%10V
402
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
0201CERM-X5R6.3V10%0.1UF
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
MF1/20W1%240
201MF
2401%1/20W
201MF1/20W1%240
201
1%2401/20WMF201
CERM-X5R-14V20%
0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF20%4V
CERM-X5R-1201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%CERM-X5R-1
20%4V
0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%20%4V
CERM-X5R-1
0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
MF1/20W1%240
201
2401%1/20WMF201
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%CERM-X5R-1
4V20%
0.47UF
201
MF1/20W1%240
201
2401%1/20WMF201
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3V
0.1UF10%
0201CERM-X5R
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%20%
10V
402
2.2UF
X5R-CERM402
10V20%
2.2UF
X5R-CERM X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
2.2UF20%10V
402X5R-CERM
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
2.2UF
X5R-CERM402
10V20%
X5R-CERM
2.2UF20%10V
402
20%
X5R-CERM
2.2UF
402
10V
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF20%10V
402
2.2UF
X5R-CERM402
10V20%
2.2UF10V20%
402X5R-CERM
FBGA
OMIT_TABLE
DDR3-1333FBGA
DDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE OMIT_TABLE
FBGADDR3-1333
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGA
OMIT_TABLE
DDR3-1333
OMIT_TABLE
DDR3-1333FBGA
DDR3 SDRAM Bank A (1 OF 2)SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
PPVREF_S3_MEM_VREFDQ_APPVREF_S3_MEM_VREFCA_APPVREF_S3_MEM_VREFDQ_A
=PP1V5R1V35_S3_MEM_A
=PP1V5R1V35_S3_MEM_A
MEM_A_ZQ<5>
MEM_A_A<4>
PPVREF_S3_MEM_VREFDQ_APPVREF_S3_MEM_VREFCA_A
MEM_A_DQ<6>
MEM_A_A<11>
MEM_A_A<11>
MEM_A_DQS_N<5>
PPVREF_S3_MEM_VREFCA_APPVREF_S3_MEM_VREFDQ_A
MEM_A_DQ<50>MEM_A_DQ<51>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_N<0>MEM_A_CLK_P<0>
MEM_A_RAS_L
MEM_A_ZQ<7>
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_BA<0>MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<8>
MEM_A_A<6>MEM_A_A<7>
MEM_A_A<5>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<4>MEM_A_A<3>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<62>
MEM_A_DQS_N<7>
MEM_A_CKE<0>MEM_A_CS_L<0>
MEM_A_DQS_P<7>
MEM_A_DQ<63>
MEM_A_DQ<61>MEM_A_DQ<60>MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>MEM_A_DQ<56>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_DQS_P<6>
MEM_A_CLK_N<0>MEM_A_CLK_P<0>
MEM_A_RAS_L
MEM_A_ZQ<6>
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_BA<0>MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<8>
MEM_A_A<6>MEM_A_A<7>
MEM_A_A<5>
MEM_A_A<1>
MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<4>MEM_A_A<3>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<54>
MEM_A_DQS_N<6>
MEM_A_CKE<0>MEM_A_CS_L<0>
MEM_A_DQ<55>
MEM_A_DQ<53>MEM_A_DQ<52>
MEM_A_DQ<49>MEM_A_DQ<48>
MEM_A_A<2>
=PP1V5R1V35_S3_MEM_A
MEM_A_CLK_N<0>MEM_A_CLK_P<0>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_BA<0>MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<8>
MEM_A_A<6>MEM_A_A<7>
MEM_A_A<5>
MEM_A_A<1>
=PP1V5R1V35_S3_MEM_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<3>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<46>
MEM_A_CKE<0>MEM_A_CS_L<0>
MEM_A_DQS_P<5>
MEM_A_DQ<47>
MEM_A_DQ<45>MEM_A_DQ<44>MEM_A_DQ<43>MEM_A_DQ<42>MEM_A_DQ<41>MEM_A_DQ<40>
MEM_A_A<2>MEM_A_DQ<32>
MEM_A_CAS_L
MEM_A_DQ<37>
MEM_A_CLK_N<0>MEM_A_CLK_P<0>
MEM_A_RAS_L
MEM_A_ZQ<4>
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_BA<0>MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<8>
MEM_A_A<6>MEM_A_A<7>
MEM_A_A<5>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<4>MEM_A_A<3>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<38>
MEM_A_DQS_N<4>
MEM_A_CKE<0>MEM_A_CS_L<0>
MEM_A_DQS_P<4>
MEM_A_DQ<39>
MEM_A_DQ<36>MEM_A_DQ<35>MEM_A_DQ<34>MEM_A_DQ<33>
MEM_A_A<2>
MEM_A_CLK_P<0>
MEM_A_CKE<0>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_N<0>MEM_A_RAS_L
MEM_A_ZQ<3>
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_BA<0>MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<8>
MEM_A_A<6>MEM_A_A<7>
MEM_A_A<5>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<4>MEM_A_A<3>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<26>
MEM_A_DQS_N<3>
MEM_A_CS_L<0>
MEM_A_DQS_P<3>
MEM_A_DQ<29>
MEM_A_DQ<25>MEM_A_DQ<30>MEM_A_DQ<28>MEM_A_DQ<27>MEM_A_DQ<24>MEM_A_DQ<31>
MEM_A_A<2>MEM_A_A<3>
=PP1V5R1V35_S3_MEM_A
MEM_A_A<2>
MEM_A_A<4>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_N<0>MEM_A_CLK_P<0>
MEM_A_RAS_L
MEM_A_ZQ<2>
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_BA<0>MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<8>
MEM_A_A<6>MEM_A_A<7>
MEM_A_A<5>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<20>
MEM_A_DQS_N<2>
MEM_A_CKE<0>MEM_A_CS_L<0>
MEM_A_DQS_P<2>
MEM_A_DQ<19>
MEM_A_DQ<23>MEM_A_DQ<18>MEM_A_DQ<17>MEM_A_DQ<16>MEM_A_DQ<21>MEM_A_DQ<22>
MEM_A_A<7>
=PP1V5R1V35_S3_MEM_A
MEM_A_DQ<14>
MEM_A_CLK_P<0>
MEM_A_A<1>
MEM_A_DQ<9>
MEM_A_A<0>
MEM_A_DQ<7>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_N<0>MEM_A_RAS_L
MEM_A_ZQ<1>
MEM_A_WE_L
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_BA<0>MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<8>
MEM_A_A<6>MEM_A_A<5>
PPVREF_S3_MEM_VREFCA_A
MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<4>MEM_A_A<3>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<8>
MEM_A_DQS_N<1>
MEM_A_CKE<0>MEM_A_CS_L<0>
MEM_A_DQS_P<1>
MEM_A_DQ<12>
MEM_A_DQ<13>MEM_A_DQ<11>MEM_A_DQ<15>MEM_A_DQ<10>
MEM_A_A<2>
MEM_A_A<7>
=PP1V5R1V35_S3_MEM_A
MEM_A_DQS_P<0>
MEM_A_CKE<0>
MEM_A_DQS_N<0>
MEM_A_A<11>MEM_A_A<12>
MEM_A_A<2>MEM_A_DQ<0>
MEM_A_DQ<5>MEM_A_DQ<3>MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_CS_L<0>
MEM_A_DQ<2>
MEM_A_A<15>MEM_A_A<14>
MEM_A_BA<2>
MEM_A_A<3>MEM_A_A<4>
MEM_A_A<10>
MEM_A_A<13>
MEM_A_A<0>MEM_A_A<1>
MEM_A_A<5>MEM_A_A<6>
MEM_A_A<8>MEM_A_A<9>
MEM_RESET_L
MEM_A_BA<1>MEM_A_BA<0>
MEM_A_CAS_L
MEM_A_ODT<0>
MEM_A_WE_L
MEM_A_ZQ<0>
MEM_A_RAS_LMEM_A_CLK_P<0>MEM_A_CLK_N<0>
C2340 1
2
C2341 1
2
C23431
2
C23441
2
C23451
2
C23531
2
C23541
2
C23551
2
C23631
2
C23641
2
C23651
2
C23731
2
C23741
2
C23751
2
R23002
1
R23102
1
R23202
1
R23302
1
C2307 1
2
C23091
2
C2308 1
2
C23191
2
C2318 1
2
C2317 1
2
C23291
2
C2328 1
2
C2327 1
2
C23391
2
C2338 1
2
C2337 1
2
C23791
2
C2378 1
2
C2377 1
2
C23691
2
C2368 1
2
C2367 1
2
C23591
2
C2358 1
2
R23702
1
R23602
1
C2357 1
2
C23491
2
C2348 1
2
C2347 1
2
R23502
1
R23402
1
C23351
2
C23341
2
C23331
2
C23251
2
C23241
2
C23231
2
C23151
2
C23141
2
C23131
2
C23051
2
C23041
2
C23031
2
C2301 1
2
C2300 1
2
C2311 1
2
C2351 1
2
C2310 1
2
C2350 1
2
C2321 1
2
C2361 1
2
C2320 1
2
C2360 1
2
C2331 1
2
C2330 1
2
C2371 1
2
C2370 1
2
U2300K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2310K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2320K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2330K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2340K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2350K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2360K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2370K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
dvt
051-0675
6.0.0
23 OF 119
23 OF 94
22 23 24 82 86 89
22 23 24 82 86 89
22 23 24 82 86 89
23 24 81
23 24 81
723 24 27 89
22 23 24 82 86 89
22 23 24 82 86 89
7 24 89
72324 27
89
72324 27
89
7 24 89
22 23 24 82 86 89
22 23 24 82 86 89
7 24 89
7 24 89
22 23 24 82 86 89
7 23 27 89
7 23 27 89
72324 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 24 27 89
21 23 24 25 26
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
23 24 81
723 24 27 89
72324 27
89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
7 24 89
7 24 89
7 23 27 89
7 23 27 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
723 24 27 89
723 24 27 89
723 27 89
7232789
72324 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
23 24 81
723 27 89
7232789
72324 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
23 24 81
723 24 27 89
72324 27
89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
724 89
723 24 27 89
723 24 27 89
723 27 89
7232789
723 24 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
7 23 27 89
7 23 27 89
22 23 24 82 86 89
7 23 27 89
72324 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 24 27 89
21 23 24 25 26
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
23 24 81
723 24 27 89
72324 27
89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
7 24 89
7 24 89
7 23 27 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
7 24 89
723 24 27 89
723 24 27 89
23 24 81
723 24 27 89
723 24 27 89
22 23 24 82 86 89
723 27 89
7232789
72324 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
723 24 27 89
72324 27
89
72324 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
23 24 81
723 27
89
723 24 27 89
723 24 27 89
7 24 89
22 23 24 82 86 89
72324 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
23 24 81
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 27 89
723 24 27 89
723 24 27 89
723 27
89
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
NCNCNCNC
NCNCNC
NC
NCNC
NC
NC NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQSVREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
FBGA
OMIT_TABLE
DDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
2401%
MF1/20W
201MF1/20W1%240
201
1%
MF
2401/20W
201MF1/20W1%240
201
CERM-X5R-14V20%
0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%20%4V
CERM-X5R-1
0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%CERM-X5R-1
0.47UF20%4V
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
2401%1/20WMF201
MF1/20W1%240
201
20%4V
0.47UF
CERM-X5R-1201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%20%4V
CERM-X5R-1
0.47UF
201
2401%1/20WMF201
MF1/20W1%240
201
20%
402
2.2UF
X5R-CERM10V
402
10V20%
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
X5R-CERM
2.2UF20%10V
402
X5R-CERM402
10V20%
2.2UF
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF20%10V
402X5R-CERM
2.2UF
402
10V20%
2.2UF
X5R-CERM402
10V20%
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF20%10V
402X5R-CERM
2.2UF
402
10V20%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
DDR3-1333FBGA
OMIT_TABLE
DDR3-1333FBGA
OMIT_TABLE OMIT_TABLE
FBGADDR3-1333
FBGADDR3-1333
OMIT_TABLE
DDR3 SDRAM Bank A (2 OF 2)SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
MEM_A_A<10>
MEM_A_A<14>
PPVREF_S3_MEM_VREFCA_A
MEM_A_A<5>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_N<1>MEM_A_CLK_P<1>
MEM_A_RAS_L
MEM_A_ZQ<15>
MEM_A_WE_L
MEM_A_ODT<1>
MEM_A_CAS_L
MEM_A_BA<1>MEM_A_BA<0>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<7>
MEM_A_A<5>MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<3>MEM_A_A<4>
MEM_A_BA<2>
MEM_A_A<15>
MEM_A_DQ<61>
MEM_A_DQS_N<7>
MEM_A_CKE<1>MEM_A_CS_L<1>
MEM_A_DQS_P<7>
MEM_A_DQ<60>
MEM_A_DQ<62>MEM_A_DQ<63>MEM_A_DQ<58>MEM_A_DQ<59>MEM_A_DQ<56>MEM_A_DQ<57>
MEM_A_A<2>
MEM_A_DQ<43>
MEM_A_A<12>MEM_A_A<11>MEM_A_A<10>
MEM_A_DQS_N<5>
MEM_A_CLK_N<1>MEM_A_CLK_P<1>
MEM_A_RAS_L
MEM_A_ZQ<14>
MEM_A_WE_L
MEM_A_ODT<1>
MEM_A_CAS_L
MEM_A_BA<1>MEM_A_BA<0>
MEM_RESET_L
MEM_A_A<9>
MEM_A_A<6>
PPVREF_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
MEM_A_A<0>
MEM_A_A<13>
MEM_A_A<3>MEM_A_A<4>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<53>
MEM_A_DQS_N<6>
MEM_A_CKE<1>MEM_A_CS_L<1>
MEM_A_DQS_P<6>
MEM_A_DQ<52>
MEM_A_DQ<54>MEM_A_DQ<55>MEM_A_DQ<50>MEM_A_DQ<51>MEM_A_DQ<48>MEM_A_DQ<49>
MEM_A_A<2>
MEM_A_CLK_N<1>
MEM_A_DQS_N<4>
MEM_A_DQ<37>MEM_A_DQ<38>
MEM_A_ODT<1>
MEM_A_CLK_N<1>MEM_A_CLK_P<1>
MEM_A_RAS_LMEM_A_CAS_L
MEM_A_BA<1>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<7>
MEM_A_A<5>MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<1>MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<3>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<45>
MEM_A_CKE<1>MEM_A_CS_L<1>
MEM_A_DQS_P<5>
MEM_A_DQ<44>
MEM_A_DQ<47>MEM_A_DQ<42>
MEM_A_DQ<40>
MEM_A_A<2>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_P<1>MEM_A_RAS_L
MEM_A_ZQ<12>
MEM_A_WE_L
MEM_A_ODT<1>
MEM_A_CAS_L
MEM_A_BA<1>MEM_A_BA<0>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<7>
MEM_A_A<5>MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<3>MEM_A_A<4>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_CKE<1>MEM_A_CS_L<1>
MEM_A_DQS_P<4>
MEM_A_DQ<36>
MEM_A_DQ<39>MEM_A_DQ<34>MEM_A_DQ<35>MEM_A_DQ<32>MEM_A_DQ<33>
MEM_A_A<2>
MEM_A_WE_L
MEM_A_A<0>
MEM_A_CLK_N<1>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_P<1>MEM_A_RAS_L
MEM_A_ZQ<11>
MEM_A_WE_L
MEM_A_ODT<1>
MEM_A_CAS_L
MEM_A_BA<1>MEM_A_BA<0>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<7>
MEM_A_A<5>MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<3>MEM_A_A<4>
MEM_A_BA<2>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<25>
MEM_A_DQS_N<3>
MEM_A_CKE<1>MEM_A_CS_L<1>
MEM_A_DQS_P<3>
MEM_A_DQ<30>
MEM_A_DQ<26>MEM_A_DQ<29>MEM_A_DQ<27>MEM_A_DQ<28>MEM_A_DQ<31>MEM_A_DQ<24>
MEM_A_A<2>MEM_A_A<2>
MEM_A_A<6>
MEM_A_DQ<21>MEM_A_DQ<22>MEM_A_DQ<17>MEM_A_DQ<16>MEM_A_DQ<19>MEM_A_DQ<20>
MEM_A_DQ<18>
MEM_A_DQS_P<2>
MEM_A_CS_L<1>MEM_A_CKE<1>
MEM_A_DQS_N<2>
MEM_A_DQ<23>
MEM_A_A<15>MEM_A_A<14>
MEM_A_BA<2>
MEM_A_A<4>MEM_A_A<3>
MEM_A_A<10>
MEM_A_A<13>MEM_A_A<12>MEM_A_A<11>
=PP1V5R1V35_S3_MEM_A
PPVREF_S3_MEM_VREFCA_A
MEM_A_A<1>
MEM_A_A<8>MEM_A_A<5>
MEM_A_A<7>MEM_A_A<9>
MEM_RESET_L
MEM_A_BA<0>MEM_A_BA<1>
MEM_A_CAS_L
MEM_A_ODT<1>
MEM_A_WE_L
MEM_A_ZQ<10>
MEM_A_RAS_LMEM_A_CLK_P<1>MEM_A_CLK_N<1>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_DQ<10>
PPVREF_S3_MEM_VREFDQ_APPVREF_S3_MEM_VREFCA_A
MEM_A_DQ<13>
=PP1V5R1V35_S3_MEM_A
MEM_A_CS_L<1>
MEM_A_CLK_N<1>
MEM_A_A<15>
MEM_A_DQS_N<0>
MEM_A_CLK_N<1>MEM_A_CLK_P<1>
MEM_A_RAS_L
MEM_A_ZQ<9>
MEM_A_WE_L
MEM_A_ODT<1>
MEM_A_CAS_L
MEM_A_BA<1>MEM_A_BA<0>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<7>
MEM_A_A<5>MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<1>MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>
MEM_A_A<10>
MEM_A_A<3>MEM_A_A<4>
MEM_A_BA<2>
MEM_A_A<14>
MEM_A_DQS_N<1>
MEM_A_CKE<1>MEM_A_CS_L<1>
MEM_A_DQS_P<1>
MEM_A_DQ<11>
MEM_A_DQ<8>MEM_A_DQ<12>
MEM_A_DQ<15>MEM_A_DQ<14>MEM_A_DQ<9>
MEM_A_A<2>
=PP1V5R1V35_S3_MEM_A
MEM_A_A<15>
MEM_A_A<13>
PPVREF_S3_MEM_VREFDQ_A
MEM_A_CLK_P<1>MEM_A_RAS_L
MEM_A_ZQ<8>
MEM_A_ODT<1>
MEM_A_CAS_L
MEM_A_BA<1>MEM_A_BA<0>
MEM_RESET_L
MEM_A_A<9>MEM_A_A<7>
MEM_A_A<5>MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<1>
PPVREF_S3_MEM_VREFCA_A
MEM_A_A<0>
MEM_A_A<11>MEM_A_A<12>
MEM_A_A<10>
MEM_A_A<3>MEM_A_A<4>
MEM_A_BA<2>
MEM_A_A<14>
MEM_A_DQ<1>
MEM_A_CKE<1>
MEM_A_DQS_P<0>
MEM_A_DQ<3>
MEM_A_DQ<2>MEM_A_DQ<4>MEM_A_DQ<7>MEM_A_DQ<5>MEM_A_DQ<0>MEM_A_DQ<6>
MEM_A_A<2>
PPVREF_S3_MEM_VREFDQ_A PPVREF_S3_MEM_VREFDQ_A
MEM_A_DQ<41>MEM_A_A<4>
MEM_A_A<1>
MEM_A_A<8>MEM_A_A<7>MEM_A_DQ<46>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_ZQ<13>
=PP1V5R1V35_S3_MEM_A
=PP1V5R1V35_S3_MEM_A
R24002
1
R24102
1
R24202
1
R24302
1
C2407 1
2
C24091
2
C2408 1
2
C24191
2
C2418 1
2
C2417 1
2
C24291
2
C2428 1
2
C2427 1
2
C24391
2
C2438 1
2
C2437 1
2
C24791
2
C2478 1
2
C2477 1
2
C24691
2
C2468 1
2
C2467 1
2
C24591
2
C2458 1
2
R24702
1
R24602
1
C2457 1
2
C24491
2
C2448 1
2
C2447 1
2
R24502
1
R24402
1
C2440 1
2
C2400 1
2
C2441 1
2
C2401 1
2
C2450 1
2
C2410 1
2
C2451 1
2
C2411 1
2
C2460 1
2
C2461 1
2
C2420 1
2
C2421 1
2
C2470 1
2
C2471 1
2
C2430 1
2
C2431 1
2
C24431
2
C24441
2
C24031
2
C24041
2
C24451
2
C24531
2
C24051
2
C24131
2
C24541
2
C24141
2
C24551
2
C24631
2
C24151
2
C24231
2
C24641
2
C24651
2
C24241
2
C24251
2
C24731
2
C24331
2
C24741
2
C24341
2
C24751
2
C24351
2
U2400K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2410K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2420K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2430K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2440K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2450K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2460K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2470K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
dvt
051-0675
6.0.0
24 OF 119
24 OF 94
723 24 27 89
723 24 27 89
22 23 24 82 86 89
723 24 27 89
22 23 24 82 86 89
7 24 27 89
7 24 27 89
72324 27 89
723 24 27 89
724 27 89
723 24 27 89
723 24 27 89
723 24 27 89
21 23 24 25 26
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
23 24 81
723 24 27 89
72324 27 89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
7 23 89
7 23 89
7 24 27 89
7 24 27 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
723 24 27 89
7 23 89
72324 27
89
72324
27 89
723 24 27 89
723 89
724 27 89
7242789
72324 27 89
723 24 27 89
724 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
23 24 81
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
7 24 27 89
7 23 89
7 23 89
7 23 89
724 27 89
724 27 89
7242789
723 24 27 89
723 24 27 89
21 23 24 25 26
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27
89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27
89
723 24 27 89
723 24 27 89
7 23 89
723 24 27 89
22 23 24 82 86 89
724 27 89
723 24 27 89
723 24 27 89
724 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
23 24 81
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
7 24 27 89
723 89
7 23 89
723 24 27 89
723 24 27 89
723 24 27 89
7 24 27 89
22 23 24 82 86 89
7 24 27 89
72324 27 89
723 24 27 89
724 27 89
723 24 27 89
723 24 27 89
723 24 27 89
21 23 24 25 26
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
23 24 81
723 24 27 89
72324 27
89
72324 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
723 24 27 89
7 23 89
7 23 89
7 24 27 89
7 24 27 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
7 23 89
723 24 27 89 723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27
89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27
89
23 24 81
22 23 24 82 86 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
724 27 89
723 24 27 89
72324 27 89
724 27
89
22 23 24 82 86 89 22 23 24 82 86 89
22 23 24 82 86 89
23 24 81
7 24 27 89
7 24 27 89
723 24 27 89
7 23 89
724 27 89
723 24 27 89
724 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27
89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
72324 27 89
723 24 27 89
7 2389
723 24 27 89
23 24 81
723 24 27 89
723 24 27 89
22 23 24 82 86 89
724 27
89
723 24 27 89
724 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
22 23 24 82 86 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 24 27 89
723 89
723 24 27 89
22 23 24 82 86 89 22 23 24 82 86 89
723 24 27 89
723 24 27 89
723 24 27 89
23 24 81
23 24 81
NCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
NCNCNC
NC
NCNC
NC
NC NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQSVREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
FBGADDR3-1333
OMIT_TABLE OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
2401%1/20WMF201
MF1/20W1%240
201
1%2401/20WMF201
1/20W1%240
MF201
0.47UF4V20%
CERM-X5R-1201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%CERM-X5R-1
4V20%
0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
MF1/20W1%240
201
1%1/20W
240
MF201
0.47UF4V20%
CERM-X5R-1201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%20%4V
0.47UF
CERM-X5R-1201
MF1/20W1%240
201
2401%1/20WMF201
20%10V
402
2.2UF
X5R-CERM
402
10V20%
X5R-CERM
2.2UF
20%10V
402
2.2UF
X5R-CERM X5R-CERM
2.2UF
402
10V20%
20%10V
402
2.2UF
X5R-CERM X5R-CERM
2.2UF20%10V
402
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF20%10V
402X5R-CERM
2.2UF
402
10V20%
X5R-CERM
2.2UF
402
10V20%
2.2UF
X5R-CERM402
10V20%
2.2UF10V
X5R-CERM
20%
402X5R-CERM
2.2UF
402
10V20%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
DDR3 SDRAM Bank B (1 OF 2)SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_ZQ<6>
MEM_B_ZQ<2>
MEM_B_A<2>
MEM_B_A<6>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_RAS_L
MEM_B_ZQ<7>
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_BA<0>MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<8>
MEM_B_A<6>MEM_B_A<7>
MEM_B_A<5>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<62>
MEM_B_DQS_N<7>
MEM_B_CKE<0>MEM_B_CS_L<0>
MEM_B_DQS_P<7>
MEM_B_DQ<63>
MEM_B_DQ<61>MEM_B_DQ<60>MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<57>MEM_B_DQ<56>
MEM_B_A<2>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_RAS_L
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<8>MEM_B_A<7>
MEM_B_A<5>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<54>
MEM_B_DQS_N<6>
MEM_B_CKE<0>MEM_B_CS_L<0>
MEM_B_DQS_P<6>
MEM_B_DQ<55>
MEM_B_DQ<53>MEM_B_DQ<52>MEM_B_DQ<51>MEM_B_DQ<50>MEM_B_DQ<49>MEM_B_DQ<48>
PPVREF_S3_MEM_VREFCA_B
MEM_B_A<5>
MEM_B_DQ<32>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_RAS_L
MEM_B_ZQ<5>
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_BA<0>MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<8>
MEM_B_A<6>MEM_B_A<7>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<46>
MEM_B_DQS_N<5>
MEM_B_CKE<0>MEM_B_CS_L<0>
MEM_B_DQS_P<5>
MEM_B_DQ<47>
MEM_B_DQ<45>MEM_B_DQ<44>MEM_B_DQ<43>MEM_B_DQ<42>MEM_B_DQ<41>MEM_B_DQ<40>
MEM_B_A<2>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_RAS_L
MEM_B_ZQ<4>
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_BA<0>MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<8>
MEM_B_A<6>MEM_B_A<7>
MEM_B_A<5>
MEM_B_A<1>
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<38>
MEM_B_DQS_N<4>
MEM_B_CKE<0>MEM_B_CS_L<0>
MEM_B_DQS_P<4>
MEM_B_DQ<39>
MEM_B_DQ<37>MEM_B_DQ<36>MEM_B_DQ<35>MEM_B_DQ<34>MEM_B_DQ<33>
MEM_B_A<2>
MEM_B_WE_L MEM_B_WE_L
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_ODT<0>
MEM_B_WE_L
MEM_B_DQ<19>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_RAS_L
MEM_B_ZQ<3>
MEM_B_CAS_L
MEM_B_BA<0>MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<8>
MEM_B_A<6>MEM_B_A<7>
MEM_B_A<5>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<31>
MEM_B_DQS_N<3>
MEM_B_CKE<0>MEM_B_CS_L<0>
MEM_B_DQS_P<3>
MEM_B_DQ<24>
MEM_B_DQ<28>MEM_B_DQ<30>MEM_B_DQ<29>MEM_B_DQ<26>MEM_B_DQ<25>MEM_B_DQ<27>
MEM_B_A<2>
MEM_B_A<8>MEM_B_A<7>
MEM_B_DQ<20>
MEM_B_DQ<17>
MEM_B_A<5>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_RAS_L
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_BA<0>MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>
MEM_B_A<6>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<22>
MEM_B_DQS_N<2>
MEM_B_CKE<0>MEM_B_CS_L<0>
MEM_B_DQS_P<2>
MEM_B_DQ<21>MEM_B_DQ<23>MEM_B_DQ<16>
MEM_B_DQ<18>MEM_B_A<2>
MEM_B_DQ<11>MEM_B_DQ<3>
MEM_B_A<12>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_RAS_L
MEM_B_ZQ<1>
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_BA<0>MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<8>
MEM_B_A<6>MEM_B_A<7>
MEM_B_A<5>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>
MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<15>
MEM_B_DQS_N<1>
MEM_B_CKE<0>MEM_B_CS_L<0>
MEM_B_DQS_P<1>
MEM_B_DQ<8>
MEM_B_DQ<12>MEM_B_DQ<10>MEM_B_DQ<13>
MEM_B_DQ<9>MEM_B_DQ<14>
MEM_B_A<2>
=PP1V5R1V35_S3_MEM_B
MEM_B_DQ<2>MEM_B_DQ<4>
MEM_B_DQ<0>
MEM_B_CKE<0>
MEM_B_DQ<5>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<0>MEM_B_CLK_P<0>
MEM_B_RAS_L
MEM_B_ZQ<0>
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_BA<0>MEM_B_BA<1>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<8>
MEM_B_A<6>MEM_B_A<7>
MEM_B_A<5>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>MEM_B_A<3>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<7>
MEM_B_DQS_N<0>
MEM_B_CS_L<0>
MEM_B_DQS_P<0>
MEM_B_DQ<1>MEM_B_DQ<6>
MEM_B_A<2>
=PP1V5R1V35_S3_MEM_B
R25002
1
R25102
1
R25202
1
R25302
1
C2507 1
2
C25091
2
C2508 1
2
C25191
2
C2518 1
2
C2517 1
2
C25291
2
C2528 1
2
C2527 1
2
C25391
2
C2538 1
2
C2537 1
2
C25791
2
C2578 1
2
C2577 1
2
C25691
2
C2568 1
2
C2567 1
2
C25591
2
C2558 1
2
R25702
1
R25602
1
C2557 1
2
C25491
2
C2548 1
2
C2547 1
2
R25502
1
R25402
1
C2540 1
2
C2500 1
2
C2541 1
2
C2550 1
2
C2501 1
2
C2510 1
2
C2551 1
2
C2511 1
2
C2560 1
2
C2561 1
2
C2520 1
2
C2521 1
2
C2570 1
2
C2571 1
2
C2530 1
2
C2531 1
2
C25431
2
C25441
2
C25031
2
C25041
2
C25451
2
C25531
2
C25051
2
C25131
2
C25541
2
C25141
2
C25551
2
C25631
2
C25151
2
C25231
2
C25641
2
C25651
2
C25241
2
C25251
2
C25731
2
C25331
2
C25341
2
C25741
2
C25751
2
C25351
2
U2500K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2510K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2520K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2530K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2540K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2550K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2560K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2570K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
dvt
051-0675
6.0.0
25 OF 119
25 OF 94
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
7 25 27 89
7 25 27 89
72526 27 89
725 26 27 89
725 27 89
725 26 27 89
725 26 27 89
725 26 27 89
21 23 24 25 26
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
7 26 89
7 26 89
7 25 27 89
7 25 27 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
725 26 27 89
22 25 26 82 86
725 27 89
7252789
72526 27 89
725 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
89
72526 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
725 26 27 89
7 26 89
22 25 26 82 86
725 27 89
7252789
72526 27 89
725 26 27 89
725 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
725 27 89
7252789
725 26 27 89
725 26 27 89
725 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
25 26 81
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
7 25 27 89
7 25 27 89
725 27 89
725 26 27 89
7 26 89
22 25 26 82 86
7 25 27 89
7 25 27 89
725 26 27 89
725 26 27 89
725 26 27 89
21 23 24 25 26
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
7 26 89
7 26 89
7 25 27 89
7 25 27 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
7 26 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
72526 27 89
725 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
7 26 89
72526 27
89
22 25 26 82 86
725 27 89
7252789
72526 27 89
725 26 27 89
725 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526
27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
25 26 81
22 25 26 82 86
725 27 89
7252789
725 26 27 89
725 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
25 26 81
NCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
NCNCNC
NC
NCNC
NC
NC NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NC
NCNCNC
NC
NCNCNC
NC
NCNC
NC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQSVREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NCNCNCNC
A12/BC*
A13
VSS
RAS*
BA2
BA1
BA0
VSSQ
NF/DQ5
NF/DQ4
CS*
CKE
NF/TDQS*
DM/TDQS
DQS*
DQS
VREFDQ
NC
CK*
CK
ZQ
WE*
ODT
CAS*
RESET*
A9
A8
A6
A7
A5
A1
VREFCA
VDDQVDD
A0
A11
A10/AP
A4
A3
A14
NF/DQ6
NF/DQ7
DQ3
DQ2
DQ1
DQ0
NC
A2
A15
(SYM VER 2)
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
DDR3-1333FBGA
1/20W
2401%
MF201
MF1/20W1%240
201
2401%1/20WMF201
MF1/20W1%240
201
0.47UF4V20%
CERM-X5R-1201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF4V20%
CERM-X5R-1201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%CERM-X5R-1
4V20%
0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%4VCERM-X5R-1
20%0.47UF
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%
MF1/20W1%240
201
2401%1/20WMF201
0.47UF
CERM-X5R-14V20%
201
0.047UF6.3VX5R201
10%0.047UF
6.3VX5R201
10%CERM-X5R-1
4V20%
0.47UF
201
MF1/20W1%240
201
2401%1/20WMF201
X5R-CERM
2.2UF
402
10V20%
402X5R-CERM
2.2UF20%10V
X5R-CERM
2.2UF
402
10V20% 20%
10V
402
2.2UF
X5R-CERM
X5R-CERM
2.2UF
402
10V20%
402
10V20%
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
402
10V20%
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
20%10V
402
2.2UF
X5R-CERM
402
20%
X5R-CERM10V
2.2UF20%10V
402
2.2UF
X5R-CERM
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
OMIT_TABLE
FBGADDR3-1333
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
DDR3 SDRAM Bank B (2 OF 2)
PPVREF_S3_MEM_VREFCA_B
MEM_B_DQ<2>
=PP1V5R1V35_S3_MEM_B
MEM_B_DQ<51>
MEM_B_BA<2>MEM_B_CLK_P<1>MEM_B_CLK_N<1>
MEM_B_A<3>MEM_B_A<6>
MEM_B_A<1>
MEM_B_CKE<1>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<1>MEM_B_CLK_P<1>
MEM_B_RAS_L
MEM_B_ZQ<15>
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<7>
MEM_B_A<5>MEM_B_A<8>
MEM_B_A<6>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<3>MEM_B_A<4>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<61>
MEM_B_DQS_N<7>
MEM_B_CKE<1>MEM_B_CS_L<1>
MEM_B_DQS_P<7>
MEM_B_DQ<60>
MEM_B_DQ<62>MEM_B_DQ<63>MEM_B_DQ<58>MEM_B_DQ<59>MEM_B_DQ<56>MEM_B_DQ<57>
MEM_B_A<2>MEM_B_A<2>
MEM_B_DQ<47>
MEM_B_CS_L<1>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_RAS_L
MEM_B_ZQ<14>
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<7>
MEM_B_A<5>MEM_B_A<8>
PPVREF_S3_MEM_VREFCA_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<4>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<53>
MEM_B_DQS_N<6>MEM_B_DQS_P<6>
MEM_B_DQ<52>
MEM_B_DQ<54>MEM_B_DQ<55>MEM_B_DQ<50>
MEM_B_DQ<48>MEM_B_DQ<49>
MEM_RESET_L
MEM_B_A<5>
MEM_B_DQ<41>
=PP1V5R1V35_S3_MEM_B
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<1>MEM_B_CLK_P<1>
MEM_B_RAS_L
MEM_B_ZQ<13>
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<7>MEM_B_A<8>
MEM_B_A<6>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<3>MEM_B_A<4>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<45>
MEM_B_DQS_N<5>
MEM_B_CKE<1>MEM_B_CS_L<1>
MEM_B_DQS_P<5>
MEM_B_DQ<44>
MEM_B_DQ<46>
MEM_B_DQ<42>MEM_B_DQ<43>MEM_B_DQ<40>
MEM_B_A<2>
MEM_B_A<6>MEM_B_A<5>
MEM_B_A<4>MEM_B_A<3>
MEM_B_CLK_P<1>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<1>MEM_B_RAS_L
MEM_B_ZQ<12>
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_B_A<9>MEM_B_A<7>MEM_B_A<8>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<37>
MEM_B_DQS_N<4>
MEM_B_CKE<1>MEM_B_CS_L<1>
MEM_B_DQS_P<4>
MEM_B_DQ<36>
MEM_B_DQ<38>MEM_B_DQ<39>MEM_B_DQ<34>MEM_B_DQ<35>MEM_B_DQ<32>MEM_B_DQ<33>
MEM_B_A<2>
MEM_B_WE_L
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<1>MEM_B_CLK_P<1>
MEM_B_RAS_L
MEM_B_ZQ<11>
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<7>
MEM_B_A<5>MEM_B_A<8>
MEM_B_A<6>
MEM_B_A<1>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<3>MEM_B_A<4>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<28>
MEM_B_DQS_N<3>
MEM_B_CKE<1>MEM_B_CS_L<1>
MEM_B_DQS_P<3>
MEM_B_DQ<30>
MEM_B_DQ<31>MEM_B_DQ<24>MEM_B_DQ<26>MEM_B_DQ<29>MEM_B_DQ<27>MEM_B_DQ<25>
MEM_B_A<2>MEM_B_A<1>
MEM_B_A<8>MEM_B_DQ<19>
=PP1V5R1V35_S3_MEM_B
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<1>MEM_B_CLK_P<1>
MEM_B_RAS_L
MEM_B_ZQ<10>
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<7>
MEM_B_A<5>MEM_B_A<6>
PPVREF_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<3>MEM_B_A<4>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<21>
MEM_B_DQS_N<2>
MEM_B_CKE<1>MEM_B_CS_L<1>
MEM_B_DQS_P<2>
MEM_B_DQ<23>
MEM_B_DQ<22>MEM_B_DQ<17>
MEM_B_DQ<16>MEM_B_DQ<18>MEM_B_DQ<20>
MEM_B_A<2>MEM_B_A<2>MEM_B_A<1>MEM_B_A<0>
MEM_B_DQS_N<1>
MEM_B_DQ<12>
MEM_B_DQ<9>MEM_B_DQ<6>
MEM_B_DQ<3>
MEM_B_CKE<1>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<1>MEM_B_CLK_P<1>
MEM_B_RAS_L
MEM_B_ZQ<9>
MEM_B_WE_L
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<7>
MEM_B_A<5>MEM_B_A<8>
MEM_B_A<6>
PPVREF_S3_MEM_VREFCA_B
MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<3>MEM_B_A<4>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_CS_L<1>
MEM_B_DQS_P<1>
MEM_B_DQ<10>
MEM_B_DQ<15>MEM_B_DQ<8>MEM_B_DQ<11>MEM_B_DQ<13>MEM_B_DQ<14>
MEM_B_A<11>
MEM_B_CS_L<1>
PPVREF_S3_MEM_VREFDQ_B
MEM_B_CLK_N<1>MEM_B_CLK_P<1>
MEM_B_RAS_L
MEM_B_ZQ<8>
MEM_B_ODT<1>
MEM_B_CAS_L
MEM_B_BA<1>MEM_B_BA<0>
MEM_RESET_L
MEM_B_A<9>MEM_B_A<7>
MEM_B_A<5>MEM_B_A<8>
MEM_B_A<6>
MEM_B_A<1>
=PP1V5R1V35_S3_MEM_B
MEM_B_A<0>
MEM_B_A<12>MEM_B_A<13>
MEM_B_A<10>
MEM_B_A<3>MEM_B_A<4>
MEM_B_BA<2>
MEM_B_A<14>MEM_B_A<15>
MEM_B_DQ<4>
MEM_B_DQS_N<0>
MEM_B_CKE<1>
MEM_B_DQS_P<0>
MEM_B_DQ<7>MEM_B_DQ<0>
MEM_B_DQ<5>
MEM_B_DQ<1>MEM_B_A<2>
=PP1V5R1V35_S3_MEM_B
R26002
1
R26102
1
R26202
1
R26302
1
C2607 1
2
C26091
2
C2608 1
2
C26191
2
C2618 1
2
C2617 1
2
C26291
2
C2628 1
2
C2627 1
2
C26391
2
C2638 1
2
C2637 1
2
C26791
2
C2678 1
2
C2677 1
2
C26691
2
C2668 1
2
C2667 1
2
C26591
2
C2658 1
2
R26702
1
R26602
1
C2657 1
2
C26491
2
C2648 1
2
C2647 1
2
R26502
1
R26402
1
C2640 1
2
C2600 1
2
C2641 1
2
C2650 1
2
C2601 1
2
C2610 1
2
C2651 1
2
C2611 1
2
C2660 1
2
C2661 1
2
C2620 1
2
C2621 1
2
C2670 1
2
C2671 1
2
C2630 1
2
C2631 1
2
C26431
2
C26441
2
C26031
2
C26041
2
C26451
2
C26531
2
C26051
2
C26131
2
C26541
2
C26141
2
C26551
2
C26631
2
C26151
2
C26231
2
C26641
2
C26651
2
C26241
2
C26251
2
C26731
2
C26331
2
C26341
2
C26741
2
C26751
2
C26351
2
U2600K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2610K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2620K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2630K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2640K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2650K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2660K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
U2670K4
L8
H8
M8
K8
N4
N8
J8
L4
K3
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
G8
G10
H3
B8
B4
C8
C3
C9
C4
D4
A1
A4
A11
F2
F10
H2
H10N1N11
E4
E9
D3
E8
A8
G2
F4
N3
A3
A10
D8
G9
G3
K2
K10
M2
M10
B10
C2
E3
E10
J9
E2
A2
B2
L10
N10
J2
L2
N2
F3
A9
D9
F9
J10
B3
D2
B9
C10
D10
H4
H9
dvt
051-0675
6.0.0
26 OF 119
26 OF 94
22 25 26 82 86
7 25 89
25 26 81
7 25 89
72526 27
89
726 27 89
7 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
7 26 27 89
22 25 26 82 86
7 26 27 89
7 26 27 89
725 26 27 89
726 27 89
725 26 27 89
725 26 27 89
21 23 24 25 26
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
7 25 89
7 25 89
7 26 27 89
7 26 27 89
7 25 89
7 25 89
7 25 89
7 25 89
7 25 89
7 25 89
7 25 89
7 25 89
725 26 27 89 725 26 27 89
7 25 89
22 25 26 82 86
72526 27 89
725 26 27 89
726 27 89
725 26 27 89
725 26 27 89
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725 26 27 89
22 25 26 82 86
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72526 27
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72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
21 23 24 25 26
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25 26 81
22 25 26 82 86
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7262789
72526 27 89
725 26 27 89
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725 26 27 89
725 26 27 89
725 26 27 89
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725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
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72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
726 27
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22 25 26 82 86
725 26 27 89
725 26 27 89
726 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
7 26 27 89
7 26 27 89
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725 26 27 89
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725 26 27 89
725 26 27 89
725 26 27 89
21 23 24 25 26
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
89
72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
725 26 27 89
7 25 89
7 25 89
7 26 27 89
7 26 27 89
7 25 89
7 25 89
7 25 89
7 25 89
7 25 89
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725 26 27 89
725 26 27 89
25 26 81
22 25 26 82 86
726 27 89
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72526 27 89
725 26 27 89
726 27 89
725 26 27 89
725 26 27 89
725 26 27 89
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725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
25 26 81
725 26 27 89
72526 27
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72526 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
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725 26 27 89
725 26 27 89 725 26 27 89
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72526 27 89
725 26 27 89
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725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
22 25 26 82 86
72526 27
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72526 27 89
725 26 27 89
725 26 27 89
72526 27 89
725 26 27 89
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725 26 27 89
22 25 26 82 86
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725 26 27 89
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725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
725 26 27 89
25 26 81
IN
IN
IN
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IN
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IN
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IN
IN
IN
IN
IN
IN
IN
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IN
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Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
Place RC end termination after last DRAM
MEM Clock Termination
Place Source Cterm at neckdown at first DRAM
725 26 89
365% 4X02011/32W
4X02011/32W36
5%
365% 4X02011/32W
4X02015%36
1/32W
365% 1/32W 4X0201
5%36
1/32W 4X0201
5%36
1/32W 4X0201
201
0.47UF20%4VCERM-X5R-1
201
0.47UF
CERM-X5R-14V20%
201
0.47UF
CERM-X5R-14V20%
201
0.47UF
CERM-X5R-14V20%
361/32W 4X02015%
201CERM-X5R-1
0.47UF4V20%
201
0.47UF
CERM-X5R-14V20%
201
4V
0.47UF
CERM-X5R-1
20%
201
4VCERM-X5R-1
0.47UF20%
201
20%4VCERM-X5R-1
0.47UF
201PLACE_NEAR=U2600.F8:3.2mm
5%25V
CERM
3.3PF
201
5%
MF1/20W
30
201PLACE_NEAR=U2470.F8:3.2mm
5%3.3PF
25VCERM
5% 4X020136
1/32W
201
5%
MF1/20W
30
201
30
1/20WMF
5%
201MF
1/20W
30
5%
10%
0.1UF
0201CERM-X5R6.3V
10%
0.1UF
0201CERM-X5R6.3V
10%
0.1UF
0201CERM-X5R6.3V
10%
0.1UF
0201CERM-X5R6.3V
201
5%
MF1/20W
30
5% 1/32W 4X020136
201
30
1/20WMF
5%
201PLACE_NEAR=U2370.F8:3.2mm
5%25V
3.3PF
CERM
201
5%1/20WMF
30
201
5%
MF
30
1/20W
201PLACE_NEAR=U2500.F8:3.2mm CERM
25V5%
3.3PF
723 89
723 89
725 89
725 89
724 89
201
0.47UF
CERM-X5R-14V20%
724 89
726 89
726 89
365% 1/32W 4X0201
724 89
1/32W36
5% 4X0201723 24 89
5% 1/32W 4X020136725 26 89
364X02015% 1/32W
201
20%4VCERM-X5R-1
0.47UF
725 26 89
364X02011/32W5%
725 26 89
4X02011/32W5%36723 24 89
4X02011/32W5%36723 24 89
1/32W5%36
4X0201725 26 89
201
0.47UF
CERM-X5R-14V20%
364X02011/32W5%
726 89
725 26 89
725 26 89
725 26 89
725 89
725 89
725 26 89
725 26 89
725 26 89
726 89
726 89
725 26 89
725 26 89
725 26 89
725 89
725 26 89
725 26 89
725 26 89
725 26 89
723 24 89
723 24 89
723 89
723 89
723 24 89
725 26 89
723 24 89
723 24 89
723 24 89
723 24 89
723 24 89
365% 4X02011/32W
1/32W36
5% 4X0201
5% 4X020136
1/32W
5%36
1/32W 4X0201
5% 4X02011/32W36
725 26 89
5%36
1/32W 4X0201
4X02011/32W36
5%
5%36
1/32W 4X0201
4X02011/32W36
5%
4X02011/32W5%36
5%36
4X02011/32W
1/32W 4X02015%36
4X02011/32W36
5%
4X02011/32W5%36
361/32W5% 4X0201
725 26 89
1/32W 4X020136
5%
5% 1/32W 4X020136
201CERM-X5R-1
0.47UF4V20%
201CERM-X5R-1
20%4V
0.47UF
201
4V20%0.47UF
CERM-X5R-1
364X02011/32W5%
1/32W 4X02015%36
365% 1/32W 4X0201
4X020136
5% 1/32W
364X02015% 1/32W
725 26 89
365% 1/32W 4X0201
1/32W 4X02015%36
365% 4X02011/32W
1/32W 4X020136
5%
201
20%4VCERM-X5R-1
0.47UF
201
20%4VCERM-X5R-1
0.47UF
201
20%4VCERM-X5R-1
0.47UF
361/32W 4X02015%
723 24 89
723 24 89
365% 4X02011/32W
723 24 89
724 89
723 24 89
723 24 89
723 24 89
723 24 89
723 89
723 24 89
723 24 89
723 24 89
5%36
1/32W 4X0201
724 89
723 24 89
4X02015% 1/32W36
5% 1/32W36
4X0201
4X02015% 1/32W36
1/32W5%36
4X0201
365% 4X02011/32W
364X02015% 1/32W
364X02015% 1/32W
5% 1/32W 4X020136
DDR3 TerminationSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
MEM_A_A<13>MEM_A_A<14>
MEM_A_A<2>MEM_A_A<1>
=PPVTT_S0_MEM_A
MEM_A_A<11>MEM_A_A<9>
MEM_A_A<7>MEM_A_A<8>
MEM_A_A<3>MEM_A_A<12>
MEM_A_CS_L<1>MEM_A_A<15>
MEM_A_ODT<1>MEM_A_A<10>
MEM_A_RAS_LMEM_A_CKE<0>
MEM_A_A<4>MEM_A_A<6>
MEM_A_A<5>MEM_A_BA<1>
MEM_A_BA<2>MEM_A_WE_L
MEM_A_A<0>MEM_A_BA<0>
MEM_B_A<5>MEM_B_A<4>
MEM_B_BA<1>MEM_B_A<0>
MEM_B_CKE<1>MEM_B_ODT<1>
MEM_B_CAS_LMEM_B_A<15>
MEM_B_A<9>MEM_B_A<14>
=PPVTT_S0_MEM_B
MEM_B_A<7>MEM_B_A<6>
MEM_B_A<8>MEM_B_A<1>MEM_B_A<11>MEM_B_A<13>
MEM_A_CAS_LMEM_A_ODT<0>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_B_A<12>
MEM_B_CS_L<1>MEM_B_A<3>MEM_B_A<2>
MEM_B_WE_LMEM_B_CKE<0>
MEM_B_BA<0>
MEM_B_RAS_LMEM_B_ODT<0>
MEM_B_CS_L<0>MEM_B_BA<2>
MEM_B_A<10>
MEM_A_CLK0_TERM_R
MEM_A_CLK1_TERM_R
MEM_B_CLK0_TERM_R
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_A_CLK_N<1>
MEM_B_CLK1_TERM_RMEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_A_CLK_P<1> RP2730 3 6
RP2726 1 8
RP2730 1 8
RP2728 2 7
RP2730 2 7
RP2724 2 7
C27301
2
C27281
2
C27261
2
RP2720 1 8
RP2724 4 5
RP2730 4 5
RP2720 3 6
RP2720 2 7
RP2722 2 7
RP2722 4 5
RP2726 3 6
RP2728 3 6
RP2728 4 5
RP2726 2 7
RP2724 3 6
RP2722 3 6
RP2720 4 5
RP2728 1 8
RP2724 1 8
RP2722 1 8
RP2726 4 5
C27241
2
C27221
2
C27201
2
RP2706 3 6
RP2701 1 8
RP2701 3 6
RP2704 4 5
RP2704 2 7
RP2707 4 5
RP2702 4 5
RP2703 3 6
RP2707 1 8
C27101
2
C27081
2
C27061
2
RP2707 2 7
RP2703 4 5
RP2704 1 8
RP2706 4 5
RP2702 3 6
RP2704 3 6
RP2703 2 7
RP2707 3 6
RP2706 1 8
RP2703 1 8
RP2702 1 8
RP2701 2 7
RP2701 4 5
RP2702 2 7
RP2706 2 7
C27041
2
C27021
2
C27001
2
C27231
2
C27271
2
C27251
2
C27071
2
C27031
2
C27051
2
C2765 1
2R27661 2
C2755 1
2
R27651 2
R27561 2
R27551 2
C27661 2
C27561 2
C27511 2
C27611 2
R27501 2
R27511 2
C2750 1
2
R27601 2
R27611 2
C2760 1
2
RP2705 1 8
RP2705 2 7
RP2725 2 7
RP2725 3 6
RP2725 1 8
RP2705 3 6
RP2705 4 5
RP2725 4 5
dvt
051-0675
6.0.0
27 OF 119
27 OF 94
81
81
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
BI
BI
IN
IN
IN
IN
OUT
OUT
OUT
BI
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
PORTS
MISC
(1 OF 2)
PCIE GEN2
DISPLAY PORT
DPSNK1_2_N
DPSNK1_2_P
DPSNK1_3_P
PERP_2
PERN_2
PETN_3
PETP_3
PETN_1
PETP_1
PETP_0
PETN_0
XTAL_25_OUT
XTAL_25_IN
EE_CS_N
DPSNK0_0_N
DPSNK0_0_P
DPSNK0_1_N
DPSNK0_1_P
DPSNK0_2_N
DPSNK0_2_P
DPSNK0_AUX_N
DPSNK0_AUX_P
DPSNK0_HPD
DPSNK1_0_N
DPSNK1_0_P
DPSNK1_1_N
DPSNK1_1_P
DPSNK1_3_N
DPSNK1_AUX_N
DPSNK1_AUX_P
DPSNK1_HPD
DPSRC_0_N
DPSRC_0_P
DPSRC_1_N
DPSRC_1_P
DPSRC_2_N
DPSRC_2_P
DPSRC_3_N
DPSRC_3_P
DPSRC_AUX_N
DPSRC_AUX_P
DPSRC_HPD_OD
EE_CLK
EE_DI
EE_DO
GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2
GPIO_14
GPIO_15
GPIO_2/TMU_CLK_IN/AC_PRESENT
GPIO_3/FORCE_PWR
GPIO_4/WAKE_OD_N
GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD
GPIO_6_OD/CIO_SDA_OD
GPIO_7_OD/CIO_SCL_OD
GPIO_8/EN_CIO_PWR_OD*
GPIO_9/SX_CTRL_OD*
MONDC0
MONOBSN
MONOBSP
PA_AUX_N
PA_AUX_P
PA_CIO0_RX_N
PA_CIO0_RX_P
PA_CIO0_TX_N/DPSRC_0_N
PA_CIO0_TX_P/DPSRC_0_P
PA_CIO1_RX_N
PA_CIO1_RX_P
PA_CIO1_TX_N/DPSRC_2_N
PA_CIO1_TX_P/DPSRC_2_P
PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE
PA_DPSRC_1_N
PA_DPSRC_1_P
PA_DPSRC_3_N
PA_DPSRC_3_P
PA_DPSRC_HPD
PA_LSRX/CIO_1_LSOE
PA_LSTX/CIO_1_LSEO
PB_AUX_N
PB_AUX_P
PB_CIO2_RX_N
PB_CIO2_RX_P
PB_CIO2_TX_N/DPSRC_0_N
PB_CIO2_TX_P/DPSRC_0_P
PB_CIO3_RX_N
PB_CIO3_RX_P
PB_CIO3_TX_N/DPSRC_2_N
PB_CIO3_TX_P/DPSRC_2_P
PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE
PB_DPSRC_1_N
PB_DPSRC_1_P
PB_DPSRC_3_N
PB_DPSRC_3_P
PB_DPSRC_HPD
PB_LSRX/CIO_3_LSOE
PB_LSTX/CIO_3_LSEO
PCIE_CLKREQ_OD_N
PCIE_RST_0_N
PCIE_RST_1_N
PCIE_RST_2_N
PCIE_RST_3_N
PERN_0
PERN_1
PERN_3
PERP_0
PERP_1
PERP_3
PERST_OD_N
PETN_2
PETP_2
PWR_ON_POC_RSTNRBIAS
REFCLK_100_IN_N
REFCLK_100_IN_P
RSENSE
RSVD
TCK
TDI
TDO
TEST_EN
THERMDA
TMS
TMU_CLK_OUT
MONDC1
TEST_PWR_GOOD
DPSNK0_3_P
DPSNK0_3_N
VCC
DO/IO1
GND THRM_PAD
CS*
CLK
WP*
HOLD*
DI/IO0
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DEBUG: For monitoring current/voltage
SNK0 AC Coupling
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
SNK1 AC Coupling
(TBT_SPI_MISO)(TBT_SPI_MOSI)
(TBT_SPI_CLK)
Used for straps in host modedepends on the code in the flash.bit in the flash, so the active-levelSecurity strap setting is XORed with
If strap != bit then security is enabled?
(TBT_SPI_CS_L)
Use AA8 GND ball for THERM_DN
DEBUG: For monitoring clock
Divides 3.3V to 1.8V
NOTE: The following pins require testpoints:8 - GPIO_159 - GPIO_11
15 - PB_LSRX14 - PB_LSTX13 - GPIO_1012 - GPIO_12
10 - GPIO_1411 - GPIO_0
5 - PCIE_RST_1_N
0 - GPIO_13
3 - GPIO_32 - GPIO_2
4 - GPIO_5
1 - GPIO_1
7 - PCIE_RST_3_N6 - PCIE_RST_2_N
5%3.3K
201
1/20WMF
79
79
201
1/20WMF
5%100
31
31 90
31 90
31 79
31 90
31 90
31 84 90
31 84 90
31 90
31 84 90
32 79
32 90
32 90
32
32 90
32 90
32 90
32 90
32 90
32 90
5%100K
201
1/20WMF
5%100K
201
1/20WMF
31 90
31 90
5%3.3K
201
1/20WMF
10% 16VX5R-CERM0.1UF 0201
80 86 94
80 86 94
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
16V10%X5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
16V10%X5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
16V10%0.1UF X5R-CERM0201
10% 16VX5R-CERM0.1UF 0201
16V10%X5R-CERM0.1UF 0201
MF1/20W
201
1K1%
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16V0.1UF X5R-CERM0201
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16VX5R-CERM0.1UF 0201
10% 16V0.1UF X5R-CERM0201
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
74 86 94
402CERM6.3V10%1UF
BYPASS=U2890:2mm
80 86 94
80 86 94
31
31
32
32
20
32 90
32 90
32 90
32 90
32 90
32 90
32
20
20
20
20
31 90
31 90
31 90
31 90
31
28 30 31
31
28 31
28 30 32
32
28 32
28 29
42
11
19 87 806
1%1/20WMF201
5%1K
201MF1/20W
201
10K
NO STUFF
1/20W5%
MF
11 88
11 88
29
0201
OMIT
NONENONE
NOSTUFFNONE
MF1/20W
201
10K5% 5%
1/20WMF201
10K
10K
MF1/20W
201
5%
NO STUFF
MF1/20W
201
10K5%
NO STUFF
5%
201
1/20WMF
100K
20
28 79
20
100K
MF1/20W
201
5%
OMIT_TABLECRITICAL
REDWOOD-RIDGEFCBGA
CRITICALOMIT_TABLE
W25X40CLXIG4MBIT
USON
28 30
28 31 32
MF1/20W
201
10K5% 5%
10K
201
1/20WMF
NO STUFF
5%10K
201
1/20WMF
5%10K
201
1/20WMF
100K5%
201
1/20WMF
5%
MF1/20W
201
10K
5%
201
1/20WMF
100K
100K5%
201
1/20WMF
28 82
5%
201
1/20WMF
100K 100K
MF1/20W
201
5%
100K
MF1/20W
201
5%
X5R-CERM16V
10% 02010.1UF
X5R-CERM16V
0.1UF 10% 0201
X5R-CERM16V
0.1UF 10% 0201
0.1UF X5R-CERM16V
10% 0201
5%3.3K
201
1/20WMF
16V0201X5R-CERM10%0.1UF
X5R-CERM16V
10%0.1UF 0201
X5R-CERM16V
0.1UF 10% 0201
X5R-CERM16V
0.1UF 10% 0201
02010.1UF X5R-CERM10% 16V
02010.1UF X5R-CERM10% 16V
02010.1UF X5R-CERM10% 16V
5%3.3K
201
1/20WMF
02010.1UF X5R-CERM10% 16V
02010.1UF X5R-CERM10% 16V
0201X5R-CERM0.1UF 10% 16V
0201X5R-CERM0.1UF 16V10%
0201X5R-CERM0.1UF 16V10%
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
Thunderbolt Host (1 of 2)SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
TBT_CLKREQ_L
PP3V3_TBTLCTP_DP_TBTSRC_ML_CN<0>
TP_DP_TBTSRC_AUXCH_CN
TBT_B_DP_PWRDNTBT_A_HV_EN
SYSCLK_CLK25M_TBT_R
PCIE_CLK100M_TBT_P
TBT_PWR_ON_POC_RST_L
TBT_PCIE_RESET_L
TBT_TMU_CLK_OUT
TP_DP_TBTSRC_ML_CP<3>TP_DP_TBTSRC_ML_CN<3>
TP_DP_TBTSRC_ML_CN<2>
TP_DP_TBTSRC_ML_CP<1>
PCIE_TBT_R2D_C_N<0>
TBT_DDC_XBAR_EN_L
TBT_B_R2D_C_N<0>
TBT_EN_CIO_PWR_L
PCIE_TBT_R2D_P<1>
PCIE_TBT_R2D_N<0>
SYSCLK_CLK25M_TBT
PP3V3_TBTLC
DP_TBTSNK0_ML_C_P<0>
PCIE_TBT_D2R_N<3>
PCIE_TBT_D2R_N<2>
PCIE_TBT_R2D_C_P<3>
DP_TBTSNK0_ML_P<3>
DP_TBTSNK1_ML_N<0>
DP_TBTSNK1_ML_C_N<1>
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_ML_C_P<1>
DP_TBTSNK0_ML_C_N<1>
DP_TBTSNK1_ML_P<0>
PCIE_TBT_R2D_C_N<3>
DP_TBTSNK1_AUXCH_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK1_ML_C_N<2>
DP_TBTSNK1_ML_N<1>
PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_P<1>
PCIE_TBT_D2R_N<1>
DP_TBTSNK0_ML_C_N<0>
DP_TBTSNK0_ML_C_P<2>
DP_TBTSNK0_ML_C_N<2>
DP_TBTSNK0_ML_C_P<3>
DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK1_ML_C_N<0>
DP_TBTSNK1_ML_C_P<1>
DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_ML_C_N<3>
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK0_ML_N<1>
DP_TBTSNK0_ML_P<1>
DP_TBTSNK0_ML_N<0>
DP_TBTSNK0_ML_P<0>
DP_TBTSNK0_ML_N<2>
DP_TBTSNK0_ML_P<2>
DP_TBTSNK1_ML_P<1>
DP_TBTSNK1_ML_P<2>
DP_TBTSNK1_ML_P<3>
DP_TBTSNK1_ML_N<3>
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_ML_N<2>
PCIE_TBT_R2D_C_P<0>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_D2R_P<3>
DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK0_ML_N<3>DP_TBTSNK0_ML_C_N<3>
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_C_P
PCIE_TBT_D2R_P<2>
DP_TBTSNK0_ML_N<3>DP_TBTSNK0_ML_P<3>
TP_TBT_THERM_DP
JTAG_TBT_TDI
TBT_RSENSE
PCIE_CLK100M_TBT_N
TBT_RBIAS
PCIE_TBT_D2R_C_P<2>PCIE_TBT_D2R_C_N<2>
PCIE_TBT_R2D_P<3>
PCIE_TBT_R2D_P<0>
PCIE_TBT_R2D_N<3>
TP_TBT_PCIE_RESET0_L
TBT_B_LSTXTBT_B_LSRX
DP_TBTPB_HPD
DP_TBTPB_ML_C_P<3>DP_TBTPB_ML_C_N<3>
DP_TBTPB_ML_C_P<1>DP_TBTPB_ML_C_N<1>
TBT_B_CONFIG2_RCTBT_B_CONFIG1_BUF
TBT_B_R2D_C_P<1>TBT_B_R2D_C_N<1>
TBT_B_D2R_P<1>TBT_B_D2R_N<1>
TBT_B_R2D_C_P<0>
TBT_B_D2R_P<0>TBT_B_D2R_N<0>
DP_TBTPB_AUXCH_C_PDP_TBTPB_AUXCH_C_N
TBT_A_LSTXTBT_A_LSRX
DP_TBTPA_HPD
DP_TBTPA_ML_C_P<3>DP_TBTPA_ML_C_N<3>
DP_TBTPA_ML_C_P<1>DP_TBTPA_ML_C_N<1>
TBT_A_CONFIG2_RCTBT_A_CONFIG1_BUF
TBT_A_R2D_C_P<1>TBT_A_R2D_C_N<1>
TBT_A_D2R_P<1>TBT_A_D2R_N<1>
TBT_A_R2D_C_N<0>
TBT_A_D2R_P<0>TBT_A_D2R_N<0>
DP_TBTPA_AUXCH_C_PDP_TBTPA_AUXCH_C_N
TP_TBT_MONDC0
TBT_B_DP_PWRDNTBT_A_DP_PWRDNTBT_B_CIO_SELTBT_A_CIO_SELTBT_B_HV_ENTBT_A_HV_EN
TP_DP_TBTSRC_ML_CP<2>
TP_DP_TBTSRC_ML_CP<0>
DP_TBTSNK1_HPD
DP_TBTSNK1_AUXCH_PDP_TBTSNK1_AUXCH_N
DP_TBTSNK1_ML_N<3>
DP_TBTSNK1_ML_P<1>DP_TBTSNK1_ML_N<1>
DP_TBTSNK1_ML_P<0>DP_TBTSNK1_ML_N<0>
DP_TBTSNK0_HPD
DP_TBTSNK0_AUXCH_PDP_TBTSNK0_AUXCH_N
DP_TBTSNK0_ML_P<2>DP_TBTSNK0_ML_N<2>
DP_TBTSNK0_ML_P<0>DP_TBTSNK0_ML_N<0>
TP_TBT_XTAL25OUT
PCIE_TBT_D2R_C_N<0>PCIE_TBT_D2R_C_P<0>
PCIE_TBT_D2R_C_P<1>PCIE_TBT_D2R_C_N<1>
PCIE_TBT_D2R_C_P<3>PCIE_TBT_D2R_C_N<3>
PCIE_TBT_R2D_N<2>
DP_TBTSNK1_ML_P<3>
DP_TBTSNK1_ML_P<2>DP_TBTSNK1_ML_N<2>
TBTROM_HOLD_L
TBTROM_WP_L
=TBT_BATLOW_LTBTDP_AUXIO_EN
TBT_DFT_STRAP_3
TBT_DFT_STRAP_1
PCIE_TBT_R2D_P<2>
PP3V3_TBTLC
TBT_A_R2D_C_P<0>
TP_DP_TBTSRC_ML_CN<1>
DP_TBTSNK0_ML_N<1>DP_TBTSNK0_ML_P<1>
PCIE_TBT_R2D_N<1>
TP_TBT_MONDC1
TBT_MONOBSNTBT_MONOBSP
TBT_SPI_MISO
TBT_SPI_CLKTBT_SPI_CS_L
TBT_SPI_MOSI
TBT_TEST_PWR_GOODTBT_TEST_ENJTAG_TBT_TDOJTAG_TBT_TCKJTAG_TBT_TMS
TP_DP_TBTSRC_AUXCH_CP
TBT_PWR_EN
TBT_CIO_PLUG_EVENT_LHDMITBTMUX_SEL_TBT
=TBT_WAKE_L
TBT_ROM_SECURITY_XOR
TBT_A_DP_PWRDN
TBT_B_HV_EN
=TBT_BATLOW_L
=PP3V3_S4_TBT
TBTDP_AUXIO_EN
TBT_DDC_XBAR_EN_LHDMITBTMUX_SEL_TBT
TBT_EN_CIO_PWR_L
=PP3V3_S4_TBT
DP_TBTSRC_HPD
DP_TBTSRC_HPD
TBT_GPIO7
TBT_GPIO2
PP3V3_TBTLC
R28901
2
C2890 1
2
R28921
2
R28911
2
R28551
2
C2801 1 2
C2800 1 2
C2802 1 2
C2803 1 2
C2804 1 2
C2805 1 2
C2806 1 2
C2807 1 2
C2840 1 2
C2841 1 2
C2842 1 2
C2843 1 2
C2845 1 2
C2844 1 2
C2846 1 2
C2847 1 2
R28251
2
R28301
2
R28311
2
R28931
2
C2829 1 2
C2828 1 2
C2827 1 2
C2826 1 2
C2825 1 2
C2824 1 2
C2823 1 2
C2822 1 2
C2821 1 2
C2820 1 2
C2830 1 2
C2831 1 2
C2832 1 2
C2833 1 2
C2834 1 2
C2835 1 2
C2836 1 2
C2837 1 2
C2838 1 2
C2839 1 2
R28951 2
R28961
2
R28991
2
R28151
2
R28881
2
R28871
2
R28861
2
R28851
2
R28801
2
R28831
2
U2800
D19
E20
D17
E18
D15
E16
D13
E14
G2
G4
AB5
D11
E12
D9
E10
D7
E8
D5
E6
H1
H3
U4
B9
A8
B11
A10
B13
A12
B15
A14
J2
J4
AC2
U8
T5
AA2
Y3
R8
N2 R2
P3 F3
T1
T3
F1
U2
L6
H5
Y7
Y1
T7
V7
M7
AD23
AC24
W16
W18
L2
L4
E22
G22
E24
G24
J22
L22
J24
L24
P1
K5
B17
A16
B19
A18
M3
J6
N8
K1
K3
N22
R22
N24
R24
U22
W22
U24
W24
D3
M1
B21
A20
B23
A22
N6
P7
M5
V3
W6
AB3
AD3
V1
AA10
AB13
AA16
AB19
AB9
AA12
AB15
AA18
P5
AD7
AD11
AD15
AD19
AD5
AD9
AD13
AD17
R4W20
AD21
AB21
U20
AD1
L8
AA6
W2
U6
R6
W8
AB7
AB1
AA4
AA24
AB23
U28906
1
5 2
4
7
9
8
3
R28611
2
R28631
2
R28671
2
R28621
2
R28811
2
R28291
2
R28841
2
R28821
2
R28781
2
R28791
2
R28321
2
dvt
051-0675
6.0.0
28 OF 119
28 OF 94
20 28 29 81
84
84
28 32
28 30 31
87
84
84
84
84
8486
84 86
20 28 29 81
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
47
8486
8486
8486
8486
84 86
84
84
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
84
84 86
84 86
84 86
8486
8486
8486
84 86
28 86 94
28 86 94
28 86 94
8486
20 28 29 81
84
28 86 94
28 86 94
84 86
90
90
90
90
84
28 31
28 30 32
28 30
28 29 30 45 81
28 31 32
28 79
28 82
28 29
28 29 30 45 81
28
28
20 28 29 81
GND
VCC
(2 OF 2)
VSSVSS
VCC3P3_RDV_DECAP
VCC3P3_LC
VCC3P3
VCC1P0_RDV_DECAP
VCC1P0_CIO
SVR_VCC1P0
SVR_AMON
SVR_IND0
NC
S
D
G
VOUT
GNDON
VIN
IN
OUTIN
IN
D
SYM_VER_3
SG
G
DS
OUT
GND
SENSE
ENABLE SENSE_OUT
CT
VCC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
U2950TPS22920
Push-pull output
Isolated to reduce noise from SVR
Part
Type
R(on)@ 1.05V
Max Current = 4A (85C)
8 mOhm Typ11.5 mOhm Max
Load Switch
Pull-up (S0) on PCH page
1.05V TBT "CIO" Switch
EDP: 1.25 A
25 mA EDP
1200 mA EDP700 mA EDP
1900 mA EDP
SVR input to RR - 1100 mA EDP
POC input to RR - 150 mA EDP
2.4 W (Single-Port)3.1 W (Dual-Port)
100 mA EDP
Internal switch not functional on RR.
Delay = 4.04ms nominal
TBT "POC" Power-up Reset
Vth = 2.508V nominal
EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).
0201-1
6.3VX5R
1.0UF20%
CRITICALOMIT_TABLE
REDWOOD-RIDGEFCBGA
0201-1
6.3VX5R
1.0UF20%20%
1.0UF6.3VX5R
0201-1
CRITICAL
680NH-30%-3.6A-35MOHM
SM
20%10UF
0402-1CERM-X5R
6.3V20%
10UF
0402-1CERM-X5R
6.3VCRITICAL
SOD-323NSR1020MW2T1G
SOT-563DMN5L06VK-7
1/20WMF201
100K5%
CRITICAL
TPS22920CSP
1.0UF
0201-1
6.3VX5R20%
0201-1
6.3VX5R
1.0UF20%
0201-1
6.3VX5R
1.0UF20%
1.0UF20%X5R
6.3V
0201-1
28
20%1.0UF
X5R6.3V
0201-1 0201-1
6.3VX5R
1.0UF20%
6.3VCERM-X5R
0402-1
10UF20%20%
10UF
0402-1CERM-X5R
6.3V20%
10UF
0402-1CERM-X5R
6.3V20%
10UF
0402-1CERM-X5R
6.3V
SM
PLACE_NEAR=C2953.1:1mm
28
330PF10%
0201X7R-CERM
16V1%24.9K
201MF1/20W
402
0.1UF10%
X5R25V
14
1/20W
100K
201MF
5%
19 30 40 41
201MF1/20W
100K5%
DMN32D2LFB4DFN1006H4-3
0402
0.001UF50V10%
X7R-CERM
DMN5L06VK-7
SOT-563
12
CRITICAL
USONTPS3895ADRY
5%
MF201
100K1/20W
20%1.0UF
X5R6.3V
0201-1
6.3VCERM-X5R
0402-1
10UF20%20%
10UF
0402-1CERM-X5R
6.3V
1.0UF
0201-1X5R
6.3V20%
0201-1
6.3VX5R
1.0UF20%20%
1.0UF
X5R6.3V
0201-1 0201-1
20%6.3VX5R
1.0UF20%
1.0UF
X5R6.3V
0201-1 0201-1
6.3VX5R
1.0UF20%
0201-1
6.3VX5R
1.0UF20%
0201-1
6.3VX5R
1.0UF20%
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
Thunderbolt Host (2 of 2)
TBT_PWR_ON_POC_RST_L
TBTPOCRST_CT
TBT_EN_CIO_PWR_L
TBT_EN_CIO_PWR
PP1V05_TBT
MIN_NECK_WIDTH=0.20 MMVOLTAGE=1.05V
MIN_LINE_WIDTH=0.38 MMPP1V05_TBTRDV
VOLTAGE=3.3V
PP3V3_TBTRDVMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM
P1V05TBT_SWMIN_NECK_WIDTH=0.20 MMDIDT=TRUESWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.50 MM
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V
PP1V05_TBTCIO
MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V
PP3V3_S4_TBT_F
=PP3V3_S4_TBTVOLTAGE=1.05V
MIN_LINE_WIDTH=0.50 MMMIN_NECK_WIDTH=0.20 MM
PP1V05_TBT
=PP3V3_S0_PCH_GPIO
TBT_PWR_REQ_L
TBTPOCRST_SENSE
=PP3V3_S4_TBT
=PP3V3_S0_PCH_GPIO
SMC_DELAYED_PWRGD
TBTPOCRST_MR_LTBT_POC_RESET_L
PP3V3_TBTLC
MIN_NECK_WIDTH=0.15 MMMIN_LINE_WIDTH=0.4 MMPP3V3_TBTLC
VOLTAGE=3.3V
C2904 1
2
C2905 1
2
C2900 1
2
C2901 1
2
C2902 1
2
C2906 1
2
C2903 1
2
C2920 1
2
C2921 1
2
C2932 1
2
C2931 1
2
C2930 1
2
U2800
B5
A4
A6
B3
J8
K9
L14
M15
M17
P17
V19
J10
J12
R14
T11
T15
U10
U14
V11
K11
L10
M11
N10
N14
P11
P15
R10
G10
G12
K19
K7
L16
M19
P19
T19
U18
V15
V17
W12
G14
W14
G16
G18
H19
H9
J18
K15
K17
D1
E2
H11
N4
V5
W4
Y5
H13
H15
H17
H7
L18
N18
R18
W10
A2
A24
AC14
AC16
AC18
AC20
AC22
AC4
AC6
AC8
B1
B7
AA14
C10
C12
C14
C16
C18
C2
C20
C22
C24
C4
AA20
C6
C8
D21
D23
E4
F11
F13
F15
F17
F19
AA22
F21
F23
F5
F7
F9
G20
G6
G8
H21
H23
AA8 J14
J16
J20
K13
K21
K23
L12
L20
M13
M21
AB11
M23
M9
N12
N16
N20
P13
P21
P23
P9
R12
AB17
R16
R20
T13
T17
T21
T23
T9
U12
U16
V13
AC10
V21
V23
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
AC12
Y9
C2911 1
2
C2910 1
2
L2920
1 2
C2922 1
2
C2923 1
2 D2920
A
K
Q29456
21
R29451
2
U2940
D1
D2
A2
B2
C2
A1
B1
C1
C29401
2
C29811
2
C29801
2
C2970 1
2
C2960 1
2
C2961 1
2
C2953 1
2
C2952 1
2
C2951 1
2
C2950 1
2
XW2960
1
2
C2995 1
2
R29911
2
C29901
2
R29951
2
R29901
2
Q2995
3
12
C2991 1
2
Q2945
3
54
U2990
5
1
2
3
4
6
R29921
2
dvt
051-0675
6.0.0
29 OF 119
29 OF 94
29
28 29 30 45 81
29
11 12 14 20 29 81
28 29 30 45 81
11 12 14 20 29 81
20 28 29 81
20 28 29 81
IN
SG
D
NC
VIN
FBX
EN/UVLO
INTVCC
VC
RT
SS
SYNC
SW
SGND GND
NC
SNS1
SNS2
IN
S
D
G
S
D
G
OUT
D
SYM_VER_3
SG
IN
G
S
D
G
S
D
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Freq = 480KHzMax Current = 2A?
8-13V Input
- =PPVIN_SW_TBTBST (8-13V Boost Input)
<R1>
Vds(max): -30VSI8409DB:
Vgs(th): -1.4V
<Ra>
<Rb>
Vout = 1.6V * (1 + Ra / Rb)no XW necessary.GND inside package,SGND shorted to
Max Vgs: 10V
UVLO(rising) = UVLO(falling) + (2uA * R1)UVLO = 4.55V (falling), 4.95 (rising)
for 2S.
<R2>
Page Notes
Vout = 15.47V
add property on another page.Voltage not specified here,
Rds(on): 46mOhm @ 4.5V Vgs
Pull-up on RR page
- =PP15V_TBT_REG (15V Boost Output)
(NONE)
(NONE)
Thunderbolt 15V Boost Regulator
BATLOW# Isolation
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
Changes required
UVLO(falling) = 1.22 * (R1 + R2) / R2
Id(max): 3.7A @ 70C
Vgs(max): +/-12V
330K1/16WMF-LF
402
5%
470K
MF-LF1/16W
402
5%25V10%0.1UF
X5R402
402
73.2K1%
MF-LF1/16W
1/16WMF-LF
330K
402
5%
26.7K
402
1/16WMF-LF
1% 0.33UF6.3VCERM-X5R
10%
402
330K
MF-LF1/16W
402
5%
19 29 40 41
NO STUFF
100PF
CERM50V
402
5% 1%1/16W
402MF-LF
15.8KCASE-D3L
20%
POLY-TANT25V
33UF-0.06OHM
1206-2X5R
10UF10%25V
NO STUFF
10UF25VX5R
10%
805
0402COG-CERM
68PF50V5%
2.2UF20%10V
402X5R-CERM
SI8409DB
CRITICAL
BGA
1%49.9K
MF-LF1/16W
402
1%200K
MF-LF1/16W
402
10UF
X5R-CERM0603
20%25V
10UF
X5R-CERM25V
0603
20%
PIMB063T-SM
3.3UH-6.5A
CRITICAL
10PF
0402C0G-CERM50V5%
CRITICAL
LT3957QFN
1/16W1%
MF-LF402
137K
PLACE_NEAR=C3095.1:2 mm
SM
MF1/20W
0201
05%
0.001UF
X7R-CERM
10%50V
0402
0402X7R-CERM
10%50V
0.0033UF20%10V
X5R-CERM402
2.2UF
X5R-CERM402
10V
2.2UF20%
CRITICAL
PDS540XFPWRDI5
28 32
SOT-563DMN5L06VK-7
SOT-563DMN5L06VK-7
28
DMN32D2LFB4DFN1006H4-3
12 42
SOT-563DMN5L06VK-7
SOT-563DMN5L06VK-7
2831
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
Thunderbolt Mobile Support
TBTBST_EN_UVLO
TBTBST_RT =PP15V_TBT_REG
TBTBST_SNS1
PPVIN_SW_TBTBSTMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
=PPVIN_SW_TBTBST
PM_BATLOW_LTBT_BATLOW_LMAKE_BASE=TRUE
TBTBST_VC_RC
TBTBST_VSNS
MIN_NECK_WIDTH=0.25 mmSWITCH_NODE=TRUE
TBTBST_BOOSTMIN_LINE_WIDTH=0.5 mm
DIDT=TRUE
TBTBST_SNS2
TBTBST_INTVCC
TBTBST_FBX
TBTBST_SHDN_DIV
TBTBST_SS
SMC_DELAYED_PWRGD
=TBT_BATLOW_L
=PP3V3_S4_TBT
TBT_B_HV_EN
MIN_NECK_WIDTH=0.25 mmVOLTAGE=0V
MIN_LINE_WIDTH=0.5 mmGND_TBTBST_SGND
TBTBST_VC
TBT_A_HV_EN
TBTBST_PWREN_DIV_L
TBTBST_PWREN_L
R30811
2
R30801
2
C30801
2
R30921
2
R30871
2
R30941
2
C30941
2
R30881
2
C30891
2
R30961
2
C30951
2
C3096 1
2
C30971
2
C30871
2
C3085 1
2
Q3080
23
1
4
R30931
2
R30911
2
C3090 1
2
C3091 1
2
L3095
1 2
C30881
2
U309025
31
12
13
14
15
16
17
28
1
2
10
35
36
33
6
3
4 23
24
37
32
8 9
20
21
38
34
30
27
R30951
2
XW309512
R30891
2
C30991
2
C30931
2
C3092 1
2
C30861
2
D30951 2
3
Q30886
21
Q30883
54
Q3000
3
12
Q3005
6
2
1
Q3005
3
5
4
dvt
051-0675
6.0.0
30 OF 119
30 OF 94
81
81
81
28 29 45 81
IN
IN
OUT
IN
IN
V3P3
ISET_V3P3
OUT
THRMGND
HV_EN
S0
EN
ISET_S0
V3P3OUT
ISET_S3
ENHVU
VHV
FAULTZ
PAD
IN
IN
IN
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
BI
IN
IN
OUT
TB+
LSRX
AUX+
CA_DET
DPMLO+
DPMLO-
HPD
THMPADGND
DP+
LSTX
DP-
HPDOUT
AUX-
VDD
DP_PD
AUXIO_EN
TB_ENATB-
AUXIO+
AUXIO-
CA_DETOUT
DDC_CLK
DDC_DAT
IN
IN
IN
ML_LANE1P
GND1
ML_LANE0N
GND0
ML_LANE0P
ML_LANE1N
ML_LANE2N
RETURN
HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
DP_PWR
AUX_CHP
AUX_CHN
ML_LANE2P
GND3
SHIELD PINS
SHIELD PINS
PORT B
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DP Dir
514-0876
down HPD input with
to 100K (DPv1.1a).greater than or equal
TBT: Unused
<RV3P3>
V3P3 must be S4 to support
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
Single-fault protection
Low: 0 - 0.8V
ILIM = 40000 / RISET
Sink HPD range:
(Both C’s)
(Both C’s)(Both C’s)
TBT Dir
(0-18.9V)
TBT: TX_0
(0-18.9V)
DP Dir
(Both C’s)
TBT: LSX_R2P/P2R (P/N)
DP Source must pull
High: 2.0 - 5.0V
TBT: LSX_A_R2P/P2R (P/N)
TBT: RX_1
(IPU)
(IPD)
(IPD)
(IPU) below
requires two R’s per HV
Single R on ISET_V3P3 OK.
12V: See
<RHVS0><RHVS3>
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) Nominal Min Max
For 12V systems:
TBT: TX_1
TBT: RX_0
TBT: RX_1
IV3P3 1100mA 1030mA 1200mA
3.3V/HV Power MUX
15.75V Max
Nominal Min Max
ISET_Sx with CD3210.
Thunderbolt Connector A
TBT Dir
470k R’s for ESD protectionon AC-coupled signals.
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
wake from Thunderbolt devices.
50V10%
0402X7R-CERM
0.01UF
28 90
28 90
0201
16V10%X5R-CERM
0.01UF
1/20WMF201
5%
12
0402
50V10%X7R-CERM
0.01UF
NO_XNET_CONNECTION=TRUE
GND_VOID=TRUE
1/20W5%
201MF
1K
NO_XNET_CONNECTION=TRUE
GND_VOID=TRUE
1/20W5%
201MF
1K
1/20W5%
201MF
100K
6.3V20%
0402CERM-X5R
10UF
X5R-CERM16V10%
0201
0.1UF
16V10%
0201X5R-CERM
0.1UF20%
6.3V
603X5R-CERM-1
22UF100UF6.3V20%
CASE-B2-SMPOLY-TANT
CRITICAL
1/20W5%
201MF
1M1/20W5%
201MF
1M16V10%
0201X7R-CERM
330PF16V10%
0201X7R-CERM
330PF
CRITICAL
FERR-120-OHM-3A
0603
28
0.1UF25V10%
402X5R
470K
MF201
5%1/20W
GND_VOID=TRUE
470K
MF201
5%1/20W
GND_VOID=TRUE
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
28 84 90
28 90
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
470K
MF201
5%1/20W
GND_VOID=TRUE
470K
MF201
5%1/20W
GND_VOID=TRUE
CRITICAL
QFNCD3211A0RGPR
28 30
65
32 65
1/20W1%
201MF
36.5K
25V10%
402X5R
0.1UF
0.1UF
0201
10%16V
X5R-CERM
28
80
80
28
28 79
28 84 90
28 84 90
28 90
28 90
02010.22UF 6.3V20%X5R
0.22UF 6.3V20%0201X5R
28 90
28 90
0.1UF 10% 16VX5R-CERM
0201
X5R-CERM0201
0.1UF 10% 16V
28 90
28 90
0.22UF 6.3V20%0201X5R
0.22UF 6.3V20%0201X5R
28 90
28 90
1/20W1%
201MF
22.6K
TBTHV:P15V
1/20W1%
201MF
22.6K
TBTHV:P15V
22.6K
MF201
1%1/20W
TBTHV:P15VTBTHV:P15V
22.6K
MF201
1%1/20W
25V10%
0603X5R-CERM
4.7UF
0.01UF
X5R-CERM0201
10%25V
GND_VOID=TRUE
GND_VOID=TRUE
25V
0201X5R-CERM
0.01UF10%
28
4V
GND_VOID=TRUE
201CERM-X5R-10.47UF 20%
2014V
GND_VOID=TRUE
CERM-X5R-10.47UF 20%
SIGNAL_MODEL=TBT_MUX
CBTL05024HVQFN24-COMBO
CRITICAL
28 32
28
28
1/20W5%
201MF
470K1/20W5%
201MF
470K
2014V0.47UF 20%CERM-X5R-1
GND_VOID=TRUE
2014V0.47UF 20%
GND_VOID=TRUE
CERM-X5R-1
F-RT-TH
CRITICAL
MDP-J44
TBTHV:P12VR3210,R32132118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
TBTHV:P12V118S0145 R3211,R32142 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
Thunderbolt Connector ASYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
TBT_A_HPD
TBT_A_D2R1_AUXDDC_NTBT_A_D2R1_AUXDDC_P
MIN_NECK_WIDTH=0.20 MMVOLTAGE=15V
MIN_LINE_WIDTH=0.38 MMPP3V3RHV_S4_TBTAPWR_F
DP_TBTPA_ML_P<3> DP_A_LSX_ML_P<1>
TBTACONN_7_CMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM
VOLTAGE=18.9V
TBT_A_R2D_N<0>
TBTACONN_1_CMIN_LINE_WIDTH=0.38 MM
VOLTAGE=18.9VMIN_NECK_WIDTH=0.20 MM
TBT_A_R2D_P<0>
DP_A_LSX_ML_N<1>
TBT_A_R2D_N<1>
TBT_A_D2R_C_P<0>TBT_A_D2R_C_N<0>
DP_TBTPA_ML_N<3>
TBT_A_R2D_P<1>
TBT_A_CONFIG1_RC
=TBT_S0_EN
TBTAPWRSW_ISET_S0_R
TBT_A_CONFIG2_RC
=PP3V3_S4_TBTAPWRSW
PP3V3_S4_TBTAPWRMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM
VOLTAGE=3.3V
DP_TBTPA_DDC_CLK
MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM
TBTACONN_20_RC
VOLTAGE=18V
DP_TBTPA_ML_C_P<1>DP_TBTPA_ML_C_N<1>
DP_TBTPA_AUXCH_C_P
TBT_A_D2R_P<0>TBT_A_D2R_N<0>
DP_TBTPA_ML_C_P<3>DP_TBTPA_ML_C_N<3>
TBT_A_R2D_C_P<0>
TBT_A_R2D_C_P<1>TBT_A_R2D_C_N<1>
TBT_A_R2D_C_N<0>
PP3V3_S4_TBTAPWR
TBT_A_CONFIG1_RC
DP_A_LSX_ML_P<1>DP_A_LSX_ML_N<1>
TBT_A_HPD
DP_TBTPA_ML_P<1>DP_TBTPA_ML_N<1>
DP_TBTPA_AUXCH_NTBT_A_DP_PWRDNTBTDP_AUXIO_EN
TBT_A_D2R1_AUXDDC_PTBT_A_D2R1_AUXDDC_N
TBT_A_CONFIG1_BUF
DP_TBTPA_DDC_DATA
TBT_A_LSTXTBT_A_LSRX
DP_TBTPA_HPDTBTAPWRSW_ISET_S3_R
DP_TBTPA_AUXCH_PDP_TBTPA_AUXCH_C_N
TBT_A_D2R_N<1>
TBT_A_D2R_C_P<1>TBT_A_D2R_P<1>
=PPHV_S4SW_TBTAPWRSW
TBTAPWRSW_ISET_S3
TBTAPWRSW_ISET_S0
=TBTAPWRSW_EN
TBT_A_HV_EN
TBTAPWRSW_ISET_V3P3
VOLTAGE=15V
MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM
PP3V3RHV_S4_TBTAPWR TBT_A_CIO_SELTBT_A_D2R_C_N<1>
L3200
1 2
C3200 1
2
C32021
2
R32011 2
C32011
2
R32941
2
R32951
2
R32411
2
C32861
2
C3285 1
2
C32811
2
C3280 1
2
C3287 1
2
R32521
2
R32511
2
C3294 1
2
C32951
2
C32101
2
R32701
2
R32711
2
C3271 1 2
C3270 1 2
C3272 1 2
C3273 1 2
R32731
2
R32721
2
U3210
5
16 4
1 2 3
13
15
11 10
9
8
12
14
17
21
19
20
18
6
7
R32121
2
C32111
2
C3220 1
2
C3232 1 2
C3233 1 2
C3230 1 2
C3231 1 2
C3278 1 2
C3279 1 2
R32111
2
R32101
2
R32141
2
R32131
2
C3215 1
2
C3205 1
2
C3206 1
2
C3274 1 2
C3275 1 2
U3220
1
2
24
23
22
1816
5
4
10
11
6
20
19
9
21
1712
13
14
157
8
25
3
R32791
2
R32781
2
C3277 1 2
C3276 1 2
J3200
B18
B16
B4
B6
B20
B1
B7B8
B13B14
B2
B5
B3
B11
B9
B17
B15
B12
B10
B19
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S24
dvt
051-0675
6.0.0
32 OF 119
31 OF 94
31
31 90
31 90
90 31 90
90
90
31 90
90
90
90
90
90
31
81
31
31
31
31 90
31 90
31
90
90
90
31 90
31 90 90
90
8190
IN
IN
OUT
IN
IN
V3P3
ISET_V3P3
OUT
THRMGND
HV_EN
S0
EN
ISET_S0
V3P3OUT
ISET_S3
ENHVU
VHV
FAULTZ
PAD
IN
IN
IN
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
BI
IN
IN
OUT
TB+
LSRX
AUX+
CA_DET
DPMLO+
DPMLO-
HPD
THMPADGND
DP+
LSTX
DP-
HPDOUT
AUX-
VDD
DP_PD
AUXIO_EN
TB_ENATB-
AUXIO+
AUXIO-
CA_DETOUT
DDC_CLK
DDC_DAT
IN
IN
IN
ML_LANE1P
GND3GND4
HPD
CONFIG2
GND2
RETURNAUX_CHN
CONFIG1
ML_LANE3N
ML_LANE3P
AUX_CHP
GND0
DP_PWR
ML_LANE0P
GND1
ML_LANE0N
ML_LANE1N
ML_LANE2N
ML_LANE2P
PORT A
SHIELD PINS
SHIELD PINS
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
V3P3 must be S4 to support
DP Source must pull
TBT: RX_1
down HPD input with
to 100K (DPv1.1a).
Thunderbolt Connector B
TBT: Unused
TBT: RX_0
For 12V systems:
Nominal Min MaxIHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
<RHVS3> <RHVS0>Single R on ISET_V3P3 OK.
requires two R’s per HVISET_Sx with CD3210.
ILIM = 40000 / RISET
below
Single-fault protection
3.3V/HV Power MUX
(IPU)
(IPD)
(IPD)
(IPU)
TBT: RX_1
TBT: LSX_A_R2P/P2R (P/N)
Sink HPD range:High: 2.0 - 5.0VLow: 0 - 0.8V
greater than or equal
TBT: LSX_R2P/P2R (P/N)
(Both C’s)
DP Dir
(0-18.9V)
TBT: TX_0
(0-18.9V)
TBT Dir
(Both C’s)
470k R’s for ESD protectionon AC-coupled signals.
(Both C’s) TBT Dir DP Dir
(Both C’s)
15.75V Max
wake from Thunderbolt devices.
Nominal Min Max
<RV3P3>
514-0876 TBT: TX_1
IV3P3 1100mA 1030mA 1200mAIHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
12V: See
50V10%
0402X7R-CERM
0.01UF
28 90
28 90
16V10%
0201X5R-CERM
0.01UF
MF
5%
12
201
1/20W
50V10%
0402X7R-CERM
0.01UF
NO_XNET_CONNECTION=TRUE
GND_VOID=TRUE
1/20W5%
201MF
1K
NO_XNET_CONNECTION=TRUE
GND_VOID=TRUE
1/20W5%
201MF
1K
1/20W5%
201MF
100K
6.3V20%
0402CERM-X5R
10UF16V10%
0201X5R-CERM
0.1UF
16V10%
0201
0.1UF
X5R-CERM20%
6.3V
603X5R-CERM-1
22UF100UF
CRITICAL
6.3V20%
CASE-B2-SMPOLY-TANT
1/20W5%
201MF
1M1/20W5%
201MF
1M16V10%
0201X7R-CERM
330PF16V10%
0201X7R-CERM
330PF
0603
FERR-120-OHM-3A
CRITICAL
28
25V10%
402X5R
0.1UF
470K
MF201
5%1/20W
GND_VOID=TRUE
470K
MF201
5%1/20W
GND_VOID=TRUE
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
28 90
28 90
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
0.22UF X5R 020120% 6.3V
GND_VOID=TRUE
470K
MF201
5%1/20W
GND_VOID=TRUE
470K
MF201
5%1/20W
GND_VOID=TRUE
QFN
CRITICAL
CD3211A0RGPR
28 30
65
31 65
36.5K1%1/20WMF201
25V10%
402X5R
0.1UF
0.1UF
0201
10%16V
X5R-CERM
28
80
80
28
28 79
28 90
28 90
28 90
28 90
X5R 020120% 6.3V0.22UF
X5R 020120% 6.3V0.22UF
28 90
28 90
0201X5R-CERM
16V10%0.1UF
16V10%X5R-CERM0.1UF
0201
28 90
28 90
0.22UF 6.3V20%0201X5R
0.22UF 6.3V20%0201X5R
28 90
28 90
TBTHV:P15V
1/20W1%
201MF
22.6K1/20W
1%
201MF
TBTHV:P15V
22.6K
TBTHV:P15V
22.6K
MF201
1%1/20W
TBTHV:P15V
22.6K
MF201
1%1/20W
25V10%
0603X5R-CERM
4.7UF
0.01UF
X5R-CERM0201
10%25V
GND_VOID=TRUE
GND_VOID=TRUE
25V10%
0201X5R-CERM
0.01UF
28
4V
GND_VOID=TRUE
201CERM-X5R-10.47UF 20%
2014V
GND_VOID=TRUE
CERM-X5R-10.47UF 20%
SIGNAL_MODEL=TBT_MUX
CBTL05024
CRITICAL
HVQFN24-COMBO
28 31
28
28
1/20W5%
201MF
470K1/20W5%
201MF
470K
GND_VOID=TRUE
2014V0.47UF 20%CERM-X5R-1
GND_VOID=TRUE
2014V0.47UF 20%CERM-X5R-1
MDP-J44
CRITICAL
F-RT-TH
TBTHV:P12VR3310,R33132118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
118S0145 TBTHV:P12VR3311,R33142 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
Thunderbolt Connector B
TBT_B_HV_EN
=PP3V3_S4_TBTBPWRSW
TBTBPWRSW_ISET_V3P3
VOLTAGE=15V
PP3V3RHV_S4_TBTBPWRMIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM
=TBT_S0_EN
=TBTBPWRSW_EN
MIN_LINE_WIDTH=0.38 MM
VOLTAGE=3.3V
PP3V3_S4_TBTBPWRMIN_NECK_WIDTH=0.20 MM
TBTBPWRSW_ISET_S3
=PPHV_S4SW_TBTBPWRSW
DP_TBTPB_AUXCH_N
DP_TBTPB_AUXCH_C_PDP_TBTPB_AUXCH_C_N
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMTBTBCONN_20_RC
VOLTAGE=18V
TBTBPWRSW_ISET_S3_RTBTBPWRSW_ISET_S0_R DP_TBTPB_HPD
TBT_B_LSRXTBT_B_LSTX
DP_TBTPB_DDC_DATADP_TBTPB_DDC_CLK
TBT_B_CONFIG1_BUF
TBT_B_D2R1_AUXDDC_NTBT_B_D2R1_AUXDDC_P
TBT_B_CIO_SELTBTDP_AUXIO_ENTBT_B_DP_PWRDN
DP_TBTPB_ML_N<1>DP_TBTPB_ML_P<1>
TBT_B_HPD
DP_B_LSX_ML_N<1>DP_B_LSX_ML_P<1>
TBT_B_CONFIG1_RC
DP_TBTPB_AUXCH_P
PP3V3_S4_TBTBPWR
TBT_B_CONFIG1_RC
TBT_B_CONFIG2_RC
TBT_B_R2D_C_N<0>
TBT_B_R2D_C_N<1>TBT_B_R2D_C_P<1>
TBT_B_R2D_C_P<0>
DP_TBTPB_ML_C_N<3>DP_TBTPB_ML_C_P<3>
TBT_B_D2R_N<0>TBT_B_D2R_P<0>
DP_TBTPB_ML_C_N<1>DP_TBTPB_ML_C_P<1>
TBT_B_D2R_N<1>TBT_B_D2R_P<1>
TBT_B_D2R_C_P<1>TBT_B_D2R_C_N<1>
TBT_B_R2D_P<1>TBT_B_R2D_N<1>
DP_B_LSX_ML_N<1>
TBT_B_R2D_N<0>
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM
VOLTAGE=18.9V
TBTBCONN_7_C
TBT_B_R2D_P<0>
PP3V3RHV_S4_TBTBPWR_F
VOLTAGE=15V
MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMTBTBCONN_1_C
VOLTAGE=18.9V
TBT_B_D2R1_AUXDDC_P
DP_TBTPB_ML_P<3>DP_TBTPB_ML_N<3>
TBT_B_D2R_C_P<0>
TBT_B_D2R1_AUXDDC_N
TBT_B_D2R_C_N<0>
TBT_B_HPD
DP_B_LSX_ML_P<1>
TBTBPWRSW_ISET_S0
L3300
1 2
C3300 1
2
C33021
2
R33011 2
C33011
2
R33941
2
R33951
2
R33411
2
C33861
2
C3385 1
2
C33811
2
C3380 1
2
C3387 1
2
R33521
2
R33511
2
C3394 1
2
C33951
2
C33101
2
R33701
2
R33711
2
C3371 1 2
C3370 1 2
C3372 1 2
C3373 1 2
R33731
2
R33721
2
U3310
5
16 4
1 2 3
13
15
11 10
9
8
12
14
17
21
19
20
18
6
7
R33121
2
C33111
2
C3320 1
2
C3332 1 2
C3333 1 2
C3330 1 2
C3331 1 2
C3378 1 2
C3379 1 2
R33111
2
R33101
2
R33141
2
R33131
2
C3315 1
2
C3305 1
2
C3306 1
2
C3374 1 2
C3375 1 2
U3320
1
2
24
23
22
1816
5
4
10
11
6
20
19
9
21
1712
13
14
157
8
25
3
R33791
2
R33781
2
C3376 1 2
C3377 1 2
J3200
A18
A16
A4
A6
A20
A1
A7A8
A13A14
A2
A5
A3
A11
A9
A17
A15
A12
A10
A19
S1
S10
S11
S2
S23
S3
S4
S5
S6
S7
S8
S9
dvt
051-0675
6.0.0
33 OF 119
32 OF 94
81
32
81
90
32 90
32 90
90
90
32
32 90
32 90
32
90
32
32
90
90
90
90
32 90
90
90
32 90
90
90
90
32 90
90
32
32 90
IN
IN
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN OUT
SYM_VER_2
G S
D
BI
BI
VCC
GND
SEL OE*
D+
D-
Y+
Y-
M+
M-
IN
NC
OUT
GND
VOUT
ON
VIN
IN
OUT
EN
MR*
GNDTHRM
IN
VDD
SENSE
RESET*
+-
PAD
(OD)
DLY
VREF
SYM_VER-1
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
L USB_BT_WAKE
Supervisor & CLKREQ # Isolation
Delay = 130 ms +/- 20%
H USB_BT
3.3V WLAN SwitchPart
25.8 mOhm Max
Load SwitchType
R(on)@ 2.5V
18.5 mOhm Typ
TPS22924C
155S0367
CURRENT SENSE1A PEAK
Max Current = 2A (85C)
516S1016
AIRPORT
SEL OUTPUT
BLUETOOTH
0603
FERR-120-OHM-3A
CERM
0.1uF10V20%
402PLACE_NEAR=J3501.1:2.54MM
0.1uF
PLACE_NEAR=J3501.1:2.54MMCERM402
20%10V
13 88
13 88
11 88
11 88
10%0.1UF
16V 0402X7R-CERM
PLACE_NEAR=J3501.5:2.54MM
10%0.1UF
16V 0402X7R-CERM
PLACE_NEAR=J3501.4:2.54MM
12 35 83 88
10%16V
0402X7R-CERM
0.01UF
20
11 18
0.1uF10V20%
402CERM
1/16W1%
402MF-LF
232K
1/16W1%
402MF-LF
100K
1/16W1%
402MF-LF
100K
40 41 83
10%0.1UF16V
0201X5R-CERM
NOSTUFF
0.6NH+/-0.1NH-0.85A0201
OMIT_TABLE
10%0.1UF16V
0201X5R-CERM
NOSTUFF
10%0.1UF16V
0201X5R-CERM
NOSTUFF0201
0.6NH+/-0.1NH-0.85A
OMIT_TABLE
10%0.1UF16V
0201X5R-CERM
NOSTUFF
X5R-CERM10%0.1UF16V
0201
NOSTUFF0.6NH+/-0.1NH-0.85A0201
OMIT_TABLE
NOSTUFF10%0.1UF16V
0201X5R-CERM
X5R-CERM10%0.1UF16V
0201
NOSTUFF0.6NH+/-0.1NH-0.85A
OMIT_TABLE0201
0.1UFNOSTUFF
X5R-CERM10%
0201
16V
13 88
13 88
3346
46
FERR-120-OHM-1.5A
PLACE_NEAR=J3501.18:2.54MM
0402-LF
DFN1006H4-3DMN32D2LFB4
NO_XNET_CONNECTION=TRUE
13 87
13 87
201
1/20W1%
MF
15K
PI3USB102EZLETQFN
CRITICAL
SIGNAL_MODEL=MOJO_MUX_USBONLY
12 21 37 40 65 78 83
10%0.1UF
0201CERM-X5R6.3V
42
CSPTPS22924
CRITICAL33 65
CRITICAL
TDFNSLG4AP041V
CRITICAL
F-RT-SMSSD-X29-D1
PLACE_NEAR=J3501.7:2.54MM
90-OHM-50MATCM0605-1
CRITICAL
117S0201 4 RES, 0OHM, 0201 L3570,L3571,L3573,L3574
X29C CONNECTOR
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=1 mm
VOLTAGE=3.3V
PP3V3_WLAN
PCIE_AP_D2R_PI_NPCIE_AP_D2R_PI_P
PM_WLAN_EN
AP_RESET_L
PP3V3_WLAN_F
PM_WLAN_EN
USB_BT_WAKEN
USB_BT_N
=BT_WAKE_L
PCIE_AP_D2R_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N
PCIE_AP_R2D_C_P
=PP3V3_S5_WLAN
=PP3V3_S5_WLAN
AP_CLKREQ_L
P3V3WLAN_VMON
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mmPP3V3_WLAN_R
VOLTAGE=3.3VVOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mmPP3V3_WLAN_F
PCIE_AP_R2D_C_N
=PP3V3_S4_BT
PM_SLP_S4_L
USB_BT_P
PCIE_AP_D2R_P
=PP3V3_S4_BT
WIFI_EVENT_L
PCIE_WAKE_L
USB_BT_CONN_P
VOLTAGE=3.3V
PP3V3_S3RS4_BT_FMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm
PCIE_AP_R2D_N
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_CONN_N
PCIE_CLK100M_AP_CONN_P
AP_CLKREQ_Q_L
USB_BT_CONN_N
AP_RESET_CONN_L
PCIE_AP_R2D_P
L3504
1 2
C3521 1
2
C3522 1
2
C35311 2
C3530
1 2
C35321
2
C35401
2
R35541
2
R35551
2
R35531
2
C35701
2
L35701 2
C35711
2
C35731
2
L35711 2
C35721
2
C35751
2
L35731 2
C35741
2
C35771
2
L35741 2
C35761
2
L350512
Q3510 3
1 2
R35121
2
U3510
6
7
3
4
5
810
9
2
1
C35101
2
U3550
C1
C2
A2
B2
A1
B1
U3540
6
5
7
3
8
4
2
9
1
J3501
19
20
21
1
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
L3501
1
2 3
4
dvt
051-0675
6.0.0
35 OF 119
33 OF 94
41 83
83 88
83 88
33 65
33 46
88
88
33 81
33 81
33 81
33 81
83 87
83
83 88
83 88
83 88
83
83 87
83
83 88
OUT
OUT
IN
IN
NC
08
NC
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
NC
08
IN
NC
RESET*
OUT
EN
MR*
GNDTHRM
IN
VDD
SENSE +-
PAD
(OD)
0.7V
DLY
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Gumstick3 Connector
Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA
Supervisor & CLKREQ# IsolationDelay = ~55ms
APN 343S0511
OOB Isolation
GND_VOID GND_VOID
514S0449
40
10VX5R-CERM0201PLACE_NEAR=L3700.1:1mm
0.1UF10%
PLACE_NEAR=J3700.1:3mm
FERR-26-OHM-6A
0603
CRITICAL
PLACE_NEAR=L3700.1:1mm
10VX5R-CERM0201
0.1UF10%
MF
1%100K1/20W
201
201
100K1/20W
MF
5% 1%
MF1/20W
232K
201
11
CERM-X5R10%0.1UF6.3V
0201
20
34
SOT89174LVC1G08
CRITICAL
BYPASS=U3711:5 mm
0201X5R-CERM
10V0.1UF
10%
13 88
13 88
13 88
13 88
13 88
13 88
13 88
13 88
16V 0201GND_VOID=TRUE
X5R-CERM0.1UF 10%
16V 0201X5R-CERMGND_VOID=TRUE
0.1UF 10%
16V 0201X5R-CERM0.1UF 10%GND_VOID=TRUE
0201GND_VOID=TRUE
16V X5R-CERM0.1UF 10%
16V 0201X5R-CERM0.1UF 10%GND_VOID=TRUE
GND_VOID=TRUEX5R-CERM16V 02010.1UF 10%
16V X5R-CERM 0201GND_VOID=TRUE
0.1UF 10%
16V 0201X5R-CERMGND_VOID=TRUE
10%0.1UF
11 88
11 88
13 88
13 88
13 88
13 88
13 88
13 88
13 88
13 88
34
40
20
18
F-RT-SM
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
SSD-GS3
TRUE
TRUE
TRUE
TRUE
TRUE
CRITICAL
TRUE
100K
MF
1%
201
1/20W
74LVC1G08
CRITICAL
SOT89140
10V
0201X5R-CERM
BYPASS=U3710:5 mm
0.1UF10%
SLG4AP016VTDFN
CRITICAL
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
SSD Connector
SSD_RESET_CONN_L
PCIE_SSD_R2D_N<1>
PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_P<3>
SSD_RESET_L
PCIE_SSD_R2D_N<0>
PCIE_SSD_R2D_N<3>PCIE_SSD_R2D_P<3>
PCIE_SSD_R2D_P<2>
PCIE_SSD_R2D_P<1>
PCIE_CLK100M_SSD_P
PCIE_SSD_D2R_P<3>
PCIE_SSD_D2R_P<2>
PCIE_SSD_D2R_N<3>
=SSD_CTRL_ENSMC_PWRFAIL_WARN_L
MIN_LINE_WIDTH=0.6mm
VOLTAGE=3.3VMIN_NECK_WIDTH=0.15mm
PP3V3_S0SW_SSD_FLT
SMC_OOB1_R2D_CONN_L
=SSD_CTRL_ENMAKE_BASE=TRUE
SSD_PWR_FET_EN
=PP3V42_G3H_SSDSAK=PP3V3_S0SW_SSD
=SSD_CTRL_ENSSD_CLKREQ_L
SSD_CLKREQ_CONN_L
P3V3SSD_VMON
SSD_DEVSLP
SMC_OOB1_D2R_CONN_L
SMC_OOB1_R2D_L
=PP3V3_S0SW_SSD
=PP3V3_S0_OOB1_PWRDN
=PP3V3_S0SW_SSD
SMC_OOB1_D2R_L
PCIE_SSD_D2R_N<1>
PCIE_CLK100M_SSD_N
PCIE_SSD_D2R_P<0>PCIE_SSD_D2R_N<0>
SSD_PCIE_SEL_L
PCIE_SSD_D2R_N<2>
=PP3V3_S0_SSD_AUX
PCIE_SSD_D2R_P<1>
NC_SSD_MFG_RSVD
PCIE_SSD_R2D_P<0>
PCIE_SSD_R2D_N<2>PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_P<2>
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_P<0>
C37021
2
L3700
1 2
C37011
2
R37421
2
R37401
2
R37411
2
C37401
2
U3711
2
1
3
6
4
C3719 1
2
C3716 1 2
C3717 1 2
C3713 1 2
C3712 1 2
C3715 1 2
C3714 1 2
C3711 1 2
C3710 1 2
J3700
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28 29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
495 50
51
52
53
54
55
56
57
58
59
6
60
61
62
63
7
8
9
R37001
2
U3710
2
1
3
6
4
C37181
2
U3740
6
5
7
3
8
4
2
9
1
dvt
051-0675
6.0.0
37 OF 119
34 OF 94
5
5
88
88
88
88
88
88
34 64
8134 45 81
34 45 81
81
34 45 81
81
88
88
NCNC
NCNC
OUT
IN
OUT
BI
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
IN
SYM 1 OF 3
DEBUG_15
DEBUG_14
DDR_PWR_SEL
SENSOR_WAKE*
PCIE_WAKE*
PCIE_CLKREQ*
JTAG_SRST*
JTAG_TRST*
JTAG_TMS
JTAG_TDO
PCIE_REFCLKN
DEBUG_03
DEBUG_04
DEBUG_05
DEBUG_09PCIE_RDP0
DEBUG_06
DEBUG_00
DEBUG_01
DEBUG_02
DEBUG_07
DEBUG_08
DEBUG_10
DEBUG_11
DEBUG_12
DEBUG_13
DEBUG_16
GPIO_00
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
I2C_CLK_DBG
I2C_CLK_SENSOR
I2C_DATA_DBG
I2C_DATA_SENSOR
JTAG_TCK
JTAG_TDI
MIPI_CP_CLK
PCIE_RDN0
PCIE_REFCLKP
PCIE_RST*
PCIE_TDN0
RESET*
SHUTDOWN*
UARTCTS
UARTRTS
UARTRXD
UARTTXD
XTAL_N
XTAL_P
MIPI_DM0
MIPI_DP0
MIPI_CM_CLK
PCIE_TDP0
PCIE_TESTN
MIPI_DP1
MIPI_DM1
STRAP_XTAL_FREQ
STRAP_XTAL_SEL
TEST_OUT
TEST_MODE
PCIE_TESTP
SYM 2 OF 3
DDR_CK_N0
DDR_CK_P0
DDR_CAS*
DDR_RAS*
DDR_CKE
DDR_AD00
DDR_AD01
DDR_AD02
DDR_AD03
DDR_AD04
DDR_AD05
DDR_AD06
DDR_AD07
DDR_AD08
DDR_AD09
DDR_AD10
DDR_AD11
DDR_AD12
DDR_AD13
DDR_AD14
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CS*
DDR_DM0
DDR_DM1
DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQS_N0
DDR_DQS_N1
DDR_DQS_P0
DDR_DQS_P1
DDR_RESET*
DDR_WE*
DDR_ZQ
SR_VLXD_O
VDD_1P35A
PCIE_GND
XTAL_AVDD1P2
VDDC
VDD1P8_O
SR_VLXC_O
SR_VDD_3P3D
SR_VDD_3P3C
SR_PVSSD
SR_PVSSC
PMU_AVSS
OTP_VDD3P3
DDR_VDDIO_CK
MIPI_AGND
VDD_3P3A
DDR_VREF_O
VSSC
XTAL_AVSS
DDR_VDDIO
PCIE_VDD1P2
VSENSE_D
VSENSE_C
PCIE_PVDD1P2
DDR_AVDD1P8
MIPI_AVDD1P8
PLL_VDD1P8
VDD1P2_O
VDDO18
SYM 3 OF 3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
NCNCNCNC
NCNC
NCNCNC
NCNCNCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PU on PCH page
PD = 1.35V
(=PP3V3_S3RS0_CAMERA)
(=PP3V3_S3RS0_CAMERA)
PU = 25MHz
A1 SILICON BUG
L3902:1L3901:1
11
36
36 83
36 83
5%
201
1/20WMF
100K
NOSTUFF
5%
201MF1/20W
100K
NOSTUFF
13 18
20
6.3VCERM-X5R0201
0.1UF10%
0201
6.3VCERM-X5R
0.1UF10%20%
1.0UF
0201-1
6.3VX5R
6.3VCERM-X5R0201
0.1UF10%20%
1.0UF
0201-1
6.3VX5R
BYPASS=U3900.D6:2.54MM
6.3VCERM-X5R0201
0.1UF10%
BYPASS=U3900.D6:2.54MM
6.3VCERM-X5R0201
0.1UF10%
5%
201
1/20WMF
100K
36
36
36 88
36 88
36 88
36 88
36 88
36 88
5%
201
1/20WMF
100K
CAM_XTAL:YES
5%
201
1/20WMF
100K
CAM_XTAL:NO
5%
201
1/20WMF
100K
1008
1.0UH-1.6A-55MOHM
PLACE_NEAR=U3900.M13:4MM
1008
PLACE_NEAR=U3900.K13:4MM
1.0UH-1.6A-55MOHMBYPASS=U3900.K13:2.54MM
4.7UF20%
402
6.3VX5R
402
20%4.7UF
PLACE_NEAR=U3900.M13:2.54MM6.3VX5R
0402
22NH
BYPASS=U3900.L7:2.54MM
6.3VCERM-X5R0201
0.1UF10%
4.7UF20%
402
6.3VX5R
PLACE_NEAR=U3900.M14:2.54MM
4.7UF20%
402
6.3VX5R
BYPASS=U3900.J1:2.54MM
6.3VCERM-X5R0201
0.1UF10%
BYPASS=U3900:5mm
6.3VCERM-X5R0201
0.1UF10%
BYPASS=U3900:5mm
6.3VCERM-X5R0201
0.1UF10%
BYPASS=U3900:5mm
6.3VCERM-X5R0201
0.1UF10%20%
402
4.7UF
BYPASS=U3900:7mm
6.3VX5R
CERM402-LF
20%2.2UF
BYPASS=U3900.F15:2.54MM
6.3V
402
10V1UF
BYPASS=U3900.G15:2.54MM
X5R10%
6.3VCERM-X5R0201
0.1UF10%
CRITICAL
BCM15700
OMIT_TABLE
FBGA
OMIT_TABLE
FBGA
CRITICAL
BCM15700
OMIT_TABLE
FBGABCM15700
CRITICAL
0201
16V1000PF
X7R-CERM
BYPASS=U3900.J1:2.54MM
10%
0201
BYPASS=U3900:3mm
16V1000PF
X7R-CERM10%
0201X7R-CERM
1000PF16V
BYPASS=U3900.L7:2.54MM
10%
BYPASS=U3900:3mm
X7R-CERM
1000PF16V
0201
10%
BYPASS=U3900.D7:2.54MM
X7R-CERM
1000PF16V
0201
10%
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36 91
36
5%
201
1/20WMF
100K
NO STUFF
5%
201
1/20WMF
100K
201
1/20WMF
240
1%
5%
201
1/20WMF
1K5%
201
1/20WMF
1K
36 91
SM
SM
5%
201
1/20WMF
100K
NOSTUFF
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
0201-1
20%1.0UF6.3VX5R
36 91
0201-1
1.0UF20%6.3VX5R
20%10UF4V
402X5R
402
10UF20%4VX5R
5%
201
1/20WMF
100K
CAM_A1
4.7UF20%
402
6.3VX5R
402
20%4.7UF6.3VX5R
0603
220-OHM-1.4A
0603
220-OHM-1.4A
5%
0
0201
1/20WMF
NOSTUFF
12 33 83 88
BYPASS=U3900.L9:2.54MM
6.3VCERM-X5R
0.1UF10%
0201
6.3VCERM-X5R0201
0.1UF10%
BYPASS=U3900.L9:2.54MM
0201X7R-CERM
1000PF16V
BYPASS=U3900.F9:2.54MM
10%
BYPASS=U3900.F9:2.54MM
6.3V0.1UF10%
0201CERM-X5RX7R-CERM
1000PF16V
0201
BYPASS=U3900.F6:2.54MM
10%
BYPASS=U3900.F6:2.54MM
6.3VCERM-X5R0201
0.1UF10%
5%
201
1/20WMF
51K5%
201
1/20WMF
51K
5%
201MF
100K1/20W
5%
201
1/20WMF
100K
5%
201
1/20WMF
100K
NOSTUFF
MF1/20W
201
5%330K
MF1/20W
201
5%330K
MF1/20W
201
5%330K
5%
201
1/20WMF
NOSTUFF
100K
5%
201
1/20WMF
100K
NOSTUFF
36 91
SYNC_DATE=04/26/2013
Camera 1 of 2SYNC_MASTER=CLEAN_J45
PP1V8_CAM
PCIE_CAMERA_R2D_N
PP1V2_CAM
P1V35_CAM_SRVLXD_PHASE
TP_CAM_LV_JTAG_TMSTP_CAM_LV_JTAG_TDOTP_CAM_LV_JTAG_TDITP_CAM_LV_JTAG_TCKTP_CAM_TEST_MODE2TP_CAM_TEST_MODE1TP_CAM_TEST_MODE0
TP_CAM_LV_JTAG_TRSTN
GND_CAM_PVSSC
MEM_CAM_A<14>MEM_CAM_A<13>
=PPVDDIO_S3RS0_CAMCLK
MEM_CAM_A<12>
MEM_CAM_BA<0>
=PP3V3_S3RS0_CAMERA
PCIE_CLK100M_CAMERA_C_P
PP1V8_CAMMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
VOLTAGE=1.8V
PP1V2_CAM_XTALPCIEVDD
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=1.2V
PP1V2_CAM_PCIE_VDD_FLT
GND_CAM_PVSSD
PP1V8_CAM
CAM_GPIO3
PP1V8_CAM
P1V2_CAM_SRVLXC_PHASE
CAM_RAMCFG2CAM_RAMCFG1
CAM_RAMCFG0
CAM_XTAL_SEL
CAM_XTAL_FREQ
CAM_TEST_MODECAM_TEST_OUT
CAM_UARTCTSTP_CAM_UARTRTS
CAM_UARTRXDTP_CAM_UARTTXD
CAM_RAMCFG1
I2C_CAM_SMBDBG_DATI2C_CAM_SMBDBG_CLK
MIPI_CLK_NMIPI_CLK_P
GND_CAM_PVSSC
VOLTAGE=1.2V
PP1V2_CAMMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
PP1V8_CAM
MIN_NECK_WIDTH=0.2MM
PP1V2_CAM_XTALPCIEVDD
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.2V
PP1V35_CAM
PP1V35_CAMPP1V2_CAM
PP1V2_CAM_PCIE_PVDD_FLTMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
VOLTAGE=1.2V
PP0V675_CAM_VREFMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0.675V
DIDT=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
P1V2_CAM_SRVLXC_PHASE
P1V35_CAM_SRVLXD_PHASEMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
DIDT=TRUE
MEM_CAM_ZQ_S2
MEM_CAM_A<0>MEM_CAM_A<1>MEM_CAM_A<2>MEM_CAM_A<3>
MEM_CAM_A<5>MEM_CAM_A<4>
MEM_CAM_A<6>MEM_CAM_A<7>MEM_CAM_A<8>
MEM_CAM_A<10>MEM_CAM_A<9>
MEM_CAM_A<11>
MEM_CAM_BA<1>MEM_CAM_BA<2>
MEM_CAM_CLK_PMEM_CAM_CLK_N
MEM_CAM_DM<0>MEM_CAM_DM<1>
MEM_CAM_CKEMEM_CAM_CS_L
MEM_CAM_DQ<15>MEM_CAM_DQ<14>MEM_CAM_DQ<13>MEM_CAM_DQ<12>MEM_CAM_DQ<11>MEM_CAM_DQ<10>MEM_CAM_DQ<9>MEM_CAM_DQ<8>MEM_CAM_DQ<7>MEM_CAM_DQ<6>MEM_CAM_DQ<5>MEM_CAM_DQ<4>MEM_CAM_DQ<3>MEM_CAM_DQ<2>MEM_CAM_DQ<1>MEM_CAM_DQ<0>
CAM_JTAG_SRST_LCAMERA_PWR_ENCAM_SENSOR_WAKE_L
TP_CAM_JTAG_TMS
TP_CAM_JTAG_TDITP_CAM_JTAG_TDO
TP_CAM_JTAG_TRST_LCAM_JTAG_SRST_L
TP_CAM_JTAG_TCK
I2C_CAM_SMBDBG_DAT
I2C_CAM_SMBDBG_CLK
MIPI_DATA_NMIPI_DATA_P
PCIE_CAMERA_R2D_P
PCIE_CAMERA_D2R_C_NPCIE_CAMERA_D2R_C_P
PP1V8_CAM
PP1V8_CAM
CAM_DEBUG_RESET_LCAM_PWR_SEL
CAM_XTAL_SEL
PP1V8_CAM
CAM_XTAL_FREQ
GND_CAM_PVSSD
CAM_UARTCTS
CAM_UARTRXD
CLK25M_CAM_CLKPCLK25M_CAM_CLKN
CAMERA_CLKREQ_L
PCIE_CLK100M_CAMERA_C_N
MEM_CAM_DQS_P<0>MEM_CAM_DQS_N<0>
MEM_CAM_DQS_P<1>MEM_CAM_DQS_N<1>
MEM_CAM_RAS_LMEM_CAM_WE_LMEM_CAM_CAS_LMEM_CAM_RESET_L
CAM_TEST_MODEPP1V8_CAM
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V
GND_CAM_PVSSD
PCIE_WAKE_L
GND_CAM_PVSSCMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V
CAM_TEST_OUT
CAM_PCIE_RESET_LCAM_PCIE_WAKE_L
PP1V2_CAM_XTALPCIEVDD
CAM_RAMCFG2
I2C_CAM_SCK
I2C_CAM_SDA
PP1V35_DDR_CLKMIN_NECK_WIDTH=0.2MMVOLTAGE=1.35V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP1V35_CAM
VOLTAGE=1.35V
CAM_RAMCFG0
R39301
2
R39321
2
C39001
2
C39241
2
C39231
2
C39221
2
C39211
2
C39101
2
C39511
2
R39011
2
R39061
2
R39071
2
R39041
2
L3901
1 2
L3902
1 2
C39121
2
C39151
2
L3906
1 2
C39161
2
C39281
2
C39261
2
C39191
2
C39371
2
C39351
2
C39401
2
C39421
2
C39411
2
C39391
2
C39601
2
U3900
G12
B11
C14
B14
A15
E11
E10
F11
F10
G11
G10
H11
H10
J10
K11
K10
L11
L10
R12
P12
P11
P10
P9
N11
N10
N9
D15
R10
C15
R9
C11
F13
E12
F12
D12
D11
R7
P7
R8
R6
P8
P6
P13
A7
B7
A10
B10
R14
B8
A8
C9
B9
N12
E15
R13
H12
C13
C12
M10
J12
D13
D14
E13
E14
A12
A13
U3900
L3
M4
N3
M3
M1
M2
P4
N2
P3
P2
J4
R2
L1
P1
R4
K3
L2
K2
H4
G2
H2
J3
L4
C1
C4
C2
E3
E4
D3
F3
F1
F4
F2
B5
C3
B1
B4
A5
C5
B2
B3
D2
A3
E2
A2
H3
R3
J2
G3
U3900
J1
A4
D4
G4
K4
N4
G5
N5
N7
N8
N6
L7
D7
C10
C7
D9
C8
D6
G14
M12
N13
P14
P15
R15
K15
L12
L13
L14
L15
M14
M15
N15
H14
H15
J13
J14
J15
M13
N14
K13
K14
F15
G15
F14
J11
F6
F7
F8
F9
L6
L5
L8
L9
B15
R11
M11
K12
A1
A6
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
B6
J9
K1
K5
K6
K7
K8
K9
A14
M9
N1
D1
P5
R1
R5E9
D5
E5
G1
G6
G7
G8
B13
B12
C39181
2
C39341
2
C39171
2
C39361
2
C39381
2
R39101
2
R39111
2
R39121 2
R39131
2
R39141
2
XW39001 2
XW39011 2
R39901
2
C39901
2
C39271
2
C39301
2
C39321
2
C39311
2
C39331
2
R39151
2
C39141
2
C39131
2
L3903
1 2
L3904
1 2
R39911 2
C39751
2
C39741
2
C39731
2
C39721
2
C39711
2
C39701
2
R39751
2
R39761
2
R39201
2
R39211
2
R39341
2
R39311
2
R39331
2
R39351
2
R39361
2
R39371
2
dvt
051-0675
6.0.0
39 OF 119
35 OF 94
35 36
35
35
35
19
46 81
35
35
35 36
35 36
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35 36 91
35 36 91
35
36 91
35
35
35
35
35
35
35 36
35 36
35
35 36
35
35
35
35
35
35 36
35
35
35 36 91
35
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
IN
IN
IN
BI
BI
SYM_VER-1
SYM_VER-1
BI
IN
A4
A14
DQSL*
DQL1
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ VSS
CAS*
RAS*
BA2
BA0
BA1
DQL7
DQL4
DQL3
DQL2
DQL0
ZQ
DQU3
DQU2
DQU4
CS*
CKE
DQU7
DQU6
DQSU*
DQU0
DQSL
A13
A11
A10/AP
A8
A5
A7
A9
CK
DML
DMU
DQL5
DQL6
DQSU
DQU1
DQU5
VREFCA
VREFDQ
CK*
WE*
VDDQ
A12/BC*
NCNCNCNCNC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NCNC
OUT
IN
OUT
OUT
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
remove DRAM SPD Straps
1
0
0
0
CFG 0
0 1
CFG 1
MICRON
SAMSUNG
HYNIX
VENDOR
1
0
1
1
CFG 2
A
ELPIDA
DIE REV
DRAM CFG Chart
96.2 mA peak77.2 mA nominal max
ALS
CAMERA SENSOR
518S0892
B
NOTE: TBD PPM crystal required
35 88
35 88
13 88
13 88
X5R-CERM 020116V0.1UF 10%
X5R-CERM 020116V0.1UF 10%
16V 0201X5R-CERM0.1UF 10%
16V 0201X5R-CERM0.1UF 10%
13 88
13 88
35 88
35 88
NO STUFF
MF1/20W
0201
0
5%
NO STUFF
MF1/20W
0201
0
5%
MF1/20W
0201
0
5%
CAM_XTAL:YES
MF1/20W
0201
0
5%
5%
0
02011/20W
MF
201
0.47UF
CERM-X5R-14V20%
BYPASS=U4000.H9:4mm
10V
2.2UF20%
X5R-CERM402
BYPASS=U4000.K2:4mm
20%10VX5R-CERM402
2.2UF
BYPASS=U4000.D2:4mm
1M1%
NOSTUFF
MF1/20W
201
NP0-C0G-CERM0201
5%
CAM_XTAL:YES
25V
12PF
0201
25VNP0-C0G-CERM
12PF
5% CAM_XTAL:YES
10%0.1UF
0201CERM-X5R6.3V
10%0.1UF
0201CERM-X5R6.3V
BYPASS=U4000.R9:4mm
0.1uF10V
CERM402
20%
35 83
35 83
10%0.1UF
0201CERM-X5R6.3V
35 91
35 91
35 91
35 91
0402-LF
FERR-120-OHM-1.5A
X5R
10UF4V20%
402
BYPASS=U4000.B2:4mm
10UF
402
4VX5R
20%
BYPASS=U4000.A1:4mm
CRITICAL
90-OHM-50MATCM0605-1
PLACE_NEAR=J4002.2:2.54MM
CRITICAL
TCM0605-190-OHM-50MA
PLACE_NEAR=J4002.5:2.54MM43 83
43 83
201
1/20WMF
1K1%
201
1/20WMF
1K1%
4GB-DDR3-256MX16
K4B4G1646B-HYK0
CRITICAL
OMIT_TABLE
FBGA
35 91
35 91
10%0.1UF
0201CERM-X5R6.3V
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
10%0.1UF
0201CERM-X5R
6.3V
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35
35 91
35 91
35 91
35 91
201
1/20WMF
84.51%
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
35 91
201
1/20WMF
NO STUFF
821%
35 91
5%
201
1/20WMF
1K
5%
201
1/20WMF
NOSTUFF
1K
201
1/20WMF
2401%
5%
0
02011/20WMF
CAM_WAKE:YES
25V
100PF
0201NP0-CERM
5%
5%0
0201
1/20WMF
CAM_WAKE:NO
CCR20-AK7100-1F-RT-SM
CRITICAL
X5R-CERM 020116V0.1UF 10%
X5R-CERM 020116V0.1UF 10%
0402-LF
FERR-120-OHM-1.5A
NOSTUFF
5%
NO STUFF
100PF
0201NP0-CERM25V
35 91
3.2X2.5MM-SM
25.000MHZ-20PPM-12PF-85CCAM_XTAL:YES
35
35
35 88
35 88
11 88
11 88
5%
201
1/20WMF
100K
19 87
Camera 2 of 2SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
CAM_SENSOR_WAKE_LCAM_SENSOR_WAKE_L_CONN
PP1V8_CAM
PCIE_CLK100M_CAMERA_N
PCIE_CAMERA_D2R_C_N
PCIE_CLK100M_CAMERA_P
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_R2D_C_P
PCIE_CLK100M_CAMERA_C_N
PCIE_CLK100M_CAMERA_C_P
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_R2D_N
PCIE_CAMERA_R2D_P
CLK25M_CAM_XTALP_R
SYSCLK_CLK25M_CAMERA
CLK25M_CAM_CLKN
CLK25M_CAM_CLKP
PP1V35_CAM
MEM_CAM_A<14>MEM_CAM_A<13>
MEM_CAM_BA<2>
MEM_CAM_CLK_N
MIPI_CLK_P
MIPI_CLK_N
MIPI_DATA_P
MIPI_DATA_NMIPI_DATA_CONN_PMIPI_DATA_CONN_N
I2C_CAM_SDAI2C_CAM_SCK=I2C_ALS_SCL=I2C_ALS_SDA
CAM_SENSOR_WAKE_L_CONN
=PP5V_S0_ALSCAMMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=5V
PP5V_S3RS0_ALSCAM_F
MEM_CAM_DQ<8>
MEM_CAM_BA<1>
MEM_CAM_A<11>
MEM_CAM_ZQ_DDR
MEM_CAM_RESET_L
MEM_CAM_A<3>
MEM_CAM_A<0>
MEM_CAM_A<6>
MEM_CAM_DM<0>
MEM_CAM_DQS_N<0>
MEM_CAM_DQ<1>
MEM_CAM_DQ<7>
MEM_CAM_DQ<4>MEM_CAM_DQ<3>MEM_CAM_DQ<2>
MEM_CAM_DQ<0>
MEM_CAM_DQ<11>MEM_CAM_DQ<10>
MEM_CAM_DQ<12>
MEM_CAM_DQ<15>MEM_CAM_DQ<14>
MEM_CAM_DQS_N<1>
MEM_CAM_DQS_P<0>
MEM_CAM_DM<1>
MEM_CAM_DQ<5>MEM_CAM_DQ<6>
MEM_CAM_DQS_P<1>
MEM_CAM_DQ<9>
MEM_CAM_DQ<13>
MEM_CAM_A<2>MEM_CAM_A<1>
MEM_CAM_A<7>MEM_CAM_A<8>
MEM_CAM_A<10>MEM_CAM_A<9>
MEM_CAM_A<12>
MEM_CAM_BA<0>
MEM_CAM_RAS_LMEM_CAM_CAS_LMEM_CAM_WE_L
MEM_CAM_A<4>MEM_CAM_A<5>
MEM_CAM_CKE_R
PP0V675_CAM_VREF
PP0V675_MEM_CAM_VREFCAMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0.675V
MIPI_CLK_CONN_PMIPI_CLK_CONN_N
=PP5V_S3_ALSCAM
MEM_CAM_CKE
MEM_CAM_CLK_P
MEM_CAM_CS_L
MEM_CAM_ODT
CLK25M_CAM_XTALP
VOLTAGE=0.675VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmPP0V675_MEM_CAM_VREFDQ
CLK25M_CAM_XTALN
C40091
2
C40071
2
C40051
2
C40111
2
C4010 1
2 R40051
2
C4033 1 2
C4032 1 2
C4031 1 2
C4030 1 2
R40091 2
R40101 2
R40081 2
R40071 2
R40001 2
C40041
2
C40081
2
C40061
2
R40121
2
C40151 2
C40141 2
C4013 1
2
L4010
12
C40031
2
C40021
2
L4009
1
2 3
4
L4007
1
2 3
4
R40221
2
R40231
2
U4000N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E7
D3
E3
F7
F2
F8
H3
H8
G2
H7
F3
G3
C7
B7
D7
C3
C8
C2
A7
A2
B8
A3
J1
J9
L1
L9
M7
K1
J3
T2
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
R40201
2
R40211
2
R40021
2
R40031
2
R40041
2
R40301 2
C40161
2
R40311
2
J4002
14
13
1
10
11
12
2
3
4
5
6
7
8
9
C4061 1 2
C4062 1 2
L4011
12
R40061
2
Y4000
24
13
dvt
051-0675
6.0.0
40 OF 119
36 OF 94
3536 83
35
35 91
83 91
83 91
36 83
8183
35 91
91
83 91
83 91
81
91
91
OUT
OUT
IN
IN
SYM_VER-1
GND
VBUSSSTX+
SSRX-
GND
SSTX-
D+
D-
GND
SXRX+
BI
BI
IN
OUT
IN
OUT
VCC
GND
SELOE*
D+
D-
Y+
Y-
M+
M-
FAULT*
IN_1
IN_0
ILIM
OUT1
OUT2
EN
GNDTHRMPAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX
USB/SMC Debug Mux
SEL=0 Choose SMC
Place L4605 and L4615 at connector pin
Left USB Port A
SEL=1 Choose USB
We can add protection to 5V if we want, but leaving NC for now
USB Port Power Switch
514-093413 87
13 87
13 87
13 87
0603
CRITICAL
FERR-120-OHM-3A
16V10% 0201X5R-CERM
0.1UF
GND_VOID=TRUE
16V10% 0201X5R-CERM
0.1UFGND_VOID=TRUE
TCM0605-190-OHM-50MA
CRITICAL
TSSLP-2-1
CRITICAL
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
ESD0P2RF-02LS
TSSLP-2-1ESD0P2RF-02LS
CRITICALCRITICAL
TSSLP-2-1ESD0P2RF-02LS
6.3V20%
CASE-B2-SM1POLY-TANT
220UF-35MOHM
CRITICAL
1/16W
402MF-LF
22.1K1%
1%22.1K
MF1/20W
201
NOSTUFF
MF1/20W
0201
0
5% NOSTUFF
MF1/20W
0201
0
5%
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
USB3.0-J44-ALTF-RT-TH
CRITICAL
603
6.3V20%X5R
10UF20%
402CERM
0.1UF10V
13 87
13 87
0.1UF
CERM20%10V
402
100K1/16WMF-LF402
5%
40 41 87
40 41 87
40
16V20%
0402X7R-CERM
0.01UF18
X5R
10UF20%
6.3V
603
MF-LF402
1/16W
05%
NOSTUFF
0.47UF10VX5R
0402
10%
CRITICAL
SIGNAL_MODEL=MOJO_MUX_USBONLY
PI3USB102EZLETQFN
SONTPS2557DRB
CRITICAL
SYNC_MASTER=CLEAN_J45
USB 3.0 CONNECTORSSYNC_DATE=04/26/2013
USB3_EXTA_R2D_P
USB3_EXTA_D2R_P
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mm
PP5V_S3_LTUSB_A_ILIM
=PP5V_S3_LTUSB
USB_LT1_NUSB_LT1_P
USB_EXTA_N
SMC_DEBUGPRT_EN_L
USB_EXTA_P
USB_PWR_EN
=PP3V42_G3H_SMCUSBMUX
PM_SLP_S4_L
USB_ILIM_R
USB_ILIMUSB_EXTA_OC_L
SMC_DEBUGPRT_RX_LSMC_DEBUGPRT_TX_L
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P
MIN_NECK_WIDTH=0.25 mmVOLTAGE=5V
PP5V_S3_LTUSB_A_FMIN_LINE_WIDTH=0.5 mm
USB3_EXTA_R2D_N
USB3_EXTA_D2R_N
L4605
1 2
C4696 1
2
C4695 1
2
C46911
2
C4650 1
2
R46501
2
C4605 1
2
C4690 1
2
R46901
2
C4692 1
2
U4650
6
7
3
4
5
8 10
9
2
1
U4600
4
8
1
5
2
3
6
7
9
C4611 1 2
C4610 1 2
L4600
1
2 3
4
D4611
1
2D4610
1
2
D4613
1
2D4612
1
2
R46001
2
R46011
2
R46511 2
R46521 2
D4600
1
2D4601
1
2
J4600
5
6
4
7
10
11
20
21
22
23
12
13
14
15
16
17
18
19
9
3
2
8
1
dvt
051-0675
6.0.0
46 OF 119
37 OF 94
87
81
87
87
81
12 21 33 40 65 78 83
87
8787
NC
P2_4
P2_6
VDD
P0_4
P0_2
P2_0P2_2P
0_0
P2_3P2_1P4_7P4_5P4_3P4_1P3_7P3_5P3_3P3_1P5_7P5_5P5_3P5_1
P1_1
P1_3
P1_5
P1_7
P7_7
VSS
D+
D-VDD
P7_0
P1_0
P1_2
P1_4
P1_6 P5_0
P5_2P5_4P5_6P3_0P3_2P3_4
P4_0P4_2P4_4P4_6
P3_6
P2_5
P2_7
P0_3
VSS
P0_5
P0_7
P0_6
PADTHRML
(SYM-VER2)
P0_1
OUT
NC
NC NC
NC
IN
S
D
G
OUT
OUT
VDD
OUT_1
GNDTHRM
OE
OUT_ALL#
OUT_3
OUT_2
IN_1
IN_3
IN_2
(IPD)
(IPD)
(IPD)
(IPD)
PAD
IN
NCNC
Apple Inc.
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REVISION
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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
SMC Manual Reset & IsolationLeft shift, option & control keys combined with power button cause SMC RESET# assertion.
Keys ANDed with PSoC power to isolate when PSoC is not powered.
No IPD on OE input pin PP3V3_S4 (symbol error).
IPD Flex Connector
TPAD Buttons Disable
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
LID CLOSE => SMC_LID_LC < 0.50V
PSOC USB CONTROLLER
0.255E-6 W
4MA (MAX)VIN
516S0689
PSOC
3V3 LDO
TMP102
18V BOOSTER
VOUT
VDD
60MA (MAX)
8MA (TYP)
14MA (MAX)
IC
VDD
V+
CURRENT
80UA
10UA
60MA (MAX)
4.7 OHM
10 OHM
1.5 OHM
0.2 OHM
2.55 KOHM
R_SNS
0.0188 V
0.021 V
0.012 V
0.012 V
294E-6 W
96E-6 W
0.72E-3 W
75.2E-6 W
0.6 V
0.0255 V
0.204 V
V_SNS POWER
16.32E-6 W
36E-3 W
(PP3V3_S3_PSOC)
ISSP SDATA/I2C SDAISSP SCLK/I2C SCL
PIN NAME
Pull-up in U5110.
Keyboard Connector518S0752
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
- TRACKPAD PICK BUTTONS- SPI HOST TO Z2- USB INTERFACES TO MLB
- KEYBOARD SCANNER
337S4426
BYPASS=U5701.22:19:5 mm
NP0-CERM0201
25V5%100PF
10%6.3VCERM-X5R
0.1UF
0201
BYPASS=U5701.22:19:8 mmBYPASS=U5701.22:19:11 mm
6.3V20%X5R402
4.7UF
MLF-1CY8C24794
OMITCRITICAL
42
1.5
MF-LF1/16W5%
402
PLACE_SIDE=BOTTOM
1/20WMF
220K
201
5%
BYPASS=U5701.49:50:5 mm
0201
100PF5%NP0-CERM25V
10%6.3V0.1UF
BYPASS=U5701.49:50:8 mm
CERM-X5R0201
BYPASS=U5701.49:50:11 mm
6.3V20%X5R
4.7UF
402
0201
10V10%0.1UF
X5R-CERMPLACE_NEAR=L4807.1:2MM
FERR-120-OHM-1.5A
0402-LF
PLACE_NEAR=J5800.18:3MM
0201
1/20WMF
5%
0
NOSTUFF
0201
0.1UF
CERM-X5R6.3V10%
49.9K1%
MF1/20W
201
CRITICAL
55560-0228M-ST-SM
40 41 42 83
DMN5L06VK-7SOT-563
CRITICAL
41
0.1UF
X7R-CERM
BYPASS=U4850.10:5:5 mm
0402
16V10%
40 41 83
CERM
0.1UF
402
10V20%
PLACE_NEAR=J4813.5:5MMMF-LF402
1/16W5%
1K
402
1/16WMF-LF
0
5%
113
MF-LF402
1/16W1%
F-RT-SM
CRITICAL
FF14A-30C-R11DL-B-3H
TQFNSLG4AP4103
1/20W
24
MF
5%
201
1/20WMF
24
201
5%
65
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
KEYBOARD/TRACKPAD (1 OF 2)
=PP3V42_G3H_TPAD Z2_KEY_ACT_L
MIN_NECK_WIDTH=0.20MMVOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
PP3V3_TPAD_CONN
Z2_MISO PICKB_L
Z2_CS_L
SMC_LID
BUTTON_DISABLE
=PP3V3_S4_TPAD
WS_KBD23WS_KBD22WS_KBD21
=I2C_TPAD_SDA
=PP5V_S5_TPAD
PSOC_SCLK
PSOC_F_CS_L
PSOC_MISOPSOC_MOSI
Z2_CLKIN
Z2_HOST_INTN
WS_KBD4
WS_KBD20WS_KBD19WS_KBD18
WS_KBD5
TP_P7_7Z2_CLKIN
TP_ISSP_SDATA_P1_0WS_KBD6
TP_PSOC_SDATP_PSOC_SCL
TP_ISSP_SCLK_P1_1TP_PSOC_P1_3
Z2_HOST_INTNWS_LEFT_SHIFT_KEY
BUTTON_DISABLE
=PP3V3_S4_TPAD
WS_KBD17WS_KBD16N
WS_KBD14WS_KBD15_C
WS_KBD12WS_KBD13
WS_KBD11WS_KBD10WS_KBD9WS_KBD8
WS_KBD3
USB_TPAD_R_N
USB_TPAD_R_P
WS_CONTROL_KEYZ2_KEY_ACT_L
PSOC_MISOPSOC_F_CS_LPSOC_MOSIPSOC_SCLKZ2_MISOZ2_CS_L
Z2_SCLKZ2_MOSI
TPAD_VBUS_EN
USB_TPAD_P
USB_TPAD_N
WS_LEFT_SHIFT_KEY
=PP3V3_S4_TPAD
WS_CONTROL_KEY
WS_LEFT_OPTION_KEYWS_LEFT_SHIFT_KBD
WS_CONTROL_KBD
WS_LEFT_OPTION_KBD
=PP3V3_S4_TPAD
WS_KBD15_CAPWS_KBD16_NUM
WS_KBD8WS_KBD7
WS_CONTROL_KBDWS_LEFT_OPTION_KBDWS_LEFT_SHIFT_KBD
WS_KBD23WS_KBD22
WS_KBD19WS_KBD20WS_KBD21
WS_KBD11
WS_KBD13WS_KBD14
WS_KBD18
WS_KBD6WS_KBD5WS_KBD4WS_KBD3WS_KBD2WS_KBD1
WS_KBD15_C
SMC_ONOFF_L WS_KBD_ONOFF_L
WS_LEFT_OPTION_KEY
WS_KBD7WS_KBD1WS_KBD2
Z2_MOSI
SMC_TPAD_RST_L
Z2_SCLK
=PSOC_WAKE_LPICKB_L
VOLTAGE=5VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM
PP5V_S5_CUMULUS=I2C_TPAD_SCL
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM
VOLTAGE=3.3V
PP3V3_S3_PSOC
WS_KBD16N
WS_KBD17
=PP3V42_G3H_TPAD
WS_KBD12
WS_KBD10WS_KBD9
C4850 1
2
C4810 1
2
R48101 2
R48151 2
R48141 2
J4813
31
32
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
U4850
5
1
2
3
4
9
8
7
6
11
10
R48021 2
R48011 2
C48021
2
C48031
2
C48011
2
U4801
20
21
45
54
46
53
47
52
48
51
25
18
26
17
27
16
28
15
412
421
43
56
44
55
3310
349
358
367
376
385
394
403
2914
3013
3112
3211
24
23
57
22
49
19
50
R48042 1
R48031
2
C48041
2
C48051
2
C48061
2
C48071
2
L4807
1 2
R48081 2
C48081
2
R48001
2
J4800
1
10
1112
1314
1516
1718
19
2
20
2122
34
56
78
9
Q4801 6
2 1
48 OF 119
6.0.0
051-0675
dvt
38 OF 94
38 81 38 83
38 83 38 83
38 83
38
38 81 83
38 83
38 83
38 83
43 83
81 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38
38
38 81 83
38 83
38
38 83
38
38 83
38 83
38 83
38 83
38 83
38 83
38 83
87
87
38
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
13 87
13 87
38
38 81 83
38
38
38 83
38 83
38 83
38 81 83
83
83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38 83
38
83
38
38 83
38 83
38 83
38 83
38 83
38 83
43 83
38
38 83
38 81
38 83
38 83
38 83
NCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
516S0899
Keyboard Backlight Connector
.
CRITICAL
AA07A-S010-VA1F-ST-SM
SYNC_DATE=04/26/2013
KEYBOARD/TRACKPAD (2 OF 2)SYNC_MASTER=CLEAN_J45
KBDBKLT_RETURN2
KBDBKLT_RETURN1
PPVOUT_S0_KBDBKLT
J4915
11
12
13
14
1
10
2
34
56
78
9
dvt
051-0675
6.0.0
49 OF 119
39 OF 94
62 83
62 83
62 83
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0AD1
LPC0AD2
AIN08
AIN07
LPC0CLKRUN*
LPC0PD*
AIN13
AIN14
PM7/FAN0TACH0
PM6/FAN0PWM0
AIN04
C1-
I2C2SDA
AIN05
AIN09
AIN11
AIN21
AIN23
PK7/FAN0TACH1
AIN15
AIN06
AIN10
AIN20
AIN22
T1CCP1/PJ1
PK5
LPC0AD0
AIN12
PECI0RX
PECI0TX
PK6/FAN0PWM1
LPC0RESET*
PQ0/IRQ124
PP6/IRQ122
PN3/FAN0TACH2
I2C0SDA
AIN01
AIN00
PQ1/IRQ125
I2C0SCL
U1TX/PB1
USB0DP
USB0DM
AIN03
AIN02
T0CCP1/PB7
T0CCP0/PB6
PQ2/IRQ126
U1RX/B0
LPC0SCI*
AIN17
AIN16
PN2/FAN0PWM2
WT4CCP1/PH7
AIN18
AIN19
WT4CCP0/PH6
WT3CCP1/PH5
WT5CCP1/PM3
LPC0SERIRQ
PH3/FAN0TACH5
WT3CCP0/PH4
PH2/FAN0PWM5
PP3/IRQ119
PP4/IRQ120
C0-
WT2CCP0/PH0
WT2CCP1/PH1
PQ5/IRQ129
PP7/IRQ123
WT0CCP0/PG4
I2C3SDA
SSI1FSS/PF3
PC5/C1+
U0RX
SSI0RX/PA4
PP5/IRQ121
PQ7/IRQ131
WT0CCP1/PG5
I2C3SCL
SSI1CLK/PF2
PN4/FAN0PWM3
PP1/IRQ117
U0TX
SSI0CLK/PA2
SSI0FSS/PA3
I2C1SCL
PP2/IRQ118
PQ6/IRQ130
I2C4SDA
SSI1RX/PF0
PN7/FAN0TACH4
PP0/IRQ116
SSI0TX/PA5
I2C1SDA
I2C5SDA
PQ3/IRQ127
PQ4/IRQ128
I2C4SCL
I2C2SCL
SSI1TX/PF1
PN6/FAN0PWM4
PN5/FAN0TACH3
I2C5SCL
T3CCP0/PJ4/C2+
T3CCP1/PJ5/C2-
PF4
PF5
T1CCP0/PJ0
T2CCP0/PJ2
T2CCP1/PJ3
C0+
(1 OF 2)
VDDC
VREFA-
SWO/TDO
TDI
RST*
HIB*
WAKE*
XOSC0
VREFA+
VDDA
GNDA
PK4/RTCCLK
GND
NC
OSC0
XOSC1
SWCLK/TCK
SWDIO/TMS
OSC1
VBAT
VDD
(2 OF 2)
IN
INBI
BI
BI
BI
IN
IN
IN
BI
OUT
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
NC
OUT
BI
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
BI
IN
IN
OUT
IN
NC
OUT
IN
IN
OUT
OUT
BI
IN
IN
IN
IN
BI
OUT
IN
BI
BI
NC
NC
OUT
OUT
OUT
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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REVISION
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THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(OD)
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
(OD)
(OD)
NOTE: Unused pins have "SMC_Pxx" names. Unused
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
LM4FSXAH5BBBGA
OMIT_TABLE
LM4FSXAH5BBBGA
OMIT_TABLE
PLACE_NEAR=U5000.A1:4MM
SM
41 49 56 83
CERM-X5R6.3V
0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
6.3VCERM-X5R0201
0.1UF10%
41
MF
1M5%1/20W
201
16VX5R-CERM0201
0.1UF10%
16VX5R-CERM0201
0.1UF10%
0201X5R-CERM16V0.1UF10%
X5R-CERM0201
16V0.1UF10%
16VX5R-CERM0201
0.1UF10%
X5R-CERM0201
16V0.1UF10%
X5R-CERM0201
16V0.1UF10%
13 49 79 83 88
13 49 79 83 88
13 49 79 83 88
13 49 79 83 88
19 88
13 49 79 83 88
20
13 49 83
12 49 83
12 20 49 83
14
43 92
43 92
43 92
43 92
43 92
43 92
42 92
42 92
42
42
43 83 92
43 83 92
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
41 65
12 83 88
19 29 30 41
41
37 41 87
37 41 87
42
49
49
49
49
37
41 75
18 19 65 83
41
12 18 88
12 19 83 88
6.3VCERM-X5R0201
0.1UF10%
14
41
41
41 49 83
41 49 83
48
48
62
48
48
42
42
38 41 42 83
41
41 42 55
41
12 21 65 83
12 21 33 37 65 78 83
12 65
38 41 83
41 42
41 65
42
33 41 83
42
41
42
65
19 41
0402
30-OHM-1.7A
6 41 57 86
34
42
34
1UF25V
402X5R10%
25V
1UF
402X5R10%
25V
402
1UF
X5R10%
55
12 18 19 83 88
41
6 86
42
42
12 41
42
42
75
0.01UF
X5R-CERM0201
10V10%
402CERM
1UF6.3V10%
402
1UF
CERM6.3V10%
42
65
34
SMCSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
SMC_SYS_KBDLED
SMC_FAN_1_CTL
TP_SMC_MPM5_LED_CHG
SYS_TDM_ONEWIRESYS_ONEWIREHISIDE_ISENSE_OC
ALL_SYS_PWRGDSMC_THRMTRIP
SMC_ADC4
PP3V3_S5_SMC_VDDA
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 MM
SMC_OOB1_R2D_LIR_RX_OUT_RCBDV_BKL_PWM
SMC_BATLOW_L
PM_PWRBTN_L
MEM_EVENT_LSMC_ADAPTER_EN
PM_PCH_SYS_PWROK
SMC_TOPBLK_SWP_L
SMC_BIL_BUTTON_LSMC_DP_HPD_L
PM_SLP_S3_L
PM_SLP_S5_L
ENET_ASF_GPIO
SMC_PME_S4_DARK_LSMC_S4_WAKESRC_EN
SMC_TX_L
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_2_S3_SDASMBUS_SMC_2_S3_SCLSMBUS_SMC_1_S0_SDA
SMBUS_SMC_4_ASF_SCLSMBUS_SMC_4_ASF_SDA
SMC_ADC8
SMC_ADC12
SMC_ADC22
SPI_DESCRIPTOR_OVERRIDE_L
SMC_ADC11
SMC_XTAL
SMC_TDI
SMC_ADC18
SMC_ADC15SMC_ADC16
SMC_ADC19SMC_ADC20
SMC_WAKE_SCI_L
SMC_DEBUGPRT_TX_L
SMC_S5_PWRGD_VIN
SMC_ADC23
SMC_ADC2
SMC_ADC0
GND_SMC_AVSS
PP3V3_S5_AVREF_SMC
SMC_RESET_L
SMC_ADC13
SMC_ADC5
SMC_TDOSMC_WAKE_L
SMC_ADC1
CPU_THRMTRIP_3V3
SPI_SMC_MISO
SMC_OOB1_D2R_L
SMC_PME_S4_WAKE_L
SMC_EXTAL
SMC_CLK32K
WIFI_EVENT_L
PM_SYSRST_L
SMC_DEBUGPRT_EN_L
SPI_SMC_CS_L
SMC_GFX_OVERTEMP
SPI_SMC_CLKSPI_SMC_MOSI
SMC_SYS_LED
SMC_PROCHOTSMC_DELAYED_PWRGD
SMC_GFX_THROTTLE_L
SMC_DEBUGPRT_RX_L
PM_DSW_PWRGDSMC_PM_G2_EN
CPU_CATERR_L
CPU_PROCHOT_L
SMC_ADC21
SMC_ADC17
SMC_ADC14
SMC_ADC3
LPC_AD<0>LPC_AD<1>
SMC_FAN_1_TACH
SMC_FAN_0_TACHSMC_FAN_0_CTL
SMBUS_SMC_5_G3_SDA
LPC_SERIRQ
LPC_FRAME_L
PM_CLKRUN_LLPC_PWRDWN_L
SMBUS_SMC_0_S0_SCL
SMC_RUNTIME_SCI_L
SMBUS_SMC_0_S0_SDA
SMC_TCK
SMBUS_SMC_3_SCL
SMBUS_SMC_5_G3_SCL
SMC_TMS
SMC_LRESET_L
LPC_CLK33M_SMCLPC_AD<3>LPC_AD<2>
SMC_VCCIO_CPU_DIV2
SMC_ADC9
SMC_ADC7SMC_ADC6
SMC_ADC10
=PP3V3_S5_SMC
SMC_WIFI_PWR_EN
PM_SLP_S4_L
G3_POWERON_L
SMC_LID
SMC_PECI_LCPU_PECI_R
SMC_ODD_DETECT
SMC_ONOFF_L
SMC_BC_ACOKSMS_INT_L
S5_PWRGD
MIN_LINE_WIDTH=0.25 MMPP1V2_S5_SMC_VDDCMIN_NECK_WIDTH=0.1 MMVOLTAGE=1.2V
SMC_RX_L
SMC_PWRFAIL_WARN_L
U5000
E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8
K2
K1
L2
E10
D13
M4
N2
N8
M8
L8
K8
N7
M7
N4
N3
B13
A13
C12
D11
H12
G11
D12
F13
C13
F12
H13
L1
C4
C6
L9
K9
J4
J2
B12
C11A12
H11
L13
G3
D10
L11N12
N11
M11
M13L12
M5
J12
J13
L5
D8
K6
D4
E4
F5
N5N6
K5
M6
L6
M2
M3
L4
N1
L10
K10
M9
N9
F4
F3
C9
B9
A9
C8
D5
C5
L3
M1
F11
E11
E13
E12
K7
L7
K3
K4
J3
H4
H3
G4
H10
U5000
A1
C7
K11
D9
E5
F9
H5
H9
J5
J8
J11
C3E3
M12
G12G13
B11
G10 C10
A10
A11
B10
K12
D7
E6
E8
E9
F10
J7
J9
J10
D3
J1
J6
K13
D6
D1
D2
N13
M10
N10
XW500012
C50141
2
C50151
2
C50161
2
C50171
2
C50131
2
R50021
2
C50061
2
C50051
2
C50091
2
C50081
2
C50041
2
C50031
2
C50071
2
C50011
2
L5001
1 2
C50111
2
C50101
2
C50121
2
C50201
2
C50211
2
C5002 1
2
dvt
051-0675
6.0.0
50 OF 119
40 OF 94
A2
41
41 49 83
41
41 44 45 46
41 83
41 49 83
41
41 49 83
41 49 83
41
41 75 81
IN
OUT
BI
IN
IN
IN OUT
IN OUT
IN
OUT
IN
NC
NC
OUT BI
OUT
SYM_VER_2
G S
D
S
D
G
S
D
G
SN0903049
PAD
REFOUT
MR1*
THRMGND
RESET*
DELAY
MR2*
VINV+
SYM_VER_2
GS
D
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
To SMC
SMC Reset "Button", Supervisor & AVREF Supply
SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ
From/To CPU/PCH
From SMC
(IPU)
(IPU)
Mac Mini: 5V
Mobiles: 3.42V
NOTE: Internal pull-ups are to VIN, not V+.
Used on mobiles to support SMC reset via keyboard.
MR1* and MR2* must both be low to cause manual reset.
Debug Power "Buttons"
SMC12 PECI SUPPORT
SMC Crystal Circuit
5% 2011/20W MF
10K
5% 2011/20W MF
100K
5% 2011/20W MF
10K
5% 2011/20W MF
100K
5% 2011/20W MF
10K
5% 2011/20W MF
10K
5% 2011/20W MF
10K
5% 2011/20W MF
10K
5% 2011/20W MF
10K
40 41
14 88
5%0
OMIT
1/10WMF-LF603
PLACE_SIDE=BOTTOM
SILK_PART=PWR_BTN
640 57 86
40
5% 2011/20W MF
10K
5% 2011/20W MF
10K
5% 2011/20W MF
470K
5% 2011/20W MF
10K
5% 2011/20W MF
10K
5%0PLACE_SIDE=TOP
MF-LF
SILK_PART=PWR_BTN
603
OMIT
1/10W
5%0
PLACE_SIDE=BOTTOM
MF-LF603
SILK_PART=SMC_RST
OMIT
1/10W
38 40 41 83
38
0201X5R-CERM
10V10%
0.01UF
20%10uF
X5R603
6.3V
0201
10V10%0.01UF
X5R-CERM
40 49 56 83
12
5%
201
1/20WMF
22
PLACE_NEAR=U1100.Y6:5.1mm40
5% 2011/20W MF
100K
5% 2011/20W MF
20K
5% 2011/20W MF
20K
5% 2011/20W MF
10K
5%
201
1/20WMF
1K
5% 2011/20W MF
100K
5%
201
1/20WMF
330
NONENONE
NONE
NOSTUFF
OMIT
0201
5%
0
0201
1/20WMF
40
201
1/20WMF
100K1%
201
1/20WMF
100K1%
5% 2011/20W MF
100K
40 41
6 14 86
5% 2011/20W MF
100K
5% 2011/20W MF
10KNOSTUFF
CRITICAL
MMBT3904LP-7DFN1006-3
5%
201
1/20WMF
4340 6 14 86
38 40 41 83
5%
201
1/20WMF
3.3K
5% 2011/20W MF
100K 5% 2011/20W MF
100K
5%
0201NP0-C0G-CERM25V
12PF5%
NP0-C0G-CERM0201
25V
12PF
201
2.49K
1%
MF1/20W
CRITICAL
3.2X2.5MM-SM12.000MHZ-30PPM-10PF-85C
6.3V
0.47UF
CERM-X5R402
10%
NO STUFF20%4.7UF6.3VX5R402
5%
201
1/20WMF
100K
0
402MF-LF1/16W5%
CRITICAL
DFN1006H4-3DMN32D2LFB4
SOT-563DMN5L06VK-7
DMN5L06VK-7SOT-563
DFN
CRITICAL
VREF-3.3V-VDET-3.0V
CRITICAL
DFN1006H4-3DMN32D2LFB4
40 75
SMC Shared SupportSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
CPU_PROCHOT_L
=PP3V3_S5_SMC PP3V42_G3H_SMC_SPVSR
VOLTAGE=3.42V
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.1 mm
=PPVIN_S5_SMCVREF
PM_CLK32K_SUSCLK_R
SMC_ADAPTER_EN
CPU_THRMTRIP_3V3
SMC_VCCIO_CPU_DIV2
CPU_PECI_R CPU_PECI
=PP3V3_S4_SMC
=PP3V3_S5_SMC
PP3V3_WLAN
=PPVCCIO_S0_SMC
SMS_INT_L
SMC_BC_ACOK
SMC_TDI
SPI_DESCRIPTOR_OVERRIDE_L
SMC_BIL_BUTTON_L
SMC_TX_L
SMC_TCK
SMC_LID
SMC_ONOFF_L
SMC_DEBUGPRT_RX_L
WIFI_EVENT_L
SMC_PM_G2_EN
SMC_S4_WAKESRC_EN
SMC_DELAYED_PWRGD
SMC_THRMTRIP
CPU_THRMTRIP_3V3
SMC_S5_PWRGD_VIN
SMC_TDO
SMC_PME_S4_DARK_L
SMC_TMS
SMC_DEBUGPRT_TX_L
G3_POWERON_L
SMC_RX_L
SMC_PECI_L_RSMC_PECI_L
SMC_PROCHOT
SMC_CLK32K
PM_THRMTRIP_L
SMC_ROMBOOT
PM_THRMTRIP_B_L
=PPVCCIO_S0_SMC
SMC_ONOFF_L
SMC_ONOFF_L
SMC_MANUAL_RST_L
SMC_RESET_LSMC_TPAD_RST_L
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.1 mmVOLTAGE=3.3V
PP3V3_S5_AVREF_SMC
MIN_NECK_WIDTH=0.1 mmVOLTAGE=0V
MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSS
PM_THRMTRIP_L_R
SMC_THRMTRIP
SMC_GFX_OVERTEMP
SMC_EXTAL
SMC_XTAL_RSMC_XTAL
R5170 1 2
R5171 1 2
R5173 1 2
R5174 1 2
R5177 1 2
R5178 1 2
R5179 1 2
R5180 1 2
R5185 1 2
R51151
2
R5189 1 2
R5181 1 2
R5187 1 2
R5193 1 2
R5172 1 2
R51161
2
R51011
2
C5101 1
2
C5125 1
2
C51261
2
R51121 2
R5190 1 2
R5175 1 2
R5176 1 2
R5186 1 2
R51881
2
R5169 1 2
R51311
2
R51331
2
R51321 2
R51971
2
R51961
2
R5192 1 2
R5194 1 2
R5195 1 2
Q51581
3
2
R51341 2
R51581 2
R5198 1 2
R5191 1 2
C51111
2
C51101
2
R51101 2
Y5110
2 4
1 3
C5120 1
2
C51271
2
R51001
2
R51271 2
Q5130 3
1 2
Q51596
21
Q51593
54
U5110
4
2
6
7
8
5
9
1 3
Q51603
12
dvt
051-0675
6.0.0
51 OF 119
41 OF 94
40 41 75 81
81
12 40
40
20 42 81
40 41 75 81
33 83
41 81
40
40 42 55
40 49 83
19 40
40
40 49 83
40 49 83
38 40 42 83
38 40 41 83
37 40 87
33 40 83
40 65
40 65
19 29 30 40
40 41
40 41
40
40 49 83
40 42
40 49 83
37 40 87
40
40 49 83
49 83
41 81
40 83
40 44 45 46
40
40
NC
NC
NC
NC
IN
IN
IN
IN
OUT
OUT
OUT
OUT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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B
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Hall Effect pads
APN: 998-3029
Spare S4 IRQ
OMIT_TABLE
SMHALL-SENSOR-MLB-PADS-K99
0.001UF50VX7R-CERM0402
10%
0201
5%
0
MF1/20W
40
40
5%
MF1/20W
201
1K
33
38
12 30
12
5%
201
1/20WMF
100K
40
MF
100K
1/20W
201
5%
40
SUBASSY,PCBA HALL EFFECT,K99607-6811 1 CRITICALJ5250
SMC Project Support
SYS_TDM_ONEWIRE
ENET_ASF_GPIO
SMC_SYS_LED
SMC_ODD_DETECT
IR_RX_OUT_RC
SMC_CHGR_BMON_ISENSEMAKE_BASE=TRUE
SMC_SSD_ISENSEMAKE_BASE=TRUE
MAKE_BASE=TRUESMC_TBT_ISENSE
SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_3_SDA
NC_SMBUS_SMC_4_ASF_SDAMAKE_BASE=TRUE NO_TEST=TRUE
NC_SMBUS_SMC_3_SCLMAKE_BASE=TRUE NO_TEST=TRUE
SMC_DP_HPD_L
BDV_BKL_PWM
SMC_BATLOW_L
NO_TEST=TRUENC_IR_RX_OUT_RC
MAKE_BASE=TRUE
SMC_ADC5
SMC_ADC7
=PP3V3_S4_SMC
SMC_PME_S4_WAKE_LMAKE_BASE=TRUE
MAKE_BASE=TRUEPM_BATLOW_L
PCH_STRP_TOPBLK_SWP_L
=BT_WAKE_L
=PSOC_WAKE_L
SMC_TOPBLK_SWP_LSMC_LID
NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_EVENT_L
NO_TEST=TRUEMAKE_BASE=TRUENC_ENET_ASF_GPIO
MAKE_BASE=TRUENC_SMC_SYS_LED
NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUENC_SMC_ODD_DETECT
SMC_CPUPKG_VSENSEMAKE_BASE=TRUE
MAKE_BASE=TRUESMC_CPU_HI_ISENSE
SMC_PME_SDCONN_L
NC_SMBUS_SMC_4_ASF_SCLNO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUENC_BDV_BKL_PWM
NO_TEST=TRUE
SMC_ADC4
SMC_ADC8
SMC_ADC2
SMC_ADC3
SMC_ADC10
SMC_ADC1
MEM_EVENT_L
NC_SYS_TDM_ONEWIRENO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUESMC_CPUDDR_ISENSE
MAKE_BASE=TRUESMC_OTHER3V3_HI_ISENSE
SMC_P1V35MEM_ISENSEMAKE_BASE=TRUE
SMC_PBUS_VSENSEMAKE_BASE=TRUE
HISIDE_ISENSE_OC
MAKE_BASE=TRUESMC_CPUPKG_ISENSE
SMC_ADC0
SMC_ADC6
SMC_ADC9
NC_SMBUS_SMC_3_SDANO_TEST=TRUEMAKE_BASE=TRUE
NC_HISIDE_ISENSE_OCNO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUESMC_BC_ACOK=CHGR_ACOK
=PP3V3_S4_SMC
SMC_LID_R
=PP3V42_S3_HALL
=TBT_WAKE_LMAKE_BASE=TRUESMC_PME_S4_DARK_L
SMC_ADC11
SMC_ADC14
SMC_LCDPANEL_ISENSEMAKE_BASE=TRUE
NO_TEST=TRUESMC_OTHER5V_HI_ISENSE
MAKE_BASE=TRUE
SMC_ADC17
SMC_ADC16
SMC_ADC21
MAKE_BASE=TRUESMC_GPUCORE_ISENSE
MAKE_BASE=TRUESMC_GPUCORE_VSENSE
SMC_LCDBKLT_ISENSEMAKE_BASE=TRUE
SMC_ADC15
MAKE_BASE=TRUESMC_DCIN_ISENSE
SMC_DCIN_VSENSEMAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUESMC_GPU_HI_ISENSE
SMC_ADC19
MAKE_BASE=TRUENC_SMC_ADC16
NO_TEST=TRUE
SMC_ADC13
SMC_ADC12
SMBUS_SMC_3_SCL
MAKE_BASE=TRUESMC_GPU_FB_VSENSESMC_ADC18
SMC_ADC20 SMC_S2_ISENSEMAKE_BASE=TRUE NO_TEST=TRUE
SMC_GPU_FB_ISENSEMAKE_BASE=TRUE
SMC_X29_ISENSEMAKE_BASE=TRUE
SMBUS_SMC_4_ASF_SCL
SMC_ADC23
SMC_ADC22MAKE_BASE=TRUESMC_GPU1V05_ISENSE
J5250
1
2
3
4 5
6
7
8
C52501
2
R52501 2
R52831 2
R52821
2
R52591
2
dvt
051-0675
6.0.0
52 OF 119
42 OF 94
40
40
40
40
40
44
45
45
40
40 92
40
40
40
20 41 42 81
38 40 41 83
45
44
20
40
40
40
40
40
40
40
46
44
45
44
40
45
40
40
40
40 41 55 56
20 41 42 81
83
81
28
40 41
40
40
46
44
40
40
40
46
45
46
40
44
44
44
40
40
40
40 92
4540
40 46
45
46
40
40
40
46
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Lynx Point
GPU Temp (Int)
(Write: 0x9E Read: 0x9F)
GK107: U8400
(Write: 0x72 Read: 0x73)
J4002
SMC
U5000 J4801
Trackpad
(MASTER)
J1800 & J1850
SMC "0" SMBus Connections
U2201
ISL6258 - U7100
(Write: 0x12 Read: 0x13)
Lynx Point
U1100
(Write: 0x88 Read: 0x89)
access PCH & CPU via PECI.
PCH "SMLink 1" Connections
SMC "3" SMBUS CONNECTIONS
UnusedU5000
(MASTER)
SMC
SMC "4" SMBUS CONNECTIONS
SMC
(MASTER)
U5000
Battery Charger
Battery
(Write: 0x16 Read: 0x17)
J7050
SMC "5" SMBUS CONNECTIONS
SMC
EMC1414-A: U5870
(Write: 0x98 Read: 0x99)
U5000
(MASTER)
SMC
(MASTER) (MASTER)
U1100
SMC
X29 TEMP
TMP105: U5823
(MASTER)
U1100
SMLink 1 is slave port to
Lynx Point
U5000
(WRITE: 0x58 READ: 0x59)
LED BACKLIGHTU7100
LED BACKLIGHT SMBUS CONNECTION
DPMUX IC
U9100
DPMUX IC
(MASTER)
U5000
(MASTER)
L&R Fin Stack Temp
(Write: 0x98 Read: 0x99)
EMC1414-A: U5850
(Write: 0x90 Read: 0x91)
NOTE: SMC RMT bus remains powered and may be active in S3 state
Need to check with SMC team
ALS
SMC "2" SMBUS CONNECTIONS
PCH "SMLink 0" Connections
(MASTER)
(Write: 0x98 Read: 0x99)
XDP Connectors
Unused
(Write: 0x30 Read: 0x31)
U2200
(MASTER)
SMC "1" SMBUS CONNECTIONS
CPU/DDR3/PCH/AIRFLOW TEMP
U9100
(WRITE: 0X92 READ: 0X93)
HDMI Redriver (on RIO)
(WRITE: 0xCC READ: 0xCD)
J9510 -> U9700
(WRITE: 0xCC READ: 0xCD)
HDMI Redriver (on RIO)
PCH SMBus "0" Connections
VRef DACs
Margin Control
J9510 -> U9700
5%
201
1/20WMF
2.0K5%
201
1/20WMF
2.0K
1K
MF1/20W
201
5%1K
MF1/20W
201
5%
5%1/16W
402MF-LF
2.0K5%
402
1/16WMF-LF
2.0K
5%8.2K
MF-LF402
1/16W5%8.2K
MF-LF402
1/16W
NO STUFF
5%
201
1/20WMF
8.2K
NO STUFF
5%
201
1/20WMF
8.2K
MF1/20W
0201
05%
MF1/20W
0201
05%
1/16W
402MF-LF
1K5%
1/16W
402MF-LF
1K5%
5%
201
1/20WMF
1K5%
201
1/20WMF
1K
201
1/20WMF
5%4.7K
201
1/20WMF
5%4.7K
SYNC_MASTER=CLEAN_J45
SMBus ConnectionsSYNC_DATE=04/26/2013
SMBUS_PCH_DATAMAKE_BASE=TRUE
SMBUS_PCH_CLKMAKE_BASE=TRUE
=SMBUS_XDP_SDA
I2C_DPMUX_A_SDAMAKE_BASE=TRUE
=PP3V3_S0_SMBUS_PCH
I2C_DPMUX_A_SDA
I2C_DPMUX_A_SCL I2C_HDMIRDRV_SCL
I2C_HDMIRDRV_SDA
I2C_HDMIRDRV_SDA
I2C_HDMIRDRV_SCL
SMB_2_S3_CLK
=I2C_PCA9557D_SDA
=I2C_PCA9557D_SCL
SMBUS_SMC_1_S0_SCLMAKE_BASE=TRUE
SMB_5_CLK
SMB_5_DATA
=I2C_TPAD_SDA
GPU_SMB_DAT_R
=I2C_TPAD_SCL
=SMBUS_GPUTHMSNS_SCL
=SMBUS_GPUTHMSNS_SDA
=I2C_DPMUX_UC_SDA
=I2C_DPMUX_UC_SCL
=PP3V3_S0_DPMUXI2C
=I2C_DPMUX_A_SCL
=I2C_DPMUX_A_SDA
I2C_DPMUX_UC_SDAMAKE_BASE=TRUE
I2C_DPMUX_UC_SCLMAKE_BASE=TRUE
=I2C_BKL_1_SCL
=I2C_BKL_1_SDA
=I2C_X29THMSNS_SDA
=I2C_X29THMSNS_SCL
SMB_0_S0_DATA
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_PCH
SMB_1_S0_CLK
=I2C_CPUTHMSNS_SDA
=I2C_CPUTHMSNS_SCL
=PP3V3_S0_SMBUS_SMC_1_S0
=PP3V42_G3H_SMBUS_SMC_5
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
=SMBUS_CHGR_SCL
SMB_1_S0_DATA
=SMBUS_CHGR_SDA
MAKE_BASE=TRUESML_PCH_1_DATA
SMBUS_SMC_5_G3_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_5_G3_SCL
SML_PCH_0_DATAMAKE_BASE=TRUE
MAKE_BASE=TRUESML_PCH_0_CLK
MAKE_BASE=TRUESML_PCH_1_CLK
SMBUS_SMC_1_S0_SDAMAKE_BASE=TRUE
=SMBUS_XDP_SCL
=PP3V3_S0_SMBUS_SMC_0_S0
SMB_0_S0_CLK
=PP3V3_S3_SMBUS_SMC_2_S3
MAKE_BASE=TRUESMBUS_SMC_2_S3_SDA
MAKE_BASE=TRUESMBUS_SMC_2_S3_SCL
SMB_2_S3_DATA
=I2C_ALS_SCL
=I2C_ALS_SDA
GPU_SMB_CLK_R
MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUEI2C_DPMUX_A_SCL
=PP3V3_S0_DPMUXI2C
4.7K5%
1/16WMF-LF
5%4.7K1/16WMF-LF
402 402
5%0
NO STUFF 1/16WMF-LF
5%0
NO STUFF
1/16WMF-LF
5%0
1/16WMF-LF
5%0
1/16WMF-LF
402
402
402
402
R53801
2
R53811
2
R53701
2
R53711
2
R53511
2
R53501
2
R53101
2
R53111
2
R53211
2
R53201
2
R5323
1 2
R53221 2
R53011
2
R53001
2
R53611
2
R53601
2
R53371
2
R53361
2
R53351
2
R53341
2
R5390
1 2
R53911 2
R5392
1 2
R53931 2
dvt
051-0675
6.0.0
53 OF 119
43 OF 94
13 83 88
13 83 88
18
43
43
43 81
43
43 43 78
43 78
43 78
43 78
22
22
40 92
38 83
75
43 81
38 83
47
47
79
79
43 81
79
62
62
47
47
22
22
43 81
43 81
47
47
81
81
55
55
56
56
13 88
4083 92
4083 92
13 88
13 88
13 88
40 92
18
81
81
4092
4092
36 83
36 83
75
4092
4092
INOUTIN
OUT
OUT
V+
REFIN+
IN- OUT
GND
OUT
IN
OUT
S
S
D
N-CHANNEL
G
D
G
P-CHANNELOUT
INS
S
D
N-CHANNEL
G
D
G
P-CHANNEL
OUT OUTIN-
IN+ REF
V+
GND
OUTIN-
IN+ REF
V+
GND
OUTOUTIN-
IN+ REF
V+
GND
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
EDP Current:5A
Gain:100x
Gain:50x
OTHERS (3.3V) High Side Current Sense / Filter
EDP Current:21.6A
SMC_ADC3
divider when SUS present.
Power Drop across R5400 at EDP becomes 1.21W
SMC Key IC0R
Enables DC-In VSense
RTHEVENIN = 4567 Ohms
SMC KEY VD0R
PBUS Voltage Sense Enable & Filter
Enables PBUS VSense
divider when in S0.
RTHEVENIN = 4508 OhmsDivider set for Vin max of 22.32V Divider set for Vin max of 13.98V
SMC_ADC5SMC Key VP0R
SMC_ADC4SMC Key ID0R
EDP Current:4.6AIPBRSMC_ADC7
SMC_ADC8
SMC_ADC9
SMC Key IO3R
SMC_ADC13
COMPUTING High Side Current Sense / Filter
DC-In Voltage Sense Enable & Filter
SMC Key IO5R
Gain:100x
EDP Current:5A
DC-IN (AMON) Current Sense FilterCHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER
From charger
IG0RSMC_ADC2
Gain:100x
GRAPHICS High Side Current Sense / Filter
EDP Current:9.85A
OTHERS (5V) High Side Current Sense / Filter
564256
PLACE_NEAR=U5000.B5:5MM
0.22UF
0201
20%
X5R6.3V
PLACE_NEAR=U5000.B5:5MM
201MF
4.53K
1%1/20W
42
PLACE_NEAR=U5000.A5:5MM
1%
4.53K
MF1/20W
201
PLACE_NEAR=U5000.A5:5MM
0201
6.3VX5R
0.22UF20%
42
INA213SC70
CRITICAL
CERM
20%10V
402
0.1UF
402
0.1UF20%
CERM10V
0.003
MF
1%1W
CRITICAL
0612
0612-3
0.005
MF
1%
CRITICAL
1W
42
0.022UF10%6.3V PLACE_NEAR=U5000.A4:5MMX5R-CERM0201
1/20WMF
45.3K
1%
PLACE_NEAR=U5000.A4:5MM
201
PLACE_NEAR=U5000.B3:5MM
201
1/20WMF
1%
45.3K
PLACE_NEAR=U5000.B3:5MM
0201
2200PF
X7R-CERM10V10%
1%100K
1/16WMF-LF402
65
42
19.1K1%
MF1/20W
201
PLACE_NEAR=U5000.A3:5MM
6.3V20%0.22UF
X5R0201
PLACE_NEAR=U5000.A3:5MM
MF1/20W
201
PLACE_NEAR=U5000.A3:5MM
1%5.90K
CRITICAL
NTUD3169CZSOT-963
1/16WMF-LF402
100K1%
42
100K
402MF-LF
1%1/16W
65
PLACE_NEAR=U5000.F1:5MM1%30.9K
MF1/20W
201
0201
PLACE_NEAR=U5000.F1:5MM
20%
X5R6.3V
0.22UF5.36K1%
MF1/20W
201
PLACE_NEAR=U5000.F1:5MM
CRITICAL
NTUD3169CZSOT-963
100K
402
1%1/16WMF-LF
402
20K
PLACE_NEAR=U5400.6:5MM
1/16WMF-LF
5%
402
20K
PLACE_NEAR=U5430.6:5MM
5%1/16WMF-LF
42
20%
X5R0201
PLACE_NEAR=U5000.A5:5MM
6.3V
0.22UF201MF
4.53K
1%
PLACE_NEAR=U5000.A5:5MM
1/20W
402
20K
PLACE_NEAR=U5420.6:5MM
MF-LF1/16W5%
10VCERM
20%0.1UF
402
0612-3
1W
CRITICAL
1%
MF
0.005
INA214
CRITICAL
SC70INA214
CRITICAL
SC70
42
6.3VX5R
0.22UF20%
PLACE_NEAR=U5000.F2:5MM
0201
1%
4.53K
MF1/20W
PLACE_NEAR=U5000.F2:5MM
201
CERM402
0.1UF20%10V
INA214
CRITICAL
SC70
0.003
CRITICAL
1%1WMF
0612
81
81
High Side Voltage and Current Sensing
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
SMC_PBUS_VSENSE
ISNS_HS_OTHER5V_N
ISNS_HS_OTHER5V_P
HS_OTHER3V3_IOUTISNS_HS_OTHER3V3_N
ISNS_HS_OTHER3V3_P
=PP3V3_S0_HS_ISNS
ISNS_HS_COMPUTING_P
PDCINVSENS_EN_L_DIV
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_COMPUTING_ISNS
ISNS_HS_COMPUTING_N SMC_CPU_HI_ISENSE
GND_SMC_AVSS
=PBUSVSENS_EN
PBUS_S0_VSENSE
=PPDCIN_S5_VSENSE
GND_SMC_AVSS
=PPBUS_S0_VSENSE
GND_SMC_AVSS
SMC_DCIN_VSENSE
PBUSVSENS_EN_LDCINVSENS_EN_L
HS_COMPUTING_IOUT
PBUSVSENS_EN_L_DIV
GND_SMC_AVSS
SMC_DCIN_ISENSECHGR_AMON
GND_SMC_AVSS
SMC_CHGR_BMON_ISENSECHGR_BMON
GND_SMC_AVSS
=PPVIN_S5_HS_OTHER5V_ISNS
=PPVIN_S5_HS_OTHER5V_ISNS_R
DCIN_S5_VSENSE
GND_SMC_AVSS
=PPVIN_S5_HS_OTHER3V3_ISNS
=PPVIN_S5_HS_OTHER3V3_ISNS_R
SMC_OTHER3V3_HI_ISENSESMC_OTHER5V_HI_ISENSE
=PP3V3_S0_HS_ISNS
HS_OTHER5V_IOUT
=DCINVSENS_EN
GND_SMC_AVSS
SMC_GPU_HI_ISENSEHS_GPU_IOUT
=PP3V3_S0_HS_ISNS
ISNS_HS_GPU_P
ISNS_HS_GPU_N
=PPVIN_S5_HS_GPU_ISNS
=PPVIN_S5_HS_GPU_ISNS_R
=PP3V3_S0_HS_ISNS
C54031
2
R54031 2
R54331 2
C54331
2
U5400
2
5
4
6
1
3
C54011
2
C54311
2
R5400
1
2
3
4
R5430
1
2
3
4
C54211
2
R54231 2
R54411 2
C54411
2
R54021
2
R54011
2
C54041
2
R54041
2
Q5400
6
3
2
5
1
4
R54051
2
R54121
2
R54131
2
C54141
2
R54141
2
Q5410
6
3
2
5
1
4
R54111
2
R54091
2
R54391
2
C54261
2
R54261 2
R54291
2
C54221
2
R5420
1
2
3
4U5430
2
5
4
6
1
3
U5420
2
5
4
6
1
3
C54191
2
R54191 2
C54111
2
U5410
2
5
4
6
1
3
R5410
1
2
3
4
dvt
051-0675
6.0.0
54 OF 119
44 OF 94
93
93
93
93
44 81
93
81
81
93
40 41 44 45 46
81
40 41 44 45 46
81
40 41 44 45 46
40 41 44 45 46 40 41 44 45 46
40 41 44 45 46
81
81
40 41 44 45 46
81
81
44 81
40 41 44 45 46
44 81
93
93
44 81
OUT
V-
V++
-
V-
V++
-
OUT
V-
V++
-
IN
IN
IN
IN
IN
IN
V-
V++
-
IN
OUT
OUT
OUT
OUT
V-
V++
-
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
SMC_ADC23
GPU Vcore Voltage Sense / Filter
removed LCD BKLT Voltage Sensing
IM0C
SSD CURRENT SENSE
EDP CURRENT: 5A
GAIN: 274X
EDP CURRENT: 0.94 ASENSE RESISTOR 0.010 OHM
IHDC
Sense Resistor 0.005 Ohm
CPU Vcore Voltage Sense / Filter
Individual Sense R is 0.75mOhm
(Effective Sense R is 0.25mOhm due to summing of the 3 phases)
Gain:137.77xScale: 29.03A / VMax VOut: 3.3V at 95.8A
VC0CSMC_ADC0
SMC_ADC1
SMC_ADC10
Gain: 182x
EDP CURRENT:8A
SMC_ADC6
IHSC
GAIN: 130X
EDP: 95A TDP :45A
DDR3 1.35V DRAM ONLY CURRENT SENSE / FILTER
TBT Router CURRENT SENSE
GAIN:136.6X
SMC_ADC14VG0C
SMC_ADC18VG1C
GPU FB Voltage Sense / Filter
IG1CSMC_ADC19
Gain: 104.9x
GPU FB (1.35V/1.5V) CURRENT SENSE
EDP Current: 15.1A
Rsense(R8380)=0.002 Ohm
IC0C
CPU PKG Load Side Current Sense / Filter
ISNS_1V35_MEM_R_P
0402X7R-CERM
0.1UF
ISENSE_P1V35MEM_IOUT
SMC_GPUCORE_VSENSE
PLACE_NEAR=U5000.B1:5MM
RES,MTL FILM,0,5,1/20W,0201,SMD,LF1117S0201 R5506 SENSOR_NONPROD:N
=PP3V3_S0SW_SSD_R
ISNS_SSD_N
0.22UF
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y
1%
ISNS_TBT_IOUT
GND_SMC_AVSS
SMC_GPU_FB_ISENSE
GPUFB_CS_P
GPUFB_CS_N ISNS_GPUFB_R_N
ISNS_GPUFB_R_P
=PP1V35_GPU_FB
ISNS_GPUFB_IOUT
=PP3V3_S0_ISNS
GPU_FB_VSENSE_IN
GND_SMC_AVSS
SMC_GPU_FB_VSENSE
=PPVCORE_GPU_REG
GPUVSENSE_IN
GND_SMC_AVSS
ISNS_TBT_R_N
ISNS_TBT_P
ISNS_SSD_P
GND_SMC_AVSS
CPUVR_ISUM_IOUT
CPUVR_ISNS_N
GND_SMC_AVSSCPUVR_IMON
SMC_P1V35MEM_ISENSE
=PP3V3_S3_ISNS
GND_SMC_AVSS
CPUVR_ISNS1_N
CPUVR_ISNS2_N
CPUVR_ISUM_R_N
CPUVR_ISNS_P
SMC_CPUPKG_ISENSE
CPUVR_ISNS2_P
CPUVR_ISNS3_P CPUVR_ISUM_R_P
CPUVR_ISNS1_P
=PP3V3_S0_CPUVRISNS
=PPVCORE_S0_CPU CPUVSENSE_IN
GND_SMC_AVSS
SMC_CPUPKG_VSENSE
GND_SMC_AVSS
ISNS_1V35_MEM_P
=PPVIN_S3_MEM_ISNS_R
SMC_TBT_ISENSE
SMC_SSD_ISENSE
=PP3V3_S4_ISNS
CPUVR_ISNS3_N
=PP3V3_S0_ISNS
=PP3V3_S0SW_SSD
=PPVIN_S3_MEM_ISNS
ISNS_SSD_IOUT
ISNS_SSD_R_P
ISNS_SSD_R_N
ISNS_TBT_R_P
=PP3V3_S4_TBT
=PP3V3_S4_TBT_R
ISNS_TBT_N
Load Side Voltage and Current Sensing
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
PLACE_NEAR=R7310.2:5 MM
SM
0201
20%6.3VX5R
0.22UF
PLACE_NEAR=U5000.E2:5MM
PLACE_NEAR=U5000.E2:7MM201MF
1/20W1%
4.53K42
NO_XNET_CONNECTION=TRUE
402
1M
MF-LF
1%
1/16W
201
MF
1/20W
9.53K
1%
201
9.53K
1/20W
MF
1%
NO_XNET_CONNECTION=TRUE
1M
MF-LF
402
1%
1/16W
SM
PLACE_NEAR=R8670.1:5 MM
SC70-5OPA333DCKG4
1/20W
201MF
4.53K
1%
PLACE_NEAR=U5000.H2:5MM
10V
402
0.1UF20%
CERM
1/20W1%
201MF
4.53K
PLACE_NEAR=U5000.H1:7MM
0201
20%6.3VX5R
0.22UF
PLACE_NEAR=U5000.H1:5MM
0.22UFPLACE_NEAR=U5000.H2:5MM
0201
6.3V20%
X5R
42
SM
PLACE_NEAR=R9210.1:5 MM
0201X5R
0.22UF20%6.3V
201
1%
MF1/20W
4.53K
PLACE_NEAR=U5000.B1:5MM
42
42
42
MF1W1%
0.005
CRITICAL
0612-3
0.003
MF
1%1W
0612
CRITICAL
57
SENSOR_NONPROD:N
PLACE_NEAR=U5550.4:7MM
MF-LF1/16W
402
0
5%
1206-1MF
CRITICAL
1%1/2W
0.010
201
3.65K
1/20WMF
1%
201
3.65K
1%
MF1/20W
1/20WMF201
1M1%
NO_XNET_CONNECTION=TRUE
1/20WMF
1%
1M
201
SC70-5OPA333DCKG4
402
20%0.1UF
10VCERM
1%1/20W
4.53K
PLACE_NEAR=U5000.A8:5MM
201MF
0.22UF
PLACE_NEAR=U5000.A8:5MM
X5R
20%
0201
6.3V
93 58 5.23K
SENSOR_NONPROD:Y
PLACE_NEAR=R7330.4:5MM
NO_XNET_CONNECTION=TRUE 0.5%
MF402
1/16W
93 58
93 58
93 58
93 58
NO_XNET_CONNECTION=TRUE
SENSOR_NONPROD:YPLACE_NEAR=R7320.4:5MM
1/16W
5.23K
0.5%
402MF
PLACE_NEAR=R7310.4:5MM
NO_XNET_CONNECTION=TRUE
SENSOR_NONPROD:Y MF
5.23K
402
0.5%1/16W
PLACE_NEAR=R7320.3:5MM
NO_XNET_CONNECTION=TRUE
MF1/16W
402
SENSOR_NONPROD:Y
0.5%
5.23K
NO_XNET_CONNECTION=TRUE
PLACE_NEAR=R7330.3:5MM
0.5%
402MF
1/16W
SENSOR_NONPROD:Y
5.23K
93 58
SENSOR_NONPROD:Y
PLACE_NEAR=R7310.3:5MM5.23K
1/16WMF
NO_XNET_CONNECTION=TRUE
402
0.5%
3.57K
402MF-LF
1%1/16W
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y
MF-LF
1%732K
1/16W
402
NO_XNET_CONNECTION=TRUE
3.57K
SENSOR_NONPROD:Y
402MF-LF
1%1/16W
MF-LF
1%
402
1/16W
SENSOR_NONPROD:Y
NO_XNET_CONNECTION=TRUE
732K
SENSOR_NONPROD:Y
OPA333DCKG4
CRITICAL
X7R-CERM
PLACE_NEAR=U5550.5:3MM
10V
0.1UF
0402
20%
1/20W
201MF
4.53K
1%PLACE_NEAR=U5000.E1:5MM
X5R6.3V20%
0201
42
7.68K
MF-LF
402
1/16W
1%
7.68K
1/16W
MF-LF
402
MF-LF
1M1%
402
1/16W
NO_XNET_CONNECTION=TRUE
1M
1%
MF-LF1/16W
402
NO_XNET_CONNECTION=TRUE
SC70-5OPA333DCKG4
0.1UF
402
20%
CERM10V
PLACE_NEAR=U5000.B4:7MM
201
1%
MF1/20W
4.53K
PLACE_NEAR=U5000.B4:5MM
6.3V
0.22UF
X5R
20%
0201
10V20%
SC70-5
1/16W
402MF-LF
7.32K
1%
MF-LF
1M1%
402
1/16W
1/16W
1M
MF-LF
1%
402
NO_XNET_CONNECTION=TRUE
7.32K
1%
MF-LF1/16W
402
0201
0.22UF20%
X5R6.3V
PLACE_NEAR=U5000.B6:5mm
PLACE_NEAR=U5000.B6:7mm
1%
4.53K
MF1/20W
201
42
SC70-5
PLACE_NEAR=U5000.E1:5MM
OPA333DCKG4
ISNS_1V35_MEM_R_N
ISNS_1V35_MEM_N
R55201 2
C55201
2
XW5520
1 2
R55771 2
C55771
2
R55731 2
R55761 2
R55751
2
R55741 2
U55601
3
4
2
5
C55601
2
C55401
2
R5564
1 2
C55581
2
U5540
1
3
4
2
5
R5563
1 2
R55621
2
R5504
1 2
R5561
1 2
C55011
2
R55061 2
C55501
2
U55501
3
4
2
5
R55551 2
R55031 2
R55541
2
R55071 2
R55051 2
R55001 2
R55081 2
R55701 2
R55711 2
R55721 2
C55001
2
R5502
1 2
C55511
2
U5500
1
3
4
2
5
R55011 2
R55531
2
R55511 2
R55521 2
R5559 1
2
3
4
R55301 2
R5560 1
2
3
4
R5549
12
34
R5535
1 2
C55351
2
XW5535
1 2
C55911
2
C55901
2
R55901 2
C55921
2
R55911 2
U5590
1
3
4
2
5
XW5590
1 2
R5594
1 2
R5596
1 2
R5595
1 2
R55931
2
dvt
051-0675
6.0.0
55 OF 119
45 OF 94
41
46 45 44 41 40
42
93 71
93 71 93
93
81
81 46 45
46 45 44 41 40
81
46 45 44 40
93
8164
93
93
46 45 44 41 40
46 45 44 41 40
93
93
81 46
46 45 44 41 40
93
93 93
81
81
46 45 44 41 40
46 45 44 41 40
93
81
81 46
81 46 45
8134
81
93
93
81 30 29 28
81
93
93
IN
OUTIN-
IN+ REF
V+
GND
IN
V-
V++
-
IN
IN
OUTIN-
IN+ REF
V+
GND
V-
V++
-
V-
V++
-
IN
IN
OUT
OUT
OUT
OUT
OUT
V-
V++
-
OUT
V-
V++
-
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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B
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C
B
A
NOTICE OF PROPRIETARY PROPERTY:
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D
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
GPU 1.05V CURRENT SENSE
X29 AIRPORT CURRENT SENSE
.
ICMCSMC_ADC20
GAIN: 332X
S2 CAMERA CONTROLLER CURRENT SENSE
GAIN: 383X
IC3CSMC_ADC11
Gain: 316x
SMC_ADC22IAPC
EDP Current: 1.06ASense Resistor 0.005 Ohm
Sense Resistor 0.010 Ohm
CPU DDR CURRENT SENSE
EDP Current: 820mA
IG0CSMC_ADC15
Gain: 3.004x
Vimon=3xIo*(0.2/R8915)*R8912
EDP:46A
GPU VCore Load Side Current Sense / Filter
ILDCSMC_ADC12
GAIN: 100X
EDP CURRENT: 1.0A
LCD PANEL CURRENT SENSE
SMC_ADC17IBLC
GAIN: 100X
LCD BKLT Current Sense
EDP Current: 0.75A
GAIN: 357X
IG2CEDP Current: 2.317A
NEED KEY FOR THIS SENSOR
EDP CURRENT: 4.2A
SMC_ADC21
10V20%
402CERM
0.1UF
SENSOR_NONPROD:Y
1M
1/20W
MF
SENSOR_NONPROD:Y
NO_XNET_CONNECTION=TRUE
1%
201
3.16K
MF1/20W
1%
201
SENSOR_NONPROD:Y
3.16K
MF1/20W
SENSOR_NONPROD:Y
1%
201
1%1M1/20W
MF
NO_XNET_CONNECTION=TRUE
SENSOR_NONPROD:Y
201
64 NC_ISNS_CPUDDRP
SENSOR_NONPROD:Y
SC70INA214
CERM402
20%10V
SENSOR_NONPROD:Y
0.1UF
67
SC70-5
SENSOR_NONPROD:Y
OPA333DCKG4
67
64 NC_ISNS_CPUDDRN
0201
20%PLACE_NEAR=U5000.G1:5MM
0.22UF
SENSOR_NONPROD:Y
6.3V
X5R
10V20%
402CERM
SENSOR_NONPROD:Y0.1UF
4.53K
MF
PLACE_NEAR=U5000.G1:7MM
1%1/20W
SENSOR_NONPROD:Y
201
SC70INA214
SENSOR_NONPROD:Y
0.22UF
SENSOR_NONPROD:Y
0201
20%PLACE_NEAR=U5000.B8:7MM6.3V
X5R
SENSOR_NONPROD:Y
PLACE_NEAR=U5000.B8:7MM
4.53K
MF
1%1/20W
201
SENSOR_NONPROD:Y
6.3V
CERM-X5R0201
0.1UF10%
SC70-5OPA333DCKG4
SENSOR_NONPROD:Y
510K
201
1%
NO_XNET_CONNECTION=TRUE
MF1/20W
SENSOR_NONPROD:Y
620
201
1%1/20W
MF
SENSOR_NONPROD:Y
620
201MF
1%1/20W
SENSOR_NONPROD:Y
CRITICAL
SM
510K
201
1/20W
MF
SENSOR_NONPROD:YNO_XNET_CONNECTION=TRUE
1%
SENSOR_NONPROD:Y
PLACE_NEAR=U5000.A6:5MM
0.22UF20%
0201
6.3V
X5R
0201
0.22UF
PLACE_NEAR=U5000.C1:7MM
SENSOR_NONPROD:Y
20%6.3V
X5R
4.53K
MF
1%1/20W
PLACE_NEAR=U5000.C1:7MM
SENSOR_NONPROD:Y
201
PLACE_NEAR=U5000.A6:7MM
1/20W
MF
4.53K
1%
201
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y1%1/20W
MF
3.01K
201
CRITICAL
SM
SENSOR_NONPROD:Y
1/20W
1%
MF
3.01K
201
402
0
5%MF-LF 1/16W
S2_PWR:S0
1/16W
S2_PWR:S3
402MF-LF5%
0
1%SENSOR_NONPROD:Y1/20W
MF
1M
NO_XNET_CONNECTION=TRUE
201 1/20W
1M
MF
1% SENSOR_NONPROD:Y
201
NO_XNET_CONNECTION=TRUE
SENSOR_NONPROD:Y
OPA333DCKG4SC70-5
0.22UF
0201
20%PLACE_NEAR=U5000.H1:7MM
SENSOR_NONPROD:Y
6.3V
X5R
6.3V
CERM-X5R0201
0.1UF10%
SENSOR_NONPROD:Y
1%
4.53K
MF1/20W
PLACE_NEAR=U5000.H1:7MM
SENSOR_NONPROD:Y
201
62 93
62 93
42
42
42
42
42
PLACE_NEAR=U5000.B7:5MM0201
SENSOR_NONPROD:Y
6.3V20%
X5R
0.22UFPLACE_NEAR=U5000.B7:5MM
201
1/20W
MF
4.53K
SENSOR_NONPROD:Y
1%
SENSOR_NONPROD:Y
0402
X7R-CERM
10V20%
0.1UF
SENSOR_NONPROD:Y
SC70-5OPA333DCKG4
201
2.8KSENSOR_NONPROD:Y
1/20W
MF
1%
201
2.8K
1/20W
MF
1%SENSOR_NONPROD:Y
NO_XNET_CONNECTION=TRUE
SENSOR_NONPROD:Y
402
1%
MF-LF
1/16W
1M
NO_XNET_CONNECTION=TRUE
SENSOR_NONPROD:Y
1/16W
MF-LF
402
1M1%
42
PLACE_NEAR=U5000.B2:5mm
NOSTUFF
4.53K
1%
MF1/20W
201
SENSOR_NONPROD:Y
PLACE_NEAR=U5000.B2:5mm0.22UF6.3V20%
X5R0201
CRITICAL
CERM
0.1UF
402
20%10V
SENSOR_NONPROD:Y
PLACE_NEAR=U5000.B2:5mm
MF
4.53K
201
1/20W1%
SENSOR_NONPROD:Y
OPA333DCKG4SC70-5
SENSOR_NONPROD:Y
MF-LF1/16W1%
1M
SENSOR_NONPROD:Y
402
NO_XNET_CONNECTION=TRUE
499K1%1/16WMF-LF402
SENSOR_NONPROD:Y
77
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
Debug Sensors
117S0008 RES,MTL FILM,100K,5,1/20W,0201,SMD,LF7 SENSOR_NONPROD:N
C5601,C5631,C5600,C5681,C5671,C5618,C5642
PP3V3_S3RS0_CAMERA_R
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM
=PP3V3_S3RS0_CAMERA
PP3V3_WLAN_R
PP3V3_WLAN_F
NC_ISNS_S2N
=PP3V3_S3_CAMERA_R
SMC_X29_ISENSE
SMC_S2_ISENSE
=PP3V3_S0_CAMERA_R
NC_ISNS_S2P
NC_ISNS_AIRPORTN
GND_SMC_AVSS
=PP3V3_S3_ISNS
ISNS_AIRPORT_R_P
GND_SMC_AVSS
ISNS_S2_R_N
GND_SMC_AVSS
ISNS_CPU_DDR_R_N
ISNS_CPU_DDR_R_P
NC_ISNS_AIRPORTP
ISNS_CPU_DDR_IOUT SMC_CPUDDR_ISENSE
ISNS_S2_R_P
ISNS_AIRPORT_IOUT
=PP3V3_S4_ISNS
=PP3V3_S3_ISNS
GND_SMC_AVSS
SMC_GPUCORE_ISENSE
=PP3V3_S0_ISNS
GPUVCORE_IOUT
GPUVCORE_INV
GFXIMVP6_IMON
=PP3V3_S0_ISNS
SMC_LCDPANEL_ISENSELCD_PANEL_IOUT
NC_ISNS_LCD_PANELP
NC_ISNS_LCD_PANELN
GND_SMC_AVSS
=PP3V3_S0_ISNS
SMC_LCDBKLT_ISENSELCDBKLT_IOUTISNS_LCDBKLT_N
ISNS_LCDBKLT_P
GND_SMC_AVSS
P1V05_GPU_CS_N
=PP3V3_S0_ISNS
SMC_GPU1V05_ISENSE1V0_GPU_IOUT
ISNS_PP1V0_S0GPU_R_N
ISNS_PP1V0_S0GPU_R_PP1V05_GPU_CS_P
ISNS_S2_OUT
ISNS_AIRPORT_R_N
C56821
2
R56841 2
R56811 2
R56821 2
R56831
2
U5670
2
5
4
6
1
3
C56701
2
U56821
3
4
2
5
C56011
2
C56021
2
R56011 2
U5601
2
5
4
6
1
3
C56311
2
R56341 2
C56301
2
U56301
3
4
2
5
R56331 2
R56301 2
R56311 2
XW56351
2
R56321
2
C56811
2
C56711
2
R56711 2
R56851 2
R56001 2
XW56751
2
R56701 2
R56771 2
R56761 2
R5672 1
2
R56731 2
U56001
3
4
2
5
C56001
2
C56031
2
R56741 2
C56421
2
R56441 2
C56431
2
U56401
3
4
2
5
R5640
1 2
R5641
1 2
R5643
1 2
R56421
2
R56101 2
C56181
2
C56101
2
R56181 2
U56101
3
4
2
5
R56171 2
R56191
2
dvt
051-0675
6.0.0
46 OF 94
56 OF 119
35 81
33
33
81
81
40 41 44 45 46
45 46 81
93
40 41 44 45 46
93
40 41 44 45 46
93
93
93
45 81
45 46 81
40 41 44 45 46
45 46 81
45 46 81
40 41 44 45 46
45 46 81
40 41 44 45 46
71 93
45 46 81
42
93
9371 93
93
BI
DP1 THERM*/ADDR
DN1
THRM_PAD
VDD
SMDATA
SMCLKGND
ALERT*
DP2/DN3
DN2/DP3
BI
BI
V+
GNDS
SDA
SCL
A0
ALERT NC
BI
BI
DP1 THERM*/ADDR
DN1
THRM_PAD
VDD
SMDATA
SMCLKGND
ALERT*
DP2/DN3
DN2/DP3
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Use GND pin B1 on U2800 for N leg
PCH PROXIMITY TEMPERATURE
PLACE Q5803 ON TOP SIDE NEAR DDR3
Placement note:
TW0P
WRITE ADDRESS: 0X92
Placement note:PLACE U5823 ON BOTTOM NEAR X29 CONN
READ ADDRESS: 0X93
X29 PROXIMITY
TC0P
Placement note:
Read Address: 0x99Write Address: 0x98
TP0P
Ta0P AIRFLOW PROXIMITY TEMPERATURE
TM0P
CLOSE TO BOARD EDGE
Placement note:PLACE Q5802 ON TOP SIDE
PLACE U5870 ON TOP SIDE UNDER CPU
PLACE Q5804 ON TOP SIDE UNDER PCH
Placement note:
THSP
DDR3 PROXIMITY TEMPERATURE
CPU PROXIMITY TEMPERATURE
DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY
TBT DIE
Placement note:PLACE U5850 ON TOP SIDE UNDER THE GPU
TG0DGPU DIE TEMPERATURE
Read Address: 0x99Write Address: 0x98
RIGHT FIN STACK TEMPERATURE
GPU PROXIMITY/GPU DIE/LEFT FIN STACK/RIGHT FIN STACK
Placement note:PLACE Q5803 ON BOTTOM SIDE NEAR RIGHT FIN STACK
CLOSE TO THE LEFT FIN STACK
PLACE Q5801 ON TOP SIDE
Placement note:
Th1H LEFT FIN STACK TEMPERATURE Th2H
10K
MF-LF402
5%1/16W
10K
MF-LF402
5%1/16W
SOT732-3BC846BMXXH
CRITICALSOT732-3BC846BMXXH
CRITICAL
0.0022uF
NO_XNET_CONNECTION=TRUE
PLACE_NEAR=U5870.2:5mmPLACE_NEAR=U5870.3:5mm
50V10%
402CERM
28
PLACE_NEAR=U2800.AC6:2mm
SM
MF-LF
PLACE_SIDE=TOP
NOSTUFF
1/16W5%
402
10K
SOT732-3BC846BMXXH
CRITICAL
DFNEMC1414-A-AIA
43
43
PLACE_NEAR=J3501:5MMPLACE_SIDE=BOTTOM
TMP105
CRITICAL
WCSP-6
402CERM10V20%0.1uF
MF-LF
5%1/16W
402
10K
10K
MF-LF402
5%1/16W
43
43
10K
MF-LF402
5%1/16W
10V20%
0402X7R-CERM
0.1UF
DFNEMC1414-A-AIA
NO_XNET_CONNECTION=TRUE
10%
402CERM50V
0.0022uF
PLACE_NEAR=U5850.2:5mmPLACE_NEAR=U5850.3:5mm
50V10%
402CERM
0.0022uF
NO_XNET_CONNECTION=TRUE
PLACE_NEAR=U5850.4:5mmPLACE_NEAR=U5850.5:5mm
1/16WMF-LF
5%
402
47
74 93
74 93
SOT732-3BC846BMXXH
CRITICALSOT732-3BC846BMXXH
CRITICAL
43
43
20%
0402
0.1UF
X7R-CERM10V
1/16W5%
402MF-LF
47
NO_XNET_CONNECTION=TRUE
PLACE_NEAR=U5870.5:5mmPLACE_NEAR=U5870.4:5mm
50V10%
402CERM
0.0022uF
Thermal SensorsSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
TBT_THERMD_PMAKE_BASE=TRUE
CPUTHMSNS_D2_N
CPUTHMSNS_D2_P
=PP3V3_S0_CPUTHMSNS PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.2 mm
=I2C_X29THMSNS_SDA
=PP3V3_S0_X29THMSNS
X29THMSNS_A0
=I2C_X29THMSNS_SCL
DDR3THMSNS_D1_N
CPUTHMSNS_THM_L
CPUTHMSNS_ALERT_L
=I2C_CPUTHMSNS_SDA
=I2C_CPUTHMSNS_SCL
TP_TBT_THERM_DP
TBT_THERMD_N
DDR3THMSNS_D1_P
GPUTHMSNS_ALERT_L
=SMBUS_GPUTHMSNS_SCL
=SMBUS_GPUTHMSNS_SDA
GPUTHMSNS_THM_L
PP3V3_S0_GPUTHMSNS_RMIN_LINE_WIDTH=0.38 mm
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm
GPU_TDIODE_N
GPU_TDIODE_P
=PP3V3_S0_GPUTHMSNS
GPUTHMSNS_D_P
GPUTHMSNS_D_N
C58701
2
R58701 2
C5890 1
2
R58721
2
R58711
2
Q5804 1
3
2
Q5802
1
3
2
C5871 1
2
XW58201 2
R58201
2
Q5806 1
3
2
U5870
83
5
2
4
6
10
9
7
11
1
U5823
C2
B2
A2
B1
A1
C1
C58231
2
R58221
2
R58521
2
R58511
2
C58501
2
U5850
83
5
2
4
6
10
9
7
11
1
C5851 1
2
C5852 1
2
R58501 2
Q5803 1
3
2
Q5801
1
3
2
dvt
051-0675
6.0.0
58 OF 119
47 OF 94
93
93
81
81
93
93
93
81
93
93
IN
OUT
IN
NC
NC
NC
NC
NC NC
DS
G
DS
G
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
518S0769
Right FanLeft Fan
518S0769
MF-LF402
1/16W5%
47K
MF-LF
47K
402
1/16W5%
47K1/16W
5%
402MF-LF
47K
MF-LF402
5%1/16W
5%1/20W
MF201
100K1/20W
5%100K
MF201
40
40
40
F-RT-SMFF14A-5C-R11DL-B-3H
CRITICAL CRITICAL
F-RT-SMFF14A-5C-R11DL-B-3H
DMN5L06VK-7SOT-563
DMN5L06VK-7SOT-563
40
402
5%
MF-LF1/16W
0
NOSTUFF402
5%
0
NOSTUFF
1/16WMF-LF
SYNC_MASTER=CLEAN_J45
Fan ConnectorsSYNC_DATE=06/23/2013
FAN_LT_PWM
=PP3V3_S0_FAN_RT
=PP3V3_S3_FAN_CTL
SMC_FAN_1_TACH
=PP3V3_S0_FAN_LT
=PP3V3_S3_FAN_CTL
SMC_FAN_1_CTL FAN_RT_PWMSMC_FAN_0_CTL
=PP5V_S0_FAN_LT
SMC_FAN_0_TACH
=PP3V3_S0_FAN_LT
FAN_LT_TACHFAN_RT_TACH
=PP3V3_S0_FAN_RT
=PP5V_S0_FAN_RT
R60501
2R60551 2
R60601
2R60651 2
R60511
2
R60611
2
J6050
7
6
1
2
3
4
5
J6060
7
6
1
2
3
4
5
Q6060
3
5
4
Q6060
6
2
1
R60711 2
R60721 2
dvt
051-0675
6.0.0
60 OF 119
48 OF 94
83
48 81
48 82
48 81
48 82
83
81
48 81
83
83
48 81
81
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
IN
IN
OUT
BI
IN
OUT
WP*
SI
HOLD*VSS
SCK
CE*
VDD
SO
BI
BI
BI
BI
IN
BI
IN
OUT
IN
IN
IN
BI
BI
BI
BI
OUT
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
WF: This termination is wrong for dual/quad-IO.
LPC+SPI Connector
516S1039
SPI ROM
override. Quad-IO support is
NOTE: Not all ROM APNs currently
compatible with Matt card ROMused support quad-IO. Also not
for experimentation only.
NOTE: If HOLD* is assertedROM will ignore SPI cyclesin normal and dual-IO modes.
SMC12 SPI SUPPORT
(SPI_IO<0>)
(SPI_IO<1>)
SPI Bus Series Termination
MF-LF402
1/16W
PLACE_NEAR=U1100.AH1:5mm 0
5%
40 41 83
40 41 83
41 83
40 41 56 83
40 41 83
40 41 83
12 20 40 83
13 40 83
49 83
49 83
12 40 83
14 49 83
13 40 79 83 88
49 83 PLACE_NEAR=J6100.12:5mm
1/16W
402MF-LF
LPCPLUS_R:YES
05%
1/16W
33
MF-LF402
PLACE_NEAR=R6126.2:5mm5%
PLACE_NEAR=J6100.14:5mm
1/16W
402MF-LF
LPCPLUS_R:YES
05%
33
MF-LF402
1/16W PLACE_NEAR=R6125.2:5mm5%
PLACE_NEAR=J6100.11:5mm
1/16W
402MF-LF
LPCPLUS_R:YES
05%
MF-LF402
1/16W PLACE_NEAR=U6100.2:5mm
33
5%
PLACE_NEAR=J6100.9:5mm
1/16W
402MF-LF
LPCPLUS_R:YES
05%
1/16W
402MF-LF
33
PLACE_NEAR=R6127.2:5mm5%
DF40C-30DP-0.4VM-ST-SM
CRITICALLPCPLUS_CONN:YES
64MBITSOIC
SST25VF064COMIT_TABLECRITICAL
10V
0.1UF
CERM20%
402
1/16WMF-LF
3.3K
402
SPI:DUAL_IO
5%
13 88
13 88
SPI:QUAD_IO
1/16W1%
402MF-LF
15
PLACE_NEAR=R6101.2:5mm
13
15
1/16W1%
402MF-LF
SPI:QUAD_IO
PLACE_NEAR=R6102.2:5mm
13
1/16WMF-LF402
SPI:DUAL_IO
0
5%
14 49 83
14 83
49 83
40 41 83
20 83
40 41 83
19 83 88
13 40 79 83 88
13 40 79 83 88
13 40 79 83 88
13 40 79 83 88
12
MF1/20W
201
5%
MF1/20W
0201
0
5%
MF1/20W
0201
0
5%
MF1/20W
0201
0
5%
40
40
40
40
1/16W
PLACE_NEAR=U1100.AJ7:5mm
402MF-LF
0
5%13 88
1/16W
402MF-LF
PLACE_NEAR=U1100.AJ11:5mm 0
5%13 88
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
SPI ROM / LPC+SPI Conn.
SPI_CS0_L
SPI_CLK
SPI_MLB_MISO
SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
=PP3V3_S5_LPCPLUS=PP5V_S0_LPCPLUS
SPI_ALT_MISOLPC_FRAME_LSPIROM_USE_MLB
PM_CLKRUN_LSPI_ALT_CLKSPI_ALT_CS_LLPC_SERIRQLPC_PWRDWN_LSMC_TDISMC_TCKSMC_RESET_LSMC_ROMBOOTSMC_RX_LSMC_TMS
LPC_CLK33M_LPCPLUSLPC_AD<0>
LPC_AD<2>
SPI_ALT_MOSI
LPC_AD<1>LPC_AD<3>
LPCPLUS_GPIOLPCPLUS_RESET_L
TP_SMC_TRST_LTP_SMC_MD1
SMC_TDO
SMC_TX_L
=PP3V3_SUS_ROM
SPIROM_WP_L
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_MLB_CLK
SPI_MLB_CS_L
SPIROM_HOLD_LSPIROM_USE_MLB
SPI_MOSI_R
SPI_CLK_R
SPI_IO<3>
SPI_CS0_R_L
SPI_IO<2>
SPI_MISO
SPI_MOSI
SPI_ALT_CS_LSPI_ALT_CLKSPI_ALT_MOSISPI_ALT_MISO
SPI_MLB_CS_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPIROM_HOLD_L
SPIROM_WP_L
R61101 2
R61111 2
R61121 2
R61261
2
R61211 2
R61251
2
R61201 2
R61281
2
R61231 2
R61271
2
R61221 2
J6100
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
4
5 6
7 8
9
U6100
1
7
6 5
2
84
3
C61001
2
R61011
2
R61301 2
R61311 2
R61021 2R6103
1 2
R61041 2
R61001 2
R61241 2
dvt
051-0675
6.0.0
61 OF 119
49 OF 94
88
88
49
81
81
83
83
81
49
49
49
49
49
49
88
49 83
49 83
49 83
49 83
49
49
49
49
49
ANALOGSYM 1 OF 2
AGND
AGND
AGND
AGND
HPGND
HPGND
HPGND
HSGND
PLLGND
VA_PLL
VA
VA_REF
VA_HP
SENSE_A1
SENSE_A2
HPOUT_L
HPOUT_R
HS3
HS4
HS4_REF
SENSE_B2
SENSE_B1
SENSE_D
SENSE_C
HS3_REF
HSIN+
HSIN-
LINEOUT1_L-
LINEOUT1_L+
LINEOUT1_R+
LINEOUT1_R-
LINEOUT2_L-
LINEOUT2_L+
LINEOUT2_R-
LINEOUT2_R+
LINEOUT3_R+
LINEOUT3_L+
LINEOUT3_R-
LINEOUT4_L+
LINEOUT4_L-
LINEOUT4_R+
LINEOUT4_R-
LINEOUT3_L-
VREF_ADC
VCOM
FLYN
FLYN
FLYP
VHP_FILT-
VREF_DAC
LINEIN_L+
LINEIN_R-
LINEIN_R+
LINEIN_L-
MICBIAS2_R
MICBIAS2_L
MICBIAS1_R
MICBIAS1_L
MICIN1_L+
MICIN2_L-
MICIN1_L-
MICIN1_R+
MICIN2_L+
MICIN2_R+
MICIN2_R-
HSBIAS_IN
HSBIAS
HSBIAS_REF
HSBIAS_FILT
MICIN1_R-
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NR/FB
NC
IN
EN
GND
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
APPLE P/N 353S4080AUDIO CODEC, ANALOG BLOCKS
LFT. SPKR AMP. SIG. SOURCE
RT. SPKR AMP. SIG. SOURCE
LFT SUBWOOFER AMP. SIG. SOURCE
RT. SUBWOOFER AMP. SIG. SOURCE
PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5
APPLE P/N 353S2456
4.5V POWER SUPPLY FOR CODEC
PLACE XW6201 NEAR 5V SOURCE
VFBGA
CS4208-CRZR
BYPASS=U6201.A1:A2:5 MM
16VX7R-CERM
10%
0402
0.1UF
X7R-CERM
10%0.1UF
16V
0402
BYPASS=U6201.N13:M11:5 mm
0805-LLP-1TANT-POLY
CRITICAL
20%16V
10UF
BYPASS=U6201.H12:H13:5 mm
0402
15UF
X5R4V
CRITICAL
20%
52 93
52 93
52 93
52 93
52 93
52 93
52 93
52 93
20%
TANT25V
1UF-10OHM
0603-LLP
CRITICAL
0805-LLP-1
10UF
CRITICAL
16V20%
TANT-POLY
BYPASS=U6201.A8:B10:5 mm
15UF
X5R4V20%
0402
CRITICAL
4.7UF20%10VX5R-CERM0402
1UF
10%25V
402X5R
201
1/20W1%
MF
2.21K
1UF
40225VX5R
10% 1UF
X5R402
25V10%
SM
2.2K
1/20WNOSTUFF 5%
201MF
FERR-22-OHM-1A-0.065-OHM
0201
1UF10%10V
402X5R
TPS71745
CRITICAL
SON
SM
CRITICAL
X5R-CERM
1.0UF20%10V
0201-1
10%
BYPASS=U6201.H12:L10:5 mm
X7R-CERM16V
0.1UF
0402
54 83
54
54
54
54
54
54
53 93
53 93
0805-LLP-1
16VTANT-POLY
20%10UF
54 83
54 83
10%
CRITICAL
X5R-CERM0201
0.01UF25V
0402X7R-CERM
10%16V
0.1UF
0402-1X5R-CERM10V20%10UF
CRITICAL
120-OHM-25%-1.3A
CRITICAL
0402
X5R-CERM
10%0.1UF
0201
16V
10%
X7R-CERM
0.1UF
16V
0402201
1/20WMF
22K
5%
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
AUDIO:CODEC, ANALOG
PP4V5_AUDIO_ANALOG
VREF_DACMIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM AUD_CH_HS_GNDMIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM HS_MIC_PMIN_LINE_WIDTH=0.3MM
HS_MIC_NMIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.5MM AUD_US_HS_GNDMIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.15MMVOLTAGE=4.5V
PP4V5_AUDIO_ANALOG
MIN_LINE_WIDTH=0.20MM
GND_AUDIO_CODEC
CODEC_MICIN2
TP_AUD_CODEC_MICBIAS2_R
MIN_LINE_WIDTH=0.3MM AUD_HP_PORT_LMIN_NECK_WIDTH=0.07MM
=PP5V_S4_AUDIO
GND_AUDIO_CODEC
4V5_NR
GND_AUDIO_CODEC
GND_AUDIO_CODEC
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.15MM
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.3MM AUD_HP_PORT_RMIN_NECK_WIDTH=0.07MM
GND_AUDIO_CODEC
AUD_HSBIAS_FILT
NC_AUD_LO4_LN
NC_AUD_LO4_LP
AUD_LO3_R_N
AUD_LO3_L_P
GND_AUDIO_CODEC
CODEC_VCOM
NC_AUD_LO4_RP
AUD_LO3_R_P
AUD_LO3_L_N
AUD_LO2_L_P
MIN_NECK_WIDTH=0.07MM AUD_HP_PORT_REFCHMIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.07MM AUD_HP_PORT_REFUSMIN_LINE_WIDTH=0.4MM
CODEC_VREF_ADC
GND_AUDIO_CODEC
NC_AUD_LO4_RN
AUD_LO2_R_N
AUD_LO2_R_P
AUD_LO2_L_N
NC_AUD_LO1_RN
NC_AUD_LO1_RP
NC_AUD_LO1_LP
NC_AUD_LO1_LN
AUD_TYPEDET
MIN_NECK_WIDTH=0.06MMMIN_LINE_WIDTH=0.3MMCODEC_HS_MIC_N
CODEC_HS_MIC_P MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.06MM
AUD_TIPDET_2
AUD_TIPDET_1
=PP3V3_S0_AUDIO
MIN_NECK_WIDTH=0.1 mmVOLTAGE=3.3VMIN_LINE_WIDTH=0.4 MMPP3V3_S0_AUDIO_ANALOG
MIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.20MM
VHP_FILTNMIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.20MM
CODEC_FLYP
MIN_LINE_WIDTH=0.20MMCODEC_FLYN
MIN_NECK_WIDTH=0.07MM
GND_AUDIO_CODEC
TP_AUD_CODEC_MICBIAS1_L
TP_AUD_CODEC_MICBIAS1_R
TP_AUD_CODEC_MICBIAS2_L
GND_AUDIO_CODEC
AUD_HSBIAS_IN
AUD_HSBIAS_REF
AUD_HSBIAS
MIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MMVOLTAGE=5V
4V5_REG_IN
4V5_REG_EN
PM_SLP_S3_BUF_L
=PP3V3_S0_AUDIO_DIG
VOLTAGE=5VMIN_NECK_WIDTH=0.20MM
PP5V_S4_AUDIO_XWMIN_LINE_WIDTH=0.60MM
U6201
M11
L6
L9
L10
B10
B11
A8
A10
C8
C10
A12
A13
C13
B13
C12
B12
L13
N11
L12
M13
D13
M6
N6
M10
N10
M9
N9
E13
E12
F12
F11
G11
F13
G13
G12
J11
H11
J13
J12
K12
K11
L11
K13
L8
L7
L5
L4
M8
N8
M7
N7
M5
N5
M4
N4
A2
C11
D12
E11
D11
M3
L3
N13
A9
A1
H12
M12
A11
N12
H13
C6218 1
2
C62171
2
C6212 1
2
C6216 1
2
C6215 1
2
C62191 2
C6210 1
2
C62111
2
C6222 1
2
C62211
2
C62201 2
R62061 2
C62241 2
C62251 2
XW6201
1 2
R62001 2
L6200
1 2
C62011
2
U6200
4
2
6
3
1
XW6200
1 2
C62031
2
C6202 1
2
C6214 1
2
C62131
2
L6201
1 2
C6226
1 2
C62001
2
R62071 2
dvt
051-0675
6.0.0
62 OF 119
50 OF 94
5
50
50
50 54
81
50 54
50 54
50 54
50 54
50 54
50 54
50 54
93
93
81
50 54
50 54
64 65 78 79 83
51 54 81
DIGITALSYM 2 OF 2
VD
VL_HD
VL_IF
VL_SP
VL_DM
NC
NC
NC
NC
NC
NC
NC
NC
NC
DMIC_SCL3
DMIC_SDA3
DMIC_SCL2
DMIC_SDA2
DMIC_SCL1
DMIC_SDA1
DMIC_SCL0
DMIC_SDA0
SPDIF_OUT
SPDIF_IN
SCL
SDA
SDIN_B
SDOUT_B
LRCK_B
SCLK_B
MCLK_B
RST*
SDO3
SDO2
SDO1
SDO0
GPIO0
GPIO1
GPIO5
GPIO4
GPIO3
GPO0
SYNC
BCLK
SDI0
GPO1
SDI1
SCLK_A
MCLK_A
LRCK_A
SDOUT_A
SDIN_A
GPIO2
DGND
LGND
LGND
LGND
LGND
LGND
PP
OUT
IN
OUT
IN
IN
IN
OUT
OUT
IN
OUT
PP
PP
PP
PP
OUT
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
AUDIO CODEC, DIGITAL BLOCKSAPPLE P/N 353S4080
CS4208-CRZRVFBGA
SHORT
402
OMIT
MF
5%1/20W
201
100K
201MF
5%100K
1/20W
SM
PLACE_NEAR=U6201.D1:5 mm
P3MM
53
0201
FERR-22-OHM-1A-0.065-OHM
11 88
11 88
11 51 88
11 51 88
201MF
5%
22
1/20W
10UF20%
0402-1X5R-CERM10V
10%0.1UF
0402
16VX7R-CERM
BYPASS=U6201.E1:F1:5 mm
0402-1X5R-CERM10V20%10UF
10%0.1UF
0201CERM-X5R6.3V
BYPASS=U6201.A7:E3:5 mm10%0.1UF
0201CERM-X5R6.3V
BYPASS=U6201.G1:F1:5 mm4.7UF20%4V
402X5R-1
10%0.1UF
0201CERM-X5R6.3V
BYPASS=U6201.K1:K3:5 mm
11 51 88
MF-LF1/16W
402
5%
3354
75
402MF-LF1/16W1%
54 83
51 54 83
10%0.1UF
X7R-CERM16V
BYPASS=U6201.J2:J1:5 mm0402
52
201
5%100K
1/20WMF
1/20W5%
MF
100K
NOSTUFF
201
P3MMSM
PLACE_NEAR=U6201.F2:5 mm
P3MMSM
PLACE_NEAR=U6201.N3:5 mm
P3MMSM
PLACE_NEAR=U6201.E2:5 mm
P3MMSM
PLACE_NEAR=U6201.D2:5 mm
53
54 83
54 83
AUDIO:CODEC, DIGITALSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
GPIO0_SPKR_SHUTDOWNPD_CS4208_GPIO1
SPKRCONN_L_ID
SPKRCONN_R_ID
DFET_OPENCH
NC_CS4208_GPO1
=PP1V5_S0_AUDIO
DFET_OPENUS
=PP3V3_S0_AUDIO_DIG
=PP3V3_S0_AUDIO_DIG
MIN_NECK_WIDTH=0.07MMVOLTAGE=1.5V
PP1V5_S0_AUDIO_DIGMIN_LINE_WIDTH=0.6 MM
HDA_BIT_CLKNC_DMIC_CLK2
NC_CS4208_SCLKB
HDA_SDIN0
HDA_SYNC
DMIC_CLK3
DMIC_SDA3
NC_DMIC_CLK0
CS4208_SPDIF_OUT SPDIF_OUT_JACK
NC_DMIC_CLK1
NC_CS4208_MCLKA
NC_CS4208_SDOUTB
NC_CS4208_LRCLKB
NC_CS4208_SCLKA
NC_CS4208_LRCLKA
NC_CS4208_SDOUTA
NC_CS4208_MCLKB
HDA_SYNC
TP_CS4208_HDA_SDOUT1
DMIC_SDA3
CS4208_SPDIF_IN
HDA_SDOUT
HDA_BIT_CLK
CS4208_HDA_SDOUT0_R
HDA_SDOUT
HDA_RST_L
CS4208_HDA_SDOUT0_R
=PP3V3_S0_AUDIO_DIG
NC_CS4208_GPO0
DMIC_CLK3_R
U6201
F2
J1
N2
M1
L1
L2
N3
N1
M2
K2
H3
H2
H1
C4
C5
C7
C9
B9
F1
E3
F3
J3
K3
B4
B5
A5
A6
F6
F7
F8
G6
G7
G8
H6
H7
H8
D3
B7
B2
B6
C6
D1
C1
B3
A4
D2
C2
C3
B1
A3
B8
G3
G2
E2
J2
K1
E1
G1
A7
L6300
1 2
C6300 1
2
C63011
2
R63311 2
C6305 1
2
C63021
2
C6306 1
2
C63071
2
C63031
2
C63041
2
R63301 2
R63321 2
R63241
2
R63221 2
PP63021
PP63011
PP63031
PP63041
R63021 2
R63231 2
R63251
2
PP63051
dvt
051-0675
6.0.0
63 OF 119
51 OF 94
81
50 51 54 81
50 51 54 81
11 51 88
51 54 83
11 51 88
51 88
11 51 88
51 88
50 51 54 81
VDD
EDGEGND
GAINSD*
OUT+
OUT-IN-
IN+
OUT
OUT
VDD
EDGEGND
GAINSD*
OUT+
OUT-IN-
IN+
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN-
IN+ OUT+
OUT-
GAINSHDN*
PVDD
NC
PGND
IN-
IN+ OUT+
OUT-
GAINSHDN*
PVDD
NC
PGND
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)APN: 353S2888 & 353S2958GAIN = +3 DB1ST ORDER FC (L&R) = NOM 569 HZ1ST ORDER FC (SUB) = NOM 9 HZ
FERR-1000-OHM
0402
CRITICAL
10%
402CERM
CRITICAL
0.22UF
16V
CRITICAL
0.22UF
10%
402CERM16V
16V
CRITICAL
CERM402
10%
0.22UF
16V
CRITICAL
CERM402
10%
0.22UF
SSM2375WLCSP
CRITICAL
54 83 93
54 83 93
BYPASS=U6430.C2:C1:5 mm
0.1UF10%16VX5R-CERM0201
CRITICAL
WLCSPSSM2375
54 83 93
54 83 93
10%0.1UF
0402X7R-CERM16V
BYPASS=U6440.C2:C1:5 mm
CRITICAL
47UF
TANT-POLYCASE-A4
20%6.3V
CRITICAL
100UF
CASE-AL16.3VTANT20%
CRITICAL
100UF20%
6.3VTANT
CASE-AL1
10%
0402
50V
4700PF
X7R-CERM
4700PF10%
0402
50VX7R-CERM
1/16W
402MF-LF
5%100K
CRITICAL0402
FERR-1000-OHM
50 93
51
FERR-1000-OHM
CRITICAL0402
54 83 93
BYPASS=U6410.A1:A2:5 mm
10%0.1UF
0402
16VX7R-CERM
BYPASS=U6420.A1:A2:5 mm
0201
0.1UF10%16VX5R-CERM
0402
FERR-1000-OHM
CRITICAL
50 93
54 83 93
CASE-A4
CRITICAL
6.3V20%
TANT-POLY
47UF
FERR-1000-OHM
CRITICAL
0402
50 93
FERR-1000-OHM
CRITICAL
0402
50 93
0.01UF
50VX7R-CERM
0402
10%
CRITICAL
0402
CRITICAL
50V10%
X7R-CERM
0.01UF
CRITICAL
X7R-CERM50V10%
0.01UF
0402
10%50V
X7R-CERM
CRITICAL
0402
0.01UF
54 83 93
54 83 93
WLPMAX98300
CRITICAL
100K5%
MF-LF402
1/16W
WLP
CRITICAL
MAX98300
MF-LF402
5%1/16W
100K
50 93
50 93
0402
FERR-1000-OHM
CRITICAL
0402
CRITICAL
FERR-1000-OHM
50 93
FERR-1000-OHM
CRITICAL
0402
50 93
AUDIO: SPEAKER AMPSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
PP5V_S0_AUDIO_AMP_L
LSUB_GAIN
RSUB_GAIN
PP5V_S0_AUDIO_AMP_R
SPKR_L_GAIN
SPKR_SHUTDOWN
SPKR_SHUTDOWN
AUD_LO2_L_P
SPKR_SHUTDOWN
AUD_LO3_L_N
AUD_LO3_L_P
AUD_LO3_R_N
AUD_LO3_R_P
AUD_LO2_R_N
SPKR_R_GAIN
AUD_LO2_R_P
AUD_LO2_L_N
LSUBIN_PNO_TEST=TRUE
LSUBIN_NNO_TEST=TRUE
NO_TEST=TRUE
RSUBIN_N
NO_TEST=TRUESPKRAMP_RIN_P
AUD_SPKRAMP_RSUBIN_P
AUD_SPKRAMP_LIN_N
NO_TEST=TRUESPKRAMP_LIN_N
AUD_SPKRAMP_RIN_P
AUD_SPKRAMP_RIN_N
SPKRCONN_SL_OUT_N MIN_NECK_WIDTH=0.10 MMMIN_LINE_WIDTH=0.40 MM
SPKRAMP_RIN_NNO_TEST=TRUE
MIN_NECK_WIDTH=0.10 MMMIN_LINE_WIDTH=0.40 MM
SPKRCONN_L_OUT_N
MIN_LINE_WIDTH=0.40 MMMIN_NECK_WIDTH=0.10 MM
SPKRCONN_L_OUT_P
MIN_NECK_WIDTH=0.10 MM
SPKRCONN_R_OUT_PMIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
SPKRCONN_R_OUT_NMIN_LINE_WIDTH=0.40 MM
NO_TEST=TRUERSUBIN_P
MIN_NECK_WIDTH=0.10 MMMIN_LINE_WIDTH=0.40 MM
SPKRCONN_SR_OUT_N
SPKRCONN_SR_OUT_P
MIN_NECK_WIDTH=0.10 MMMIN_LINE_WIDTH=0.40 MM
SPKRCONN_SL_OUT_P
MIN_LINE_WIDTH=0.40 MMMIN_NECK_WIDTH=0.10 MM
PP5V_S0_AUDIO_AMP_R
AUD_SPKRAMP_RSUBIN_N
GPIO0_SPKR_SHUTDOWN
SPKR_SHUTDOWN
PP5V_S0_AUDIO_AMP_L
NO_TEST=TRUE
SPKRAMP_LIN_P
AUD_SPKRAMP_LIN_P
AUD_SPKRAMP_LSUBIN_N
AUD_SPKRAMP_LSUBIN_P
R64001
2
L6401
1 2
L6411
1 2
C64111
2
C64211
2
L6421
1 2
C6412 1
2L6410
1 2
L6420
1 2
C6423
1 2
C6424
1 2
C6414
1 2
C6413
1 2
U6410
C3
B3
A3
C1
B1
A2
A1
C2
R64101
2
U6420
C3
B3
A3
C1
B1
A2
A1
C2
R64201
2
L6441
1 2
L6440
1 2
L6431
1 2
L6430
1 2
C6443
1 2
C6444
1 2
C6434
1 2
C6433
1 2
U6430
B2
A3
C1
A1
B1
B3
C3
A2
C2
C64311
2
U6440
B2
A3
C1
A1
B1
B3
C3
A2
C2
C64411
2
C6422 1
2
C6432 1
2
C6442 1
2
C64361
2
C64461
2
dvt
051-0675
6.0.0
64 OF 119
52 OF 94
B2
B2
52 82
52 82
52
52
52
93
93
93
93
93
9393
52 82
93
52
52 82
93
93
93
93
OUT
OUT IN
IN
IN
OUT
OUT
OUT
OUT
IN
PSEL
CP
GND
OUT2
OUT1
VDD
PSEL
CP
GND
OUT2
OUT1
VDD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
NOISE ISSUE SEEN ON EARLY HEADSETSR/C6550 FILTER TO ADDRESS OUT-OF-BAND
(SEE RADAR # 6210118)
50 93
50 93
201
100K1/20W
MF
5%
402MF-LF1/16W
2.2K
5%
27PF
CRITICAL
NP0-C0G25V
0201
5%
1/16W5%
2.2K
402MF-LF
54 93
54 93
NP0-C0G
1000PF25V5%
0402
51
53 54 83
53 54 83
53 54
53 54
51
25VNP0-C0G
1000PF5%
0402
402
1/16WMF-LF
10K5%
10%
X5R-CERM
0.1UF16V
0201
BYPASS=U6501.B2:3MM
CERM-X5R
1.0UF
0402
10%35V
10%10V
CRITICAL
0201X7R-CERM
3300PF
0.01UF10VX5R-CERM0201
10%
BYPASS=U6501.B2:3MM
TAIC3027A0YFFRWCSP
TAIC3027A0YFFRWCSP
5%10K
MF-LF1/16W
402
10%
0201X5R-CERM10V
0.01UF
BYPASS=U6500.B2:3MM
0201
16V
0.1UF
X5R-CERM
10%
BYPASS=U6500.B2:3MM
35V10%
0402
1.0UF
CERM-X5R
AUDIO: JACKSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
DFET_CPO2
AUD_CONN_SLEEVE_XWAUD_CONN_SLEEVE_XW
HS_MIC_N
HS_MIC_P
MIN_NECK_WIDTH=0.06MM
AUD_HS_MIC_NMIN_LINE_WIDTH=0.2MM
AUD_HS_MIC_PMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.06MM
DFET_OPENUS
DFET_OPENCH
DFET_CPO1
AUD_CONN_RING2_XWAUD_CONN_RING2_XW
R65561
2
R65501 2
C65581
2R65591 2
C65011
2
C65021
2
R65201
2
C65421
2
C65301
2
C65501
2
C65431
2
U6500
C1
B1
A1
A2
C2
B2
U6501
C1
B1
A1
A2
C2
B2
R65211
2
C65631
2
C65621
2
C65601
2
dvt
051-0675
6.0.0
65 OF 119
53 OF 94
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
NC
GND
VDD
AUDIO GND
SHELL
VIN
MIC
DET2
DET1
1RTN
2RTN
R.AUDIO
AUDIO GND
PINS
POFOPERATING VOLTAGE 3.3
AUDIO
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
HIGH = DFETs OPEN
TWEETERS 0X03 (3)
0X04 (4)
PIN COMPLEX
HIGH = FG, LOW = MERRY
CODEC OUTPUT SIGNAL PATHS
VREF
3.3V
CODEC GPIO0
CODEC GPIO0
0X1C (28)DMIC 2
2.7V0X18 (24)0X07 (7)
PIN COMPLEX
0X02 (2)
0X03 (3) APN: 518S0672
SPEAKER CONNECTOR
INPUT
HP=80HZ
CODEC INPUT SIGNAL PATHS
HP/HS OUT N/A
N/A
FUNCTION MUTE CONTROLCONVERTERVOLUME
0X10 (16)
FUNCTION
0X02 (2)
SPDIF OUT
0X04 (4)
CONVERTER
N/A
0X12 (18)
0X13 (19)
0X21 (33)
GPIO3
INPUTGPIO2
0X09 (9)
0X09 (9) 3.3V
0X1C (28)
0X0E (14)
OTHER CODEC GPIO LINES
APN: 518S0769
2-MIC CONNECTOR
GPIO4 OUTPUT
RIGHT SPEAKER ID
LEFT SPEAKER ID
HEADSET MIC
DMIC 1
SUB
HIGH = FG, LOW = MERRY
APN: 514-0875
DFET CONTROL
CRITICAL
78171-6006M-RT-SM
78171-6006
CRITICAL
M-RT-SM
52 83 93
52 83 93
52 83 93
51 83
52 83 93
51 83
52 83 93
52 83 93
52 83 93
52 83 93
51 83
51 83
SHORT
OMIT
402
50 83
50 83
53 93
53 93
50
50
50
50
50 83
FERR-470-OHM
0201
CRITICAL
120-OHM-25%-1.3A
0402
CRITICAL 0201
CRITICAL
FERR-470-OHM
CRITICAL
120-OHM-25%-1.3A
0402
50
50
CRITICAL
0201
FERR-470-OHM
10%
X5R402-1
1UF10V
10%0.1UF
0201CERM-X5R6.3V
MF-LF1/16W
10K
402
5%
SM
PLACE_NEAR=J6600.3:2.54mm
PLACE_NEAR=J6600.5:2.54mm
SM
SM
SM
FF14A-5C-R11DL-B-3HF-RT-SM
ESDALC5-1BM2SOD882
CRITICAL
CRITICAL
SOD882ESDALC5-1BM2
ESDALC5-1BM2SOD882
CRITICAL
SOD882ESDALC5-1BM2
CRITICALCRITICAL
SOD882ESDALC5-1BM2
ESDALC5-1BM2
CRITICAL
SOD882
SOD882
CRITICAL
ESDALC5-1BM2
51
NP0-CERM25V
100PF5%
0201
120-OHM-25%-1.3A
CRITICAL
0402
120-OHM-25%-1.3A
CRITICAL
0402
120-OHM-25%-1.3A
CRITICAL
0402
120-OHM-25%-1.3A
0402
CRITICAL
0201
25VNP0-CERM
100PF5%
25VNP0-CERM
0201
5%100PF
100PF5%
0201
25VNP0-CERM
25VNP0-CERM
100PF5%
0201
5%25V
0201NP0-CERM
100PF
NP0-CERM25V
100PF5%
0201
AUDIO-SPDIF-J44F-RT-TH
MF1/20W
201
5%2.2K
2.2K5%1/20WMF201
AUDIO: JACK TRANSLATORSSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
AUD_HP_PORT_REFUS
AUD_HP_PORT_L
AUD_HP_PORT_R
GND_AUDIO_CODEC
AUD_CONN_TIPDET_2
MIN_LINE_WIDTH=0.3MMAUD_CONN_HP_LEFT
MIN_NECK_WIDTH=0.06MM
AUD_CONN_TIPDET_1
AUD_CONN_HP_RIGHT
MIN_NECK_WIDTH=0.06MMMIN_LINE_WIDTH=0.3MM
AUD_TIPDET_2
AUD_CONN_RING2
MIN_NECK_WIDTH=0.06MMMIN_LINE_WIDTH=0.4MM
AUD_CONN_SLEEVE
MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.06MM
DMIC_CLK3
DMIC_SDA2
AUD_CONN_SLEEVE_XWMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.1MM
=PP3V3_S0_AUDIO_DIG
AUD_CONN_TYPEDET
AUD_CH_HS_GND
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.5MMAUD_CONN_RING2_XW
SPKRCONN_SR_OUT_N
SPKRCONN_R_OUT_N
SPKRCONN_R_OUT_P
DMIC_SDA3
=PP3V3_S0_AUDIO_DIG
AUD_TYPEDET
SPKRCONN_L_ID
SPKRCONN_L_OUT_P
SPKRCONN_SR_OUT_P
SPKRCONN_R_ID
SPKRCONN_SL_OUT_P
SPKRCONN_SL_OUT_N
SPKRCONN_L_OUT_N
AUD_HP_PORT_REFCH
AUD_HS_MIC_P
AUD_US_HS_GND
AUD_HS_MIC_N
SPDIF_OUT_JACK
AUD_TIPDET_1
J6602
7
8
1
2
3
4
5
6
J6603
7
8
1
2
3
4
5
6
R66801 2
L6606
1 2
L6605
1 2
L6607
1 2
L6604
1 2
L6608
1 2
C6600 1
2
C66011
2
R66011
2
XW66001 2
XW66021 2
XW66011 2
XW66031 2
J6601
7
6
1
2
3
4
5
DZ6607
1
2
DZ66021
2
DZ66061
2
DZ66041
2
DZ66011
2
DZ6603
1
2
DZ66051
2
C6608 1
2
L6611
1 2
L6612
1 2
L6613
1 2
L6614
1 2
C66071
2
C6602 1
2
C6605 1
2
C6606 1
2
C6604 1
2
C66031
2
J6600
1
10
11
12
13
14
15
2
3
4
5
6
7
8
9
R6603
1
2
R6602
1
2
dvt
051-0675
6.0.0
66 OF 119
54 OF 94
50
83
53 83
50 51 54 81
53
50 51 54 81
VCC
EXT INT
NC GND
NC
POS
NEG
SYS_DETECT
SDA
POS
POS
POS
SCL
NEG
NEG
NEG
VER 1
NCNC
BI
NC
G
D
S
SW
BOOSTVIN
BIAS
SHDN*
GND
NC
FB
PADTHRM
IN
Y
B
A
Apple Inc.
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SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
1-Wire OverVoltage Protection
send transients onto ADAPTER_SENSE when AC is
The chassis ground will otherwise float and can
Vout = 1.25V * (1 + Ra / Rb)
APN:353S3733
300MA MAX OUTPUT
Vout = 3.425V
(Switcher limit)
MagSafe DC Power Jack
3.425V "G3Hot" SupplySupply needs to guarantee 3.31V delivered to SMC VRef generator
<Rb>
<Ra> BATTERY CONNECTOR
518-0376
6.8V Zener
for D2 design only
When input voltage is 2V the FET will be off
connected.
518S0508
When input voltage is at 16V+, FET willconduct and power charger and 3.42V reg
properly detected.blocking the leakage path and 22.1K can be
sparkitecture requirementsInput impedance of 22.1K meets
CRITICAL
0603
6AMP-32V-0.0095OHM
NOSTUFF
0.01UF50VCERM0603
20%
CRITICAL
SC70-5MAX9940
10%25VX5R
0.1UF
402
10%25VX5R
1UF
603-1
RCLAMP2402B
SC-75
CRITICAL
MF-LF
10K
402
1/16W5%
50V
22PF
0201NP0-C0G-CERM
5%
1%200K
MF1/20W
201
20%
603
6.3V
22UF
X5R-CERM-1
348K1%
MF1/20W
201
1/8W
10
805MF-LF
5%
805
1%
47
1/3WMF
CRITICAL
BAT30CWFILMSOT-323
DP418C-SM
33UH-20%-0.39A-0.435OHM
CRITICAL0.22UF
CERM10V10%
402
BAT-J5F-ST-TH
CRITICAL
CRITICAL
M-RT-SMWTB-PWR-M82
40
402
1/16W
2.0K
MF-LF
5%
SI5419DUPOWERPAK
100K
MF1/20W
201
5%
22.1K1%
MF1/20W
201
SMCDZ6.8B
0603X5R-CERM
10%35V
4.7UF4.7UF
0603
10%35V
X5R-CERM
NOSTUFF
0603
35V10%
4.7UF
X5R-CERM
10%35V
X5R-CERM
4.7UF
0603
4.7UF
NOSTUFF
0603
35V10%
X5R-CERM
4.7UF10%35V
X5R-CERM0603
NOSTUFF
0.047UF10%25VX5R0402 10K
MF1/20W
201
5%
DFN
CRITICAL
LT3470AED
10V20%
402CERM
0.1UFPLACEMENT_NOTE=PLACE NEAR U7100 and U7001
40 41 42
CRITICAL
TC7SZ08FEAPESOT665
0.1UF
CERM402
20%10V
MF1/20W
0201
0
5%
NOSTUFFNONE
402NONENONE
OMIT NOSTUFF
49.9K1%
MF1/20W
201
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
DC-In & Battery Connectors
SMC_BC_ACOK_VCC
DCIN_ISOL_GATE_R
DCIN_ISOL_GATE
SYS_DETECT_L
P3V42G3H_SHDN_L
P3V42G3H_FB
=PP3V42_G3H_REG
PPVBAT_G3H_CONN
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
TP_TDM_ONEWIRE_MPM
=PP20V_DCIN_CONN
=PP3V42_G3H_ONEWIREPROT
SYS_ONEWIRE
SMC_BC_ACOK
ADAPTER_SENSE
=PPBUS_G3H
=PP20V_DCIN_ISOL
VOLTAGE=20V
PP20V_DCIN_CONN_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
PPVIN_G3H_P3V42G3H
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
VOLTAGE=20V
PP20V_DCIN_FUSE
VOLTAGE=20V
MIN_LINE_WIDTH=1MMMIN_NECK_WIDTH=0.20MM
P3V42G3H_BOOSTDIDT=TRUE
MIN_NECK_WIDTH=0.25 mm
DIDT=TRUESWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.5 mmP3V42G3H_SW
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
PPBUS_G3H_R
VOLTAGE=18.5V
F7005
1 2
C70051
2
U7000
5
2
4
1
C7050 1
2
C7060 1
2
D7050
3
1 2
R70501
2
C70951
2
R70961
2
C70991
2
R70951
2
R70051 2
R70201 2 D7005
1
2
3
L7095
1 2
C7094 1
2
J7050
1021
1122
112
213
314
415
516
617
718
819
920
J7000
1
2
3
4
5
6
R70291
2
Q7010
1
4
5
5A R70101
2
R70121
2
D7010
A
K
C7091 1
2
C7090 1
2
C7092 1
2
C7093 1
2
C7096 1
2
C7097 1
2
C70121
2 R70111 2
U7090
2
3
1
5
8 4
9
6
C70081
2
U7001
2
1
3
5
4
C7000 1
2
R70011 2
C7001 1
2
R70021
2
dvt
051-0675
6.0.0
70 OF 119
55 OF 94
3
7
83
81
56 83
43
43
81
81
83
56 81
81
83
OUT
OUT
IN
BI
OUT
AMON
BMON
ACOK
LGATE
PHASE
BOOT
SGATE
AGATE
CSIP
CSIN
DCIN
VNEG
CSOP
CSON
THRM_PAD
PGND
VDDPVDD
BGATE
UGATE
ICOMP
VCOMP
ACIN
SDA
VFRQ
CELL
VHST
SCL
SMB_RST_N
IN
S
G
D
G
D
S
IN
NC
SW
BOOSTVIN
BIAS
SHDN*
GND
NC
FB
PADTHRM
NC
NCNCNC
G G
S D SD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(L7130 limit)
f = 400 kHz
Reverse-Current Protection
(CHGR_DCIN)
(CHGR_SGATE)
For Erp Lot6 spec
TO SYSTEM
(P5V1_BIAS)
(CHGR_CSO_P)
(PPVBAT_G3H_CHGR_R)
(GND)
Vout = 5.50V
Vout = 1.25V * (1 + Ra / Rb)
20V/V
TO/FROM BATTERY
36V/V
(AGND)
(CHGR_BGATE)
(CHGR_AGATE)
(PPVBAT_G3H_CHGR_R)
353S2392
(OD)
Max Current = 8A
(Switcher limit)100MA MAX OUTPUT
<Rb>
<Ra>
FROM ADAPTER
30mA max load
(CHGR_CSO_N)
Inrush Limiter
152S1466
Sparkitecture impedance is set by R7112 in D2
Divider sets ACIN threshold at 13.55V
ACIN pin threshold is 3.2V, +/- 50mV
X5R-CERM0402
10%50V0.1UF
50V10%
0402CERM
470PF
1%
402MF-LF
3.01K1/16W
50V10%
0402X7R-CERM
220PF
1/16W5%
402MF-LF
330K
10V10%
402X5R
1UF
1UF
402-1
10V10%
X5R
1/16W5%
402MF-LF
4.7
16V
0402
0.01UF10%
X7R-CERM16V10%
0402X7R-CERM
0.1UFPLACE_NEAR=U7100.22:1mmPLACE_NEAR=U7100.29:1mm
SM
10V10%
402X5R
1UF25V10%
402X5R
0.1UF25V10%
402X5R
0.1UF
0.047UF10V10%
0402X5R-CERM
10V
PLACE_NEAR=U7100.25:2mm
10%
402CERM
0.22UF
LFPAK-HFRJK0305DPB
CRITICAL
1/16W5%
402MF-LF
10
5%
MF-LF
10
402
1/16W
1/16W5% 402MF-LF2.2
1/16W5% 402MF-LF0
44
44
43
43
16V10%
0402X7R-CERM
0.01UF
16V10%
402X5R
1UF
50V10%
0402X7R-CERM
0.001UF
42
CRITICAL
1W
0612
0.5%0.020
MF-LF
50V10%
0402X7R-CERM
0.001UF
50V10%
0402
0.001UF
X7R-CERM
TQFN
ISL6259
CRITICAL
NO STUFF
1/16W5%
402MF-LF
100K
65
SO-8SI7137DP
CRITICAL
SOT-323BAT30CWFILM
CRITICAL
1/16W1%
402MF-LF
1K
LFPAK-SMRJK0332DPB-01
CRITICAL
16V20%
CASE-D2E-SMPOLY-TANT
68UF
CRITICAL
1/16W5%
402MF-LF
20
35V10%
603X5R
1UF
CRITICAL
35V10%
603X5R
1UF
CRITICAL
25V10%
X5R
1UF
603-1
1/16W5%
402MF-LF
04041
49
83
25V10%
X5R402
0.1UF1/16W1%
402MF-LF
470K
1/16W1%
402MF-LF
332K 5%
402MF-LF
62K1/16W
1/16W5%
MF-LF
100K
402
8AMP-32V-0.006OHM
0603
CRITICAL
8AMP-32V-0.006OHM
0603
CRITICAL
0612-3
1W1%
MF
0.005
CRITICAL
PIME173T-SM
4.7UH-20%-14.5A-9MOHM
CRITICAL
35V20%
CASE-D2-SMTANT-POLY
10UF
CRITICAL
35V20%
CASE-D2-SMTANT-POLY
10UF
CRITICAL
35V20%
CASE-D2-SMTANT-POLY
10UF
CRITICAL
35V20%
CASE-D2-SMTANT-POLY
10UF
CRITICAL
35V20%
CASE-D2-SMTANT-POLY
10UF
CRITICAL
1/16WMF-LF402
5%1K
1/20W1%
201MF
681K 10V20%
0603X5R
10UF
CRITICAL
1/20W1%
201MF
200K
10V10%
402CERM
0.22UF
DP418C-SM
33UH-20%-0.39A-0.435OHM
CRITICAL
50V5%
0201NP0-C0G-CERM
22PF
35V10%
0805X5R-CERM
4.7UF
DFNLT3470A
CRITICAL
NOSTUFF
1/16W5% 402MF-LF
0
CHGR_5V:LDO
1/16W5% 402MF-LF
0
10V20%
0603X5R
10UF
CRITICAL
MF-LF
CHGR_5V:LDO
1/16W5% 402
0
50V10%
0603-1X5R-CERM
0.22UF
1/16W1%
402MF-LF
130K
1/16W1%
402MF-LF
40.2K
NOSTUFFNONENONENONE
OMIT
603IRF9395TRPBF
CRITICAL
DIRECTFET-MC
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
PBus Supply & Battery Charger
PPVBAT_G3H_CONN
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 mm
VOLTAGE=12.6V
PPVBAT_G3H_CHGR_R
CHGR_BGATE
PP5V1_CHGR_VDD
VOLTAGE=5.1V
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm
CHGR_CSO_R_P
CHGR_CSO_R_N
CHGR_AGATECHGR_CSI_P
=PPDCIN_S5_CHGR
=PPBUS_G3H
CHGR_CSO_N
=CHGR_ACOKCHGR_BMON
CHGR_VCOMP_R
CHGR_ICOMP
PP5V1_CHGR_VDDP
CHGR_DCIN
CHGR_DCIN_D_R
SMC_RESET_L
CHGR_AMON
CHGR_VCOMP
=SMBUS_CHGR_SCL
GND_CHGR_AGND
CHGR_VFRQ
CHGR_RST_L
CHGR_VNEG
CHGR_ICOMP_RC
=SMBUS_CHGR_SDA
P5V1_FB
=PP3V42_G3H_CHGR
CHGR_VNEG_R
CHGR_CELL
CHGR_ACIN
CHGR_CSI_N
CHGR_CSI_R_N
CHGR_CSI_R_P
CHGR_CSO_P
=PPDCIN_S5_CHGR_ISOL
CHGR_DCIN
CHGR_SGATE
CHGR_UGATEMIN_LINE_WIDTH=0.6 mm
DIDT=TRUEGATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=0V
GND_CHGR_AGND
VOLTAGE=20VMIN_NECK_WIDTH=0.25 mm
PPDCIN_G3H_INRUSHMIN_LINE_WIDTH=0.6 mm
CHGR_AGATE_DIVMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm
CHGR_SGATE_DIV
P5V1_BIAS
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
P5V1_VIN
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mmCHGR_DCIN_D_RMIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmCHGR_LGATE DIDT=TRUEGATE_NODE=TRUE
P5V1_BOOSTDIDT=TRUE
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmP5V1_SW
SWITCH_NODE=TRUEDIDT=TRUE
VOLTAGE=5.1V
MIN_LINE_WIDTH=0.2 mmPP5V1_CHGR_VDDPMIN_NECK_WIDTH=0.2 mm
CHGR_BOOT DIDT=TRUE
SWITCH_NODE=TRUE
CHGR_PHASE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=20VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmPPDCIN_G3H_CHGR
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmPPVBAT_G3H_CHGR_REG
VOLTAGE=12.6V
C71421
2
C71161
2
R71161
2
C7115 1
2
R71151
2
C7102 1
2
C71001
2
R71011 2
C7157 1
2
C7156 1
2
XW71001 2
C7101 1
2
C71211
2
C7122 1
2
C71201
2
C71251
2
Q7135
5
4
1 2 3
R71221 2
R71211 2
R7151 1 2
R7152 1 2
C7111 1
2
C71501
2
C7126 1
2
R71202
1
4
3
C71371
2
C71451
2
U7100
3
14
1
9
16
15
25
627
28
17
18
2
5
21
22
23
11
10
2613
29
24
7
19
20
4
12
8
R71021
2
Q7155
5
4
12
3
D7105
1
2
3
R71121
2
Q7130
5
4
1 2 3
C71401
2
R71051 2
C71351
2
C71361
2
C7155 1
2
R71001 2
C71851
2
R71851
2
R71861
2
R71811
2
R71801
2
F71411 2
F71401 2
R7150
2 14 3
L7130
1 2
C71301
2
C71311
2
C71321
2
C71331
2
C71341
2
R71421
2
R71951
2
C71981
2
R71961
2
C7194 1
2 L7195
1 2
C71951
2
C7190 1
2 U7190
2
3
1
5
8 4
9
6
R71901 2
R71911 2
C71991
2
R71921 2
C7105 1
2
R71101
2
R71111
2
C71801
2
Q7180
8 79 10
6 3
4 15 2
dvt
051-0675
6.0.0
71 OF 119
56 OF 94
7
55 83
93
93
92
81
55 81
92
56
56
56
56
65 81
92
93
93
92
81
56
56
56
56
BI
IN
OUT
IN
OUT
ISEN3
ISEN2
ISEN1
IMON
ISUMN
ISUMP
FB2
FB
RTN
COMP
SCLK
ALERT*
SDA
NTC
VINVDD
FCCM
PWM1
PWM2
PWM3
DRSEL
PGOOD
THRM
VR_ON
PROG3
NC
NC
NC
NC
PROG2
SLOPE
VR_HOT*
PROG1
PAD
OUT
OUT
NC
NCNC
OUT
OUT
OUT
NC
IN
IN
IN
IN
OUT
IN
IN
IN
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(GND)
(CPU_VCCSENSE_N)
(CPUVR_ISUMP)
886
886
886
65
640 41 86
201
1/20WMF
1%54.9
PLACE_NEAR=U7200.32:2mm
201
1/20WMF
1101%
PLACE_NEAR=U7200.30:2mm
LLP
CRITICAL
ISL95826
OMIT_TABLE
19
58
58
58
58
MF
2.49M
0402
1/16W1%
5%
402
10
MF-LF1/16W
0402
0.22UF10%25VX7R
PLACE_NEAR=U7200.17:2mm
5%
1
402MF-LF1/16W
PLACE_NEAR=U7200.16:2mm
X5R10V10%1UF
402-1
58
58
58
0.22UF
X6S-CERM6.3V20%
0201X6S-CERM
0.22UF
0201
20%6.3V
20%6.3V
0201X6S-CERM
0.22UF
58
0.1UF10%
X6S0201
6.3V
201
1/20WMF
1%4.02K
201
1/20WMF
154K1%
45
93.1K1%
MF1/20W
201X7R
10%1500PF
10V
0201
58
NO_XNET_CONNECTION=TRUE
201
10%25V
X7R-CERM
220PF201
1/20W MF
845
1% 20110V X7R-CERM10%
2700PF
5% 20125V NP0-C0G
39PF
886
986
16V10%330PF
0201X7R-CERM
0201X7R-CERM16V10%330PF
X7R-CERM
10%25V
1800PF
0201
5%
NP0-CERM0201
25V
NO_XNET_CONNECTION=TRUE
100PF
5%
NO_XNET_CONNECTION=TRUE
25V
0201NP0-C0G-CERM
18PF
1%
201
1/20WMF
NO_XNET_CONNECTION=TRUE
365K
201
1/20WMF
1%
1K5%
0
0201
1/20WMF
201
1/20WMF
1%
9.31K
201
1/20WMF
1%95.3K
0201
100KOHM
201
1/20WMF
NO_XNET_CONNECTION=TRUE
NO STUFF
1%
2K
0201
10%16VX7R-CERM
330PF
NO STUFF
201
1/20WMF
1%
2.87K
201
1/20WMF
487
1%
201
1/20WMF
102K1%
201
1/20WMF
9.31K1%
0201
5%
NP0-C0G-CERM
47PF25V
16V10%
0402X7R-CERM
0.01UF
U7200 CRITICALIC,ISL95826R6200,PWM,PGOOD,SCREEN,32P,QFN353S4170 1
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
CPU VR12.5 VCC Regulator IC
CPUVR_NTC_R
CPU_VIDALERT_LCPU_VIDSOUT
CPUVR_NTCPPVCCIO_S0_CPU
CPU_VCCSENSE_P_R
CPUVR_COMPCPUVR_ISUMP
CPUVR_VR_ON
CPUVR_PROG2
CPU_VCCSENSE_P
CPUVR_COMP_RC
CPUVR_PROG3 CPUVR_PWM1
CPUVR_ISUMN_RC
=PPVIN_S0_CPUVR
CPUVR_PGOOD
CPUVR_PWM3CPUVR_PWM2
CPUVR_FCCM
CPUVR_DRSEL
=PP5V_S0_CPUVR
CPUVR_SLOPE
PPVIN_S0_CPUVR_VINMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=12.9V
PP5V_S0_CPUVR_VDDMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm
VOLTAGE=5V
CPUVR_FB_RC
CPU_PROCHOT_L
CPUVR_ISEN3
CPUVR_PROG1
CPU_VIDSCLK
CPU_VCCSENSE_P_RC
CPUVR_FB2
CPU_VCCSENSE_N
CPUVR_ISEN1
CPUVR_ISUMN_R
CPUVR_FB
CPUVR_IMON
CPUVR_ISEN2
CPUVR_ISUMN
R72791
2
R72801
2
U7200
31
6
25
7
8
18
3
12
11
10
14
15
9
19
21
24
5
2
28
27
26 20
22
23
13
32
30
29
33
16
17
4
1 R72241 2
R72021 2
C7202 1
2
R72011 2
C72011
2
C72101
2
C72111
2
C72121
2
C7213 1
2
R72201
2
R72211
2
R72301
2
C7230 1
2
C7214 1
2
R72151 2
C72151 2
C72161 2
C72601
2
C72611
2
C7240 1
2
C724212
C7241 1
2
R72401
2
R724212
R72431 2
R72351 2
R72361
2
R7237
1
2
R72501 2
C72501
2
R72411 2
R72101 2
R72231
2
R72221
2
C7231 1
2
C72791
2
dvt
051-0675
6.0.0
72 OF 119
57 OF 94
5 6 8 10 18
58 81 58 81
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
PWM
VCIN
VDRV
CGND
NC
VIN
VSWH
PGND
BOOT
DISB*
GL
GH
PHASE
ZCD_EN*
THWN*
NC
NC
NC
NC
PWM
VCIN
VDRV
CGND
NC
VIN
VSWH
PGND
BOOT
DISB*
GL
GH
PHASE
ZCD_EN*
THWN*NC
NC
NC
NC
IN
NC
NC
NC
NC
PWM
VCIN
VDRV
CGND
NC
VIN
VSWH
PGND
BOOT
DISB*
GL
GH
PHASE
ZCD_EN*
THWN*
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Additonal Input Bulk CapsTHESE TWO CAPS ARE FOR EMC
Vout = 1.85V max95A max outputf = 450 kHz
THESE TWO CAPS ARE FOR EMC
THESE TWO CAPS ARE FOR EMC
152S1538
353S3836
PHASE 1
PHASE 3
PHASE 2
353S3836
353S3836
152S1538
152S1538
CRITICAL
68UF
POLY-TANT16V20%
CASE-D2E-SM
CRITICAL
68UF
CASE-D2E-SMPOLY-TANT16V20%
16V20%68UF
POLY-TANTCASE-D2E-SM
CRITICAL
0.001UF10%50VX7R-CERM0402
0.001UF10%
0402
50VX7R-CERM
1UF10%
0402X6S-CERM16V
10UF20%
X6S-CERM16V
CRITICALNOSTUFF
0603
NOSTUFFCRITICAL
10UF
0603X6S-CERM16V20%
0.00075
1W1%
MF0612
CRITICAL
1/20WMF201
1%3.9
CRITICAL
68UF
16V20%
CASE-D2E-SMPOLY-TANT
68UF
16V20%
POLY-TANTCASE-D2E-SM
CRITICAL
PIMS103T-SM
CRITICAL
0.36UH-20%-36A-0.00108OHM
NOSTUFF
5%2.2
1/10WMF-LF
603
0402X7R-CERM
10%50V
NOSTUFF
0.001UF57
57 58
CRITICAL
68UF
POLY-TANT16V20%
CASE-D2E-SM
201MF
1%1/20W
10K
NO_XNET_CONNECTION=TRUE
MF
1%1K
201
1/20W
57
57 58
57 58
10K
1/20W1%
MF201
NO_XNET_CONNECTION=TRUE
X7R-CERM0402
50V10%0.001UF
57 58
X7R-CERM
0.001UF50V
0402
10%
X6S-CERM0402
10%1UF16V
1/20WMF201
1%3.9
10UF
NOSTUFFCRITICAL
X6S-CERM16V
0603
20%
CRITICAL
10UF20%
X6S-CERM0603
16V
NOSTUFF
CASE-D2E-SMPOLY-TANT
20%16V
68UF
CRITICALCRITICAL
20%
CASE-D2E-SMPOLY-TANT
68UF
16V
CRITICAL
PIMS103T-SM
0.36UH-20%-36A-0.00108OHM
X7R-CERM
0.001UF
NOSTUFF
10%50V
0402
NO_XNET_CONNECTION=TRUE
10K1/20W
201MF
1%1%1K
201MF
1/20W
NOSTUFF
5%
603
2.2
1/10WMF-LF
57
0402X7R-CERM50V
0.001UF10%
57 58
0.001UF10%50VX7R-CERM0402
10%1UF16VX6S-CERM0402
1/20WMF201
1%3.9
NOSTUFFCRITICAL
20%16VX6S-CERM0603
10UF
CRITICALNOSTUFF
20%10UF16VX6S-CERM0603
68UF20%16V
CRITICAL
CASE-D2E-SMPOLY-TANT
CRITICAL
20%68UF
16V
CASE-D2E-SMPOLY-TANT
CRITICAL
0.36UH-20%-36A-0.00108OHM
PIMS103T-SM
NOSTUFF
0402X7R-CERM
10%50V
0.001UF
NO_XNET_CONNECTION=TRUE
1/20W
10K
MF
1%
201
1K
201
1%
MF1/20W
NOSTUFF
2.25%
MF-LF603
1/10W
57
57 58
57
57 58
CRITICAL
PQFNFDMF6808N5%
MF-LF
0
402
1/16W
10%16VCERM402
0.22UF
1UF16V10%
X6S-CERM0402
CRITICAL
PQFNFDMF6808N
1UF
16V10%
X6S-CERM0402
5%
MF-LF1/16W
0
402
10%16VCERM
0.22UF
402
57 58
0402X6S-CERM
10%16V
1UF
FDMF6808NPQFN
CRITICAL
0
1/16WMF-LF
5%
402
402
0.22UF
CERM16V10%
57
57 58
CRITICAL
0612
0.00075
1W1%
MF
CRITICAL
0612MF1W
0.000751%
20%16V
CASE-D2E-SMPOLY-TANT
CRITICAL
68UF20%16VPOLY-TANTCASE-D2E-SM
68UF
CRITICAL
16V20%68UF
POLY-TANTCASE-D2E-SM
CRITICAL
20%15UF
TANTSM
16V
CRITICAL CRITICAL
16V20%
TANTSM
15UF
CRITICAL
16V20%15UF
TANTSM
CRITICAL
16V20%15UF
TANTSM
10K
NO_XNET_CONNECTION=TRUE1/20W1%
MF201
MF1/20W
201
10K
1% NO_XNET_CONNECTION=TRUE
MF1/20W
201
10K
1% NO_XNET_CONNECTION=TRUE
MF1/20W
201
10K
1% NO_XNET_CONNECTION=TRUE
NO_XNET_CONNECTION=TRUE1%
10K
201
1/20WMF
SYNC_DATE=04/26/2013
CPU VR12.5 VCC Power StageSYNC_MASTER=CLEAN_J45
=PPVCC_S0_CPU_REG
=PPVIN_S0_CPUVR
CPUVR_ISUMN
CPUVR_ISNS2_P
CPUVR_PH2_SNUBDIDT=TRUE
CPUVR_ISEN1
CPUVR_ISNS3_N
CPUVR_PHASE3_K
CPUVR_PHASE2_K
CPUVR_PHASE1_K
=PP5V_S0_CPUVR
CPUVR_PWM1 CPUVR_ISNS2_N
CPUVR_ISNS1_N
=PP5V_S0_CPUVR
CPUVR_PWM3
CPUVR_FCCM
CPUVR_FCCM
=PP5V_S0_CPUVR
CPUVR_PWM2
CPUVR_ISNS2_N
CPUVR_ISUMP
CPUVR_ISUMP
CPUVR_ISUMP
CPUVR_ISNS3_P CPUVR_ISNS3_N
CPUVR_ISUMN
CPUVR_FCCM
CPUVR_ISNS1_N
CPUVR_ISNS3_N
CPUVR_ISEN2
CPUVR_ISNS1_N
CPUVR_ISNS2_N
CPUVR_ISEN3
DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MM
CPUVR_BOOT2VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
PPVCC_S0_CPU_PH2
PPVCC_S0_CPU_PH1
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
DIDT=TRUE
CPUVR_PH1_SNUB
DIDT=TRUE
CPUVR_PH3_SNUB
CPUVR_BOOT1_RC
DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MMDIDT=TRUE
CPUVR_BOOT3_RC
MIN_LINE_WIDTH=0.25 MM
DIDT=TRUEMIN_NECK_WIDTH=0.2 MM
CPUVR_BOOT1
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MMDIDT=TRUE
CPUVR_BOOT3
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=1.5 MM
SWITCH_NODE=TRUE
DIDT=TRUE
CPUVR_PHASE1
DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MM
CPUVR_BOOT2_RC MIN_NECK_WIDTH=0.2 MM
CPUVR_PHASE2MIN_LINE_WIDTH=1.5 MM
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM
DIDT=TRUE
SWITCH_NODE=TRUE
CPUVR_PHASE3
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=1.8V
PPVCC_S0_CPU_PH3
CPUVR_ISNS1_P
CPUVR_ISUMN
C73721
2
C73711
2
C73701
2
C73191
2
C73181
2
C73171
2
C73161
2
C73151
2
R7310
1 2
3 4
R73141
2
C73141
2
C73131
2
L7310
1 2
R73121
2
C73121
2
C73731
2
R73161
2
R73151
2
R73171 2
C73291
2
C73281
2
C73271
2
R73241
2
C73261
2
C73251
2
C73241
2
C73231
2
L7320
1 2
C73221
2
R73261
2
R73251
2
R73221
2
C73391
2
C73381
2
C73371
2
R73341
2
C73361
2
C73351
2
C73341
2
C73331
2
L7330
1 2
C73321
2
R73361
2
R73351
2
R73321
2
U73104
5
37
41
39
6
36
16
17
26
27
28
18
19
20
21
22
23
24
25
7
40
38
2
3
9
10
11
12
13
14
42
15
29
30
31
32
33
34
35
43
1
R731121
C73111 2
C7310 1
2
U73204
5
37
41
39
6
36
16
17
26
27
28
18
19
20
21
22
23
24
25
7
40
38
2
3
9
10
11
12
13
14
42
15
29
30
31
32
33
34
35
43
1
C7320 1
2
R732121
C73211 2
C7330 1
2
U73304
5
37
41
39
6
36
16
17
26
27
28
18
19
20
21
22
23
24
25
7
40
38
2
3
9
10
11
12
13
14
42
15
29
30
31
32
33
34
35
43
1
R733121
C73311 2
R7320
1234
R7330
1 23 4
C73761
2
C73751
2
C73741
2
C73771
2
C73781
2
C73791
2
C73801
2
R73181 2
R73271 2
R73281 2
R73371 2
R73381 2
dvt
051-0675
6.0.0
73 OF 119
58 OF 94
8
8
8
81
57 81
45 93
45 58 93
57 58 81
45 58 93
45 58 93
57 58 81
57 58 81
45 58 93
45 93 45 58 93
45 58 93
45 58 93
45 58 93
45 93
IN
V5IN
REFIN
S5
VREF
S3
MODE
TRIP
SW
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
VTTREF
DRVH
VBST
VLDOIN
THRMVTTGNDPGND PADGND
OUT
INVSW
PGND
TGR
TG
BG
VIN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
f = 400 kHz
Vout = 1.35V
18A max output
(Q7335 limit)
10mA max load
(VDDQ/VTTREF Enable)
(DDRREG_VDDQSNS)
(DDRREG_LL)
152S0905
(VTT Enable)
C7460, C7461 close to memory
DDR3L (1V35 S3) REGULATOR
(DDRREG_DRVH)
(DDRREG_DRVL)
20%10UF
X5R603
10V
BYPASS=U7400.12:10:5MM
CRITICAL
20%68UF
POLY-TANTCASE-D2E-SM
16V
1
MF-LF402
5%1/16W
CRITICAL
68UF
POLY-TANTCASE-D2E-SM
20%16V
1UF
X5R10%25V
603-1
603-1
50V10%
X7R
0.1UF
0.001UF
X7R-CERM0402
10%50V
CRITICAL
TANTCASE-B4-SM
20%2V
270UF
PCMB103T
CRITICAL
0.68UH-18A-3.3MOHM
CRITICAL
270UF
TANTCASE-B4-SM
20%2V
10UF
X5R603
20%6.3V
0.001UF
0402
10%50VX7R-CERM
SM
PLACE_NEAR=C7440.1:1MM
65
CRITICAL
QFNTPS51916
65
PLACE_NEAR=C7461.1:3mm
SM
SM
BYPASS=U7400.5:7:5mm
CERM402
10V10%
0.22UF
10UF
X5R20%
6.3V
PLACE_NEAR=C2730.1:1mm
603
21 82
0.1UF
X7R-CERM0402
10%16V
6.3V20%
603X5R
10UF
PLACE_NEAR=C2724.1:3mm
1/16W1%
402MF-LF
200K
19.6K1/16W1%
402MF-LF
60.4K
402
1%1/16WMF-LF
0.01UF
X7R-CERM0402
10%16V
10UF
X5R603
20%10V
BYPASS=U7400.2:10:5MM
603-1
1UF
X5R10%25V
CRITICAL
CSD58872Q5DSON5X6
52.3K
MF-LF402
1%1/16W
15UF
SM
CRITICAL
20%
TANT16V
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
1.35V DDR3L SUPPLY
DDRREG_MODEDDRREG_TRIP
=DDRVTT_EN
=PPVTT_S3_DDR_BUF
=PP5V_S3_DDRREG
DDRREG_FB
=PPVIN_S0_DDRREG_LDO
=PPVTT_S0_DDR_LDO
DDRREG_PGOOD=PPDDR_S3_REG
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.17 mm
DDRREG_DRVH_R
MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.6 mm
DDRREG_DRVLGATE_NODE=TRUE DIDT=TRUE
DDRREG_VBST MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.6 mm
DIDT=TRUEGATE_NODE=TRUEDDRREG_DRVH
MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.17 mm
DDRREG_LLDIDT=TRUESWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.2 mm
DDRREG_VDDQSNSSWITCH_NODE=TRUEDIDT=TRUE
MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.6 mm
DDRREG_VSW
=PPVIN_S3_DDRREG
DDRREG_VTTSNS
DDRREG_1V8_VREF
=DDRREG_EN
VOLTAGE=0V
GND_DDRREG_SGNDMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.17 mm
C7400 1
2
C7430 1
2
R74301 2
C7431 1
2
C74321
2
C74251 2
C74331
2
C74401
2
L7430
1 2
C7441 1
2
C74451
2
C74461
2
XW7401
1
2
U7400 14
11
719
10
20
8
17
16
13
21
18
12 15
9
2
6
3
45
1
XW74601 2
XW7400
1
2 C7450 1
2
C7460 1
2
C7415 1
2
C74611
2R74171
2
R74151
2
R74161
2
C74161
2
C7401 1
2
C74341
2
Q7430
5
9
3
4
1
6
7
8
R74181
2
C7435 1
2
dvt
051-0675
6.0.0
74 OF 119
59 OF 94
81
65 81
22
81
81
81
81
OUT
IN
EN
EN2EN1
DRVL2
SKIPSEL1
SKIPSEL2
DRVL1
V5SW
VBST2VBST1
VREG5
VREF2
VIN
THRM_PAD
SW2SW1
RF
PGOOD2PGOOD1
GND
DRVH2DRVH1
CSP2
CSN2CSN1
COMP2COMP1
VREG3
VFB1 VFB2
OCSEL
MODE
CSP1
IN
IN
OUT
VSW
PGND
TGR
TG
BG
VIN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
F = 400 KHZ
VOUT = 5V100MA MAX OUTPUT
VOUT = 3.3V
10A MAX OUTPUT
VOUT = 5.0V
F = 400 KHZ
152S0754
(P5VP3V3_VREF2) (P5VP3V3_VREF2)
11A MAX OUTPUT
25V10%
603-1X5R
1UF
1.0UH-22A
CRITICAL
PCMC063T-SM603-1X7R50V10%
0.1UF
6.3V20%
603X5R
10UF
0.1UF50V10%
603-1X7R
CRITICAL
330UF6.3V
POLY-TANTCASE-D3L-SM
20% 10V10UF
X5R20%
805
CRITICAL
1UF
X5R603-1
10%25V
10V20%
402
2.2UF
X5R-CERM
20%
603X5R
10UF6.3V
249K
MF-LF1/16W
1%
402
65
SM
PLACE_NEAR=L7560.2:3MM
10V10%
402CERM
0.22UF
1/16W1%
402MF-LF
23.2K
1/16W1%
402MF-LF
10K
1/16W1%
402MF-LF
40.2K
1/16W1%
402MF-LF
10K
CRITICAL
68UF20%16V
CASE-D2E-SMPOLY-TANT
0.15UF
402X5R10V10%
SM
PLACE_NEAR=L7560.1:3MM0.15UF
402X5R10V10%
1/16W1%
402MF-LF
3.24K
4.75K
MF-LF402
1%1/16W
PLACE_NEAR=L7520.1:3MM
SM
PLACE_NEAR=L7520.2:3MM
SM 1/16W1%
402MF-LF
12.1K
1/16W1%
402MF-LF
10K
5%50V
15PF
402CERM
PLACE_NEAR=L7560.2:3MM
SM
PLACE_NEAR=L7520.1:3MM
SM
CRITICAL
6.3V20%
CASE-D3L-SMPOLY-TANT
330UF
MF-LF402
1%1/16W
20.0K
5%
402
47PF50VCERM
1/16W1%
402MF-LF
12.1K
65NO STUFF
50V
0402X7R-CERM
0.0033UF10%
603
5%1
MF-LF1/10W
NO STUFF
5%1/10W
603MF-LF
10
NO STUFF
X7R-CERM0402
50V10%
0.001UF
0.001UF
X7R-CERM0402
10%50V
0.001UF50V10%
0402X7R-CERM
0.001UF50VX7R-CERM0402
10%
CRITICAL
QFN
TPS51980
16VPOLY-TANT
CRITICAL
68UF
CASE-D2E-SM
20%
CRITICAL
68UF
POLY-TANT20%
CASE-D2E-SM
16V
65
WPAK2RJK0214DPA
CRITICAL
1K
1/16W1%
402MF-LF
1%1/16W
402MF-LF
4.02K
5%
0
1/16W
402MF-LF
5%1/16W
402MF-LF
1
603-1
1UF25V10%X5R
65
65
50V10%
0402X7R-CERM
0.001UF
NO STUFF
SMPLACE_NEAR=U7501.28:1MM
SON5X6CSD58872Q5D
CRITICAL5%0
0201
1/20WMF
SKIP_5V3V3:AUDIBLE5%0
0201
1/20WMF
SKIP_5V3V3:INAUDIBLE
CRITICAL
20%
CASE-B2-SM
6.3VPOLY-TANT
150UF-0.035OHM
CASE-B2-SMPOLY-TANT
6.3V
150UF-0.035OHM
20%
CRITICALCASE-B2-SMPOLY-TANT
CRITICAL150UF-0.035OHM
6.3V20%
PCMB103T-SM
CRITICAL
2.2UH-20%-13A-9MOHM
100V10%
402CERM
4700PF100V10%
402CERM
4700PF
150UF-0.035OHM
CASE-B2-SMPOLY-TANT
6.3V20%
CRITICAL
150UF-0.035OHM
CASE-B2-SM6.3V20%
CRITICAL
POLY-TANT
NO STUFF
TANT16V20%
15UF
SM
CRITICALCRITICAL
15UF20%
TANT16V
SM
16V
CRITICAL
SM
20%
TANT
15UF
POLY-TANTCASE-D2E-SM
16V20%
68UF
CRITICAL
5V / 3.3V Power SupplySYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
=PPVIN_S5_P3V3
=PP5V_S5_LDO
P3V3S5_TGMIN_LINE_WIDTH=0.6 MM
DIDT=TRUEGATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMDIDT=TRUE GATE_NODE=TRUE
P3V3S5_DRVLMIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE DIDT=TRUEMIN_LINE_WIDTH=0.6 MMP5VS4_DRVL
P5VS4_DRVHDIDT=TRUEGATE_NODE=TRUEMIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
P5VS4_VBSTDIDT=TRUE
DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMP3V3S5_SNUBR
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMP5VS4_TG
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
P5VS4_LLDIDT=TRUESWITCH_NODE=TRUEMIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
P3V3S5_DRVHDIDT=TRUE GATE_NODE=TRUE
DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMP5VS4_SNUBR
P3V3S5_CSP2_RDIDT=TRUE
P5VS4_CSP1
P5VP3V3_SKIPSEL
P5VP3V3_VREG3
P3V3S5_PGOOD
=PP5V_S4_REG
=P5VS4_EN
P5VS4_COMP1_R
=P3V3S5_EN
P5VS4_VFB1_R
P5VS4_PGOOD
P5VS4_COMP1
=P5VS5_EN
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
DIDT=TRUEP3V3S5_VBST
P5VS4_CSP1_RDIDT=TRUE
P5VS4_VFB1
P5VS4_CSN1
P3V3S5_COMP2_R
P3V3S5_VFB2_R
P3V3S5_COMP2
=PPVIN_S5_P5V
P5VS4_VSWMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMDIDT=TRUE
=PP5V_S4_REG
MIN_LINE_WIDTH=0.2 MMGND_5V3V3_AGND
VOLTAGE=0VMIN_NECK_WIDTH=0.2 MM
P5VP3V3_VREF2
P3V3S5_VFB2
P3V3S5_CSN2
MIN_NECK_WIDTH=0.2 MM
P3V3S5_LLMIN_LINE_WIDTH=0.6 MMDIDT=TRUE SWITCH_NODE=TRUE
=PP3V3_S5_REG
P3V3S5_RF
P3V3S5_CSP2
C7500 1
2
L7560
12
C7564 1
2
C75901
2
C75241
2
C7552 1
2
C7550 1
2
C75811
2
C75031
2
C75051
2
R75061
2
XW7561
1
2
C7501 1
2
R75601
2
R75611
2
R75201
2
R75211
2
C75801
2
C75881 2
XW7560
1
2
C75181 2
R75471 2
R75561
2
XW7520
1
2
XW7521
1
2 R75361
2
R75371
2
C7537 1
2
XW7562
1
2
XW7522
1
2
C75921
2
R75391
2
C75391
2
R75381
2
C7599 1
2
R75991
2
R75981
2
C7572 1
2
C75831
2
C75701
2
C75711
2
U7501
10 15
8 17
7 18
1 24
30 27
12
4 21
28
11
14
5 20
3
6
19
32 25
33
2
31 26
9 16
23
13
22
29
C75421
2
C75821
2
Q75602
1
6
7
3 4 5
R75461 2
R75161
2
R75631 2
R75441
2
C75411
2
C75981
2
XW7500
1
2
Q7520
5
9
3
4
1
6
7
8
R75001
2
R75011
2
C75531
2
C7554 1
2
C7593 1
2
L7520
1
2
C75361
2
C7538 1
2
C7594 1
2
C75551
2
C7585 1
2
C7584 1
2
C7543 1
2
C7544 1
2
dvt
60 OF 94
051-0675
6.0.0
75 OF 119
81
81
60 65 81 81
60 65 81 81
OUT
IN BOOT
UGATE
LGATE
PHASE
RTN
FSEL
PGOOD
OCSET
VO
SREF
VCC PVCC
GND PGND
EN
FB
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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D
8 7 6 5 4 3
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A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Vout = 1.05V
12A MAX OUTPUT
Vout = 0.5V * (1 + Ra / Rb)
(PCHVCCIOS0_OCSET)
(PCHVCCIOS0_VO)
1V05 S0 REGULATOR
376S0953
OCP = 14.4A
f = 300 kHz
<Rb><Rb>
152S0955
<Ra><Ra>
OCP = R7641 x 8.5uA / R7640
402MF-LF
3.01K1%1/16W
65
65
BYPASS=Q9800.13:1:5mm
2.2UF
X5R603
10%16V
0
MF-LF402
5%1/16W
NO STUFF
PLACE_NEAR=U7600.1:1mm
SM
CRITICAL
UTQFN
ISL95870
1/16W
2.2
MF-LF402
5%10UF
X5R603
20%10V
BYPASS=Q9800.14:16:5mm
1UF
X5R402
16V10%
0.0018UF
X7R-CERM50V10%
0402
25V5%
1000PF
CERM0402
PLACE_NEAR=L7630.2:1.5mm
16V20%
CASE-D2E-SM
68UF
POLY-TANT
CRITICAL
16V20%
CASE-D2E-SMPOLY-TANT
68UF
CRITICAL
1000PF25V
BYPASS=Q7630.2:5:6mm
CERM
5%
0402
2V20%270UF
CRITICAL
TANTCASE-B4-SM
CRITICAL
0.001
MF-10612
1%1W
CRITICAL
270UF
TANTCASE-B4-SM
20%2V
0
MF-LF603
5%1/10W
10PF
C0G-CERM0402
5%50V
CRITICAL
RJK0214DPAWPAK2
PLACE_NEAR=U1100.AJ12:1MM
SM
PLACE_NEAR=U1100.AK14:1MM
SM
MF-LF402
1/16W
1.2K5%
MF-LF402
1/16W
1.2K5%
10PF
0402
5%50VC0G-CERM
0.68UH-25A-5.5MOHM
PCMC063T-SM
CRITICAL
X7R-CERM0402
10%16V0.047UF
2.74K
MF-LF402
1%1/16W1/16W
2.74K
MF-LF402
1%
3.01K
402
1%1/16WMF-LF
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
1V05V POWER SUPPLY
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm
DIDT=TRUE
P1V05S0_VBST
P1V05S0_CS_P
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm
PP5V_S0_P1V05S0_VCC
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
P1V05S0_DRVH
MIN_LINE_WIDTH=0.3 mm
DIDT=TRUE
P1V05S0_BOOT_RCMIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm
P1V05S0_DRVL
=PP1V05_S0_REG P1V05S0_SENSE_P
P1V05S0_SREF
=P1V05S0_EN
P1V05S0_PGOOD
=PP1V05_S0_REG
P1V05S0_SENSE_N
=PP5V_S0_P1V05S0
P1V05S0_CS_N
=PPVIN_S0_P1V05S0
PP1V05_S0_REG_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P1V05S0_AGND
P1V05S0_OCSET
SWITCH_NODE=TRUEDIDT=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_LL
P1V05S0_FB
P1V05S0_VO
P1V05S0_FSEL
P1V05S0_RTN
C7604 1
2
C76051
2
C76031
2
R76451
2
R76051
2
R76041
2
R76441
2
C7602 1
2
R76031
2
XW76001 2
U7600
123
6
5
1
15
7
16
9
10
14
2
4
11
13
8
R76011
2
C76011
2 C76301
2
C764012
C7623 1
2
C7620 1
2
C7621 1
2
C76221
2
C76481
2
R7640
2 14 3
C7649 1
2
R76301
2
Q76302
1
6
7
3 4 5
XW76011 2
XW76021 2
R76421
2
R76411
2
L7630
1 2
dvt
051-0675
6.0.0
76 OF 119
61 OF 94
93
61 81 93
61 81
93
81
93
81
GND_SW
GND_SW
SW2
FB2
KEYB1
KEYB2
SDA
SCL
PWM_KEYB
EN
SENSE_OUT
FB
THRM
GNDA
GNDD
GND_SW2
SD
VSENSE_N
VSENSE_P
SW
ISET_KEYB
GD
VDDA
VDDD
SW
PAD
IN
IN
OUT
OUT
VDDA VDDD
SDA_MFILTER
SYNC
PWM
EN
SDA
SCL
ISET
NC
NC
NC
SCL_M
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
THRM
GNDD
GND_L
GNDA
GND
PAD
NCNCNC
IN
IN
IN
IN
IN
IN
IN
IN
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Power aliases required by this page:
C7723, C7724 SHOULD BE PLACED MIRRORED
(PPBUS_S0_BKLT_PWR_F)(PPBUS_S0_BKLT_PWR_R)
353S4159
PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE
C7718, C7719 SHOULD BE PLACED MIRRORED
BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds
C7720, C7721 SHOULD BE PLACED MIRRORED
(IPU)
(IPU)
152S1527
371S0572152S1701
C7715, C7716 SHOULD BE PLACED MIRRORED
- =PP5V_S0_BKLTCTRL (5V Backlight Driver Input)
APN353S4229
BKLT:PROD - Stuffs 0 ohm series R for production
BOM options provided by this page:
- =PP5V_S0_KBDLED (5V Keyboard Backlight Input)
- =PPVIN_S0_LCDBKLT (9-12.6V LCD Backlight Input)
Page Notes
CRITICAL
LP8548B1SQ_-03QFN
603-HF
3AMP-32V-467
CRITICAL22UH-20%-2.4A-0.105OHM
DEM8030C-SM
CRITICAL
CRITICAL
PST041H-CDH46D14-SM
10UH-20%-1.4A-0.17OHM
201
1/20WMF
80.6K1%
X7R-CERM0201
1000PF10%16V
1%63.4K
402
1/16WMF-LF
FDC638APZ_SBMS001
CRITICAL
SSOT6-HF
0.1UF
X5R-CERM
10%16V
0201
10%2.2UF
X5R-CERM603
25V 50V0.001UF10%
X7R-CERM0402
5%
0
0201
1/20WMF
5%
0201
33PF25V
NO STUFF
NPO-C0G
5%
0
0201
1/20WMF
402-2
10V10%1UF
X5R402-2
1UF
X5R10%10V
5%1/20WMF
1M
201
10.2
1/16WTF402
0.1%
BKLT:ENG
SM
402X5R25V
0.1UF10%
79 83
40
NOSTUFF
0.001UF10%
402CERM50V
25V
4.7UF
0603X6S-CERM
10%
X6S-CERM
10%4.7UF
0603
25V
201
1/20WMF
31.6K1%
RB160M-60G
SOD-123
CRITICAL
10%50VX7R0805
1.0UF50VX7R0805
10%1.0UF
X5R-CERM
10%25V2.2UF
603
5%
NO STUFF
25VNPO-C0G
33PF
0201
SMPLACE_NEAR=D7720.K:2MM
0.0251%
0612
1WMTL
46 93
46 93
LP8549B1SP_-03
CRITICAL
LLP
BKLT:ENG
402
0.1%
10.2
TF1/16W
150K1%
MF-LF1/16W
402
402
1/16WMF-LF
1%18.2K
1210-1
10%2.2UF
X7R100V
PLACE_NEAR=D7701.K:3MM
CRITICALDFLS2100
POWERDI-123
CRITICAL
PLACE_NEAR=L7710.2:3MM
1210-1X7R
10%2.2UF
CRITICAL
PLACE_NEAR=D7701.K:5MM
100V
1210-1X7R
2.2UF10%
CRITICAL
PLACE_NEAR=D7701.K:3MM
100V
1210-1
PLACE_NEAR=D7701.K:5MM
100V
2.2UF
CRITICAL
10%
X7R X7R-CERM0603
PLACE_NEAR=R7708.1:5MM
10%1000PF
100V
PLACE_NEAR=L7710.2:3MM
PWRPK-1212-8SI7812DN
CRITICAL
402
BKLT:ENG
TF
10.2
0.1%1/16W
402
BKLT:ENG
0.1%
TF
10.2
1/16W
1/16W
402TF
0.1%
10.2
BKLT:ENG
67 83
67 83
67 83
67 83
67 83
67 83
402
BKLT:ENG
10.2
TF
0.1%1/16W
BKLT:ENG
1/16WTF
10.2
0.1%
402
67 79 83 02015%
01/20WMF
NOSTUFF
402
1/16W
10.2
TF
0.1%
BKLT:ENG
402-2
1UF10VX5R10%
402-2
10%10V1UF
X5R
27.4K1%1/16WMF-LF402
SM
1UF
NOSTUFF
10V10%
X5R402-2
NOSTUFF
X5R
10%10V
1UF
402-2
5%
0
1/20WMF
NOSTUFF
0201
5%
201
1/20WMF
100K
NOSTUFF
01/16WMF-LF402
5%
5%
0
0201
1/20WMF
5%
0
0201
1/20WMF
5%
201
1/20WMF
NOSTUFF
4.7K5%
201
1/20WMF
4.7K
NOSTUFF
MF-LF402
5%10K1/16W
1/20W5%
00201
MF
1/20W5%
00201
MF
5%0
0201 1/20WMF
79
5%
0
1/16W
402MF-LF
0
402MF-LF
5%1/16W
0
402MF-LF
5%1/16W
10%50VX7R0805
1.0UF
0805X7R50V10%1.0UF
R7717,R7718,R7719,R7720,R7721,R7722,R7723,R7724RES,MTL FILM,0 OHM,1A MAX,0402,SMD116S0004 BKLT:PROD8
SYNC_DATE=04/26/2013
LCD/KBD Backlight DriverSYNC_MASTER=CLEAN_J45
MIN_NECK_WIDTH=0.25 MMVOLTAGE=55V
MIN_LINE_WIDTH=0.5 MMPPVOUT_S0_LCDBKLT
LCDBKLT_EN_L
PP5V_S0_BKLT_VDDA
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM
PP5V_S0_BKLT_VDDDMIN_LINE_WIDTH=0.4 MM
VOLTAGE=5VMIN_NECK_WIDTH=0.2 MM
GND_BKLT_SGND
PPVOUT_S0_KBDBKLTMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=40V
KBDBKLT_RETURN1MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MM
PPVOUT_BKLT_FB2MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.4 MM
VOLTAGE=40V
BKLT_SD
KBDBKLT_SWMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MMDIDT=TRUE
VOLTAGE=0V
GND_BKLT_SGNDMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM
BKLT_PWM_KEYB
BKLT_SCL
BKLT_SDA
BKLT_KEYB1
=PP5V_S0_BKLTCTRL
=PP5V_S0_BKLTCTRL
GND_LCDBKLT_SGND
BKL_FB
ISNS_LCDBKLT_P
LCD_BKLT_PWM_R
SMC_SYS_KBDLED
BKLT_SDA_R
BKL_ISEN1MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mm
BKLT_SYNC
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm
BKL_ISEN3
MIN_NECK_WIDTH=0.25 mm
GND_LCDBKLT_SGNDMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 MMBKL_FET_CNTLMIN_NECK_WIDTH=0.25 MMDIDT=TRUE
BKL_SW
DIDT=TRUEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=2 mm
BKLT_KEYB2
MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mm
BKL_ISEN4
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm
BKL_ISEN2
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm
BKL_ISEN5
BKL_1_SDA
LCD_FSS
=I2C_BKL_1_SCL
LCD_BKLT_PWM
=I2C_BKL_1_SDA
BKLT_SCL_R
BKLT_SDA_R
BKLT_EN_R
GND_BKLT_SGND
BKL_FET_CNTL_RMIN_LINE_WIDTH=0.6 MM
DIDT=TRUEMIN_NECK_WIDTH=0.25 MM
BKLT_SCL_RLCD_BKLT_EN
BKLT_FLT_RC
PPBUS_S0_LCDBKLT_PWR_SW
DIDT=TRUESWITCH_NODE=TRUEVOLTAGE=45V
MIN_LINE_WIDTH=2 MMMIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=2 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=12.6V
PPBUS_SW_BKL
VOLTAGE=12.6V
MIN_LINE_WIDTH=2 MMMIN_NECK_WIDTH=0.25 MM
PPBUS_SW_LCDBKLT_PWR=PPVIN_S0_LCDBKLT
MIN_NECK_WIDTH=0.25 MM
KBDBKLT_RETURN2MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.35 mmLED_RETURN_1
MIN_LINE_WIDTH=0.35 mmMIN_NECK_WIDTH=0.20 mm
LED_RETURN_2
LED_RETURN_3MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.35 mm
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_4MIN_LINE_WIDTH=0.35 mm
LED_RETURN_6MIN_LINE_WIDTH=0.35 mmMIN_NECK_WIDTH=0.20 mm
BKLT_FLT
GND_BKLT_SGND
=PP5V_S0_KBDLED
MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=5V
PP5V_S0_KBDLED_R
=PP5V_S0_BKLTCTRL
BKLT_SENSE_OUT
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm
BKL_ISEN6
MIN_NECK_WIDTH=0.20 mm
LED_RETURN_5MIN_LINE_WIDTH=0.35 mm
BKLT_ISET_KEYB
BKLT_ISET_LCD
BKL_1_SCL
BKLT_EN_R_JERRY
MIN_NECK_WIDTH=0.25 MMVOLTAGE=12.6V
MIN_LINE_WIDTH=2 MMPPBUS_S0_LCDBKLT_FUSED
ISNS_LCDBKLT_N
U7701
17
21
8
4
7
23
24
223
20
13
14
12
15
11
16
19
6
1
2
25
18
5
9
10
F77001 2
L7710
1 2
L7720
1 2
R77011
2
C77001
2
R77021
2
Q7706
1
2
5
6
3
4
C77221
2
C77211
2
C77251
2
R77471 2
C77471
2
R77421 2
C7740 1
2
C77411
2
R77401
2
R77231 2
XW77001 2
C77121
2
C77011
2
C77101
2
C77111
2
R77411
2
D7720A K
C77231
2
C77241
2
C77201
2
C77421
2
XW7720
1
2
R7700
1 23 4
U7750
10
13
9
21
12 3
17
14
15
16
24
23
22
20
19
18
7
6
2
5
1
8
25
11
4
R77241 2
R77091
2
R77081
2
C77151
2
D7701A K
C77161
2
C77181
2
C77191
2
C77171
2
Q7701
5
4
1 2 3
R77221 2
R77211 2
R77201 2
R77191 2
R77181 2
R77551 2
R77171 2
C7750 1
2
C77511
2
R77541
2
XW77011 2
C77531 2
C775212
R77521 2
R77531 2
R77031
2
R77571 2
R77581 2
R77611
2
R77601
2
R77561
2
R77801 2
R77811 2
R77821 2
R77831 2
R77441
2
R77431
2
C77261
2
C77271
2
dvt
051-0675
6.0.0
77 OF 119
62 OF 94
67 83
62
39 83
39 83
62
62 81
62 81
62
62
62
43
43
62
62
62
62
81
81
39 83
62
81
62 81
IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GND THRM_PAD
OUT
NC
IN
BIAS
NC
OUT
THRM
EN
PADGND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
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A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
Freq = 1.6MHZ
<Ra>
Pull-ups (3) must be 51 ohms to support XDP (not required in production).70mA is required to support pull-ups. Alternative is strong voltage
Vout = 1.05VMax Current = 0.35A
1.05V SUS LDOLynx Point-H requires JTAG pull-ups to be powered at 1.05V in SUS.
dividers (200/100) to 3.3V SUS, which burns 100mW in all S-states.
Max Current = 1.5A
1.5V S0 Regulator
Vout = 1.508V65
DFNISL8009B
CRITICAL
CRITICAL
CERM6.3V20%
805
22UF
CRITICAL
2.2UH-3A
PCMB042T-IHLP1616BZ
113K1/16W1%
402MF-LF
0402-1
50V5%
CERM
27PF1/16W
100K1%
402MF-LF
6.3V20%
CRITICAL
X5R0805
47UF
65
6.3V10%
402X5R
2.2UF
XDP_PCH
SONTPS720105
CRITICALXDP_PCH
6.3V10%
402CERM
1UF
XDP_PCH
SYNC_MASTER=CLEAN_J45
Misc Power SuppliesSYNC_DATE=04/26/2013
P1V5S0_SW
DIDT=TRUESWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
P1V5S0_FB
=PP3V3_SUS_P1V05SUSLDO =PP1V05_SUS_LDO
=PP3V3_S5_P1V5S0
=P1V5S0_EN
P1V5S0_PGOOD
=PP1V5_S0_REG
U7810
2
7
8
3
54
9
6
1 C78501
2L7870
1 2
R78811
2
C7876 1
2
R78801
2C78711
2C78411
2
U7840
4
3
5
6 1
7C7840 1
2
dvt
051-0675
6.0.0
78 OF 119
63 OF 94
2
8181
81
81
IN
IN
DS
G
IN
DS
G
DS
G
IN
IN
S
G
D
OUT
OUT
DS
G
IN
GND
VDD
D
SON
CAP
S
D
G
S
D
G
S
G
D
GND
VOUT
ON
VIN
IN
S
D
G
S
D
G
SYM_VER_2
G S
D
SYM_VER_2
G S
D
SYM_VER_2
G S
D
IN
SYM_VER_2
G S
D
IN
DS
G
DS
G
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
4.8 A (EDP)LOADING
RDS(ON)
N-TYPE
0.8V/ms = 19.75nF
1.35V S3/S0 FET
RDS(ON)
LOADING
CHANNEL
MOSFET
3.3V S0 GPU FET
SiA427
P-TYPE 8V/5V
26 mOhm @1.8V
2.8 A (EDP)
0.5 A (EDP)
MOSFET
5 A (EDP)
SI7615DN
5.0V S0 FET
3.3V S0 SSD FET
LOADING
5.5 mOhm @4.5V
5.5 MOHM @4.5V
P-TYPE 20V/12V
R(on)@ 2.5V
U8030
18.5 mOhm Typ
LOADING
RDS(ON)
CHANNEL
SI7615DN
RDS(ON)
26 mOhm @1.8V
P-TYPE 8V/5VCHANNEL
SiA427MOSFET
3.3V SUS FET
3.3V SUS FET
CHANNEL
5.0V S0 FET
P-TYPE 20V/12V
3.3V S0 SSD FET
MOSFET
LOADING
RDS(ON)
25.8 mOhm Max
Type
Part
APN 353S2741
3.3V S0 Switch
Max Current = 2A
3.3V S0 GPU FET
0.6A (EDP)
1.3 A (EDP)
26 mOhm @1.8V
EDP is per J45 Power Budget rev5
P-TYPE 8V/5V
3.3V S4 FET
SiA427
CHANNEL
MOSFET
RDS(ON)
LOADING
3.3V S4 FET
376S0945
P-TYPE 8V/5V
SiA427
3.3V S3 FET
CHANNEL
MOSFET
26 mOhm @1.8VRDS(ON)
1.1 A (EDP)LOADING
P-TYPE 8V/5V
26 mOhm @1.8V
0.3 A (EDP)
SiA427
5V S3 FET
MOSFET
CHANNEL
RDS(ON)
LOADING
SLG5AP1438V
9.6 mOhm
CHANNEL
Integ. MOSFET
Slew rate :
3.3V S0 MISC GPU FET
26 mOhm @1.8V
0.11A (EDP)
P-TYPE 8V/5V
SiA427MOSFET
RDS(ON)
CHANNEL
LOADING Load Switch
TPS22924C
3.3V S3 FET
3.3V S0 GPU MISC FET
1.35V S3/S0 FET
5V S3 FET
21
0402
0.01UF
10%16V
X7R-CERM
0.033UF
X5R402
16V10%
39K
402MF-LF1/16W5%
47K1/16WMF-LF
402
5%
65
SC70-6L
SIA413DJCRITICAL
402
20%10V
CERM
0.1UF
65
5%
402
1/16W
MF-LF
220K
MF-LF1/16W5%
47K
402
0.033UF10%16VX5R402
SC70-6LSIA413DJ
CRITICAL
0.01UF
10%16V
X7R-CERM0402
10%
402
16V
X5R
0.033UF
SIA413DJ
CRITICAL
SC70-6L
0402
10%
0.01UF
16VX7R-CERM
5%
402
MF-LF
100K1/16W
5%1/16WMF-LF402
12K
65
65
5%270K
1/16WMF-LF
402
5%
6.2K
1/16W
MF-LF
402
0.12UF
402
10%10.0V
CERM-X5R
0.47UF
0402
10V10%
X5R
CRITICAL
PWRPK-1212-8SI7615DN
402
16VX7R
10%0.018UF
46
46
SIA427DJSC70-6LCRITICAL
0.033UF16VX5R402
10%
5%
MF-LF1/16W
402
5.1K
5%200K
1/16WMF-LF
402
0402
0.01UF
10%16V
X7R-CERM
65
SM
CRITICALTDFN
SLG5AP1438V
SOT-563DMN5L06VK-7
DMN5L06VK-7SOT-563
X7R-CERM
0.01UF
0402
16V10%
CRITICALPLACE_NEAR=R5549.2:6mm
SI7615DNPWRPK-1212-8
10%
X5R402
16V
0.033UF
5%
MF-LF
33K
402
1/16W
5%47K1/16WMF-LF
402
CSPTPS22924
CRITICAL
10%
402X5R
1UF6.3V
65
SOT-563DMN5L06VK-7
DMN5L06VK-7SOT-563
DMN32D2LFB4DFN1006H4-3
DFN1006H4-3DMN32D2LFB4
SSD_PWR_EN:GPIO
MF1/20W0201
0
5%
5%
0
0201 1/20W MF
SSD_PWR_EN:S0
0402
0.01UF
X7R-CERM16V10%
402CERM-X5R
0.47UF10%
6.3V
402
1/16WMF-LF
1K
5%
402
1/16WMF-LF
33K5%
DMN32D2LFB4DFN1006H4-3
66
0402X7R-CERM
0.01UF
10%16V
0402X6S-CERM
6.3V10%
0.33UF
402
1/16WMF-LF
1K
5%
402
1/16WMF-LF
33K5%
DFN1006H4-3DMN32D2LFB4
66
SC70-6L
CRITICAL
SIA413DJ
SC70-6LSIA413DJ
CRITICAL
SYNC_DATE=04/26/2013
Power FETsSYNC_MASTER=CLEAN_J45
=PP1V35_S3RS0_FET_ISNS
NC_ISNS_CPUDDRN
=PP1V35_S3RS0_FET
NC_ISNS_CPUDDRP
P3V3S4_EN_L
=PP5V_S4_P5VS3FET
P3V3GPU_EN_L
=PP3V3_S0SW_SSD_R
=PP3V3_S5_P3V3SUSFET
P5V0S0_EN_L
=PP5V_S4_P5VS0FET
=P5VS0_EN
P3V3SUS_SS
=P3V3S0_EN
=PP3V3_SUS_FET
P5V0S0_SS
P3V3_SSD_EN_L P3V3_SSD_SS
=PP5V_S0_FET
=PP3V3_S5_P3V3S0SW_SSD
=PP3V3_S0_P3V3S0FET
=P3V3SUS_ENP3V3SUS_EN_L
=PP3V3_S0_FET
=PP3V3_S0GPU_FET=PP3V3_GPU_P3V3GPUFET
=P3V3GPU_EN
=PP3V3_S4_FET
P3V3S3_S4
=PP3V3_S4_P3V3S4FET
=P3V3S4_EN
=PP3V3_S3_FET
P3V3S3_SS
=PP3V3_S3_P3V3S3FET
P3V3S3_EN_L=P3V3S3_EN
PM_SLP_S3_BUF_L
SSD_PWR_EN
SSD_PWR_FET_EN
=PP5V_S3_FET
P5VS3_EN_L=P5VS3_EN
=PPVIN_S3_P1V35S3RS0_FET
P1V35CPU_SLEW_CTL
CPUVDDQ_EN
=PP3V3_S0GPU_MISC_FET
P3V3GPU_MISC_SSP3V3GPU_MISC_EN_L
=P3V3GPU_MISC_EN
P3V3GPU_SS
=PP3V3_GPU_MISC_P3V3GPUMISCFET
=PP5V_S5_P1V35S3RS0FET
P5VS3_SS
C8010
1 2
C8011 1
2
R80101 2
R8012 1
2
Q8010
1
3
47
C8001 1
2
R8002 1
2 R80001 2
C8009 1
2
Q8000
1
3
47
C8000
1 2
C8021 1
2
Q8020
1
3
47
C80201 2
R8022 1
2 R80201 2
R80621
2 R80601 2
C8061 1
2
C80601 2
Q8060
5
4
12
3
C8002 1
2
Q8050
1
3
47
C8051 1
2
R80501 2
R8052 1
2 C8050
1 2
XW80051 2
U8001
7 3
8
2 5
1
Q8002 6
2 1
Q8052 6
2 1
C8070
1 2
Q8070
5
4
12
3
C8071 1
2
R80701 2
R80721
2
U8030
C1
C2
A2
B2
A1
B1
C8030 1
2
Q8002 3
5 4
Q8052 3
5 4
Q8012 3
1 2
Q8072 3
1 2
R80731 2
R80741 2
C80801 2
C8081 1
2
R80801 2
R80821
2
Q8082 3
1 2
C80901 2
C8091 1
2
R80901 2
R80921
2
Q8092 3
1 2
Q8090
1
3
47
Q8080
1
3
47
dvt
051-0675
6.0.0
80 OF 119
64 OF 94
8181
81
81
81
81
81
81
81 81
66 81 81
81
81
81
81
50 65 78 79 83
13 18
34
81
81
8181
81
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
NC
NC
Q3
Q2
Q4
Q1
OUT
IN
SENSE
CT
VDD
GND
RESET*
MR*
IN
OUT
OUT
IN OUT
OUT
VDD
MR*
RST*V4MON
V3MON
V2MON
GND THRM_PAD
OUTIN
OUT
OUT
OUT
IN NC
NC
OUT
IN
OUT
OUT
OUT
SYM_VER_2
G S
D
SYM_VER_2
G S
D
S
D
G S
D
G
OUT
OUT
OUT
G
D
S
OUTIN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(For development only)
P1V5S0_PGOOD from U7810
1V05_VMON divider0.716V @1.02V
S0 Rail PGOOD Circuitry (ISL Version in development)
Vbe 0.7V max @2mA
P5V_VMON divider
353S2310(IPU)
0.717V @1.31V
keep R8171 DDRCPU 1.35V only
3.16V @4.5V
Q1 Vth 0.7~1V @Id 250uA
V4MON: 0.572V-0.630VV3MON: 0.572V-0.630V
Thresholds:
VDD: 2.734V-3.010VV2MON: 2.815V-3.099V
Deep Sleep (dS4AC)
0
S0 ENABLE
3V3 Divider:1.07V
CHGR VFRQ Generation
Vce(sat) 0.1V max @1mA
1V5 S0 "PGOOD" Delay
S5 Rail Enables & PGOOD
Power State Debug LEDs
VFRQ Low: Fix FrequencyVFRQ High: Variable Frequency
VBEon: 0.58~0.7V1V5 Divider:0.75~0.85V
Vgs:0.7V~1.0V Unused PGOOD signals
S3 ENABLE
SMC-->PM_DSW_PWRGD
S5_PWRGD-->SMC
PM_RSMRST_L goes to U1100.C21
Battery Off (G3HotAC)
SMC_ADAPTER_ENState
0
0
1
Mobile System Power State Table
0
00
0
1
0
353S2809
(PM_SLP_S3_BUF_L)
5.0V Divider:1.07V
Min delay time
1V35_VMON divider
Deep Sleep (dS5AC)
0
PM_SLP_S3_L
0
0
1
0
0
0
0
0
0
PM_SLP_S4_LPM_SLP_S5_L
1
1
11
1
PM_SLP_SUS_L
1
1
1
1
1
1
SMC_S4_WAKESRC_EN
1 0 0
0
0
0
00
0
0
0
0
0
1
1
1
10
X
SMC_PM_G2_ENABLE
Sleep (S3)
Sleep (S3AC)
Run (S0)
1 1
1
1
0
1
10
0
0
1
toggle 3Hz
Deep Sleep (dS4)
Deep Sleep (dS5)
Battery Off (G3Hot)
PM_SLP_S4_L:100K pull down in PCH page
threhold is 3.07V
0
U8130 Sense input
No stuff C8131, 12ms
S0 Rail PGOOD (BJT Version)
PM_SLP_S3_L:100K pull down in PCH page
PM_SLP_S5_L:100K pull down on PCH page
S4 Power Enable
CPUVCORE ENABLE
PM_SLP_SUS_L: 100K pull down on PCH page
3.3V SUS Detect
3.3V SUS Enable
NOTE: S4 term is guaranteed by S4 pull-up on open-drain AP_PWR_EN signal."WLAN" = ("S4" && "AP_PWR_EN" && ("AC" || "S0"))
WLAN Enable Generation
59
64
1/16W
402
5%
PLACE_NEAR=Q8012.1:6mm
MF-LF
0
0.47UF
PLACE_NEAR=Q8012.1:6mm
6.3V
402CERM-X5R
10%
NO STUFF
57
44
61
PLACE_NEAR=U7400.16:6mm
5.1K
MF-LF1/16W
402
5%
PLACE_NEAR=U7400.16:6mm
6.3V10%
402CERM-X5R
0.47UF
12 21 33 37 40 65 78 83
130K
402MF-LF1/16W5%
PLACE_NEAR=U7600.3:6mm
PLACE_NEAR=U7600.3:6mm
X5R
0.82UF10%6.3V
402
100K5%
402MF-LF1/16W
56
12 21 40 83
31
402MF-LF1/16W
5%10K
18 19 40 65 83
MF-LF402
1/16W5%
100
1/16WMF-LF
5%
402
100
470K1/16W
402MF-LF
5%
60
1/16WMF-LF
S0PGOOD_ISL
5%
402
330
61
1%
402MF-LF1/16W
150K
402
1K
1/16WMF-LF
5%
54.9K
402MF-LF1/16W
1%
1/16WMF-LF
1%
402
15.0K
CRITICAL
ASMCC0179DFN2015H4-8
402
5%1/16WMF-LF
1K
1/16WMF-LF402
1K
5%
64
12 40
SOT23-6
CRITICAL
TPS3808G33DBVRG4
NO STUFF
CERM50V
402
20%0.001UF
100K
MF-LF1/16W
402
5%
BYPASS=U8130.6::2:2.3mm
10V
402CERM
20%0.1uF
1/16W
402
100
5%
MF-LF
63
1/16W
100
402
5%
MF-LF
63
12 83 88
40 41
0402
NO STUFF
PLACE_NEAR=U7501.21:7mmX7R-CERM50V10%0.0033UF
100
PLACE_NEAR=U7501.21:7mm
5%1/16WMF-LF402
60
40
PLACE_NEAR=U7501.20:7mm
1/16W
100K
402
5%
MF-LF
CRITICAL
ISL88042IRTEZTDFN
S0PGOOD_ISL
1%
MF-LF
S0PGOOD_ISL
6.04K
402
1/16W
15.0K
402
1%
MF-LF
S0PGOOD_ISL
1/16W
1/16W
402MF-LF
1%10K
S0PGOOD_ISL
MF-LF
402
1/16W
1%
12.4K
S0PGOOD_ISL
6.04K
402
MF-LF
1/16W
S0PGOOD_ISL
1%
S0PGOOD_ISL
15.0K
402
1%
MF-LF
1/16W
6412
32
NO STUFFPLACE_NEAR=Q8052.2:6MM
0.47UF6.3V10%
CERM-X5R402
01/16W
PLACE_NEAR=Q8052.2:6MM
5%
MF-LF402
64
31 32
40 41
74LVC1G32SOT891
402CERM10V20%
0.1uF
BYPASS=U8170.6:3:2.3mm
PLACE_NEAR=J4801.17:10MM
402CERM-X5R6.3V10%0.47UF
NO STUFF
5%
PLACE_NEAR=J4801.17:10MM
201
3.3K
MF1/20W
38
0.1UF
S0PGOOD_ISL
X7R-CERM
20%10V
0402
PLACE_NEAR=U8160.2:4mm
LTQH9G-SMGREEN-56MCD-2MA-2.65V
SILK_PART=S5_ON
DBGLED
PLACE_SIDE=BOTTOMLTQH9G-SMGREEN-56MCD-2MA-2.65V
PLACE_SIDE=BOTTOM
DBGLED
SILK_PART=S4_ON
LTQH9G-SMGREEN-56MCD-2MA-2.65V
DBGLED
PLACE_SIDE=BOTTOMSILK_PART=S0_ON
LTQH9G-SMGREEN-56MCD-2MA-2.65V
SILK_PART=S3_ONPLACE_SIDE=BOTTOM
DBGLED
20K5%1/20W
DBGLED
MF201
DBGLED
5%
201MF1/20W
20K
MF
DBGLED
201
1/20W5%20K
5%
MF201
1/20W
DBGLED
20K
PLACE_SIDE=BOTTOM
1/16W
402
5%
0
DBGLED
MF-LF
MF1/20W5%
201
470K
59
MF-LF1/16W
402
15.0K1%
MF-LF1/16W1%
402
7.15K
402MF-LF1/16W
20K5%
64
0.68UF
402
6.3V10%
CERM
NO STUFF
0.68UF
PLACE_NEAR=Q8052.5:6mm
402
6.3V10%
CERM
PLACE_NEAR=Q8052.5:6mm
1/16WMF-LF
5%
402
0
64
2.2UF
PLACE_NEAR=U7501.4:6mm
10%6.3V
402X5R
PLACE_NEAR=U7501.4:6mm
5%43K
MF-LF1/16W
402
60
DMN32D2LFB4DFN1006H4-3
DBGLED
DFN1006H4-3DMN32D2LFB4DMN5L06VK-7
DBGLED
SOT-563DMN5L06VK-7
DBGLED
SOT-563
402
240
1/16W5%
MF-LF
PLACE_NEAR=R8185.2:6mm
5%1/16WMF-LF402
820
MC74VHC1G08SC70-HF
44
60
NO STUFF
100K5%1/16WMF-LF402
PLACE_NEAR=R8138.1:6mm
BAT54XV2T1SOD-523
BAT54XV2T1SOD-523
PLACE_NEAR=R8174.1:6mm
BYPASS=U8180.5:3:2.3mm
0.1uF
402CERM10V20%
18 19 40 65 83
CRITICAL
SOT-563DMB53D0UV
1%23.7K
402
1/16WMF-LF
CRITICAL
DMB53D0UVSOT-563
10%2.2UF
6.3V
402X5R
54.9K
MF-LF
1%
402
1/16W
402
61.9K1/16W
1%
MF-LF
100
MF-LF402
5%1/16W
1%2.0K1/16WMF-LF
402
33
5%330K
201
1/20WMF
40
50 64 65 78 79 83
X7R-CERM
20%0.1UF
S0PGOOD_ISL
0402
10V
PLACE_NEAR=U8160.2:4mm
S0PGOOD_ISL
MF-LF
10
5%1/16W
402PLACE_NEAR=U8160.2:4mm
PLACE_NEAR=U8160.7:4mm
S0PGOOD_ISL
10MF-LF
4025%
1/16W
X7R-CERM
20%
NOSTUFF
0402
10V
0.1UF
PLACE_NEAR=U8160.2:7mm
0.1UF
NOSTUFF
10V
0402X7R-CERM
20%
PLACE_NEAR=U8160.2:7mm
MF-LF1/16W
NOSTUFF
402
100K5%
PLACE_NEAR=U8160.1 :4mm
Power Control 1/ENABLESYNC_DATE=06/23/2013SYNC_MASTER=CLEAN_J45
P5VS4_EN_D
=P5VS4_ENMAKE_BASE=TRUEP5VS4_EN
P1V05S0_ENMAKE_BASE=TRUE
=PP5V_S0_VMON
P1V5_DIV_VMON
VMON_MR
P1V05S0_PGOOD
MIN_LINE_WIDTH=0.5 MMVOLTAGE=3.3V
PP3V3_S0_VMON_P2
MIN_NECK_WIDTH=0.2 MM
PP3V3_S0_VMON_P7
S0PGD_BJT_GND_R
P5V_DIV_VMON VMON_MR
=PP1V35_S3RS0_VMON
ALL_SYS_PWRGD_R
MIN_LINE_WIDTH=0.5 MM
PP3V3_S0_VMON_P7
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
=PP1V05_S0_VMON
=PP3V3_S0_VMON=PP3V3_S0_VMON
PM_SLP_S3_BUF_L
ALL_SYS_PWRGD
P1V05_VID_VMON
MIN_NECK_WIDTH=0.25 MMVOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MMPP3V3_S5_DBGLED
P1V5S0_PGOOD
S4_PWR_ENMAKE_BASE=TRUE
P3V3S3_ENMAKE_BASE=TRUE
MAKE_BASE=TRUEP5VS3_EN
DDRREG_ENMAKE_BASE=TRUE
PM_SLP_S4_L
SMC_WIFI_PWR_EN
=PP3V3_S4_WLAN
MAKE_BASE=TRUEPM_WLAN_EN
=PP3V3_S5_PWRCTL
ALL_SYS_PWRGD
S0PGD_C
VMON_Q2_BASE
MAKE_BASE=TRUEP5VS0_EN
MAKE_BASE=TRUEALL_SYS_PWRGD
MAKE_BASE=TRUES5_PWRGD
MAKE_BASE=TRUEPM_SLP_SUS_L
MAKE_BASE=TRUESMC_PM_G2_EN P3V3S5_EN
MAKE_BASE=TRUE
PM_SLP_S3_R_LMAKE_BASE=TRUE
=TBT_S0_EN
DBGLED_S5
DBGLED_S0_D
PM_1V5_PGD_L
=PP3V3_S5_1V5PGOOD
PM_1V5_PGD_L_R
PM_P1V5_PGD_DIV
DELAY_1V5S0_PGD
=PP1V5_S0_DIV
=PP3V42_G3H_CHGR
ALL_SYS_PWRGD
PM_SLP_S3_R_L
DBGLED_S3_D
TPAD_VBUS_EN
PM_SLP_S3_BUF_L
VMON_Q3_BASE
SUS_PGOOD_CT
=P3V3S5_EN
=P5VS5_EN
TP_SUS_PGOOD_MR_L
P5VS4_PGOOD
DDRREG_PGOOD
=PP5V_S3_DDRREG
=PP5V_S4_REG
CHGR_VFRQ
VMON_3V3_DIV
=PP1V35_S3RS0_VMON
=PP3V3_S0_VMON
P3V3S5_PGOOD
=PP3V42_G3H_PWRCTL
CPUVR_VR_ON
DBGLED_S4_D
=P3V3S4_EN
PM_RSMRST_L
DBGLED_S3
=P3V3S3_EN
PM_SLP_S5_L
VMON_Q4_BASE
=TBTBPWRSW_EN=TBTAPWRSW_EN
P1V05_EN_D
=PP3V3_SUS_CNTRL
DBGLED_S4
S4_PWR_ENPM_SLP_S4_L
DBGLED_S0
=PP3V3_SUS_CNTRL
=PP5V_S0_VMON
VMON_5V_DIV
=PP3V3_S5_VMON
=DDRREG_EN
=P5VS3_EN
=P1V5S0_EN
=DCINVSENS_EN
SMC_S4_WAKESRC_EN
=P1V05S0_EN
=P3V3S0_EN
=PP3V3_S5_PWRCTL
=PBUSVSENS_EN
P3V3S0_P1V5_S0_ENMAKE_BASE=TRUE
=PP3V3_S5_PWRCTL
PM_SLP_S3_L
=PP3V3_S5_DBGLED
=P3V3SUS_EN
=P5VS0_EN
PM_SLP_S3_BUF_L
R81121
2
C81121
2
R81111
2
C81101
2
R81851
2
C81851
2
R81311
2
R81671
2
R81571
2
R81691 2
R81651
2
R81621 2
R81561
2
R81531 2
R81511
2
R81521
2
Q8150
5
7
1
6 4
8
2
3
R81541 2
R81551 2
U8130
4
2
3
15
6
C81311
2
R81331
2
C8130 1
2
R81681 2
R81781 2
C81421
2
R81401 2 R81411
2
U8160
4
1
8
9
3
5
6
2 7
R81721
2
R81731
2
R81701
2
R81711
2
R81601
2
R81611
2
C81131
2
R81131
2
U81702
1
3
6
4
C8170 1
2
C81141
2
R81141
2
C8160 1
2
D8190A
K
D8191A
K
D8193A
K
D8192A
K
R81901
2
R81911
2
R81921
2
R81931
2
R819412
R81201
2
R81581
2
R81591
2
R81861
2
C81861
2
C81871
2
R81871
2
C81741
2
R81741
2
Q8131 3
1 2
Q8191 3
1 2
Q8190 6
2 1
Q8190 3
5 4
R81751 2
R81381 2
U8180
3
2
1
4
5
R81801
2
D8185A
K
D8174A
K
C8180 1
2
Q8151
6
2
1
R81361
2
Q81515
3
4
C8134 1
2
R81351
2
R81341
2
R81371 2
R81391
2
R81251
2
C8161
1
2
R81951 2
R81961 2
C8162 1
2
C8163 1
2
R81971
2
dvt
051-0675
6.0.0
81 OF 119
65 OF 94
5
65 81
65
65
65 81
65
81
65 81 6581
50 64 65 78 79 83
65
81
65 81
18 19 40 65 83
18 19 40 65 83
81
81
56 81
65
50 64 65 78 79 83
59 81
60 81
65 81
65 81
60
81
65 81
65
12 21 33 37 40 65 78 83
65 81
65 81
81
65 81
65 81
81
OUTIN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
NOTE: NO PU ON 3V3 AND 1V8 PGOODS SINCE THEY ARE SYNTHETIC.
NOTE: 1V8 MAY NOT BE REQUIRED FOR KEPLER IF THERE IS NO LVDS
1) GPU_3.3V
2) IFPX IOVDD - 1.8V
EXT GPU PWRGD Pullup
3) GPUVCORE
5) PEXVDD/Q
NOTE 2: CHECK IF 1V8 IS READ AS LOGIC HIGH BY GMUX
PLACE R8210 - R8217 CLOSE TO U8000
PLACE R8220 - R8227 CLOSE TO U1000
OR IFPY IOVDD - 1.05V
up in the following order:
PCIE TEST STRUCTURES (FOR LAB USE)
KEPLER GPU REQUIRES RAILS TO COME
GPU Rail Sequencing
4) FBVDDQ/GDDR5 1.35V
6464 81
77
71
100K
MF201
5%1/20W
100K
MF201
5%1/20W
100K
MF201
5%1/20W
77
71
71
82
79
79
79
79
71
64
NOSTUFF
82
MF201
5%1/20W
NOSTUFF
82
MF201
5%1/20W
NOSTUFF
82
MF201
5%1/20W
NOSTUFF
82
MF201
5%1/20W
NOSTUFF
82
MF201
5%1/20W 1/20W
NOSTUFF
82
MF201
5%
NOSTUFF
82
MF201
5%1/20W
79
Power Sequencing EG/PCH S0
SYNC_DATE=01/13/2012SYNC_MASTER=D2_KEPLER
GPU_PGOOD3
GPU_PGOOD1
GPU_PGOOD4
=P1V8GPU_EN
=PP3V3_S0_PWRCTL
GPU_PGOOD2MAKE_BASE=TRUE
TP_GPU_PGOOD2
=PP3V3_S0GPU_FET
PEG_R2D_P<7>
PEG_R2D_N<7>
PEG_R2D_P<5>
PEG_R2D_N<5>
PEG_R2D_P<3>
PEG_R2D_N<3>
PEG_R2D_P<0>
PEG_R2D_N<0>
PEG_D2R_P<0>
=P1V05_GPU_EN
=GPUVCORE_ENEG_RAIL3_EN
EG_RAIL2_EN
EG_RAIL4_EN
=P3V3GPU_EN
=P1V35FB_EN
=P3V3GPU_MISC_EN
PEG_D2R_N<4>
PEG_D2R_P<4>
PEG_D2R_N<7>
PEG_D2R_P<7>
PEG_D2R_N<0>
EG_RAIL1_EN
EG_RAIL5_EN
PM_ALL_GPU_PGOODP1V35GPUFB_ENMAKE_BASE=TRUE
P1V8GPU_ENMAKE_BASE=TRUE
GPUVCORE_ENMAKE_BASE=TRUE
GPUVCORE_PGOODMAKE_BASE=TRUE
P1V05_S0GPU_ENMAKE_BASE=TRUE
GPUFB_PGOODMAKE_BASE=TRUE
P1V05_S0GPU_PGOODMAKE_BASE=TRUE
MAKE_BASE=TRUEP3V3GPU_EN
R82011
2
R82021
2
R82001
2
R82201
2
R82241
2
R82271
2
R82131
2
R82101
2
R82151
2
R82171
2
dvt
051-0675
6.0.0
82 OF 119
66 OF 94
81
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 82 86
79
79
79
68 82 86
68 82 86
68 82 86
68 82 86
68 82 86
79
79
IN
GND THRM
ON
VIN_1
VIN_2
VOUT_1
VOUT_2
PAD
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
NC
OUT
OUT
OUT
OUT
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
LCD PANEL INTERFACE (eDP)
518S0829
LCD Panel HPD & AUX strapping
16VX7R-CERM
0402
0.1UF10%
0805
FERR-220-OHM
CRITICAL
79 83
0.001UF
0402X7R-CERM
50V10%
16VX7R-CERM
0402
0.1UF10%
MFET-2X2-8IN
CRITICAL
FPF1009
16VX7R-CERM0402
0.1UF10%
603
20%10UF
6.3VX5R
X5R-CERM 020116V
0.1UF10%
0.1UF X5R-CERM 020116V10%
79 86 94
79 86 94
0.1UF X5R-CERM 020116V10%
X5R-CERM 020116V
0.1UF10%
79 86 94
79 86 94
X5R-CERM16V
0.1UF10%
0201
X5R-CERM 020116V
0.1UF10%
79 86 94
79 86 94
0201X5R-CERM16V
0.1UF10%
0201X5R-CERM16V
0.1UF10%
79 86 94
79 86 94
X5R-CERM 020116V
0.1UF10%
X5R-CERM 020116V
0.1UF10%
79 86 94
79 86 94
CRITICAL
F-RT-SM20525-130E-01
10%100V
1000PF
X7R0603
62 79 83 5%
0
02011/20W MF79
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
5%
201
1/20WMF
1M
46
46
CRITICAL
15OHM-100MA-8.5GHZDLP0NS
15OHM-100MA-8.5GHZDLP0NS
CRITICAL
CRITICAL
DLP0NS15OHM-100MA-8.5GHZ
15OHM-100MA-8.5GHZDLP0NS
CRITICAL
CRITICAL
SM
+/-0.1PF
50V
C0G-CERM0201
9.1PF+/-0.1PF
50V
C0G-CERM0201
9.1PF+/-0.1PF
50V
C0G-CERM0201
9.1PF+/-0.1PF
50V
C0G-CERM0201
9.1PF+/-0.1PF
50V
C0G-CERM0201
9.1PF 9.1PF
0201C0G-CERM
50V
+/-0.1PF
eDP Display ConnectorSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<3>
LCD_PWR_EN
LED_RETURN_1
DP_INT_ML_P<1>
DP_INT_ML_P<0>
DP_INT_AUX_N
DP_INT_ML_P<3>
DP_INT_ML_N<3>
DP_INT_ML_N<1>
DP_INT_ML_P<2>
DP_INT_ML_N<2>
DP_INT_AUX_N
=PP3V3_S0_LCD
DP_INT_AUX_PLCD_HPD_CONN
PPVOUT_S0_LCDBKLT
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
PP5VR3V3_SW_LCD=PP5V_S0_LCD
DP_INT_ML_F_P<0>
DP_INT_ML_F_N<0>
LCD_HPD_CONN
DP_INT_AUX_P
DP_INT_ML_N<1>
DP_INT_ML_P<0>
DP_INT_ML_N<0>
DP_INT_ML_P<1>
DP_INT_ML_N<2>
DP_INT_ML_N<3>
DP_INT_ML_P<2>
DP_INT_ML_P<3>
NC_ISNS_LCD_PANELN
DP_INT_ML_F_P<1>
DP_INT_ML_F_N<1>
DP_INT_ML_F_P<2>
DP_INT_ML_F_N<2>
DP_INT_ML_F_P<3>
DP_INT_ML_F_N<3>
LCD_FSS
LCD_HPD
DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N
DP_INT_ML_C_N<0>
DP_INT_ML_C_P<1>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<3>
DP_INT_ML_N<0>
NC_ISNS_LCD_PANELP
PP5VR3V3_SW_LCD_UF
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP5VR3V3_SW_LCD_ISNS
VOLTAGE=5V
C8301 1
2
L8300
1 2
C8302 1
2
C8309 1
2
U8300
6
1
7
2
3
4
5
C83111
2
C83121
2
C8321 1 2
C8320 1 2
C8323 1 2
C8322 1 2
C8325 1 2
C8324 1 2
C8327 1 2
C8326 1 2
C8329 1 2
C8328 1 2
J8300
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
5
6
7
8
9
C8300 1
2
R8300 1 2
R83021
2
R83031
2
R83011
2
R83131 2
R83141 2
R83151 2
R83161 2
R83121 2
R83171 2
R83181 2
R83111 2
FL83001 2
34
FL83021 2
34
FL83011 2
34
FL83031 2
34
XW83201 2
C83501
2
C83511
2
C83521
2
C83531
2
C83541
2
C83551
2
dvt
051-0675
6.0.0
83 OF 119
67 OF 94
62 83
62 83
62 83
62 83
62 83
62 83
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
81
67 83 86 94 67 83
62 83
8381
86 94
86 94
67 83
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
67 83 86 94
86 94
86 94
86 94
86 94
86 94
86 94
67 83 86 94
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
NC
NCNC
NCNC
NCNC
NCNC
NCNC
NC
NCNC
NC
NCNC
NCNC
NCNC
NC
NC
NCNC
NCNC
NCNC
NC
IN
OUT
IN
IN
NCPEX_SVDD_3V3
PEX_TX0*
PEX_TX0PEX_RX0
PEX_RX1
PEX_RX6*
PEX_REFCLK*
PEX_WAKE*
PEX_CLKREQ*
PEX_RST*
PEX_REFCLK
PEX_RX15
PEX_RX15*
PEX_RX14*
PEX_RX14
PEX_RX12*
PEX_RX12
PEX_RX11*
PEX_RX11
PEX_RX10*
PEX_RX10
PEX_RX9*
PEX_RX9
PEX_RX8*
PEX_RX8
PEX_RX7
PEX_RX7*
PEX_RX6
PEX_RX5
PEX_RX5*
PEX_RX4*
PEX_RX4
PEX_RX3*
PEX_RX3
PEX_RX2
PEX_RX2*
PEX_RX1*
PEX_TSTCLK_OUT*
PEX_TERMP
PEX_TX15
PEX_TX15*
PEX_TSTCLK_OUT
PEX_TX14*
PEX_TX14
PEX_TX13*
PEX_TX13
PEX_TX12
PEX_TX12*
PEX_TX11
PEX_TX11*
PEX_TX10
PEX_TX10*
PEX_TX9*
PEX_TX8*
PEX_TX9
PEX_TX8
PEX_TX7
PEX_TX6*
PEX_TX6
PEX_TX5*
PEX_TX5
PEX_TX4
PEX_TX3*
PEX_TX3
PEX_TX2
PEX_TX2*
PEX_TX1*
PEX_TX1
PEX_TX4*
PEX_RX0*
PEX_RX13*
PEX_RX13
PEX_TX7*
(1 OF 10)
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
- =PP3V3_GPU_VDD33
(NONE)
(NONE)
Signal aliases required by this page:
Page Notes
BOM options provided by this page:
Power aliases required by this page:
66 82 86
66 82 86
82 86
82 86
82 86
82 86
66 82 86
66 82 86
82 86
82 86
82 86
82 86
82 86
82 86
GND_VOID=TRUE 6.3V
0.22UF20% X6S-CERM 0201
75 82
68 75
82 86
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
82 86
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
GND_VOID=TRUE 6.3V X6S-CERM
0.22UF20% 0201
1/20WMF
1%
NOSTUFF
200
201
MF1/20W
2.49K
1%
201
10K1%1/20WMF201
0201MF 5% 1/20W
0
NV-GK107
OMIT_TABLE
BGA
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 86
82 83 88
82 83 88
66 82 86
66 82 86
KEPLER PCI-E
SYNC_MASTER=D2_MLB SYNC_DATE=07/31/2012
PEG_R2D_C_P<0>
PEG_R2D_P<2>
PEG_R2D_P<0>
PEG_R2D_C_P<3>
PEG_R2D_N<2>
PEG_R2D_N<3>PEG_R2D_C_N<3>
PEG_R2D_N<6>
PEG_D2R_C_N<4>
PEG_R2D_P<7>
PEG_R2D_P<5>
PEG_R2D_P<2>
PEG_D2R_C_N<2>
PEG_R2D_C_P<4>
PEG_R2D_P<1>
PEG_R2D_N<1>
PEG_R2D_N<5>
PEG_D2R_N<0>
PEG_R2D_C_P<6>
PEG_D2R_C_P<1>
PEG_D2R_N<1>
PEG_D2R_C_N<4>
PEG_D2R_C_P<5>
PEG_D2R_C_P<6>
PEG_D2R_C_N<5>
PEG_D2R_C_P<7>
PEG_D2R_C_N<7>
PEG_D2R_C_N<6>
PEG_R2D_C_P<5>
PEG_R2D_C_P<7>
PEG_R2D_C_N<6>
PEG_R2D_N<7>
PEG_R2D_P<4>
PEG_R2D_P<3>
PEG_D2R_C_P<4>
PEG_D2R_C_N<3>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_P<7>
PEG_D2R_C_N<1>
PEG_D2R_C_N<0>
PEG_D2R_C_P<0>
PEG_D2R_P<1>
PEG_D2R_P<0>
PEG_D2R_P<2>
PEG_D2R_N<2>
PEG_D2R_P<4>
PEG_D2R_N<5>
PEG_D2R_P<5>
PEG_D2R_N<4>
PEG_D2R_N<3>
PEG_R2D_N<4>
PEG_R2D_C_N<7>
PEG_R2D_C_N<5>
PEG_R2D_P<6>
PEG_R2D_C_N<4>
PEG_R2D_C_N<0>
PEX_CLKREQ_L_R
PEG_D2R_P<3>
PEG_D2R_C_P<2>
PEG_D2R_C_P<3>
PEG_D2R_P<6>
GPU_RESET_L
PEG_R2D_C_P<1>
PEG_R2D_N<0>
=PP3V3_GPU_VDD33
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_P<2>
PEG_D2R_C_N<7>
PEG_R2D_N<0>
PEG_D2R_C_P<1>
PEG_D2R_C_N<1>
PEG_D2R_C_N<2>
PEG_D2R_C_P<2>
PEG_D2R_C_P<3>
PEG_D2R_C_N<3>
PEG_D2R_C_P<4>
PEG_D2R_C_P<5>
PEG_D2R_C_N<5>
PEG_D2R_C_P<6>
PEG_D2R_C_N<6>
PEG_D2R_C_P<7>
PEX_TSTCLK_O_P
GPU_PEX_TERMP
PEX_TSTCLK_O_N
PEG_R2D_N<1>
PEG_R2D_N<2>
PEG_R2D_P<3>
PEG_R2D_N<3>
PEG_R2D_P<4>
PEG_R2D_N<4>
PEG_R2D_N<5>
PEG_R2D_P<5>
PEG_R2D_P<6>
PEG_R2D_N<7>
PEG_R2D_P<7>
PEG_CLK100M_P
GPU_RESET_R_L
PEX_CLKREQ_L_R
PEG_CLK100M_N
PEG_R2D_N<6>
PEG_R2D_P<1>
PEG_R2D_P<0> PEG_D2R_C_P<0>
PEG_D2R_C_N<0>
PP3V3_GPU_PEX_PLL_HVDD
C8420 1 2
C8421 1 2
C8422 1 2
C8423 1 2
C8424 1 2
C8425 1 2
C8426 1 2
C8427 1 2
C8428 1 2
C8429 1 2
C8430 1 2
C8431 1 2
C8432 1 2
C8433 1 2
C8434 1 2
C8435 1 2
C8456 1 2
C8457 1 2
C8458 1 2
C8459 1 2
C8460 1 2
C8461 1 2
C8463 1 2
C8464 1 2
C8465 1 2
C8466 1 2
C8468 1 2
C8469 1 2
C8470 1 2
C8462 1 2
C8467 1 2
C8455 1 2
R84021 2
R84051 2
R84011
2
R84001 2
U8400
AK12
AL13
AK13
AJ12
AN12
AM12
AN14
AM14
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AG12
AP29
AJ26
AK26
AK14
AJ14
AH14
AG14
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AJ11
dvt
051-0675
6.0.0
84 OF 119
68 OF 94
68 86
66 68 86
68 86
66 68 86
68 86
68 86
66 68 86
66 68 86
68 86
68 86
68 86
68 86
66 68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
66 68 86
68 86
66 68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 75
68 86
68 86
66 68 86
74 75 76 81
68 86
66 68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
68 86
94
94
68 86
68 86
66 68 86
66 68 86
68 86
68 86
66 68 86
66 68 86
68 86
66 68 86
66 68 86
68 86
68 86
66 68 86 68 86
68 86
76
NCNCNCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNCNCNC
NCNC
NCNCNC
NCNC
NCNC
NC
NC
NCNCNCNC
NCNC
NCNCNC
XVDD
VDD
VDD
(10 OF 10)
FBVDDQFBVDDQ
(7 OF 10)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
EDP = 30 A
EDP = 6500 MA
BOM options provided by this page:
Signal aliases required by this page:
(NONE)
(NONE)
Page Notes
- =PP1V35_GPU_FBVDDQ- =PPVCORE_GPU
Power aliases required by this page:
GPU FB DE-COUPLING
GPU VCORE DE-COUPLING
NOTE: ATLEAST 2 GND VIAS & 2 POWER VIAS PER CAP
1UF
0201CERM-X6S4V20%
1UF
0201CERM-X6S4V20%
1UF
0201CERM-X6S4V20%
6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%
20UF
0402X6T-CERM2V20%
20UF
0402X6T-CERM2V20%
20UF
0402X6T-CERM2V20%
20UF
0402X6T-CERM2V20%
0201
20%
CRITICAL
4VCERM-X6S
1UF
0201
20%
CRITICAL
4VCERM-X6S
1UF
0201
20%
CRITICAL
4VCERM-X6S
1UF
0201
20%
CRITICAL
4VCERM-X6S
1UF
1UF
0201CERM-X6S4V
CRITICAL
20%
0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
10%16VX7R-CERM
1000PF
0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S
0201
10%16V
1000PF
X7R-CERM
0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S
OMIT_TABLE
NV-GK107BGA
NV-GK107BGA
OMIT_TABLE
0805X6S4V20%47UF
NOSTUFF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
NOSTUFF
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
NOSTUFF
4VX5R-CERM
20%
CRITICAL
20UF
0603
NOSTUFF
20%
CRITICAL
X6S-CERM4V
22UF
0603
NOSTUFF
20%
CRITICAL
X6S-CERM4V
22UF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
NOSTUFF
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
NOSTUFF
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
NOSTUFF
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402-2
4VX5R-CERM
20%
CRITICAL
20UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
0402
6.3VCERM
20%10UF
4VX6S-CERM0402-1
10UF20%
4VX6S-CERM0402-1
10UF20%
4VX6S-CERM0402-1
10UF20%
4VX6S-CERM0402-1
10UF20%
1UF
0201CERM-X6S4V20%
SYNC_DATE=07/31/2012SYNC_MASTER=D2_MLB
KEPLER CORE/FB POWER
=PPVCORE_GPU
=PPVCORE_GPU
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_FBVDDQ =PP1V35_GPU_FBVDDQ
=PPVCORE_GPU
C85041
2
C85031
2
C85021
2
C85011
2
C85141
2
C85131
2
C85121
2
C85111
2
C85101
2
C85091
2
C85081
2
C85071
2
C85061
2
C85051
2
C85251
2
C85261
2
C85271
2
C85281
2
C85861
2
C85871
2
C85881
2
C85891
2
C85901
2
C85911
2
C85921
2
C85931
2
C85941
2
C85951
2
C85961
2
C85191
2
C85201
2
C85211
2
C85221
2
C85231
2
C85241
2
C85971
2
C85151
2
C85181
2
U8400
AA12
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
AA14
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
AA16
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
AA19
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
AA21
U15
U17
U18
U20
U22
V13
V15
V17
V18
V20
AA23
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
AB13
Y18
Y20
Y22
AB15
AB17
U1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
U2
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U3
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
U4
U5
U6
U7
U8
V1
U8400
AA27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
AA30
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
AB27
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
AB33
V27
W27
W30
W33
Y27
AC27
AD27
AE27
AF27
AG27
C85611
2
C85621
2
C85631
2
C85641
2
C85651
2
C85821
2
C85831
2
C85981
2
C85991
2
C85451
2
C85511
2
C85501
2
C85491
2
C85481
2
C85471
2
C85461
2
C85661
2
C85671
2
C85681
2
C85691
2
C85701
2
C85711
2
C85721
2
C85731
2
C85741
2
C85751
2
C85761
2
C85771
2
C85781
2
C85791
2
C85801
2
C85811
2
C85841
2
C85851
2
dvt
051-0675
6.0.0
85 OF 119
69 OF 94
69 76 81
69 76 81
69 72 73 81
69 72 73 81 69 72 73 81
69 76 81
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
NCNCNCNCNCNC
NCNC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NCNC
NCNC
NCNC
NCNC
NCNC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
NC
NCNCNCNCNCNCNC
NCNC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NCNC
NCNC
NCNC
NCNC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
FBA_CMD5
FBA_CMD0
FBA_CLK1*
FBA_CLK1
FBA_CLK0*
FB_GND_SENSE
FBA_WCKB67
FBA_D0
FBA_WCKB67*
FBA_WCKB45*
FBA_WCKB23*
FBA_WCKB45
FBA_WCKB01*
FBA_WCKB23
FBA_WCK67*
FBA_WCKB01
FBA_WCK67
FBA_WCK45*
FBA_WCK23*
FBA_WCK45
FBA_WCK01*
FBA_WCK23
FBA_WCK01
FBA_D63
FBA_D62
FBA_D60
FBA_D61
FBA_D57
FBA_D58
FBA_D59
FBA_D56
FBA_D55
FBA_D54
FBA_D52
FBA_D53
FBA_D50
FBA_D51
FBA_D47
FBA_D49
FBA_D48
FBA_D45
FBA_D46
FBA_D42
FBA_D43
FBA_D44
FBA_D40
FBA_D41
FBA_D39
FBA_D37
FBA_D38
FBA_D34
FBA_D35
FBA_D36
FBA_D32
FBA_D33
FBA_D31
FBA_D30
FBA_D29
FBA_D27
FBA_D28
FBA_D24
FBA_D25
FBA_D26
FBA_D22
FBA_D19
FBA_D20
FBA_D16
FBA_D17
FBA_D18
FBA_D14
FBA_D15
FBA_D11
FBA_D12
FBA_D13
FBA_D9
FBA_D10
FBA_D8
FBA_D7
FBA_D6
FBA_D4
FBA_D5
FBA_D3
FBA_D2
FBA_D1
FB_VDDQ_SENSE
FBA_CMD_RFU
FB_CLAMP
FBA_CMD_RFU
FB_CAL_PU_GND
FB_CAL_TERM_GND
FBA_DEBUG
FB_CAL_PD_VDDQ
FBA_PLL_AVDD
FBA_DEBUG
FBA_DQS_WP7
FB_DLL_AVDD
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP3
FBA_DQS_WP2
FBA_DQS_WP1
FBA_DQS_WP0
FBA_DQS_RN7
FBA_DQS_RN6
FBA_DQS_RN5
FBA_DQS_RN4
FBA_DQS_RN3
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN0
FBA_DQM7
FBA_DQM5
FBA_DQM6
FBA_DQM4
FBA_DQM3
FBA_DQM2
FBA_DQM0
FBA_DQM1
FBA_CLK0
FBA_CMD31
FBA_CMD29
FBA_CMD30
FBA_CMD27
FBA_CMD28
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD22
FBA_CMD23
FBA_CMD21
FBA_CMD19
FBA_CMD20
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD14
FBA_CMD15
FBA_CMD13
FBA_CMD12
FBA_CMD11
FBA_CMD4
FBA_CMD1
FBA_CMD3
FBA_CMD2
FBA_D23
FBA_D21
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
(3 OF 10)MEM INTERFACE A
FBB_CMD31
FBB_CMD10
FBB_CMD14
FBB_CMD24
FBB_CMD25
FBB_CMD_RFU1
FBB_CMD_RFU0
FBB_D12
FBB_D10
FBB_D7
FBB_D1
FBB_D2
FBB_D3
FBB_CMD16
FBB_DQS_RN4
FBB_DQM4
FBB_CLK1
FBB_CMD22
FBB_CLK0
FBB_CLK0*
FBB_CLK1*
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD15
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD23
FBB_CMD26
FBB_CMD27
FBB_CMD29
FBB_CMD30
FBB_D0
FBB_D4
FBB_D5
FBB_D6
FBB_D8
FBB_D9
FBB_D11
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DEBUG0
FBB_DEBUG1
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_PLL_AVDDFBB_WCK01
FBB_WCK01*
FBB_WCK23
FBB_WCK23*
FBB_WCK45
FBB_WCK45*
FBB_WCK67
FBB_WCK67*
FBB_WCKB01*
FBB_WCKB23
FBB_WCKB23*
FBB_WCKB45
FBB_WCKB45*
FBB_WCKB67
FBB_WCKB67*
FB_VREF
FBB_WCKB01
FBB_D31
FBB_D30
FBB_CMD28
(4 OF 10)MEM INTRERFACE B
SYM_VER_2
GS
D
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
- =PP1V35_GPU_S0_FB
FB PLL & DLL VDD
(NONE)
BOM options provided by this page:
- =PP1V05_GPU_PEX_IOVDD
Power aliases required by this page:
Signal aliases required by this page:
PLACE CLOSE TO BGA
MEM VREFC & VREFD SWITCH
(NONE)
Page Notes
ESR = 0.05OHM
ESR = 0.05OHM
FB VREF GEN (TEST ONLY)
NOTE:GDDR5 MODE H MAPPING
72 94
72 94
72 94
72 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
PLACE_NEAR=U8400.H26:8.4MM
X6S
0.1UF10%
NOSTUFF
6.3V
0201
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
PLACE_NEAR=U8400.H25:8.4MM
60.4 1/20W1% MF 201
PLACE_NEAR=U8400.H27:8.4MM
1/20WMF
40.21%
201
40.2
PLACE_NEAR=U8400.J27:8.4MM
1%1/20WMF201
MF
1%60.4
1/20W
201
1%60.4
1/20WMF201
20UF
2VX6T-CERM0402
20%
X6S
0.1UF10%6.3V
0201
4VCERM-X6S0201
1UF20%
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
MF1/20W1%10K
201MF1/20W1%10K
201
MF1/20W1%10K
201
1%
MF
10K
1/20W
201
73 94
73 94
73 94
73 94
X6S
0.1UF10%6.3V
0201
4VCERM-X6S0201
1UF20%
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
MF1/20W1%60.4
201
60.41%1/20WMF201
1/20W
10K1%
MF201
MF
1%1/20W
10K
201
10K
MF
1%1/20W
201
1/20WMF
10K
201
1%
PLACE_NEAR=U8400.H26:8.4MM
1/20W1%1.33K
NOSTUFF
MF201
PLACE_NEAR=U8400.H26:8.4MM
NOSTUFF
1.33K1%1/20WMF201
1% 1/20WMF
10K
201
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
70 72 94
70 72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
72 94
70 72 94
70 72 94
72 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
70 73 94
70 73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
73 94
70 73 94
73 94
70 73 94
73 94
75
72 73
CRITICAL
FERR-220-OHM-2A
0603
CRITICAL
FERR-220-OHM-2A
0603
20UF
2VX6T-CERM0402
20%4V
0201
1UF20%
CERM-X6S X6S
0.1UF10%6.3V
0201
71
71
1005%1/20WMF201
1/20W
1005%
MF201
BGA
OMIT_TABLE
NV-GK107
BGA
OMIT_TABLE
NV-GK107
DFN1006H4-3DMN32D2LFB4
SYNC_MASTER=D2_MLB
KEPLER FRAME BUFFER I/F
SYNC_DATE=07/31/2012
FB_SW_LEG
GPU_ALT_VREF
FB_B1_DBI_L<2>
GPU_FBA_DEBUG1
FB_A0_EDC<1>
FB_A0_EDC<2>
FB_A0_EDC<0>
PP1V05_GPU_FB_PLL_AVDD
FB_B1_CAS_L
FB_B0_A<0>
FB_B0_CKE_L
FB_B1_ABI_L
FB_B1_A<8>
FB_B0_DQ<12>
FB_B0_DQ<10>
FB_B0_DQ<7>
FB_B0_DQ<1>
FB_B0_DQ<2>
FB_B0_DQ<3>
FB_B1_CS_L
FB_B1_DBI_L<0>
FB_B1_CLK_P
FB_B1_A<7>
FB_B0_CLK_P
FB_B1_CLK_N
FB_B0_CS_L
FB_B0_A<3>
FB_B0_A<2>
FB_B0_A<4>
FB_B0_A<5>
FB_B0_WE_L
FB_B0_A<7>
FB_B0_A<6>
FB_B0_ABI_L
FB_B0_A<8>
FB_B0_A<1>
FB_B0_RAS_L
FB_B0_RESET_L
FB_B0_CAS_L
FB_B1_A<3>
FB_B1_A<2>
FB_B1_A<4>
FB_B1_A<5>
FB_B1_WE_L
FB_B1_A<6>
FB_B1_RESET_L
FB_B1_CKE_L
FB_B0_DQ<0>
FB_B0_DQ<4>
FB_B0_DQ<5>
FB_B0_DQ<6>
FB_B0_DQ<8>
FB_B0_DQ<9>
FB_B0_DQ<11>
FB_B0_DQ<13>
FB_B0_DQ<14>
FB_B0_DQ<15>
FB_B0_DQ<16>
FB_B0_DQ<17>
FB_B0_DQ<18>
FB_B0_DQ<19>
FB_B0_DQ<20>
FB_B0_DQ<21>
FB_B0_DQ<22>
FB_B0_DQ<23>
FB_B0_DQ<24>
FB_B0_DQ<25>
FB_B0_DQ<26>
FB_B0_DQ<27>
FB_B0_DQ<28>
FB_B0_DQ<29>
FB_B1_DQ<0>
FB_B1_DQ<1>
FB_B1_DQ<2>
FB_B1_DQ<3>
FB_B1_DQ<4>
FB_B1_DQ<8>
FB_B1_DQ<9>
FB_B1_DQ<10>
FB_B1_DQ<11>
FB_B1_DQ<12>
FB_B1_DQ<13>
FB_B1_DQ<14>
FB_B1_DQ<15>
FB_B1_DQ<16>
FB_B1_DQ<17>
FB_B1_DQ<18>
FB_B1_DQ<19>
FB_B1_DQ<20>
FB_B1_DQ<21>
FB_B1_DQ<22>
FB_B1_DQ<23>
FB_B1_DQ<24>
FB_B1_DQ<25>
FB_B1_DQ<26>
FB_B1_DQ<27>
FB_B1_DQ<28>
FB_B1_DQ<29>
FB_B1_DQ<30>
FB_B1_DQ<31>
GPU_FBB_DEBUG0
GPU_FBB_DEBUG1
FB_B0_DBI_L<0>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>
FB_B1_DBI_L<1>
FB_B1_DBI_L<3>
FB_B0_EDC<0>
FB_B0_EDC<2>
FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>
FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>
FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>
FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>
FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>
FB_VREF
FB_B0_DQ<31>
FB_B0_DQ<30>
FB_B1_RAS_L
FB_A0_A<4>
FB_A1_CLK_N
FB_A1_CLK_P
FB_A0_CLK_N
GPU_FBGND_SENSE
FB_A0_DQ<0>
FB_A1_WCLK_N<1>
FB_A1_WCLK_P<1>
FB_A1_WCLK_N<0>
FB_A0_WCLK_N<1>
FB_A1_WCLK_P<0>
FB_A0_WCLK_N<0>
FB_A0_WCLK_P<1>
FB_A0_WCLK_P<0>
FB_A1_DQ<31>
FB_A1_DQ<30>
FB_A1_DQ<28>
FB_A1_DQ<29>
FB_A1_DQ<25>
FB_A1_DQ<26>
FB_A1_DQ<27>
FB_A1_DQ<24>
FB_A1_DQ<23>
FB_A1_DQ<22>
FB_A1_DQ<20>
FB_A1_DQ<21>
FB_A1_DQ<18>
FB_A1_DQ<19>
FB_A1_DQ<15>
FB_A1_DQ<17>
FB_A1_DQ<16>
FB_A1_DQ<13>
FB_A1_DQ<14>
FB_A1_DQ<10>
FB_A1_DQ<11>
FB_A1_DQ<12>
FB_A1_DQ<8>
FB_A1_DQ<9>
FB_A1_DQ<7>
FB_A1_DQ<5>
FB_A1_DQ<6>
FB_A1_DQ<2>
FB_A1_DQ<3>
FB_A1_DQ<0>
FB_A1_DQ<1>
FB_A0_DQ<31>
FB_A0_DQ<30>
FB_A0_DQ<29>
FB_A0_DQ<27>
FB_A0_DQ<24>
FB_A0_DQ<25>
FB_A0_DQ<26>
FB_A0_DQ<22>
FB_A0_DQ<19>
FB_A0_DQ<18>
FB_A0_DQ<14>
FB_A0_DQ<15>
FB_A0_DQ<12>
FB_A0_DQ<13>
FB_A0_DQ<8>
FB_A0_DQ<7>
FB_A0_DQ<6>
FB_A0_DQ<4>
FB_A0_DQ<5>
FB_A0_DQ<3>
FB_A0_DQ<2>
GPU_FBVDDQ_SENSE
FB_CLAMP
FB_CAL_PU_GND
FB_CAL_TERM_GND
FB_CAL_PD_VDDQ
PP1V05_GPU_FB_PLL_AVDD
GPU_FBA_DEBUG0
FB_A1_EDC<3>
PP1V05_GPU_FB_DLL_AVDD
FB_A1_EDC<0>
FB_A1_EDC<1>
FB_A1_EDC<2>
FB_A0_EDC<3>
FB_A1_DBI_L<3>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<0>
FB_A0_DBI_L<3>
FB_A0_DBI_L<2>
FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_CLK_P
FB_A1_CAS_L
FB_A1_RESET_L
FB_A1_CKE_L
FB_A1_RAS_L
FB_A1_A<8>
FB_A1_A<0>
FB_A1_A<6>
FB_A1_A<4>
FB_A1_A<5>
FB_A1_CS_L
FB_A1_A<3>
FB_A1_A<2>
FB_A0_CKE_L
FB_A0_CAS_L
FB_A0_RESET_L
FB_A0_RAS_L
FB_A0_A<1>
FB_A0_A<5>
FB_A0_A<3>
FB_A0_A<2>
FB_A0_DQ<21>
FB_A0_A<7>
FB_A0_A<6>
FB_A0_A<8>
FB_A0_A<0>
FB_A1_RESET_L
FB_A0_CKE_L
=PP1V35_GPU_S0_FB
=PP1V35_GPU_S0_FB
=PP1V35_GPU_S0_FB
=PP1V35_GPU_S0_FB
FB_VREF
FB_CAL_PU_GND
GPU_FBB_DEBUG0
GPU_FBB_DEBUG1
FB_B1_CKE_L
FB_A0_RESET_L
FB_B1_RESET_L
FB_CAL_PD_VDDQ
FB_B0_RESET_L
FB_A1_CKE_L
FB_B0_CKE_L
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_IOVDD
FB_A1_DQ<4>
FB_A0_DQ<28>
FB_A0_DQ<23>
FB_A0_DQ<20>
FB_A0_DQ<1>
FB_A0_DQ<11>
FB_A0_DQ<10>
FB_A0_DQ<9>
FB_A0_ABI_L
FB_A0_DQ<17>
FB_A0_DQ<16>
FB_A1_WE_L
FB_A1_A<7>
FB_B1_A<1>
FB_B1_A<0>
FB_A0_WE_L
FB_A0_CS_L
FB_B0_CLK_N
FB_B0_DBI_L<1>
FB_B0_EDC<3>
FB_B0_EDC<1>
FB_B1_DQ<6>
FB_B1_DQ<7>
FB_B1_DQ<5>
FB_A1_A<1>
FB_A1_ABI_L
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.05V PP1V05_GPU_FB_PLL_AVDD
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MM
PP1V05_GPU_FB_DLL_AVDD
C86601
2
R86011 2
R86041
2
R86051
2
R86021
2
R86031
2
C86011
2
C86031
2
C86021
2
R86501
2
R86511
2
R86521
2
R86531
2
C86071
2
C86061
2
R86071
2
R86061
2
R86551
2
R86571
2
R86541
2
R86561
2
R86581
2
R86591
2
R86611 2
L8601
1 2
L8602
1 2
C86081
2
C86041
2
C86051
2
R86701
2
R86711
2
U8400
J27
H27
H25
E1
K27
F2
F1
R30
R31
AB31
AC31
U30
T31
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
U29
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
R34
Y33
V31
R33
U32
U33
U28
V28
V29
R32
AC32
L28
M29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
L29
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
M28
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
N31
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
P29
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
R29
AF31
AG34
AG32
AG33
P28
J28
H29
R28
AC28
P30
F31
F34
M32
AD31
AL29
AM32
AF34
M30
H30
E34
M34
AF30
AK31
AM34
AF32
M31
G31
E33
M33
AE31
AK30
AN33
AF33
U27K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
U8400
H26
D12
E12
E20
F20
D13
E14
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
F14
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
A12
B17
E17
B12
C14
B14
G15
F15
E15
C12
C20
G9
E9
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
G8
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
F9
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
F11
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
G11
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
F12
B24
C24
B26
C26
G12
G6
F5
G14
G20
E11
E3
A3
C9
F23
F27
C30
A24
D9
E4
B2
A9
D22
D28
A30
B23
D10
D5
C3
B9
E23
E28
B30
A23
H17F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27
Q86653
12
dvt
051-0675
6.0.0
86 OF 119
70 OF 94
70
70
70
70
79
70
70
70
70
70 72 94
70 72 94
70 81
70 81
70 81
70 81
70
70
70
70
70 73 94
70 72 94
70 73 94
70
70 73 94
70 72 94
70 73 94
70 76 81
70 76 81
70
70
BG
TGR
TG
PGND
VIN
VSW
BOOT
UGATE
LGATE
PHASE
RTN
FSEL
PGOOD
OCSET
VO
SREF
VCC PVCC
GND PGND
EN
FB
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
FB
EN
PVCCVCC
SREF
VO
OCSET
PGOOD
FSEL
RTN
PHASE
LGATE
UGATE
BOOT
PGNDGND
SET0
SET1
VID0
VID1
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
GPIO(16) VID1 VID0 FBVDD
VOUT = 1.5V / 1.35V
VOUT = 1.05V
376S0959
GPU FB SUPPLY
<Ra>
<Rb><Rb>
<Ra>
F = 500 KHZ
1 0 1.35V
0 0 1.5V
F = 500 KHZ
5.3A MAX OUTPUT
Vout = 0.5V * (1 + Ra / Rb)
GPU 1V05 SUPPLY
13A MAX OUTPUT
376S1038
0402CERM
PLACE_NEAR=L8760.2:1.5MM
5%1000PF
25V
0402CERM
PLACE_NEAR=Q8760.1:1.5MM
25V5%1000PF
CRITICAL
16V
68UF
CASE-D2E-SMPOLY-TANT
20%
10%0.1UF
16V
0402X7R-CERM
402
0
1/16WMF-LF
5%
CRITICALSIZ710DT
POWERPAK-6X3.7
2V20%
TANT
270UF
CASE-B4-SM
PLACE_NEAR=L8760.2:3MM
CRITICAL
402
1
1/16W5%
MF-LF
IHLP2525CZ-SM1
CRITICAL
2.2UH-14A
10%0.1UF
16V
0402X7R-CERM
402MF-LF1/16W
1
5%
1/16W
402MF-LF
5%2.2
CRITICAL
CASE-B4-SM
270UF
2V20%
TANT
PLACE_NEAR=L8710.2:3MM
CERM
PLACE_NEAR=L8710.2:1.5MM
5%1000PF
25V
0402
0402
PLACE_NEAR=Q8710.1:1.5MM
CERM25V5%1000PF
16V
CASE-D2E-SMPOLY-TANT
20%68UF
CRITICAL
CSD58873Q3DQ3D
CRITICAL
10%
X5R
1UF
603-1
25V
10%
X5R
1UF
603-1
25V
CRITICAL
CASE-B4-SMTANT
20%2V
PLACE_NEAR=L8760.2:3MM
270UF
X5R603
10UF20%10V
402
1/16W
2.2
MF-LF
5%
ISL95870UTQFN
CRITICAL
SM
PLACE_NEAR=U8710.1:1mm
66
66
402
3.01K
1/16WMF-LF
1%
402
1/16W1%
3.01K
MF-LF
10%
X5R16V
603
2.2UF1/20WMF
NOSTUFF
0
201
5%
10%16VX7R-CERM0402
0.047UF
50VC0G-CERM0402
10PF5%
50VC0G-CERM
0402
10PF5%
402
2.74K1%1/16WMF-LF
402
2.74K
1/16W1%
MF-LF
76 93
76 93
10%16V
X7R-CERM
1000PF
0201
0.003
0612MF1W1%
CRITICAL
SM
SM
5%
MF1/20W
0
0201
10UF
10V20%
X6S-CERM0603
402
2.2
MF-LF
5%1/16W
66
66
301K1%
MF1/20W
201
1/20W1%
MF
150K
201
SM
PLACE_NEAR=U8750.3:1mm
NOSTUFF
0
201
1/20WMF
5%
75
0603X6S-CERM
2.2UF10%16V
27K
1/20WMF201
1%
10%16V
0402
0.01UF
X7R-CERM
70
70
UTQFN
CRITICAL
ISL95870AHCRITICAL
1WMF0612
0.0021%
SM
10%16V
X7R-CERM
1000PF
0201
SM
4.64K
MF1/20W1%
NOSTUFF
201
NOSTUFF
MF1/20W1%4.64K
201
1%1/20WMF201
1.62K
1/20W1%
1.62K
MF201
COG-CERM0201-1
50V
10PF5%
COG-CERM0201-1
50V
10PF5%
0.68UH-25A-5.5MOHM
CRITICAL
PCMC063T-SM
MF1/20W1%2.74K
201
2.74K1%
1/20WMF201
1%
MF201
1/20W
4.75K
4.75K1%
1/20WMF201
1V05 GPU / 1V35 FB POWER SUPPLY
SYNC_MASTER=D2_MLB SYNC_DATE=07/31/2012
GPUFB_SET_R
GPUFB_OCSET
GPUFB_SENSE_DIV
GPUFB_GPU_OCSET_R
GPUFB_GPU_VO_R
P1V05_GPU_OCSET_R
P1V05_GPU_OCSET
P1V05_GPU_VO_R
=PP5V_S0GPU_P1V0P1V35_GPU
GPUFB_FSEL
P1V05_GPU_SREF
P1V05_S0GPU_PGOOD
=PP1V05_S0GPU_REG
FBVDD_ALTVO
P1V05_GPU_FSEL
=P1V05_GPU_EN
P1V05_GPU_RTN
P1V05_GPU_FB
GPUFB_CS_N
P1V05_GPU_CS_P
GPUFB_SREF
GPUFB_SET1
=PP5V_S0GPU_P1V0P1V35_GPU
P1V05_GPU_VO
GPUFB_PGOOD
GPUFB_SET0
GPUFB_RTN_DIV
GPUFB_VO
=P1V35FB_EN
MIN_LINE_WIDTH=0.6 mmPP5V_S0GPU_P1V35_GPU
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm
GPUFB_VBST
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
GPUFB_DRVH_R
DIDT=TRUEGATE_NODE=TRUE
GPUFB_LLMIN_LINE_WIDTH=0.6 mm
DIDT=TRUESWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 mm
DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmGPUFB_DRVL
VOLTAGE=1.05V
P1V05_GPU_PEX_IOVDD_SNS_P
GATE_NODE=TRUEDIDT=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
GPUFB_DRVH
VOLTAGE=0V
GPU_FBGND_SENSE
GPU_FBVDDQ_SENSE
VOLTAGE=1.35V
PP5V_S0GPU_P1V05_GPU
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P1V05_GPU_AGNDMIN_LINE_WIDTH=0.6 mm
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mm
DIDT=TRUEP1V05_GPU_VBST
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm
VOLTAGE=0V
P1V05_GPU_PEX_IOVDD_SNS_N
DIDT=TRUE
GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
P1V05_GPU_DRVH_R
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V
PP1V5R1V35_GPU_REG_R
MIN_LINE_WIDTH=0.6 mmP1V05_S0GPU_REG_R
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm
P1V05_GPU_LL_FETMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
DIDT=TRUESWITCH_NODE=TRUE
GATE_NODE=TRUEDIDT=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P1V05_GPU_DRVH
SWITCH_NODE=TRUEDIDT=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
P1V05_GPU_LL
MIN_NECK_WIDTH=0.2 mmDIDT=TRUE
P1V05_GPU_BOOT_RCMIN_LINE_WIDTH=0.3 mm
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
GPUFB_AGND
MIN_LINE_WIDTH=0.3 mm
DIDT=TRUEMIN_NECK_WIDTH=0.2 mm
GPUFB_BOOT_RC
P1V05_GPU_DRVL
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
DIDT=TRUEGATE_NODE=TRUE
GPUFB_CS_P
=PPVIN_S0GPU_P1V5P1V0
=PP1V5R1V35_GPU_REG
=PPVIN_S0GPU_P1V5P1V0
P1V05_GPU_CS_N
C8761 1
2
C87581
2
C8756 1
2C87551
2
R87591
2
Q8760
1
6
4 5
2 3 7
8
C8760 1
2
R878912
L8710
1 2
C87451
2
R874612
R87251
2
C8710 1
2
C8709 1
2
C87081
2
C8707 1
2
Q8710
5
9
3
4
1
6
7
8
C87621
2
C87121
2
C8763 1
2
C87011
2
R87011
2
U8710
123
6
5
1
15
7
16
9
10
14
2
4
11
13
8
XW8700
1 2
R87051
2
R87041
2
C8702 1
2
R87031
2
C87031
2
C87051
2
C8704 1
2
R87071
2
R87061
2
C8720
12
R8745
1 23 4
XW8701
1
2
XW8702
1
2
R87501 2
C87711
2
R87511
2
R87671
2
R87681
2
XW8750
1 2
R87631
2
C87721
2
R87491
2
C8773 1
2
U8750
1815
10
13
3
1
11
2
14
16
20
4
8
9
7
17
19
6
5
12
R8780
1 23 4
XW8751
1
2
C8770
12
XW8752
1
2
R87521
2
R87541
2
R87811 2
R87531 2
C87651
2
C87761
2
L8760
1 2
R87221
2
R87211
2
R87721
2
R87711
2
dvt
051-0675
6.0.0
87 OF 119
71 OF 94
71 81
81
45 93
46 93
71 81
45 93
71 81
81
71 81
46 93
WCK01
DQ24
DQ31
NC
DQ14
DBI0*
DQ27
DQ15
DQ13
RAS*
EDC3
EDC0
DQ26
DQ25
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ12
DQ7
DQ2
DQ1
DQ0
DBI3*
DBI1*
CS*
CK
ABI*
DQ30
CK*
A8/A7
A9/A1
DBI2*
WE*
BA2/A4
BA3/A3
DQ11
DQ10
DQ9
DQ8
DQ6
DQ5
DQ4
DQ3
BA0/A2
CKE*
A10/A0
DQ28
EDC2
EDC1
RESET*
WCK23*
WCK23
WCK01*
DQ29
BA1/A5
A11/A6
CAS*
SEN
MF
ZQ
(MF=0)
(1 OF 2)
IN IN
IN
IN
WCK01
DQ24
DQ31
NC
DQ14
DBI0*
DQ27
DQ15
DQ13
RAS*
EDC3
EDC0
DQ26
DQ25
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ12
DQ7
DQ2
DQ1
DQ0
DBI3*
DBI1*
CS*
CK
ABI*
DQ30
CK*
A8/A7
A9/A1
DBI2*
WE*
BA2/A4
BA3/A3
DQ11
DQ10
DQ9
DQ8
DQ6
DQ5
DQ4
DQ3
BA0/A2
CKE*
A10/A0
DQ28
EDC2
EDC1
RESET*
WCK23*
WCK23
WCK01*
DQ29
BA1/A5
A11/A6
CAS*
SEN
MF
ZQ
(MF=0)
(1 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
IN
IN
IN
IN
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
BOM options provided by this page:
CK TERMINATION - A0
Signal aliases required by this page:
Power aliases required by this page:
CK TERMINATION - A1
PLACE CLOSE TO U8850
- =PP1V5R1V35_S0_FB_VDD
(NONE)
PLACE CLOSE TO U8800
Page Notes
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
1/20W1%
MF
120
201
1/20W1%
MF
120
201
1/20W1%
MF
120
2011/20W
1%
MF
120
201
1/20W1%
MF
120
201
1/20W1%
MF
120
201
BGAH5GQ1H24AFR-T2C
32MX32-1.25GHZ-MFL
OMIT_TABLEPLACE_NEAR=U8800.J12:8.4MM
201
1/20W1%
MF
40.2
PLACE_NEAR=U8850.J12:8.4MM
MF
40.2
1%1/20W
201
PLACE_NEAR=U8800.J11:8.4MM
10VX7R-CERM
0.01UF10%
0201
PLACE_NEAR=U8850.J11:8.4MM
X7R-CERM10V0.01UF10%
0201
PLACE_NEAR=U8800.J11:8.4MM
1/20W1%
MF
40.2
201
PLACE_NEAR=U8850.J11:8.4MM
MF201
1/20W1%
40.2
PLACE_NEAR=U8800.J14:8.4MM
1/20W1%
MF
931
201
PLACE_NEAR=U8800.J14:8.4MM
1/20W1%
MF
549
201
PLACE_NEAR=U8800.J14:8.4MM
1/20W1%
MF
1.33K
201
PLACE_NEAR=U8800.J14:8.4MM
820PF25VX7R-CERM10%
0201
70 72 73
PLACE_NEAR=U8850.J14:8.4MM
1/20W1%
MF
1.33K
201
70 72 73
PLACE_NEAR=U8850.J14:8.4MM
1/20W1%
MF
931
201
PLACE_NEAR=U8850.J14:8.4MM
1/20W1%
MF
549
201
PLACE_NEAR=U8850.J14:8.4MM
820PF25VX7R-CERM10%
0201
PLACE_NEAR=U8800.U10:8.4MM
820PF25VX7R-CERM10%
0201
PLACE_NEAR=U8800.U10:8.4MM
1/20W1%
MF
549
201
70 72 73
PLACE_NEAR=U8800.U10:8.4MM
1/20W1%
MF
931
201
PLACE_NEAR=U8800.U10:8.4MM
1/20W1%
MF
1.33K
201
PLACE_NEAR=U8800.A10:8.4MM
820PF
X7R-CERM25V10%
0201
PLACE_NEAR=U8850.U10:8.4MM
1/20W1%
MF
1.33K
201
70 72 73
PLACE_NEAR=U8850.U10:8.4MM
1/20W1%
MF
931
201
PLACE_NEAR=U8850.U10:8.4MM
1/20W1%
MF
549
201
PLACE_NEAR=U8850.U10:8.4MM
820PF25VX7R-CERM10%
0201
PLACE_NEAR=U8850.A10:8.4MM
25VX7R-CERM
820PF10%
0201
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
BGAH5GQ1H24AFR-T2C
OMIT_TABLE
32MX32-1.25GHZ-MFL
H5GQ1H24AFR-T2C
OMIT_TABLE
BGA32MX32-1.25GHZ-MFL
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 72 94
70 72 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 72 94
70 72 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
BGAH5GQ1H24AFR-T2C
32MX32-1.25GHZ-MFL
OMIT_TABLE
X6S
0.1UF10%6.3V
0201X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
SYNC_DATE=07/31/2012SYNC_MASTER=D2_MLB
GDDR5 Frame Buffer A
FB_A0_MFFB_A0_ZQFB_A0_RAS_L
FB_A0_DQ<5>
FB_A0_DQ<0>
FB_A0_SEN
FB_A0_DBI_L<3>
FB_A0_DQ<14>
=PP1V35_GPU_FBVDDQ
FB_A0_CS_L
FB_A0_WCLK_P<0>FB_A0_WCLK_N<0>
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_FBVDDQ
FB_A0_WCLK_P<1>
FB_A1_DQ<31>FB_A1_DQ<30>FB_A1_DQ<29>FB_A1_DQ<28>FB_A1_DQ<27>FB_A1_DQ<26>FB_A1_DQ<25>FB_A1_DQ<24>FB_A1_DQ<23>FB_A1_DQ<22>FB_A1_DQ<21>FB_A1_DQ<20>FB_A1_DQ<19>FB_A1_DQ<18>FB_A1_DQ<17>
FB_A1_DQ<15>FB_A1_DQ<14>FB_A1_DQ<13>FB_A1_DQ<12>FB_A1_DQ<11>FB_A1_DQ<10>FB_A1_DQ<9>FB_A1_DQ<8>FB_A1_DQ<7>FB_A1_DQ<6>FB_A1_DQ<5>FB_A1_DQ<4>FB_A1_DQ<3>FB_A1_DQ<2>
FB_A1_ABI_L
FB_A1_EDC<0>
FB_A1_RESET_LFB_A1_DQ<16>
FB_A1_SEN
FB_A1_RAS_L
FB_A1_MFFB_A1_ZQ
FB_A1_DQ<0>FB_A1_DQ<1>
FB_A1_CAS_L
FB_A1_CLK_N
FB_A1_DBI_L<3>FB_A1_DBI_L<2>FB_A1_DBI_L<1>
FB_A0_DQ<20>
FB_A0_A<6>
FB_A0_DBI_L<2>
FB_A0_DQ<1>FB_A0_DQ<2>FB_A0_DQ<3>
FB_A0_A<7>
FB_A0_DQ<27>
FB_A0_DQ<31>FB_A0_DQ<30>
FB_A0_DQ<28>
FB_A0_DQ<26>
FB_A0_DQ<22>
FB_A0_DQ<25>FB_A0_DQ<24>FB_A0_DQ<23>
FB_A0_DQ<21>
FB_A0_DQ<19>FB_A0_DQ<18>FB_A0_DQ<17>
FB_A0_RESET_LFB_A0_DQ<16>FB_A0_DQ<15>
FB_A0_DQ<12>FB_A0_DQ<11>FB_A0_DQ<10>
FB_A0_DQ<7>FB_A0_DQ<6>
FB_A0_DQ<4>
FBA1_CK_MIDFB_A1_CLK_P
FBA0_CK_MID
FB_A0_CAS_L
FB_SW_LEG
FB_SW_LEG
FB_A1_VREFDFB_A1_VREFC
FB_A0_VREFDFB_A0_VREFC
FB_A0_A<1>
FB_SW_LEG
FB_A0_A<8>
FB_SW_LEG
FB_A1_WCLK_N<1>
FB_A0_CLK_P FB_A0_CLK_N
FB_A0_A<2>
FB_A0_A<3>
FB_A0_A<5>
FB_A0_DQ<13>
FB_A0_DBI_L<0>FB_A0_DBI_L<1>
FB_A1_WCLK_N<0>
FB_A1_WCLK_P<1>
FB_A1_WCLK_P<0>
FB_A1_A<6>
FB_A1_A<5>
FB_A1_A<0>
FB_A1_CKE_L
FB_A1_A<2>
FB_A1_A<3>FB_A1_A<4>
FB_A1_WE_L
FB_A1_A<1>FB_A1_A<7>
FB_A1_CS_L
FB_A1_DBI_L<0>
FB_A1_A<8>
FB_A0_A<4>
FB_A0_CLK_PFB_A0_CLK_N
FB_A1_CLK_P
FB_A0_DQ<29>
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_FBVDDQ
FB_A0_CKE_L
FB_A0_WE_L
FB_A0_ABI_L
FB_A0_WCLK_N<1>
FB_A0_EDC<0>
FB_A0_EDC<3>FB_A0_EDC<2>FB_A0_EDC<1>
FB_A1_EDC<2>FB_A1_EDC<1>
FB_A1_EDC<3>
FB_A0_DQ<9>FB_A0_DQ<8>
FB_A1_CLK_N
FB_A0_A<0>
FB_A1_VREFD
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 mm
FB_A0_VREFD
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 mm
FB_A1_VREFC
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 mm
FB_A0_VREFC
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 mm
U8800
H4
K5
K4
H5
J4
H11
K10
K11
H10
L3
J12
J11
J3
G12
D2
D13
P13
P2
A4
A2
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
B4
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
B2
M4
M2
E4
E2
F4
F2
A11
A13
C2
C13
R13
R2
J1
A5
J5
U5
G3
J2
J10
D4
D5
P4
P5
L12
J13
U8800
C5
C10
L14
P11
R5
R10
D11
G1
G4
G11
G14
L1
L4
L11
B1
B3
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
B12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
B14
P12
P14
T1
T3
T12
T14
D1
D3
D12
D14
E5
E10
J14
A10
U10
B5
B10
L10
P10
T5
T10
D10
G5
G10
H1
H14
K1
K14
L5
A1
A3
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
A12
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
A14
R12
R14
U1
U3
U12
U14
C1
C3
C4
C11
C12
C14
C88161
2
C88171
2
C88181
2
C88191
2
C88201
2
C88211
2
C88221
2
C88231
2
C88241
2
C88251
2
U8850
C5
C10
L14
P11
R5
R10
D11
G1
G4
G11
G14
L1
L4
L11
B1
B3
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
B12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
B14
P12
P14
T1
T3
T12
T14
D1
D3
D12
D14
E5
E10
J14
A10
U10
B5
B10
L10
P10
T5
T10
D10
G5
G10
H1
H14
K1
K14
L5
A1
A3
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
A12
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
A14
R12
R14
U1
U3
U12
U14
C1
C3
C4
C11
C12
C14
C88671
2
C88661
2
C88711
2
C88751
2
C88701
2
C88741
2
C88691
2
C88731
2
C88681
2
C88721
2
C88001
2
C88011
2
C88021
2
C88031
2
C88041
2
C88051
2
C88501
2
C88511
2
C88521
2
C88531
2
C88541
2
C88551
2
R88031
2
R88041
2
R88001
2
R88531
2
R88541
2
R88501
2
U8850
H4
K5
K4
H5
J4
H11
K10
K11
H10
L3
J12
J11
J3
G12
D2
D13
P13
P2
A4
A2
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
B4
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
B2
M4
M2
E4
E2
F4
F2
A11
A13
C2
C13
R13
R2
J1
A5
J5
U5
G3
J2
J10
D4
D5
P4
P5
L12
J13
R88011 2
R88511 2
C88901
2
C88911
2
R88021 2
R88521 2
R88341
2
R88301
2
R88311
2
C88311
2
R88811
2
R88841
2
R88801
2
C88811
2
C88331
2
R88321
2
R88351
2
R88331
2
C88321
2
R88831
2
R88851
2
R88821
2
C88831
2
C88821
2
C88561
2
C88571
2
C88581
2
C88591
2
C88601
2
C88611
2
C88621
2
C88631
2
C88641
2
C88651
2
C88061
2
C88071
2
C88081
2
C88091
2
C88101
2
C88111
2
C88121
2
C88131
2
C88141
2
C88151
2
dvt
051-0675
6.0.0
88 OF 119
72 OF 94
69 72 73 81
69 72 73 81
69 72 73 81
69 72 73 81
7072
94
72
72
72
72
70 72 94
70 72 94
69 72 73 81
69 72 73 81
707294
72
72
7272
IN
BI
IN
IN
IN
IN
WCK01
DQ24
DQ31
NC
DQ14
DBI0*
DQ27
DQ15
DQ13
RAS*
EDC3
EDC0
DQ26
DQ25
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ12
DQ7
DQ2
DQ1
DQ0
DBI3*
DBI1*
CS*
CK
ABI*
DQ30
CK*
A8/A7
A9/A1
DBI2*
WE*
BA2/A4
BA3/A3
DQ11
DQ10
DQ9
DQ8
DQ6
DQ5
DQ4
DQ3
BA0/A2
CKE*
A10/A0
DQ28
EDC2
EDC1
RESET*
WCK23*
WCK23
WCK01*
DQ29
BA1/A5
A11/A6
CAS*
SEN
MF
ZQ
(MF=0)
(1 OF 2)
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
IN
IN
IN
IN
VSSQ
VSS
VREFD
VREFC
VDDQ
VDD
(2 OF 2)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
NC
NC
WCK01
DQ24
DQ31
NC
DQ14
DBI0*
DQ27
DQ15
DQ13
RAS*
EDC3
EDC0
DQ26
DQ25
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ12
DQ7
DQ2
DQ1
DQ0
DBI3*
DBI1*
CS*
CK
ABI*
DQ30
CK*
A8/A7
A9/A1
DBI2*
WE*
BA2/A4
BA3/A3
DQ11
DQ10
DQ9
DQ8
DQ6
DQ5
DQ4
DQ3
BA0/A2
CKE*
A10/A0
DQ28
EDC2
EDC1
RESET*
WCK23*
WCK23
WCK01*
DQ29
BA1/A5
A11/A6
CAS*
SEN
MF
ZQ
(MF=0)
(1 OF 2)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PLACE CLOSE TO U8900
PLACE CLOSE TO U8950
Power aliases required by this page:
CK TERMINATION - B1
CK TERMINATION - B0
(NONE)
Page Notes
(NONE)
- =PP1V5R1V35_S0_FB_VDD
Signal aliases required by this page:
BOM options provided by this page:70 94
70 94
20%6.3V4.7UF
0402X6S
20%6.3V4.7UF
0402X6S
20%6.3V4.7UF
0402X6S
20%6.3V4.7UF
0402X6S
20%6.3V4.7UF
0402X6S
20%6.3V4.7UF
0402X6S
4.7UF20%6.3V
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
20%6.3V
4.7UF
0402X6S
MF201
1/20W1%
120
201
1/20W1%
MF
120
201
1/20W1%
MF
120
201
1/20W1%
MF
120201
1/20W1%
MF
120
PLACE_NEAR=U8900.J11:8.4MM201
1/20W1%
MF
40.2
PLACE_NEAR=U8900.J11:8.4MM0201
10%0.01UF
X7R-CERM10V
PLACE_NEAR=U8900.J12:8.4MM201
1/20W1%
MF
40.2
PLACE_NEAR=U8950.J11:8.4MM201
1%
MF
40.2
1/20W
PLACE_NEAR=U8950.J11:8.4MM
10VX7R-CERM0201
10%0.01UF
PLACE_NEAR=U8950.J12:8.4MM
1%1/20W
201MF
40.2
PLACE_NEAR=U8900.J14:8.4MM
201
1.33K1/20W1%
MF
70 72 73
PLACE_NEAR=U8900.J14:8.4MM
201
9311/20W1%
MF
PLACE_NEAR=U8900.J14:8.4MM
201
1/20W1%
MF
549
PLACE_NEAR=U8900.J14:8.4MM
0201
10%820PF25VX7R-CERM
PLACE_NEAR=U8900.U10:8.4MM
201
1/20W1%
MF
1.33K
PLACE_NEAR=U8900.U10:8.4MM
201
1/20W1%
MF
931
PLACE_NEAR=U8900.U10:8.4MM
201
1/20W1%
MF
549
70 72 73
PLACE_NEAR=U8900.A10:8.4MM
0201
10%25VX7R-CERM
820PF
PLACE_NEAR=U8900.U10:8.4MM
0201
10%820PF25VX7R-CERM
PLACE_NEAR=U8950.J14:8.4MM
201
1/20W1%
MF
549
70 72 73
PLACE_NEAR=U8950.J14:8.4MM
201
1/20W1%
MF
931
PLACE_NEAR=U8950.J14:8.4MM
201
1/20W1%
MF
1.33KPLACE_NEAR=U8950.J14:8.4MM
0201
10%820PF25VX7R-CERM
PLACE_NEAR=U8950.U10:8.4MM
0201
10%820PF25VX7R-CERM
70 72 73
PLACE_NEAR=U8950.U10:8.4MM
201
1/20W1%
MF
931
PLACE_NEAR=U8950.U10:8.4MM
201
1/20W1%
MF
549
PLACE_NEAR=U8950.U10:8.4MM
201
1/20W1%
MF
1.33KPLACE_NEAR=U8950.A10:8.4MM
0201
10%25VX7R-CERM
820PF
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
20%1UF
0201CERM-X6S4V
BGAH5GQ1H24AFR-T2C
32MX32-1.25GHZ-MFL
OMIT_TABLE
BGA32MX32-1.25GHZ-MFL
OMIT_TABLE
H5GQ1H24AFR-T2C
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 73 94
70 73 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
201
1/20W1%
MF
120
70 94
70 94
70 94
70 94
70 94
0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 73 94
70 73 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
BGAH5GQ1H24AFR-T2C
OMIT_TABLE
32MX32-1.25GHZ-MFL
0201
6.3V10%0.1UF
X6S0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
0201
6.3V10%0.1UF
X6S
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
70 94
BGAH5GQ1H24AFR-T2C
32MX32-1.25GHZ-MFL
OMIT_TABLE
SYNC_DATE=07/31/2012SYNC_MASTER=D2_MLB
GDDR5 Frame Buffer B
FB_B0_DQ<29>
FB_B0_DQ<31>
=PP1V35_GPU_FBVDDQ
FB_B0_VREFDFB_B0_VREFC
=PP1V35_GPU_FBVDDQ
FB_B1_CLK_N
FB_B1_WCLK_N<1>
FB_B1_ZQ
FB_B1_A<6>
FB_B1_A<3>FB_B1_A<4>
FB_B1_A<2>
FB_B0_DQ<17>
FB_B0_DQ<22>
FB_B1_CLK_P
FB_B1_CKE_L
FB_B1_CAS_LFB_B1_RAS_L
FB_B1_SEN
FB_B0_DQ<23>FB_B0_DQ<24>FB_B0_DQ<25>FB_B0_DQ<26>
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_FBVDDQ
FB_B0_DQ<30>
FB_B0_DQ<27>
FB_SW_LEG
FB_SW_LEG
FB_B0_RAS_L
FB_B1_VREFDFB_B1_VREFC
FB_SW_LEG
FB_B1_RESET_LFB_B0_RESET_L
FB_B0_CS_LFB_B0_WE_LFB_B0_CAS_L
FB_B0_WCLK_N<1>FB_B0_WCLK_P<1>
FB_B0_WCLK_N<0>
FB_B0_A<6>FB_B0_A<0>FB_B0_A<1>
FB_B1_WCLK_P<1>
FB_B1_WCLK_N<0>FB_B1_WCLK_P<0>
FB_B1_WE_L
FB_B1_A<0>FB_B1_A<1>FB_B1_A<7>
FB_B1_A<5>FB_B1_DBI_L<2>FB_B1_DBI_L<1>FB_B1_DBI_L<0>
FB_B0_DBI_L<0>
FB_B0_CKE_L
FB_B1_CS_LFB_B1_CLK_N
FB_B0_CLK_PFB_B0_CLK_N
FB_B0_CLK_P
FB_B0_SEN
FB_B0_ABI_L
FBB0_CK_MID
FB_B1_CLK_P
FB_B0_CLK_N
FB_B0_MF
FBB1_CK_MID
FB_B0_DBI_L<1>FB_B0_DBI_L<2>FB_B0_DBI_L<3>
FB_B0_DQ<7>FB_B0_DQ<8>
FB_B0_DQ<13>
FB_B0_DQ<10>
FB_B0_DQ<15>
FB_B0_DQ<0>FB_B0_DQ<1>FB_B0_DQ<2>FB_B0_DQ<3>FB_B0_DQ<4>FB_B0_DQ<5>FB_B0_DQ<6>
FB_B0_DQ<9>
FB_B0_DQ<11>FB_B0_DQ<12>
FB_B0_DQ<16>
FB_B0_DQ<18>FB_B0_DQ<19>
FB_B0_DQ<28>
FB_B0_WCLK_P<0>
FB_B1_DQ<0>FB_B1_DQ<1>
FB_B1_A<8>
FB_B1_DBI_L<3>
FB_B1_DQ<2>FB_B1_DQ<3>FB_B1_DQ<4>FB_B1_DQ<5>FB_B1_DQ<6>FB_B1_DQ<7>FB_B1_DQ<8>FB_B1_DQ<9>FB_B1_DQ<10>FB_B1_DQ<11>FB_B1_DQ<12>FB_B1_DQ<13>FB_B1_DQ<14>FB_B1_DQ<15>FB_B1_DQ<16>FB_B1_DQ<17>FB_B1_DQ<18>FB_B1_DQ<19>FB_B1_DQ<20>FB_B1_DQ<21>FB_B1_DQ<22>FB_B1_DQ<23>FB_B1_DQ<24>FB_B1_DQ<25>FB_B1_DQ<26>FB_B1_DQ<27>FB_B1_DQ<28>FB_B1_DQ<29>FB_B1_DQ<30>FB_B1_DQ<31>
FB_B0_DQ<14>
FB_B0_DQ<20>FB_B0_DQ<21>
FB_B0_A<3>
FB_B0_A<5>FB_B0_A<4>
FB_B0_A<7>
FB_B1_ABI_L
FB_B1_MF
FB_B1_EDC<2>FB_B1_EDC<1>
FB_B1_EDC<3>
FB_B1_EDC<0>FB_B0_EDC<0>
FB_B0_EDC<2>FB_B0_EDC<3>
FB_B0_EDC<1>
FB_B0_ZQ
FB_SW_LEG
FB_B0_A<8>
=PP1V35_GPU_FBVDDQ
FB_B0_A<2>
=PP1V35_GPU_FBVDDQ
MIN_NECK_WIDTH=0.1 mm
FB_B0_VREFC
MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 mm
FB_B0_VREFD
FB_B1_VREFD
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm
FB_B1_VREFC
MIN_LINE_WIDTH=0.25 MM
U8900
H4
K5
K4
H5
J4
H11
K10
K11
H10
L3
J12
J11
J3
G12
D2
D13
P13
P2
A4
A2
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
B4
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
B2
M4
M2
E4
E2
F4
F2
A11
A13
C2
C13
R13
R2
J1
A5
J5
U5
G3
J2
J10
D4
D5
P4
P5
L12
J13
U8900
C5
C10
L14
P11
R5
R10
D11
G1
G4
G11
G14
L1
L4
L11
B1
B3
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
B12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
B14
P12
P14
T1
T3
T12
T14
D1
D3
D12
D14
E5
E10
J14
A10
U10
B5
B10
L10
P10
T5
T10
D10
G5
G10
H1
H14
K1
K14
L5
A1
A3
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
A12
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
A14
R12
R14
U1
U3
U12
U14
C1
C3
C4
C11
C12
C14
R89001
2
C89161
2
C89171
2
C89181
2
C89191
2
C89201
2
C89211
2
C89221
2
C89231
2
C89241
2
C89251
2
U8950
C5
C10
L14
P11
R5
R10
D11
G1
G4
G11
G14
L1
L4
L11
B1
B3
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
B12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
B14
P12
P14
T1
T3
T12
T14
D1
D3
D12
D14
E5
E10
J14
A10
U10
B5
B10
L10
P10
T5
T10
D10
G5
G10
H1
H14
K1
K14
L5
A1
A3
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
A12
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
A14
R12
R14
U1
U3
U12
U14
C1
C3
C4
C11
C12
C14
C89671
2
C89661
2
C89711
2
C89751
2
C89701
2
C89741
2
C89691
2
C89731
2
C89681
2
C89721
2
U8950
H4
K5
K4
H5
J4
H11
K10
K11
H10
L3
J12
J11
J3
G12
D2
D13
P13
P2
A4
A2
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
B4
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
B2
M4
M2
E4
E2
F4
F2
A11
A13
C2
C13
R13
R2
J1
A5
J5
U5
G3
J2
J10
D4
D5
P4
P5
L12
J13
C89001
2
C89011
2
C89021
2
C89051
2
C89041
2
C89031
2
C89501
2
C89511
2
C89521
2
C89531
2
C89541
2
C89551
2
R89041
2
R89031
2
R89531
2
R89541
2
R89501
2
R89021 2
C89901
2
R89011 2
R89521 2
C89911
2
R89511 2
R89311
2
R89341
2
R89301
2
C89311
2
R89331
2
R89351
2
R89321
2
C89321
2
C89331
2
R89801
2
R89841
2
R89811
2
C89811
2
C89831
2
R89851
2
R89821
2
R89831
2
C89821
2
C89061
2
C89071
2
C89081
2
C89091
2
C89101
2
C89111
2
C89121
2
C89131
2
C89141
2
C89151
2
C89561
2
C89571
2
C89581
2
C89591
2
C89601
2
C89611
2
C89621
2
C89631
2
C89641
2
C89651
2
dvt
051-0675
6.0.0
89 OF 119
73 OF 94
69 72 73 81
73
73
69 72 73 81
707394
69 72 73 81
69 72 73 81
73
73
70 73 94
7073
94
70 73 94
69 72 73 81
69 72 73 81
73
73
73
73
BI
BI
BI
BI
BI
BI
IN
OUT
IN
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
NC
NCNC
NCNC
NCNCNC
NCNCNC
NC
NCNCNC
NCNCNCNC
NCNC
OUT
BI
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
G
DSG
DS
BI
BI
IFPEF_PLLVDD
IFPEF_RSET
IFPD_RSET
IFPD_PLLVDD
I2CA_SDA
IFPF_IOVDD
IFPAB_PLLVDD
IFPAB_RSET
IFPC_PLLVDD
IFPC_RSET
IFPC_L1
IFPC_L0*
IFPC_L0
IFPC_AUX_I2CW_SCL
IFPB_TXD7*
IFPA_TXD3*
IFPB_TXC
DACA_VREF
DACA_RSET
IFPE_IOVDD
I2CA_SCL
IFPC_L3*
IFPF_L3*
IFPF_L3
IFPF_L2*
IFPF_L2
IFPF_L1*
IFPF_L1
IFPF_L0*
IFPF_L0
IFPF_AUX_I2CZ_SDA*
IFPF_AUX_I2CZ_SCL
IFPE_L3*
IFPE_L3
IFPE_L2*
IFPE_L2
IFPE_L1*
IFPE_L1
IFPE_L0*
IFPE_L0
IFPE_AUX_I2CY_SDA*
IFPE_AUX_I2CY_SCL
IFPD_L3*
IFPD_L3
IFPD_L2
IFPD_L1*
IFPD_L1
IFPD_L0*
IFPD_L0
IFPD_IOVDD
IFPC_L3
IFPC_L1*
IFPC_IOVDD
IFPC_AUX_I2CW_SDA*
IFPB_TXD7
IFPB_TXD6*
IFPB_TXD6
IFPB_TXD5*
IFPB_TXD5
IFPB_TXD4*
IFPB_TXD4
IFPB_TXC*
IFPB_IOVDD
IFPA_TXD3
IFPA_TXD2*
IFPA_TXD2
IFPA_TXD1*
IFPA_TXD1
IFPA_TXD0*
IFPA_TXD0
IFPA_TXCIFPA_IOVDD
I2CS_SDA
I2CS_SCL
I2CC_SDA
I2CC_SCL
I2CB_SDA
I2CB_SCL
DACA_VSYNC
DACA_VDD DACA_RED
DACA_HSYNC
DACA_GREEN
DACA_BLUE
CEC
IFPA_TXC*
IFPD_L2*
IFPC_L2
IFPC_L2*
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA*
(5 OF 10)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NCNC
NCNC
NC
NCNC
THERMDP
THERMDN
JTAG_TRST*
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
STRAP3
STRAP4
STRAP2
STRAP1
STRAP0
XTAL_SSIN
XTAL_OUTBUFF
XTAL_OUT
XTAL_IN
VID_PLLVDD
PLLVDD
SP_PLLVDD
TESTMODE
MULTI_STRAP_REF0_GND
ROM_SO
ROM_SI
ROM_SCLK
ROM_CS*
VDD33
GPIO20
GPIO16
GPIO0
GPIO1
GPIO2
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO13
GPIO14
GPIO15
GPIO17
GPIO18
GPIO19
GPIO21
GPIO11
GPIO12
GPIO4
GPIO3
(6 OF 10)
IN
IN
IN
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DDC 3.3V/5V LEVEL TRANSLATOR
DISABLE PHY A & B FOR 15" MBP
Power aliases required by this page:
- =PP3V3_GPU_IFPB_IOVDD
IFPX PLLVDD
PD FOR AUX CHANNELS (FOR NVIDIA)
---------------------
GPU 3V3 VDD
ESR = 0.05OHM
(NONE)
- J31:YES
Page Notes
BOM options provided by this page:
- =PP3V3_GPU_VDD33
Signal aliases required by this page:
- =PP3V3_GPU_IFPX_PLLVDD
- =PP1V8_GPU_IFPA_IOVDD
- =PP1V8_GPU_DPLL
- =PP1V05_GPU_IFPEF_IOVDD
- =PP1V05_GPU_DPLL
IFP EF IOVDD
ESR = 0.05OHM
I2CB -> IFPF
DDC MAPPING
IFP CD IOVDD
I2CC -> SSC CLK GEN
I2CA -> IFPE
ESR = 0.05OHM
PLACE BELOW GPU NEAR DISPLAY SECTION
GPU PLL VDD
Note: PP3v3_GPU_MISC and pp3v3_GPU_VDD33 have to be isolated from each other
PD FOR RSET
- =PP1V05_GPU_IFPCD_IOVDD
- D2:YES
75
75
75
75
75
75
47 93
47 93
75
75
75 94
75 94
74 94
40.2K
1/20W0.1%
MF0201
PLACE_NEAR=U8400.J1:5MM
0402X6S-CERM
1UF10%25V25V
1UF10%
X6S-CERM0402
10V
0603
10UF20%
X6S-CERM
4.7UF
0402X6S6.3V20%
4.7UF
0402X6S6.3V20%
4VCERM-X6S0201
20%1UF
75
75
75
75
75
MF1/20W
201
1%10K
PLACE_NEAR=U8400.J4:8.4MM
1%1/20WMF201
10K
PLACE_NEAR=U8400.H1:8.4MM
80
80
1%1/20W
201
100K
MF1/20W
100K1%
MF201
1/20W
100K
201MF
1%100K
201MF1/20W1%
100K
201MF1/20W1%
201
100K
1/20W1%
MF201
1K
MF1/20W1%
PLACE_NEAR=U8400.AN2:5MM
1K
201MF1/20W1%
PLACE_NEAR=U8400.AD6:5MM
80
80
75
75
20UF
2VX6T-CERM0402
20%
FERR-220-OHM-2A
0603
CRITICAL
0603
CRITICAL
FERR-220-OHM-2A
CRITICAL0603
FERR-220-OHM-2A
0603X6S-CERM
4.7UF
6.3V10%
4.7UF
0402X6S6.3V20%
4VCERM-X6S0201
20%1UF
4VCERM-X6S0201
20%1UF
1%1/20WMF201
4.7K1%
MF
4.7K
1/20W
201
MF1/20W1%
201
1K
PLACE_NEAR=U8400.AF8:5MM
X6S-CERM0402-1
10UF
4V20%
4VCERM-X6S0201
20%1UF
7894
7894
7894
7894
78 94
78 94
78 94
78 94
78
201
4.7K1%1/20WMF
4.7K1%1/20W
201MF
1/20W
100K
201MF
1%
NO STUFF
1/20W
100K
201MF
1%
NO STUFF
78
4.7UF
0402X6S6.3V20%
75
75
0201
0.1UF20%16VX6S-CERM
0201
0.1UF20%16VX6S-CERM
0201X6S-CERM16V20%0.1UF 0.1UF
20%16VX6S-CERM0201
X6S-CERM16V20%0.1UF
0201X6S-CERM16V20%0.1UF
0201
0201
0.1UF20%16VX6S-CERM X6S-CERM
16V20%0.1UF
0201
X6S-CERM16V20%
0201
0.1UF 0.1UF20%16VX6S-CERM0201
0201
0.1UF20%16VX6S-CERM X6S-CERM
16V20%0.1UF
0201
X6S-CERM16V20%0.1UF
0201
X6S-CERM16V20%0.1UF
0201 0201
0.1UF20%16VX6S-CERM
0201
0.1UF20%16VX6S-CERM X6S-CERM
16V20%0.1UF
0201
DMN5L06VK-7SOT-563
DMN5L06VK-7SOT-563
74 79 94
74 79 94
BGA
OMIT_TABLE
CRITICAL
NV-GK107
79 94
79 94
79 94
79 94
79 94
79 94
79 94
79 94
74 80 94
74 80 94
74 80 94
74 80 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
28 86 94
MF
10K1%
201
1/20W
201
10K
MF1/20W1%
10K
201MF1/20W1%
10K
201MF1/20W1%
25VX6S-CERM0402
1UF10%
10VX6S-CERM0603
10UF20%
CRITICAL
330-OHM-1.2A
0603
10VX6S-CERM0603
10UF20%
25VX6S-CERM0402
1UF10%
25VX6S-CERM0402
1UF10%
X6S-CERM0402-1
10UF
4V20%
4VCERM-X6S0201
20%1UF
4VCERM-X6S0201
20%1UF4.7UF
0402X6S6.3V20%
OMIT_TABLE
NV-GK107BGA
10K
1/20W
201
1%
MF
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
KEPLER EDP/DP/GPIO
SYNC_MASTER=D2_MLB SYNC_DATE=07/31/2012
GPU_ROM_SO
GPU_MLS_STRAP2
GPU_MLS_STRAP1
HDMI_EG_DATA_C_N<0>
=PP3V3_GPU_MISC
=PP3V3_GPU_VDD33
GPU_ROM_CS_L
PP1V05_GPU_PLLVDD
DP_INT_EG_ML_P<0>
GPU_OSC_27M_XTAL_BUFFOUT_R
GPU_ROM_SCLK
GPU_TESTMODE
PP1V05_GPU_VID_PLLVDD
PP3V3_GPU_IFPB_IOVDD
PP1V8_GPU_IFPA_IOVDD
HDMI_EG_CLK_C_P
HDMI_EG_DATA_C_P<0>
HDMI_EG_DATA_C_N<2>
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N
GPU_MLS_STRAP3
=PP1V05_GPU_PEX_PLLVDD
PP3V3_GPU_IFPX_PLLVDD
IFPEF_RSET
IFPD_RSET
PP3V3_GPU_IFPX_PLLVDD
DPA_EG_DDC_DATA
PP1V05_GPU_IFPEF_IOVDD
PP1V05_GPU_IFPAB_PLLVDD
PP3V3_GPU_IFPX_PLLVDD
IFPC_RSET
PP1V05_GPU_IFPEF_IOVDD
DPA_EG_DDC_CLK
HDMI_EG_CLK_C_N
DP_TBTSNK1_ML_C_N<3>
DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK1_ML_C_N<2>
DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_ML_C_N<1>
DP_TBTSNK1_ML_C_N<0>
DP_TBTSNK1_EG_AUXCH_N
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK0_ML_C_N<3>
DP_TBTSNK0_ML_C_P<3>
DP_TBTSNK0_ML_C_N<2>
DP_TBTSNK0_ML_C_P<2>
DP_TBTSNK0_ML_C_N<1>
DP_TBTSNK0_ML_C_P<1>
DP_TBTSNK0_ML_C_N<0>
DP_TBTSNK0_ML_C_P<0>
DP_INT_EG_ML_N<3>
DP_INT_EG_ML_N<1>
DP_INT_EG_ML_P<1>
PP1V05_GPU_IFPCD_IOVDD
HDMI_EG_DATA_C_N<1>
PP1V05_GPU_IFPCD_IOVDD
GPU_SMB_DAT
GPU_SMB_CLK
GPU_SSC_SMB_DAT
DPB_EG_DDC_DATA
DPB_EG_DDC_CLK
DAC_AVDD
DP_INT_EG_ML_N<2>
DP_INT_EG_AUX_P
DP_INT_EG_AUX_N
GPU_OSC_27M_XTALIN
=PP3V3_GPU_VDD33
=PP3V3_GPU_VDD33
IFPD_RSET IFPEF_RSETIFPC_RSET
PP1V05_GPU_SP_PLLVDD
=PP1V05_GPU_IFPCD_IOVDD
=PP1V05_GPU_IFPEF_IOVDD
PP1V05_GPU_VID_PLLVDD
GPU_OSC_27M_SSIN
GPU_OSC_27M_SSIN
GPU_OSC_27M_XTALOUT
GPU_MLS_STRAP0
GPU_MLS_STRAP4
GPU_JTAG_TRST_L
GPU_JTAG_TCK
GPU_JTAG_TDO
GPU_JTAG_TMS
GPU_TESTMODE
GPU_OSC_27M_XTAL_BUFFOUT_R
GPU_JTAG_TDI
GPU_TDIODE_N
MULTI_STRAP_REF
GPU_TDIODE_P
HDMI_EG_DDC_CLK_Q
=PP3V3_GPU_IFPX_PLLVDD
HDMI_EG_DDC_DATA_Q
GPU_ROM_SI
DP_TBTSNK0_EG_AUXCH_P
DP_INT_EG_AUX_N
DP_INT_EG_AUX_P
DP_TBTSNK0_EG_AUXCH_N
GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2
GPU_GPIO_3
GPU_GPIO_4
GPU_GPIO_5
GPU_GPIO_6
GPU_GPIO_7
GPU_GPIO_8
GPU_GPIO_9
GPU_GPIO_10
GPU_GPIO_11
GPU_GPIO_12
GPU_GPIO_13
GPU_GPIO_14
GPU_GPIO_15
GPU_GPIO_16
GPU_GPIO_17
GPU_GPIO_18
GPU_GPIO_19
GPU_GPIO_20
GPU_GPIO_21
GPU_SSC_SMB_CLK
DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK1_ML_C_P<1>
=PP3V3_GPU_VDD33
=PP3V3_GPU_MISC
HDMI_EG_DATA_C_P<1>
HDMI_EG_DATA_C_P<2>
DP_INT_EG_ML_P<2>
DP_INT_EG_ML_P<3>
HDMI_EG_DDC_CLK
HDMI_EG_DDC_CLK_Q
=PP3V3_GPU_VDD33
HDMI_EG_DDC_DATA_Q
HDMI_EG_DDC_DATA
DP_INT_EG_ML_N<0>
DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
PP1V05_GPU_IFPEF_IOVDD
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.41 MM
VOLTAGE=1.05V PP1V05_GPU_PLLVDD
MIN_LINE_WIDTH=0.5 MM
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm
PP1V05_GPU_IFPCD_IOVDD
PP1V8_GPU_IFPA_IOVDD
VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 MM
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm
PP3V3_GPU_IFPB_IOVDDMIN_LINE_WIDTH=0.5 MM
PP1V05_GPU_IFPAB_PLLVDD
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 MM
PP1V05_GPU_SP_PLLVDDMAKE_BASE=TRUE
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 MM
PP3V3_GPU_IFPX_PLLVDD
U8400
L3
AL9
AL10
AM9
AK9
AP8
AG10
AP9
AN9
R4
R5
R7
R6
R2
R3
T4
T3
AG8 AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
AH8
AJ8
AG9
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
AG3
AG2
AF6
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
AF7
AF8
AK3
AK2
AG6
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
AG7
AN2
AB3
AB4
AC7
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
AB8
AD6
AF3
AF2
AC8
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
R90001
2
R90011
2
R90021
2
R90031
2
C90111
2
C90101
2
L9004
1 2
C90131
2
C90151
2
C90161
2
C90291
2
C90361
2
C90351
2
C90341
2
U8400
P6
M3
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
L6
P4
P1
P5
P7
L7
M7
N8
M1
M2
AM10
AM11
AP12
AP11
AN11
J1
AD8
H6
H4
H5
H7
AE8
J2
J7
J6
J5
J3
AK11
K4
K3
J8
K8
L8
M8
AD7
H3
H2
J4
H1
R90081
2
R90091 2
C90421
2
C90411
2
C90401
2
C90461
2
C90451
2
C90521
2
R90111
2
R90121
2
R90131
2
R90141
2
R90151
2
R90161
2
R90171
2
R90181
2
R90061
2
R90071
2
C90511
2
L9006
1 2
L9005
1 2
L9007
1 2
C90191
2
C90331
2
C90301
2
C90261
2
R90231
2
R90241
2
R90211
2
C90551
2
C90561
2
R90261
2
R90251
2
R90281
2
R90271
2
C90251
2
C90501
2
C90121
2
C90171
2
C90181
2
C90271
2
C90281
2
C90311
2
C90321
2
C90371
2
C90381
2
C90431
2
C90441
2
C90491
2
C90531
2
C90541
2
C90571
2
C90581
2
Q9000
3
54
Q9000
6
21
dvt
051-0675
6.0.0
90 OF 119
74 OF 94
74 81
68 74 75 76 81
74
74 94
74
74
74
74
74 80 94
74 80 94
76 81
74
74
74
74
74
74
74
74
74
74
74
68 74 75 76
81
68 74 75 76 81
74 7474
74 76
81
81
74
74 94
74
7494
74
81
74
74 80 94
74 79 94
74 79 94
74 80 94
68 74 75 76 81
74 81
74
68 74 75 76
81
74
74
74
74
74
74 76
74
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
GNDTHRM
VCC
CS*
WP*
SI SCLK
SO
HOLD*
PAD
NC
NC
IN
OUT
NC
08
NC
BI
OUT
BI
IN
BI
G
DSG
DS
SYM_VER_2
G S
D
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
StrapDie RevGPU GC6 ROM
Straps for GK107. GF108 support has been removed.
GP
GP
STUFF R9104 FOR THICK DIE
CURRENTLY STUFFED FOR GF108a/GK107-GTX
STRAP NOTES:
STUFF R9105 FOR THIN DIE
GPU internal Temp isolation
GPU overtemp masking
GC6 SUPPORT
Unused signals
CONFIG STRAPS - MLPS
GP
GP
GP
GPIOs Native Func
GPU XTAL 27 MHZ
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GPIOs
GP
GP
GP
Native Func
GP
Note: PU to non GPU_S0 3v3 source
GP
Hynix_29nm
ELPIDA_29nm
ELPIDA
Hynix 0x4
0x5
0x0
0x1
GP
MF1/20W
NO STUFF
5%
00201
MF1/20W5%
00201
40 41 75
5%
201
1/20W
10K
MF
5%
201
1/20WMF
10K
75 79
75 79
71 75
74 94
74 94
MF5% 1/20W
00201
GPU_ROM:YES1/20W
33
MF
5%
201
0201X6S6.3V10%0.1UF
GPU_ROM:YES
79
NOSTUFF
5.62K
MF
1%1/20W
201
74
74
1/20W
3.24K
201MF
1%
NOSTUFF
74
201MF
1%1/20W
5.62K
NOSTUFF
74
74
NOSTUFF
201MF
1%3.24K
1/20W
74 75
NOSTUFF
201
1%1/20WMF
3.24K
74 75
74 75
MF
1%1/20W
45.3K
201
OMIT_TABLE
25.5K
MF
1%1/20W
201
OMIT_TABLE
1MBIT
CRITICAL
USON
MX25L1005CMI-12G
5%
NO STUFF
1/20WMF
0
0201
5%
MF1/20W
GPU_ROM:YES
0
0201
33
MF1/20W201 5% GPU_ROM:YES
GPU_ROM:YES
33
MF1/20W
201
5%
1/20W5%
10K
GPU_ROM:YES
MF201
5%18PF
0201NP0-C0G-CERM25V
18PF
0201NP0-C0G-CERM25V5%
1%
201MF1/20W
20K
MF1/20W
33
201
5%GPU_ROM:YES
5%
201
10K
1/20WMF
5%
201
10K
MF1/20W
5%
201MF
1/20W
10K 10K
1/20WMF
201
5%
NO STUFF
201MF
1%10K
NOSTUFF
1/20W
1%
201
1/20WMF
10K
OMIT_TABLE
1%1/20W
10K
201MF
6882
4041
75
5%
201
10K1/20W
MF
MF
10K
1/20W
201
5%
NOSTUFF
74LVC1G08SOT891
40
74
74
2011/20W5% MF
10K
5%NOSTUFF
1/20W MF
0
0201
5% 201MF1/20W
10K
5% 1/20W MFNOSTUFF
0
0201
43
43
OMIT_TABLE
201
24.9K1%1/20WMF
OMIT_TABLE
1%30K
MF1/20W
201
201
45.3K
1/20W1%
MF
5%1/20W
MF
0
0201
1/20WMF
5%
NOSTUFF
0
0201
NOSTUFF
5%
201MF
1/20W
10K
MF
1%
201
45.3K
1/20W
MF1/20W
5%10K
201 201
10K5%
1/20WMF
NOSTUFF
OMIT_TABLE
201
1%
MF1/20W
34.8K
27MHZ-30PPM-18PF-60OHM
CRITICAL
2.50X2.00MM-SM
SOT-563DMN5L06VK-7
SOT-563DMN5L06VK-7
DFN1006H4-3DMN32D2LFB4
SYNC_DATE=07/31/2012SYNC_MASTER=D2_MLB
KEPLER GPIOS,CLK & STRAPS
118S0013 1 R9114 GK107:GTRES, 10KOHM, 0201,1%
1 R9115 GK107:GXRES, 34.8KOHM, 0201, 1%118S0315
118S0315 RES, 34.8KOHM, 0201,1% GK107:GTR91051
118S0013 GK107:GX1 R9104RES, 10KOHM, 0201,1%
RES, 15.0 KOHM, 0201,1%118S0105 FB_4G_HYNIX1 R9111
RES, 4.99 KOHM, 0201,1% FB_2G_ELPIDA_29nmR91111118S0409
RES,MF,24.9KOHM,1,1/20W,0201,1%118S0230 FB_2G_HYNIX_A_DIE1 R9111
118S0280 RES,MF,30.1KOHM,1,1/20W,0201,1% FB_2G_ELPIDA1 R9111
RES, 10KOHM, 0201,1% FB_2G_HYNIX_29nm118S0013 1 R9111
GPU_GPIO_2
GPU_GPIO_3
MAKE_BASE=TRUEGFXIMVP_VID<0>
=PP3V3_GPU_VDD33
GPU_ROM_WP_L
GPU_SMB_DAT GPU_SMB_DAT_R
GPU_ROM_SCLK
GPU_GPIO_0
GPU_GPIO_1
MAKE_BASE=TRUEDP_TBTSNK0_HPD_EGMAKE_BASE=TRUEDP_INT_EG_HPD
MAKE_BASE=TRUEDP_EXTB_CA_DET_EG
DP_EXTA_CA_DET_EGMAKE_BASE=TRUE
DP_TBTSNK1_HPD_EGMAKE_BASE=TRUE
GFXIMVP_VID<3>MAKE_BASE=TRUE
MAKE_BASE=TRUEGFXIMVP_PSI_R_L
MAKE_BASE=TRUEEG_LCD_PWR_EN
MAKE_BASE=TRUETP_GPU_JTAG_TDI
PP3V3_GPU_OVERTEMPMIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3VMIN_LINE_WIDTH=0.2 MM
MAKE_BASE=TRUEGFXIMVP_VID<2>MAKE_BASE=TRUEGFXIMVP_VID<1>
GFXIMVP_VID<4>MAKE_BASE=TRUE
MAKE_BASE=TRUEGFXIMVP_VID<5>
MAKE_BASE=TRUEGPU_ALT_VREF
MAKE_BASE=TRUETP_GPU_JTAG_TDO
MAKE_BASE=TRUEFBVDD_ALTVO
MAKE_BASE=TRUENC_GPU_GPIO_21_RSVD
NO_TEST=TRUE
NC_GPU_GPIO_20_RSVDNO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUEHDMI_EG_HPD
MAKE_BASE=TRUESMC_GFX_THROTTLE_R_LMAKE_BASE=TRUESMC_GFX_OVERTEMP_R_L
SMC_GFX_OVERTEMP_Q
EG_LCD_PWR_EN
SMC_GFX_THROTTLE_R_L
GPU_OSC_27M_XTALIN
GPU_OSC_27M_XTALOUT
GPU_JTAG_TRST_L
GPU_MLS_STRAP0 GPU_MLS_STRAP4
GPU_GPIO_13
=PP3V3_GPU_VDD33
GPU_GPIO_18
GPU_JTAG_TDI
GPU_GPIO_7
=PP3V3_GPU_VDD33
GPU_GPIO_12
=PP3V3_S0_DPMUX_UC
GPU_JTAG_TDO
GPU_GPIO_11
GPU_GPIO_14
GPU_GPIO_10
GPU_GPIO_6
GPU_GPIO_5
GPU_GPIO_4
SMC_GFX_OVERTEMPSMC_GFX_THROTTLE_L
GPU_ROM_SO
GPU_GPIO_17
=PP3V3_S5_SMC
=PP3V3_GPU_VDD33
EG_BKLT_EN
FBVDD_ALTVO
SMC_GFX_OVERTEMP
GPU_GPIO_15
GPU_GPIO_16GPU_JTAG_TMS
FB_CLAMP_TOGGLE_REQ_L
=PP3V3_GPU_VDD33
GPU_ROM_SI
=PP3V3_GPU_VDD33
GPU_GPIO_9
=PP3V3_GPU_VDD33
GPU_SMB_CLK
=PP3V3_GPU_VDD33
GPU_SMB_CLK_R
EG_CLKREQ_IN_L
=PP3V3_GPU_VDD33
GPU_MLS_STRAP1
=PP3V3_GPU_VDD33
PEX_CLKREQ_L_R
=PP3V3_GPU_VDD33
GPU_RESET_L
GPU_ROM_SCLKGPU_MLS_STRAP3
SMC_GFX_OVERTEMP_R_L
GPU_GPIO_8MAKE_BASE=TRUEFB_CLAMP_TOGGLE_REQ_L GPU_GPIO_21
GPU_GPIO_20
GPU_GPIO_19
MAKE_BASE=TRUETP_GPU_JTAG_TCK GPU_JTAG_TCK
MAKE_BASE=TRUEEG_BKLT_EN
SMC_GFX_OVERTEMP_R_L
=PP3V3_GPU_VDD33
=PP3V3_GPU_VDD33
GPU_MLS_STRAP2
GPU_ROM_SI_R
GPU_ROM_CS_L_R
GPU_ROM_CS_L
GPU_ROM_SCLK_R
GPU_ROM_SI
GPU_ROM_SOGPU_ROM_SO_R
=PP3V3_GPU_VDD33
R9198 1 2
R9199 1 2
R91971
2
R91961
2
R9195 1 2
R91231 2
C91211
2
R91011
2
R91021
2
R91071
2
R91081
2
R91101
2
R91001
2
R91111
2
U9101
1
4
7
65
2
9
8
3
R91221
2
R91211
2
R91241 2
R91251 2
R91201
2
C91001
2
C91011
2
R91061
2
R91261 2
R91921
2
R91931
2
R91941
2
R91901
2
R91131
2
R91121
2
R91041
2
R91521
2
R915312
U91022
1
3
6
4
R91541 2
R91811 2
R91551 2
R91801 2
R91141
2
R91051
2
R91091
2
R91561
2
R91571
2
R91911
2
R91031
2
R91511
2
R91581
2
R91151
2
Y9100
2 4
1 3
Q9102
6
21
Q9102
3
54
Q9101 3
1 2
dvt
051-0675
6.0.0
91 OF 119
75 OF 94
5
74
74
77
68 74 75 76 81
74 75
74
74
79
79
79
79
79
77
77
75 79
77
77
77
77
70
71 75
79
75
75
75
74
74
68 74 75 76 81
74
74
74
68 74 75 76 81
74
79 81
74
74
74
74
74
74
74
74
40 41 81
68 74 75 76 81
74
7474
75 79
68 74 75 76 81
68 74 75 76 81
74
68 74 75 76 81
68 74 75 76 81
68 74 75 76 81
68 74 75 76 81
68
68 74 75 76 81
75
74
75 79 74
74
74
74
75 79
75
68 74 75 76 81
68 74 75 76 81
74
7475
7475
68 74 75 76 81
NCNC
OUT
OUT
OUT
OUT
GND
(9 OF 10)
GND
(8 OF 10)
GND_SENSE
NC
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_PLLVDD
NC
NC
NC
NC
NC
NC
NC
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDNC
PEX_IOVDDQ
NC
NC
NC
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
BUFRST*
NC
NC
PEX_PLL_HVDD
VDD_SENSE
GND_OPT
GND_OPT
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
(2 OF 10)
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
GPU SP PLLVDD - =PP1V05_GPU_PEX_IOVDD- =PP1V05_GPU_PEX_PLLVDD
- =PP3V3_GPU_VDD33
Power aliases required by this page:
(NONE)
(NONE)
Page Notes
BOM options provided by this page:
Signal aliases required by this page:
ESR = 0.05OHM
PLACE XW9200 & XW9204 CLOSE TO C9203
PEX IOVDD & PEX IOVDDQ
EDP = 2000 MA
2VX6T-CERM0402
20%20UF
X6S0402
4.7UF
6.3V20%
X6S0402
4.7UF
6.3V20%
X6S0402
4.7UF6.3V20%
X6S0402
4.7UF6.3V20%
X6S
0.1UF10%6.3V
0201
4VCERM-X6S0201
1UF20%
MF
10K
1/20W1%
201
77 93
77 93
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
X6S0402
4.7UF6.3V20%
2V
0402
20%
X6T-CERM
20UF
CRITICAL0603
FERR-220-OHM-2A
5%100PF
25VNP0-CERM0201
5%100PF
25VNP0-CERM0201
5%100PF
25VNP0-CERM0201
5%100PF
25VNP0-CERM0201
X6S0402
4.7UF
6.3V20%
4VCERM-X6S0201
1UF20%
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
X6S
0.1UF10%6.3V
0201
2VX6T-CERM0402
20%20UF
4VCERM-X6S0201
1UF20%
4VCERM-X6S0201
1UF20%
X6S-CERM0402-1
10UF
4V20%
X6S-CERM0402-1
10UF
4V20%
2VX6T-CERM0402
20%20UF
2VX6T-CERM0402
20%20UF
X6S0402
4.7UF
6.3V20%
4VCERM-X6S0201
1UF20%
X6S
0.1UF10%6.3V
0201X6S-CERM0402-1
10UF
4V20%
X6S-CERM0402-1
10UF
4V20%
4VCERM-X6S0201
1UF20%
X6S
0.1UF10%6.3V
0201
SM
SM
SM
SM
PLACE_NEAR=C9203.1:2MM
71 93
SM
PLACE_NEAR=C9203.2:2MM
71 93
5%
MF1/20W
100
201
5%1/20W
100
201MF
5%
0
MF-LF603
1/10W
5%
0
1/16WMF-LF402
0201
0.1UF20%16VX6S-CERM
0201X6S-CERM16V20%0.1UF
X6S-CERM16V20%0.1UF
0201
0.1UF20%16VX6S-CERM0201
BGANV-GK107
OMIT_TABLE
NV-GK107BGA
OMIT_TABLE
NV-GK107BGA
OMIT_TABLE
SYNC_DATE=07/31/2012SYNC_MASTER=D2_MLB
KEPLER PEX PWR/GNDS
GPU_BUFRSTN
GPUVCORE_SENSE_N
GPUVCORE_SENSE_P
=PP1V05_GPU_PEX_PLLVDD
=PP3V3_GPU_VDD33
P1V05_GPU_PEX_IOVDD_SNS_N
P1V05_GPU_PEX_IOVDD_SNS_P
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_PLLVDD
=PPVCORE_GPU
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_IOVDD
VOLTAGE=0V
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM GND_GPU_SP_PLLVDD
PP1V05_GPU_SP_PLLVDDVOLTAGE=1.05VMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
PP3V3_GPU_PEX_PLL_HVDD
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.8 MM
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MM
PP1V05_GPU_PEX_PLLVDD
MIN_NECK_WIDTH=0.2 MMVOLTAGE=0V
MIN_LINE_WIDTH=0.3 MMGND_GPU_PEX_PLLVDD
VOLTAGE=0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MMGND_GPU_PEX_PLL_HVDD
U8400
C7
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
U8400
AG11
AB12
C28
AB14
AB16
AB19
AB2
AB21
AB23
AB28
AB30
AB32
A2
AB5
AB7
AC13
AC15
AC17
AC18
AC20
AC22
AE2
AE28
A33
AE30
AE32
AE33
AE5
AE7
AH10
AH13
AH16
AH19
AH2
AA13
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AA15
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AA17
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AA18
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AA20
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
AA22
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
U8400
L2
C16
W32
L5
P8
D23
D26
H31
T8
V32
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
AG19
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AK27
AL27
AM28
AN28
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AH12
AG26
L4
C92011
2
C92021
2
C92221
2
C92271
2
C92261
2
C92291
2
C92281
2
R92001
2
C92331
2
C92321
2
C92311
2
C92301
2
L9204
1 2
C92191
2
C92201
2
C92211
2
C92181
2
C92231
2
C92241
2
C92251
2
C92141
2
C92081
2
C92001
2
C92131
2
C92071
2
C92121
2
C92061
2
C92041
2
C92031
2
C92051
2
C92161
2
C92171
2
C92151
2
C92091
2
C92101
2
C92111
2
XW9201
1 2
XW9202
1 2
XW9203
1 2
XW9204
1 2
XW9200
1 2
R92101
2
R92111
2
R92031 2
R92021 2
C92341
2
C92351
2
C92361
2
C92371
2
dvt
051-0675
6.0.0
92 OF 119
76 OF 94
74 76 81
68 74 75 81
70 76 81
74 76 81
69 81
70 76 81
70 76 81
74
68
S
D
G
D
S
G
S
D
G
D
S
G
NC
IN
IN
IMON
THRM
ISUM-
ISUM+
ISEN1
VSSP1
LGATE1A
UGATE1
BOOT1
PHASE1
ISEN2
LGATE1B
VSSP2
LGATE2
PHASE2
UGATE2
BOOT2
RTN
VSEN
FB
FB2
COMP
VW
VR_ON
DPRSLPVR
VID6
VID5
VID4
VID1
VID2
VID0
CLK_EN*
VR_TT*
PGOOD
VINVDD
NTC
RBIAS
VCCP
PSI*
VID3
PAD
NCNC
NCNC
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
353S3679
Line Width & DIDTon all DIDT nets
Do not config
Stuff option for GPIO control
R9381 = PSI Control
(GND_GFXIMVP_AGND)
R9382 = VID6 control (old connection)R9382 = DPSLP Control
GPU VCORE VID STRAPS
DEFAULT = 0.9 V
PSI_L = HIGH & DPSLP_EN = HIGH
376S1011
376S1011
25A max per phase
16V
CRITICAL
POLY-TANT
68UF20%
CASE-D2E-SM
20%68UF
POLY-TANT
CRITICAL
16VCASE-D2E-SM
2VCASE-B2-SM
270UF
TANT
CRITICAL
20%270UF2VTANTCASE-B2-SM
CRITICAL
20%2VTANT20%
CASE-B2-SM
270UF
CRITICAL
10K1/20W
MF
1%
201
NOSTUFF
10K1/20W
MF
1%
NOSTUFF
201
10K1/20W
MF
1%
201
NOSTUFF
10K1/20W
MF
1%
NOSTUFF
201
10K1/20W
MF
1%
201
10K1/20W
MF
NOSTUFF
1%
201
10K1/20W
MF
1%
201
10K1/20W
MF
1%
201
10K1/20W
MF
1%
201
10K1/20W
MF
1%
201
10K1/20W
MF
NOSTUFF
1%
201
10K1/20W
MF
NOSTUFF
1%
201
10K1/20W
MF
1%
201
10K1/20W
MF
1%
201
POLY-TANTCASE-D2E-SM
68UF
CRITICAL
16V20%
DIRECTFET-SAIRF6802SDTRPBF
DIRECTFET_S3C
CRITICAL
649135PBF
IRF6802SDTRPBFDIRECTFET-SA
CRITICAL
649135PBFDIRECTFET_S3C
PLACE_NEAR=U9300.41:1mm
SM
5%1/20WMF
100K
201
5%1/20WMF
100K
NOSTUFF
201
66
MF1/20W5%
0201
0
MF1/20W5%
NOSTUFF
0201
075
ISL62882CTQFN
CKPLUS_WAIVE=PdifPr_badTerm
PLACE_NEAR=Q9331.3:1mm
SM
5%
MF-LF1/10W
603
0
16VCERM
0.22UF
402
10%
5%
MF-LF1/10W
603
0
16VCERM402
10%0.22UF
PLACE_NEAR=Q9361.3:1mm
SM
1.001%1/20W
0201MF-LF
1/20WMF
1%
201
1K10K1/20W
MF
1%
201
10K1/20W
MF
1%
201
10K1/20W
MF
1%
201
1/20W1%1.00
MF-LF0201
MF
1K1%
201
1/20W
10K
MF
1%
201
1/20W
NOSTUFF
1/20WMF
1.15K
1%
201
NOSTUFF
X6S
0.1UF6.3V
0201
10%
X6S
0.1UF6.3V
0201
10%
5600PF
201
10VCERM
10%
6.3VX6S-CERM0201
0.22UF
20%
6.3VX6S-CERM
0.22UF
20%
0201
25VX6S-CERM
0402
1UF10%
PLACE_NEAR=U9300.25:1mm
5%1/20WMF
1
201
X6S
0.1UF6.3V
0201
NO_XNET_CONNECTION=TRUE
10%
46
76 93
76 93
1000PF16V
0201
10%
X7R-CERM
NO_XNET_CONNECTION=TRUE
1000PF
X7R-CERM16V
0201
10%
NO_XNET_CONNECTION=TRUE
X7R-CERM16V
0201
10%1000PF
1/20WMF
NOSTUFF
49.91%
201
5600PF
NOSTUFF
201
10VCERM
10%
1/20WMF
3011%
201
NO_XNET_CONNECTION=TRUE
1/20WMF
49.91%
201
16VX7R-CERM
330PF
0201
10%
NP0-C0G-CERM
5%22PF
50V
NOSTUFF
0201
75 77
75 77
75 77
75 77
75 77
75 77
66
1/20WMF
1%
147K
201
1/20WMF
NOSTUFF
1%499
201
NOSTUFF
1/20W5%
MF0201
0
25VX6S-CERM
0402
1UF10%
25VX6S-CERM
0402
1UF10%
MF
0.000751%1W
0612
0.00075
MF0612
1%1W
NO_XNET_CONNECTION=TRUE
10%10V
3300PF
X7R-CERM0201
1/20WMF
8.06K1%
201
TANT
15UF
SM
CRITICAL
16V20%
5%1/20WMF
NOSTUFF
100K
201
5%1/20WMF
100K
201
MF1/20W1%5.11K
201
1%10K1/20W
MF201
NO_XNET_CONNECTION=TRUE
X7R-CERM
560PF50V
0201
10%
CRITICAL
CASE-D2E-SM
20%16V
POLY-TANT
68UF
30.1K
1%1/20WMF201
X6S-CERM
1UF25V
0402
10%
PLACE_NEAR=U9300.16:1mm
0402X7R
0.22UF25V10%
PLACE_NEAR=U9300.17:1mm
1.24K
1%1/20WMF201
0.001UF
X7R-CERM0402
50V10%
0.001UF50V
X7R-CERM0402
10%
PIMB063T-SM
CRITICAL
0.2UH-20%-24A-0.003OHM
0.2UH-20%-24A-0.003OHM
PIMB063T-SM
CRITICAL
201
105%1/20WMF
20%
CRITICAL
330UF-6MOHM2.0VPOLY-TANTD15T-ECGLT-COMBO
SYNC_MASTER=D2_MLB SYNC_DATE=07/31/2012
GFX IMVP VCore RegulatorGFXIMVP_PSI_R_L
=PPVCORE_S0_GFX_REG
=PPVIN_S0_GFXIMVP
GFXIMVP_VW
GATE_NODE=TRUEGFXIMVP_UGATE1
GATE_NODE=TRUEGFXIMVP_UGATE2
GFXIMVP_BOOT1
GFXIMVP_ISEN2
GATE_NODE=TRUEGFXIMVP_LGATE2
SWITCH_NODE=TRUEGFXIMVP_PHASE2
GFXIMVP_COMP
GPUVCORE_SENSE_P
GFXIMVP_FB2
GPUVCORE_SENSE_N
GFXIMVP_ISUMNGFXIMVP_ISUMP
GFXIMVP_VID<1>
=PP3V3_S0_GFX3V3BIAS
GFXIMVP_VR_TT_L
GFXIMVP_VID<4>
GFXIMVP_FB
GFXIMVP_VID<3>
GFXIMVP_VID<6>
GFXIMVP_DPSLP_EN
GFXIMVP_FB_SNS_R
GFXIMVP_VID<4>
GFXIMVP_PSI_L
GFXIMVP_ISNS1_NGFXIMVP_ISNS1_P
GFXIMVP_ISNS2_P GFXIMVP_ISNS2_N
GFXIMVP_ISNS2_N
GFXIMVP_FB_GND_R
GFXIMVP_VR_TT_LGFXIMVP_PSI_L
GFXIMVP_VID<6>GFXIMVP_VID<5>
GFXIMVP_VID<2>
GFXIMVP_VID<0>
GFXIMVP_DPSLP_EN
=PPVIN_S0_GFXIMVP
GFXIMVP_VID<0>
GFXIMVP_VID<5>
GFXIMVP_PSI_L
GFXIMVP_DPSLP_EN
GFXIMVP_ISNS1_N
=PP3V3_S0_GFX3V3BIAS
GFXIMVP_COMP_R
=GPUVCORE_EN
GFXIMVP6_IMON
GPUVCORE_PGOOD
GFXIMVP_ISUMPGFXIMVP_ISUMN
GFXIMVP_VID<6>
GFXIMVP_ISUMN
GFXIMVP_ISUMN_R
GFXIMVP_ISUMP_C
GFXIMVP_ISUMP
GFXIMVP_ISEN1
GFXIMVP_RBIAS
=PP5V_S0_GFXIMVP
GFXIMVP_NTC
GFXIMVP_VID<1>GFXIMVP_VID<2>GFXIMVP_VID<3>
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
PP5V_S0_GFXIMVP_VDD
MIN_NECK_WIDTH=0.2MM
GFXIMVP_PHASE1SWITCH_NODE=TRUE
PPVIN_S0_GFXIMVP_RVOLTAGE=12.8VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MMVOLTAGE=0V
GFXIMVP_VSSP1
MIN_LINE_WIDTH=0.6MM
MIN_LINE_WIDTH=0.6MM
DIDT=TRUEMIN_NECK_WIDTH=0.2MM
GFXIMVP_BOOT2
GATE_NODE=TRUEGFXIMVP_LGATE1
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0V
GFXIMVP_VSSP2MIN_NECK_WIDTH=0.2MM
GFXIMVP_BOOT2_R
MIN_LINE_WIDTH=0.6MM
DIDT=TRUEMIN_NECK_WIDTH=0.2MM
GFXIMVP_BOOT1_RDIDT=TRUE
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
PPVCORE_S0_GFX_PH2VOLTAGE=1.05V
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05VPPVCORE_S0_GFX_PH1
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GND_GFXIMVP_AGNDMIN_LINE_WIDTH=0.6MM
VOLTAGE=0V
C9320 1
2
C9321 1
2
C93621
2
C93631
2
C93611
2
R93431
2
R93441
2
R93461
2
R93451
2
R93481
2
R93491
2
R93471
2
R93521
2
R93531
2
R93561
2
R93551
2
R93541
2
R93511
2
R93501
2
C9322 1
2
Q9330
7 8
2
3
Q9331
1 2 8 7
4
3 5 6
Q9330
5 6
1
4
Q9361
1 2 8 7
4
3 5 6
XW9300
12
R93711
2
R93721
2
R93811 2
R93821 2
U9300
19
30
40
7
39
8
9
18
11
10
14
15
23
24
26
5
1
21
28
2
3
13
41
20
29
25
16
31
32
33
34
35
36
37
17
38
4
12
22
27
6
XW9330
12
R93301
2
C9330 1
2
R93601
2
C9365 1
2
XW9331
12
R93641
2
R93631
2
R93611
2
R93621
2
R93311
2
R93341
2
R93331
2
R93321
2
R93111 2
C9312 1
2C93111
2
C93101
2
C93661 2
C93311 2
C9302 1
2
R93011 2
C93131
2
C93141
2
C9315 1
2
C93191
2
R93171
2
C93411
2
R93151
2
R93161
2
C93171
2
C9318 1
2
R93401 2
R93701
2
R93831 2
C9323 1
2
C9324 1
2
R9399
1 23 4
R9398
1234
C93401
2
R93131
2
C9325 1
2
R93741
2
R93731
2
R93141
2
R93121
2
C9316 1
2
C9326 1
2
R93181 2
C9301 1
2
C93001
2
R93101 2
C9328 1
2
C9327 1
2
L9330
1 2
L9360
1 2
R93001
2
C93641
23
dvt
051-0675
6.0.0
93 OF 119
77 OF 94
81
77 81
77
77
75 77
77 81
77
75 77
75 77
77
77
77
77 93 93
93 77 93
77 93
77
77
77
75 77
75 77
75 77
77
77 81
77
77
77 93
77 81
77
77
77
77
77
81
IN
IN
BI
BIIN
IN
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IN
TP
TP
TP
TP
TP
TP
IN
IN
IN
BIOUT
IN
BI
IN
OUT
OUT
GND
GND
GND
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Board-to-Board (Flex) Connector
Note. Pin1 in symbol is different to 516S0853 in J15.
516S1106
Wire-to-Board (Micro-coax) Connector
518S0829
74 94
74 94
13 83 87
13 83 87 13 87
13 87
13 83 87
13 83 87
CRITICAL
20525-130E-01
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
F-RT-SM
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
74 94
74 94
74 94
74 94
20 83 88
20 83 88
20 83 88
20 83 88
74 94
74 94
NO_XNET_CONNECTION=TRUE
BEAD-PROBESM
BEAD-PROBESM
NO_XNET_CONNECTION=TRUE
SMNO_XNET_CONNECTION=TRUE
BEAD-PROBE
SMNO_XNET_CONNECTION=TRUE
BEAD-PROBE
BEAD-PROBESM
NO_XNET_CONNECTION=TRUE
SM
BEAD-PROBE
NO_XNET_CONNECTION=TRUE
0.1UF
GND_VOID=TRUE
10% X5R-CERM16V 0201
0.1UF
GND_VOID=TRUE
020116V X5R-CERM10%
50 64 65 79 83
12 21 33 37 40 65 83
74
7420 83
13 18 83
43
43
20 79
18 83
RIO_PWR:1V5
MF-LF
0
5%1/16W
402
5%
0
402
RIO_PWR:1V35
1/16WMF-LF
0.1uF
402
10V20%
CERM
0.1uF10VCERM20%
402
20590-032E-25
CRITICAL
F-ST-SM
RIO ConnectorsSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
HDMI_EG_DATA_C_P<0>HDMI_EG_DATA_C_N<0>
HDMI_EG_DATA_C_N<1>
HDMI_EG_DATA_C_P<2>
USB3_EXTB_D2R_N
HDMI_EG_DATA_C_P<1>
HDMI_EG_DATA_C_N<2>
HDMI_EG_CLK_C_P
USB3_EXTB_R2D_PUSB3_EXTB_R2D_N
HDMI_EG_CLK_C_N
USB3_SD_R2D_C_P
=PP1V5_S0_RIO
=PP1V35_S0_RIO
USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P
USB3_SD_R2D_C_N
USB_EXTB_NUSB_EXTB_P
USB3_EXTB_D2R_P
PM_SLP_S3_BUF_LPM_SLP_S4_LHDMI_EG_DDC_CLKHDMI_EG_DDC_DATA
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5V
PP1V5R1V35_S0_RIO
=PP5V_S4_RIO
USB_EXTB_OC_L
RIO_SDCONN_STATE_CHANGE_L
=PP3V3_S3_RIO
=PP3V3_S4_RIOI2C_HDMIRDRV_SCLI2C_HDMIRDRV_SDA
SD_PWR_EN
HDMI_HPD
USB3_SD_D2R_NUSB3_SD_D2R_P
J9500
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
5
6
7
8
9
BP95011
BP95021
BP95051
BP95061
BP95031
BP95041
C9501 1 2
C9502 1 2
R953512
R953412
C9510 1
2
C95111
2
J9510
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
4
56
78
9
dvt
051-0675
6.0.0
95 OF 119
78 OF 94
83 87
83 87
81
81
83
81
81
81
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
BI
OUT
OUT
OUT
P45/PWMU3B/TCMCKI2/TCMMCI2
P44/TMO1/PWMU2B/TCMCYI2
P43/TMI1/TCMCKI1/TCMMCI1
P41/TMO0/TCMCKI0/TCMMCI0
P52/SCL0
P51/FRXD
P50/FTXD
P47/PWMU5B
P46/PWMU4B
P42/TCMCYI1
P40/TMI0/TCMCYI0
P37/SERIRQ
P36/LCLK
P35/LRESET*
P34/LFRAM*
P33/LAD3
P32/LAD2
P31/LAD1
P30/LAD0
P26
P27
P25
P22
P21
P23
P24
P20
P10/WUE0*
P11/WUE1*
P12/WUE2*
P13/WUE3*
P14/WUE4*
P15/WUE5*
P16/WUE6*
P17/WUE7*
P96/EXCL
P95/IRQ14*
P94/IRQ13*
P93/IRQ12*
P92/IRQ0*
P83/LPCPD*
P82/CLKRUN*
P90/IRQ2*
P91/IRQ1*
P85/IRQ4*/RXD1
P84/IRQ3*/TXD1
P86/IRQ5*/SCK1
P97/SDA0/IRQ15*
P77/AN7
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P80/PME*
P81/GA20
P70/AN0
P66/KIN6*
P65/KIN5*
P64/KIN4*
P63/KIN3*
P62/KIN2*
P61/KIN1*
P60/KIN0*
P67/IRQ7*/KIN7*
SYM 1 OF 3
IN
IN
IN
IN
IN
IN
NC
NC
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
PC2/TIOCC0/TCLKA/WUE10*
PC3/TIOCD0/TCLKB/WUE11*
PC5/TIOCB1/TCLKC/WUE13*
PC7/TIOCB2/TCLKD/WUE15*
PD6/SSCK
PD7/SCS
PD5/SSI
PD4/SSO
PD3/AN11
PD2/AN10
PC4/TIOCA1/WUE12*
PC6/TIOCA2/WUE14*
PD1/AN9
PD0/AN8
PB6/CTS*/FSICK
PB7/RTS*/FSISS
PC0/TIOCA0/WUE8*
PB5/DTR*/FSIDI
PB4/DSR*/FSIDO
PB3/DCD*/PWMU1B
PC1/TIOCB0/WUE9*
PB1/LSCI
PB0/LSMI*
PA5/KIN13*/PS2BD
PA0/KIN8*/SDA1
PA1/KIN9*/SCL1
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
PA4/KIN12*/PS2BC
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PEVREF
PECI
PH1/EXIRQ7*
PH0/IRQ6*
PG7/EXIRQ15*/SCLD
PG6/EXIRQ14*/SDAD
PG5/EXIRQ13*/SCLC
PG4/EXIRQ12*/SDAC
PF3/IRQ11*/TMOX
PF4/PWMU2A/EXDSR
PF5/PWMU3A/EXDTR
PF6/PWMU4A/EXCTS
PF7/PWMU5A/EXRTS
PG2/EXIRQ10*/SDAB
PG3/EXIRQ11*/SCLB
PF2/IRQ10*/TMOY
PE4/ETMS
PE1/ETCK
PE2/ETDI
PE3/ETDO
PE0/EXEXCL
PE5/ETRST*
PF0/IRQ8*/PWMU0A
PF1/IRQ9*/PWMU1A
PG1/EXIRQ9*/TMIY/SCLA
PG0/EXIRQ8*/TMIX/SDAA
PB2/RI*/PWMU0B
SYM 2 OF 3
IN
IN
OUT
IN
IN
IN
IN
IN
NC
NC
IN
IN
IN
IN
IN
BI
OUT
IN
IN
OUT
OUT
DIN1_1-
DIN1_1+
VDD
VDD
GND
GND
GND
GND
DIN1_0-
DIN1_3-
DOUT_0+
DOUT_1-
DAUX1-
DIN2_0+
DIN2_0-
DAUX2+
DIN2_3-
DIN2_3+
DIN2_2-
DIN2_2+
HPDIN
AUX+
DIN2_1-
DDC_AUX_SEL
DIN2_1+DOUT_3-
DOUT_3+
DOUT_2-
DOUT_2+
DDC_DAT1
DDC_CLK1
DOUT_1+
DIN1_2+
GPU_SEL
HPD_2
DDC_CLK2
DAUX2-
DDC_DAT2
DIN1_3+
DAUX1+
DIN1_2-
HPD_1
XSD*
DIN1_0+
GND
GND
AUX-
DOUT_0-
OUT
G
D S
IN
G
D S
SYM_VER_2
G S
D
IN
GND
VCC
NCNC
YA
NC NC
VSS
VSS
VSS
AVSS
EXTAL
VBAT
AVREF
VCL
AVCC
VCC
VCC
VCC
RES*
XTAL
VSS
VSS
MD2
MD1
NMI
NC
MDCKNSYM 3 OF 3
BI
BI
NCNC
NCNC
BI
BI
IN
IN
IN
IN
OUTIN
IN
IN
IN
BI
BI
OUT
IN
IN
IN
BI
BI
BI
BI
OUT
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DPMUX UC PULL-UPS
PU on PCH Page
DP 2:1 ANALOG MUX
DPMUX UC DEBUG HEADER
PU OFFPAGE
CONNECT I2C TO LCD BKLT IC
DPMUX UC PULL-DOWNS
CA_DET ISOLATION
67 86 94
1/20W MF 2015%
10K NOSTUFF
67 86 94
MF 2015% 1/20W
10K
66 79
67 86 94
66 79
66 79
66 79
66 79
10K5% 2011/20W MF
10KMF1/20W 2015%
5% 201MF
10K1/20W
1/20W MF 2015%
10K
MF5% 1/20W 201
10K
79 82
67 86 94
79 82
MF 2015% 1/20W
10K
10K5% 2011/20W MF
62 67 83
67 86 94
79 82
79 82
80
80
80
80
82
82
43
43
14 82
62 79
OMIT_TABLE
TLP-145VR4F2113NLG
10KMF1/20W 2015%
5%
10K2011/20W MF
75
75
75
66
20 79
82
NOSTUFF5% MF 2011/20W
10K
5%
10KMF1/20W 201
1/20W 201MF
10K5%
NOSTUFFMF1/20W 2015%
10K
NOSTUFF5% 2011/20W MF
10K
1/20W MF 2015%
10K
5% 2011/20W MF
10K
10KMF 2015% 1/20W
82
67
DPMUX_DEBUG
M-RT-SM1909782
0
5%1/16WMF-LF402
0
1/16WMF-LF402
5%
1/20W
10K201MF5%
201MF1/20W5%
10K
10K201MF1/20W5%
201
10KMF5% 1/20W
10KMF1/20W 2015%
67 79 83
62 79 83
75
75
75 79
20 79
1/16W5%
0
MF-LF
NOSTUFF
402
75 79
75 79
28
28
80
R4F2113NLG
OMIT_TABLE
TLP-145V
100K201MF1/20W5%
NOSTUFF5% MF 2011/20W
100K
2015%
100KMF1/20W
74 94
201
1/20W5%
10K
MF
DPMUX:HOCO
0201NPO
DPMUX:XTAL
15PF25V5%
0201NPO25V5%
15PF
DPMUX:XTAL
DPMUX:XTAL
201
1/20W5%
0
MF
100K201MF1/20W5%
1/20W
100K201MF5%
74 94
201MF1/20W
100K5%
201MF1/20W
100K5%
1/20W
100KMF 2015%
100KMF1/20W5% 201
75
1%
100K
201MF1/20W
74 94
28 31
1/20W
201MF
5%
100K
74 94
100K
201MF
1/20W5%
28 32
74 94
66
66
66
66
74 94
43
43
28
74 94
79 82
79 82
CBTL06142EEETFBGA
CRITICAL
70
20MHZ-30PPM-12PF-50OHM
DPMUX:XTAL
2.50X2.00MM-SM
1/20W
100KMF 2015%
100KMF1/20W5% 201
DMN5L06VK-7SOT-563
74 94
SOT-563DMN5L06VK-7
DFN1006H4-3DMN32D2LFB4
20 78
74LVC1G07GFSOT891
1/20W
201
5%
MF
47K
470K1/20W
201
5%
MF
0.1UF
X5R-CERM0201
16V10%
TLP-145V
OMIT_TABLE
R4F2113NLG
67 86 94
67 86 94
74 94
74 94
82 94
82 94
82 94
82 94
67 86 94 82 94
82 94
82 94
82 94
82 94
82 94
10VX7R-CERM0402
0.1UF20%
67 86 94
10VX7R-CERM0402
0.1UF20%
20
20 79
13 40 49 83 88
13 40 49 83 88
13 40 49 83 88
13 40 49 83 88
13 40 49 83 88
67 86 94
10VX7R-CERM
0402
0.1UF20%
10VX7R-CERM
0402
0.1UF20%
10VX7R-CERM
0402
0.1UF20%
10VX7R-CERM
0402
0.1UF20%
0402X6S-CERM
6.3V
0.47UF10%
0.1UF
X7R-CERM10V
0402
20%
eDP Mux
SYNC_MASTER=D2_MLB SYNC_DATE=07/31/2012
=PP3V3_S5_GMUX_SLP_S3_L
TBT_A_CONFIG1_BUF
MAKE_BASE=TRUE
GMUX_SLP_S3_BUF_L
EG_RAIL5_EN
LCD_PWR_EN
=I2C_DPMUX_A_SCL
DPMUX_UC_UNUSED
HDMI_HPD
IG_LCD_PWR_EN
IG_BKLT_EN
DPMUX_LRESET_L
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
=PP3V3_S0_DPMUX_UC
GPU_PGOOD4
GPU_PGOOD2
GPU_PGOOD1
DPMUX_UC_RESET_L
DPMUX_UC_TDO
DPMUX_UC_MD1
MIN_LINE_WIDTH=0.3MM
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MM
PP3V3_S3_DPMUX_UC_R
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
VOLTAGE=3.3V
PP3V3_S0_DPMUX_UC_R
DPMUX_UC_UNUSED
FB_CLAMP_TOGGLE_REQ_L
DP_A_CA_DET_BUF DP_B_CA_DET_BUFTBT_B_CONFIG1_BUF
=PP3V3_S0_DPMUX_UC
DP_TBTPB_HPD_BUF
DP_TBTPA_HPD_BUF
DP_INT_EG_HPD
DP_INT_IG_HPD
DP_TBTSNK1_HPD_EG
DP_TBTSNK1_HPD_IG
DP_TBTSNK0_HPD_IG
DP_TBTSNK0_HPD_EG
EG_RESET_L
DPMUX_UC_UNUSED
DPMUX_UC_PEVREF
DPMUX_UC_PECI
DPMUX_UC_MD2
DPMUX_UC_NMI
DPMUX_UC_MD1
LCD_BKLT_PWM
LCD_BKLT_EN
EG_RAIL4_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL1_EN
DPMUX_UC_RESET_L
DPMUX_UC_MD1
DPMUX_UC_NMI
TP_DPMUX_UC_P10
TP_DPMUX_UC_P11
DPMUX_UC_EXTAL
TP_DPMUX_UC_P96
DPMUX_UC_XTAL
DPMUX_UC_MD2
=PP3V3_S0_DPMUX_UC
DPMUX_LRESET_L
DPMUX_UC_TCK
DP_A_CA_DET_BUF
TBT_DDC_XBAR_EN_L
=I2C_DPMUX_UC_SCL
DPMUX_UC_UNUSED
LCD_BKLT_PWM
TP_LCD_MUX_REQ
LCD_MUX_EN
GPU_PGOOD3
DPMUX_UC_UNUSED
EG_RAIL4_EN
TP_DPMUX_UC_P42
DPMUX_LRESET_L
FB_CLAMP
TP_DPMUX_UC_P37
LPC_FRAME_L
TP_DPMUX_UC_P41
LCD_MUX_SEL
TP_DPMUX_UC_P46
TP_DPMUX_UC_P47
DPMUX_UC_TX
DPMUX_UC_RX
TP_DPMUX_UC_P52
TP_LCD_IRQ
DPMUX_UC_BOOT_RX
DP_TBTPB_HPD_BUF
DPMUX_UC_UNUSED
LPC_AD<2>
DPMUX_UC_BOOT_TX
DPMUX_UC_CLK32K
DPMUX_UC_PECI
DPMUX_UC_PEVREF
TP_DPMUX_UC_P67
=I2C_DPMUX_UC_SDA
TP_DPA_EG_HPD
DPMUX_UC_IRQ
DPMUX_UC_UNUSED
EG_CLKREQ_IN_L
PM_ALL_GPU_PGOOD
EG_BKLT_EN
EG_LCD_PWR_ENDPMUX_UC_UNUSED
TP_DPB_EG_HPD
EG_RAIL5_EN
LPC_AD<0>
DPMUX_UC_CLK32K
DP_DDC_MUX_CROSSBAR_L
TP_DPB_IG_HPD
DP_INT_IG_HPD
TP_DPMUX_UC_P13
LPC_AD<3>
LPC_AD<1>
DPMUX_UC_UNUSED
DPMUX_UC_RESET_L
DPMUX_UC_TX
EG_RAIL1_EN
TP_DPMUX_UC_P45
EG_CLKREQ_OUT_L
TP_DPMUX_UC_P14
PP3V3_S0_DPMUX_UC_R
DP_EXTA_MUX_EN
TP_DPMUX_UC_P63
TP_DPMUX_UC_P62
DP_EXTB_MUX_EN
DP_EXTA_MUX_SEL_EG
DPMUX_UC_RX
DPMUX_UC_MD1
EG_RAIL3_EN
LCD_BKLT_EN
TP_DPMUX_UC_P17
TP_DPMUX_UC_P16
EG_RESET_L DPMUX_UC_UNUSED
TP_DPMUX_UC_P40
TP_HDMI_IG_HPD
=I2C_DPMUX_A_SDA
DP_EXTB_MUX_SEL_EG
DPMUX_UC_UNUSED
TP_DPA_IG_HPD
DPMUX_UC_TRST_L
DPMUX_UC_TMS
TP_DP_EXTA_CA_DET_IG
EG_RAIL2_EN
TP_DPMUX_UC_P12
DP_INT_EG_HPD
HDMI_EG_HPD
DP_EXTB_CA_DET_EG
LCD_PWR_EN
DP_EXTA_CA_DET_EG
DP_TBTSNK1_HPD_EG
DP_TBTSNK0_HPD_EG
TP_DPMUX_UC_PC3
TP_DPMUX_UC_PC2
TP_DP_EXTB_CA_DET_IG
DP_TBTSNK0_HPD_IG
DP_TBTSNK1_HPD_IG
=PP3V3_S3_DPMUX_UC
DPMUX_UC_VCL
LCD_FSS
DP_INT_ML_C_N<0>
DP_INT_AUXCH_C_N
DP_INT_IG_ML_P<0>
LCD_MUX_EN
DP_INT_IG_ML_N<2>
DP_INT_IG_AUX_P
DP_INT_IG_ML_P<3>
DP_INT_EG_AUX_N
LCD_MUX_SEL
DP_INT_IG_ML_P<2>
DP_INT_ML_C_P<1>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<3>
DP_INT_ML_C_N<3>DP_INT_EG_ML_P<1>
DP_INT_EG_ML_N<1>
DP_INT_AUXCH_C_P
DPMUX_HPD_PD
DP_INT_EG_ML_P<2>
DP_INT_EG_ML_N<2>
DP_INT_EG_ML_P<3>
DP_INT_EG_ML_N<3>
DP_INT_EG_AUX_P
DP_INT_EG_ML_N<0>
DP_INT_EG_ML_P<0>
DP_INT_IG_AUX_N
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<0>
DP_INT_IG_ML_N<3>
DP_INT_IG_ML_N<0>
=PP3V3_S0_DPMUX
DP_INT_IG_ML_P<1>
DP_INT_IG_ML_N<1>
DPMUX_UC_TDI
DPMUX_UC_TDO
DPMUX_UC_TRST_L
DPMUX_UC_TMS
LPC_CLK33M_DPMUX_UC
DPMUX_UC_NMI
DPMUX_UC_MD2
DPMUX_UC_RESET_L
DPMUX_UC_XTAL_R
DPMUX_UC_MD1
DPMUX_UC_MD2
EG_CLKREQ_OUT_L
=PP3V3_S0_DPMUX_UC
LCD_HPD
PM_SLP_S3_BUF_L
DP_B_CA_DET_BUF
DP_TBTSNK1_HPD
DP_TBTSNK0_HPD
DP_TBTPA_HPD_BUF
TP_DPMUX_UC_P83
TP_DPMUX_UC_P82
TP_DPMUX_UC_P81
TP_DPMUX_UC_P80
DPMUX_UC_UNUSED
=PP3V3_S0_DPMUX_UC
DPMUX_UC_UNUSED
TP_DPMUX_UC_P15
DPMUX_UC_UNUSED
TP_DPMUX_UC_P66
DPMUX_UC_TDI
DPMUX_UC_TCK
TP_DPMUX_UC_P63
U9600B12
A13
A12
B13
D11
C13
C12
D10
D13
E11
D12
F11
E13
E12
F13
E10
A9
D9
C8
B7
A8
D8
D7
D6
D4
A5
B4
A1
C2
B2
C1
C3
G2
F3
E4
L13
K12
K11
J12
K13
J10
J11
H12
N10
M11
L10
N11
N12
M13
N13
L12
A7
B6
C7
D5
A6
B5
C6
J4
G3
H2
G1
H4
G4
F4
F1
U9600N3
N1
M3
M2
N2
L1
K3
L2
B8
C9
B9
A10
C10
B10
C11
A11
G11
G13
F12
H13
G10
G12
H11
J13
M10
N9
K10
L8
M9
N8
K9
L7
K1
J3
K2
J1
K4
H3
A4
B3
K5
N5
M6
L5
M5
N4
L4
M4
M8
N7
K8
K7
K6
N6
M7
L6
E2
F2
U9600
M12
L11
L9
A2
D1
H1
C4
E3
D3
J2
B1
M1
H10
E1
D2
L3
F10
C5
B11
A3
C96501
2
C96511
2
C9600 1
2
C9601 1
2
C9602 1
2
C9603 1
2
C9605 1
2
C96041
2
R9620 1 2
R9610 1 2
R9621 1 2
R9622 1 2
R9623 1 2
R9624 1 2
R9625 1 2
R9626 1 2
R9627 1 2
R9628 1 2
R9611 1 2
R9629 1 2
R9612 1 2
R9613 1 2
R9631 1 2
R9630 1 2
R9632 1 2
R9633 1 2
R9614 1 2
J9600
7
8
1
2
3
4
5
6
R96001 2
R96011 2
R9615 1 2
R9616 1 2
R9617 1 2
R9618 1 2
R9634 1 2
R96021 2
R9635 1 2
R9619 1 2
R9640 1 2
R96501
2
C96411
2
C9640 1
2
R96511 2
R9636 1 2
R9637 1 2
R9638 1 2
R9639 1 2
R9645 1 2
R9646 1 2
R9662
1 2
R96601 2
R96611 2
U9650
H1
H2
J9
H9
J6
H6
C2
H8
H5
J8
J5
A4
B4
A5
B5
A6
B6
A9
A8
B9
B8
D9
D8
E9
E8
F9
F8
B1
B2
D1
D2
E1
E2
F1
F2
B3
C8
G8
H4
H7
G2
A1
J2
H3
J1
A2
J4
B7
Y9600
2 4
1 3
R9647 1 2
R9648 1 2
Q9610
6
21
Q9610
3
54
Q9690 3
1 2
U9670
2
3
1 5
6
4
R96701
2
R96711
2
C9670 1
2
dvt
051-0675
6.0.0
96 OF 119
79 OF 94
E5
81
66 79
67 79 83
79
79
79
75 79 81
79
79
79
79
79
75
79 79
75 79 81
79
79
75 79
20 79
75 79
79 82
79 82
75 79
79 82
79
79
79
79
79
79
62 79
62 79 83
66 79
66 79
66 79
66 79
79
79
79
79
75 79 81
20 79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79 82
79
79
79 82
79
79
79
79
79
81
79
79
80 81
79
79
79
79
79
79
79
79
79
79 82
75 79 81
50 64 65 78 83
79
79
79
75 79 81
79
79
79
79
79
SBI
INB+VCC
OUTA1+
OUTA1-
OUTA0+
OUTA0-
SAO
OUTB1+
OUTB1-
OUTB0-
OUTB0+
SBO
ENA
INA-
INA+
SAI
INB-
GND
THRM
ENB
PAD
BI
IN
SBI
INB+
VCC
OUTA1+
OUTA1-
OUTA0+
OUTA0-
SAO
OUTB1+
OUTB1-
OUTB0-
OUTB0+
SBO
ENA
INA-
INA+
SAI
INB-
GND
THRM
ENB
PAD
BI
IN
IN
IN
IN
BI
BI
IN
BI
IN
BI
IN
IN
IN
OUT
BI
BI
OUT
IN
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
0 1 1 OUTB1 OUTA1 1 0 0 OUTA0 OUTB0 1 0 1 OUTA0 OUTB1 1 1 0 OUTA1 OUTB0 1 1 1 OUTA1 OUTB1
0 1 0 OUTB0 OUTA1
DP A & DP B DDC MUXDP A & DP B AUX MUX
SAI/SBI SAO SBO | INA INBMUX TRUTH TABLE
0 0 0 OUTB0 OUTA0 0 0 1 OUTB1 OUTA0
TS3DS10224QFN
28 86 94
79 80
QFNTS3DS10224
28 86 94
79 80
79 80
82
74
74
82
74
74
82
82
79 80
79 80
79
5%1/16WMF-LF
10K
402
MF1/20W1%470K
201
1/20W1%470K
MF201201
MF
1%470K1/20W
201MF1/20W1%470K
31
31
32
32
470K
MF
1%1/20W
201
470K1%
MF1/20W
201
470K1%1/20WMF201
470K1%
MF201
1/20W
79 80
74 94
74 94
82 86
82 86
74 94
74 94
79 80
10VX7R-CERM0402
0.1UF20%
82 86
82 86
28 86 94
28 86 94
79 80
10VX7R-CERM0402
0.1UF20%
eDP Muxed Graphics Support
SYNC_DATE=08/14/2012SYNC_MASTER=CLEAN_D2
DP_DDC_MUX_CROSSBAR_L
=PP3V3_S0_DPMUX
DP_EXTB_MUX_EN
DP_TBTPB_DDC_CLK
DP_TBTPA_DDC_DATA
DP_TBTPA_DDC_CLK
DPA_IG_DDC_CLK
DPB_IG_DDC_DATA
DPA_EG_DDC_DATA
DPB_IG_DDC_CLK
DPA_IG_DDC_DATA
DP_EXTA_MUX_EN
DPA_EG_DDC_CLK
DP_TBTPB_DDC_DATA
DP_EXTB_MUX_EN
DP_EXTA_MUX_SEL_EG
DPB_EG_DDC_DATA
DP_EXTB_MUX_SEL_EG
DPB_EG_DDC_CLK
DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
DPA_IG_AUX_CH_P
DPA_IG_AUX_CH_N
DP_EXTA_MUX_SEL_EG
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N
DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DP_EXTB_MUX_SEL_EG
DP_EXTA_MUX_EN
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_P
U970016
10
5
2
1
4
3
17
18
19
20
9
8
7
6
14 15
12 11
21
13
C97001
2
C97101
2
U971016
10
5
2
1
4
3
17
18
19
20
9
8
7
6
14 15
12 11
21
13R97101
2
R97401
2
R97501
2
R97201
2
R97301
2
R97531
2
R97541
2
R97521
2
R97511
2
dvt
051-0675
6.0.0
97 OF 119
80 OF 94
79 81
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
G3H/5V Rails
"GPU" Rails
1.5V/1.35V/1.05V/VCORE/BKLT Rails3.3V Rails TBT RAILS
Power AliasesSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
=PP3V3_S5_FAN_CTL
=PPVIN_S5_P3V3
=PP3V3_S5_VMON=PP3V3_S5_WLAN=PP3V3_S5_XDPJTAGISOL
PP3V3_S4MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3VMIN_NECK_WIDTH=0.1 MM MAKE_BASE=TRUE
=PP3V3_S4_SMC
=PP3V3_S4_ISNS
=PP3V3_S4_FAN_CTL=PP3V3_S4_WLAN
=PP3V3_S4_FET
=PP3V3_S4_TPAD=PP3V3_S4_TBT_R
=PP3V3_S4_RIO=PP3V3_S4_BT
PP3V3_S5VOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
=PP3V3_S5_GMUX_SLP_S3_L
=PP3V3_S0_PWRCTL=PP3V3_S0_DPMUX_UC=PP3V3_S0_DPMUXI2C=PP3V3_S0_DPMUX
=PP3V3_S0_X29THMSNS=PP3V3_S0_VMON=PP3V3_S0_SSD_AUX=PP3V3_S0_SMBUS_SMC_1_S0=PP3V3_S0_SMBUS_SMC_0_S0=PP3V3_S0_SMBUS_PCH=PP3V3_S0_SB_PM=PP3V3_S0_RSTBUF=PP3V3_S0_PCH_VCC_FUSE=PP3V3_S0_PCH_VCCCLK3_3=PP3V3_S0_PCH_VCC3_3_USB
=PP3V3_S0_PCH_VCC3_3_HVCMOS=PP3V3_S0_PCH_VCC3_3_THRM
=PP3V3_S0_PCH_VCC3_3_GPIO=PP3V3_S0_PCH_GPIO
=PP3V3_S0_OOB1_PWRDN=PP3V3_S0_PCH
=PP3V3_S0_LCD=PP3V3_S0_ISNS=PP3V3_S0_HS_ISNS=PP3V3_S0_FAN_RT=PP3V3_S0_GPUTHMSNS=PP3V3_S0_FAN_LT=PP3V3_S0_CPUVRISNS
=PP3V3_S0_FET
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_AUDIO_DIG=PP3V3_S0_CAMERA_R
=PP3V3_S0_AUDIO
=PP3V3_S3_VREFMRGN=PP3V3_S3_DPMUX_UC
=PP3V3_S3_SMBUS_SMC_2_S3
=PP3V3_S3_FET
=PP3V3_S3_SDBUF
=PP3V3_S3_MEMRESET=PP3V3_S3_RIO
=PP3V3_S3_ISNS=PP3V3_S3_CAMERA_R=PP3V3_S3RS4_PCH_GPIO
=PP3V3_SUS_ROM
=PP3V3_SUS_FET
=PP3V3_SUS_PCH_VCC_SPI=PP3V3_SUS_PCH_VCCSUS_USB3
=PP3V3_SUS_PCH_VCCSUS_RTC=PP3V3_SUS_PCH_VCCSUS_USB
=PP3V3_SUS_PCH_VCCSUS_GPIO=PP3V3_SUS_PCH_GPIO=PP3V3_SUS_P1V05SUSLDO=PP3V3_SUS_CNTRL
PP3V3_S0VOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.075 MM
MIN_LINE_WIDTH=0.4 MM
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3VMAKE_BASE=TRUE
PP3V3_S3
PP3V3_SUSVOLTAGE=3.3VMIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM
=PPVIN_S5_HS_COMPUTING_ISNS
=PP3V3_GPU_P3V3GPUFET=PP3V3_GPU_MISC_P3V3GPUMISCFET
=PP3V3_S5_SYSCLK=PP3V3_S5_PWRCTL=PP3V3_S5_PCH_VCCDSW=PP3V3_S5_PCH_GPIO=PP3V3_S5_P3V3SUSFET=PP3V3_S5_P3V3S0SW_SSD=PP3V3_S5_P1V5S0=PP3V3_S5_DBGLED=PP3V3_S5_CPU_VCCDDR=PP3V3_S5_1V5PGOOD=PP3V3_S4_TBTBPWRSW=PP3V3_S4_TBTAPWRSW=PP3V3_S4_P3V3S4FET=PP3V3_S3_P3V3S3FET
=PP3V3_S4_SYSCLK=PP3V3_S0_P3V3S0FET
=PP3V3_S5_REG
=PP5V_S0_FAN_LT=PP5V_S0_CPUVR
MAKE_BASE=TRUEMIN_LINE_WIDTH=0.4 MMPP5V_S0MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
=PP5V_S0_AUDIO_XW
=PP5V_S0GPU_P1V0P1V35_GPU
=PP5V_S0_XDPJTAGISOL
=PP5V_S0_ALSCAM=PP5V_S0_VMON
=PP5V_S0_LPCPLUS
=PP5V_S3_MEMRESET
=PP5V_S3_LTUSB
=PPVIN_S0_GFXIMVP
=PPVIN_S5_HS_GPU_ISNS_R
=PPVIN_S3_DDRREG
=PPVIN_S5_HS_OTHER5V_ISNS
=PPDCIN_S5_CHGR
PPDCIN_G3H_ISOLMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUEVOLTAGE=20V
=PPDCIN_S5_CHGR_ISOL=PPDCIN_S5_VSENSE
=PP3V42_G3H_REG
=PP5V_S4_RIO
=PP5V_S0_PCH
=PP5V_S0_GFXIMVP
=PP5V_S4_REG
=PP3V3_S5_LPCPLUS
PP1V05_S0VOLTAGE=1.05VMIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM
=PP1V05_S0_REG
=PP20V_DCIN_ISOL
=PP5V_S0_FET
=PP3V42_G3H_TPAD
=PP3V42_G3H_PWRCTL
=PP1V05_S0GPU_REG
=PPVCORE_GPU_REGMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM
PPVCORE_GPUMIN_LINE_WIDTH=0.6 MMVOLTAGE=1.0V
MAKE_BASE=TRUEVOLTAGE=1.05V
PP1V0_S0GPU_ISNSMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
=PPVCORE_S0_GFX_REG
=PPVCORE_GPU
=PP1V05_GPU_IFPCD_IOVDD=PP1V05_GPU_IFPEF_IOVDD
=PP1V05_GPU_PEX_PLLVDD=PP1V05_GPU_PEX_IOVDD
=PP5V_S0_LCD
=PP1V5R1V35_GPU_REG PP1V5R1V35_S0GPU
VOLTAGE=1.5VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_FB=PP1V35_GPU_S0_FB
PP5V_S3MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_DDRREG
=PP5V_S0_BKLTCTRL
VOLTAGE=3.3VMAKE_BASE=TRUE
PP3V3_S0SW_SSD_RMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
=PP3V3_S0GPU_MISC_FET
=PP3V3_S0GPU_FET
PP3V3_S0GPU_MISC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.10MM
MAKE_BASE=TRUE
PP3V3_S0GPU
VOLTAGE=3.3VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.10MM
=PP3V3_GPU_IFPX_PLLVDD=PP3V3_S0_GFX3V3BIAS=PP3V3_GPU_VDD33
=PP3V3_GPU_MISC
=PPVTT_S3_DDR_BUF
MAKE_BASE=TRUEVOLTAGE=3.3V
PP3V3_TBTLCMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.15 MM
=PP5V_S5_TPAD
MIN_LINE_WIDTH=0.5 MMPP5V_S5MIN_NECK_WIDTH=0.1 MM
VOLTAGE=5VMAKE_BASE=TRUE
=PP5V_S4_AUDIO
MIN_LINE_WIDTH=0.2 MMMAKE_BASE=TRUEVOLTAGE=1.35V
MIN_NECK_WIDTH=0.17 MM
PP1V35_S3
=PPVIN_S3_P1V35S3RS0_FET
PP1V35_S3_MEMMIN_NECK_WIDTH=0.17 MMMIN_LINE_WIDTH=0.2 MM
MAKE_BASE=TRUEVOLTAGE=1.35V
=PP1V35_S0_RIO
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
PP1V5_S0VOLTAGE=1.5VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MMPP1V35_S3RS0_FET
VOLTAGE=1.35V
=PP15V_TBT_REG
VOLTAGE=1.8VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE
PPVCC_S0_CPU
=PPBUS_SW_BKL
=PP3V3_S4_TBT
MIN_NECK_WIDTH=0.2 MM
PP3V3_S0SW_SSDMIN_LINE_WIDTH=0.5 MM
MAKE_BASE=TRUEVOLTAGE=3.3V
=PP1V5_S0_AUDIO
=PP1V5_S0_REG
=PP1V35_S3RS0_FET_ISNS
=PPVIN_S3_MEM_ISNS
=PP1V5R1V35_S3_MEM_A
=PP1V5_S0_PCH_CLK
=PPVTT_S0_MEM_A
PPVIN_SW_TBTBSTVOLTAGE=12.8V
=PPVIN_S3_MEM_ISNS_R
=PP1V05_S0_PCH_VCCCLK_CLK135
=PP1V05_S0_PCH_VCCIO=PP1V05_S0_PCH_VCCIO_FDI
=PP1V05_S0_CPU_JTAG=PP1V05_S0M_PCH_VCCASW
=PP1V05_S0_PCH_VCCUSBPLL=PP1V05_S0_PCH_VCC_CLK
=PP1V05_S0_PCH_VCCIO_USB2=PP1V05_S0_PCH_VCCIO_GPIO
=PP1V05_S0_PCH_VCCCLK_SSC100=PP1V05_S0_PCH_VCCCLK_SSC
=PP1V05_S0_PCH_VCCCLK_CLK100=PP1V05_S0_PCH_VCC
=PPVDDIO_S0_SBCLK
=PP1V5_S0_PCH_VCCVRM
PPVTT_S0_DDRMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.675VMAKE_BASE=TRUE
=PPVTT_S0_VTTCLAMP
=PP5V_S0_FAN_RT
=PP1V5_S0_PCH_SATA=PP1V5_S0_PCH_RCOMP
=PP1V05_SUS_PCH_JTAG
=PPVTT_S0_DDR_LDO
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
PPVTTDDR_S3MAKE_BASE=TRUEVOLTAGE=0.675V
=PP1V5_S0_DIV=PP1V5_S0_RIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PPHV_S4SW_TBTAPWRSW=PPHV_S4SW_TBTBPWRSW
MIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUEVOLTAGE=20V
MIN_NECK_WIDTH=0.25 MM
PPDCIN_G3H
=PPVIN_S4_TPAD
MAKE_BASE=TRUEVOLTAGE=3.3V
PP3V3_S3RS0_CAMERAMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM
=PP5V_S3_ALSCAM
=PP3V3_S3RS0_CAMERA
=PP3V3_S3RS0_CAMPWREN
=PP3V3_S0SW_SSD
PP3V3_S4_TBTMIN_NECK_WIDTH=0.1 MM MAKE_BASE=TRUE
VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MM
=PP3V3_S0SW_SSD_R
=PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUEVOLTAGE=28V
PPVIN_S4_TPADMIN_NECK_WIDTH=0.25 MM
=PP5V_S0_P1V05S0
=PP5V_S0_KBDLED
=PP5V_S3_FET
=PPVRTC_G3_OUT
MAKE_BASE=TRUEVOLTAGE=15V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP15V_TBT
MIN_LINE_WIDTH=0.4 MMPP1V05_SUS
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V
PPBUS_SW_BKLMIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.6VMAKE_BASE=TRUE
MIN_LINE_WIDTH=2 MM
=PPDDR_S3_REG
=PP1V35_S3RS0_VMON
=PPVCC_S0_CPU
=PPVCC_S0_CPU_REG
=PPDDR_S3_MEMVREF=PP1V5_S3_MEMRESET
=PP1V05_SUS_LDO
=PP1V35_S3RS0_FET
=PP1V5R1V35_S3_MEM_B
=PPVIN_S0_DDRREG_LDO
=PPVTT_S0_MEM_B
=PP1V5R1V35_S0_CPU
MAKE_BASE=TRUEVOLTAGE=1.35V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP1V35_S3RS0_CPUDDR
=PPVDDIO_TBTLC_CLK
=PP3V3_TBTLC_FET=PPBUS_G3H
=PP5V_S5_P1V35S3RS0FET
=PP3V42_S3_HALL=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_SMBUS_SMC_5=PP3V3_S5_SMC=PP3V42_G3H_SMCUSBMUX=PPVIN_S5_SMCVREF=PPVBAT_G3_SYSCLK
=PP3V42_G3H_PCHPWRGD=PP3V42_G3H_SSDSAK
=PPVRTC_G3_PCH
MAKE_BASE=TRUEVOLTAGE=3.42V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MMPP3V42_G3H
=PP5V_S5_LDO
VOLTAGE=5VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MMPP5V_S4
=PP5V_S4_P5VS0FET
VOLTAGE=3.42VMAKE_BASE=TRUE
PPVRTC_G3HMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
=PP5V_S4_P5VS3FET
=PPVIN_S0_P1V05S0
=PPBUS_S0_VSENSE
MIN_NECK_WIDTH=0.25 MMVOLTAGE=12.8V
PPVIN_S5_HS_OTHER3V3_ISNSMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM=PPVIN_S5_HS_OTHER3V3_ISNS
=PPVIN_S0_CPUVR
=PP20V_DCIN_CONN
=PPVIN_T101_BOOSTRPBUS_ISNS
MIN_NECK_WIDTH=0.25 MM
PPVIN_S5_HS_OTHER5V_ISNSMAKE_BASE=TRUEVOLTAGE=12.8VMIN_LINE_WIDTH=0.6 MM
=PPVIN_S0GPU_P1V5P1V0
PPVIN_S5_HS_GPU_ISNSMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM VOLTAGE=12.8VMIN_NECK_WIDTH=0.25 MM
=PPVIN_S5_HS_GPU_ISNS
=PPVIN_S5_HS_OTHER5V_ISNS_R=PPVIN_S0_LCDBKLT=PPVIN_SW_TBTBST
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_OTHER3V3_ISNS_R
MIN_NECK_WIDTH=0.25 MMVOLTAGE=12.8VMIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUE
PPVIN_S5_HS_COMPUTING_ISNS
=PP1V05_S0_PCH_V_PROC_IO
=PPVCCIO_S0_SMC=PP1V05_S0_VMON
=PPVIN_S5_P5V
MIN_LINE_WIDTH=0.6 MM VOLTAGE=12.8VPPBUS_G3HMIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MMGND
VOLTAGE=0VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.085 MM
dvt
051-0675
6.0.0
100 OF 119
81 OF 94
82
60
65
33
18
83
20 41 42
45 46
82
65
64
38 83
45
78
33
83 93
79
66
75 79
43
79 80
47
65
34
43
43
43
19
20
15 17
15 17
15 17
15 17
15 17
15 17
11 12 14 20 29
34
13
67
45 46
44
48
47
48
45
64
47
50 51 54
46
50
22
79
43
64
20
21
78
45 46
46
13
49
64
13 15 17
15
15 17
15 17
15 17
11 12 13 14
63
65
83 93
83
44
64
64
19
65
15 17
12 14
64
64
63
65
21
65
32
31
64
64
19
64
60
48
57 58
83
82
71
18
36
65
49
21
37
77
44
59
44
56
56
44
55
78
19
77
60 65
49
8361
55
64
38
65
71
45
77
69 76
74
74
74 76
70 76
67
71
69 72 73
45
70
83
59 65
62
64
64 66
74
77
68 74 75 76
74
59
20 28 29
38 83
83
50
83
64
89
78
83
30
83
28 29 30 45
83
51
63
64
45
23 24
11
27
30
45
15 17
15 17
15 17
18
15 17
15 17
17
15 17
15
15 17
15 17
15 17
15 17
19
17
83
21
48
11
12 13
18
59
83
65
78
15 17 19
31
32
83
36
35 46
13
34 45
45 64
45
61
62
64
19
62
59
65
6 8 10
22
21
63
64
25 26
59
27
6 8 10 21
93
19
55 56
64
42
56 65
55
43
40 41 75
37
41
19
19
34
11 12 15
83
60
83
64
64
61
44
44
57 58
55
71
44
44
62
30
44
44
14 15 17
41
65
60
83
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Display Aliases
Thunderbolt Signals Through PEG
MAKE_BASEVOLTAGE
CPU signals
Unused signals
SM
SM
1/20WMF
0
5%
02010
MF1/20W5%
NOSTUFF
0201
Signal AliasesSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMVOLTAGE=3.3V
PP3V3_S3_FAN_CTL
MAKE_BASE=TRUE
=PP3V3_S3_FAN_CTL
=PP3V3_S5_FAN_CTL
=PP3V3_S4_FAN_CTL
MAKE_BASE=TRUEDPB_IG_AUX_CH_P
TP_DP_IG_A_AUXCHN
TP_DP_IG_B_DDC_CLK
PP5V_S0_AUDIO_AMP_R
VOLTAGE=5V
MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM
VOLTAGE=5VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MMPP5V_S0_AUDIO_AMP_L
=PP5V_S0_AUDIO_XW
HDMITBTMUX_SEL_TBTSDCONN_OC_L
PEG_CLKREQ_L
AUD_IP_PERIPHERAL_DET
ENET_LOW_PWR_PCH
DPMUX_UC_IRQTBT_GO2SX_BIDIRAUD_I2C_INT_L
MEM_VDD_SEL_1V5_LBT_PWRRST_L
ENET_CLKREQ_L
AUD_IPHS_SWITCH_EN_PCH
PPVREF_S3_MEM_VREFDQ_A
PPVREF_S3_MEM_VREFCA_B
PPVREF_S3_MEM_VREFCA_A
=DDRVTT_EN
FW_PWR_EN_PCH
PPVREF_S3_MEM_VREFDQ_B
ENET_MEDIA_SENSE_RDIV
PP0V75_S3_MEM_VREFCA_B0.675V TRUE
PP0V75_S3_MEM_VREFCA_A0.675V TRUE
0.675V PP0V75_S3_MEM_VREFDQ_BTRUE
MAKE_BASE=TRUEMEMVTT_EN
DP_TBT_SELFW_PME_LWOL_EN
=PEG_D2R_P<7..0>MAKE_BASE=TRUEPEG_D2R_P<7..0>
MAKE_BASE=TRUEPEG_R2D_C_N<7..0>
PEG_R2D_C_P<7..0>MAKE_BASE=TRUE
=PEG_R2D_C_N<15..12>MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_PEG_R2D_CP<15..12>
MAKE_BASE=TRUEPCIE_TBT_D2R_P<3..0>
MAKE_BASE=TRUENC_PCIE_PEG_R2D_CN<15..12>
NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_PEG_D2RN<15..12>
PEG_CLK100M_PMAKE_BASE=TRUE
PEG_CLK100M_NMAKE_BASE=TRUE
IG_BKLT_EN
TP_DP_IG_A_MLP<3..0>MAKE_BASE=TRUEDP_INT_IG_ML_P<3..0>
MAKE_BASE=TRUEDP_INT_IG_AUX_P
MAKE_BASE=TRUEDP_INT_IG_AUX_N
TP_DP_IG_C_AUXCHP
TP_DP_IG_C_DDC_CLK
TP_DP_IG_C_DDC_DATA
TP_DP_IG_B_AUXCHN
TP_DP_IG_B_AUXCHP
TP_DP_IG_B_HPD
TP_DP_IG_C_AUXCHN
EG_CLKREQ_OUT_LMAKE_BASE=TRUEPEG_CLKREQ_L
MAKE_BASE=TRUEDPB_IG_AUX_CH_N
DP_TBTSNK0_HPD_IGMAKE_BASE=TRUE
MAKE_BASE=TRUEDP_TBTSNK1_HPD_IG
DPA_IG_AUX_CH_NMAKE_BASE=TRUE
MAKE_BASE=TRUEDPMUX_UC_RX
DPA_IG_DDC_DATAMAKE_BASE=TRUE
DPB_IG_DDC_DATAMAKE_BASE=TRUE
DPB_IG_DDC_CLKMAKE_BASE=TRUE
DPMUX_UC_TXMAKE_BASE=TRUE
DP_AUXCH_ISOL_LMAKE_BASE=TRUE
PP0V75_S3_MEM_VREFDQ_ATRUE0.675V
=P1V8GPU_ENTP_P1V8GPU_EN
PEG_D2R_N<7..0>MAKE_BASE=TRUE
=PEG_R2D_C_N<7..0>
=PEG_R2D_C_P<7..0>
=PEG_D2R_N<7..0>
MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_PEG_D2RP<15..12> =PEG_D2R_P<15..12>
=PEG_D2R_N<15..12>
=PEG_R2D_C_P<15..12>
=PEG_D2R_P<11..8>
=PEG_R2D_C_P<11..8>
=PEG_R2D_C_N<11..8>
=PEG_D2R_N<11..8>
TP_DP_IG_B_DDC_DATA
DPA_IG_AUX_CH_PMAKE_BASE=TRUE
DP_INT_IG_ML_N<3..0>MAKE_BASE=TRUE
DPA_IG_DDC_CLKMAKE_BASE=TRUE
IG_LCD_PWR_EN
EG_RESET_LMAKE_BASE=TRUE
DP_AUXIO_EN
DPMUX_UC_BOOT_TX
GPU_RESET_L
DPMUX_UC_BOOT_RX
TP_DP_IG_C_HPD
TP_PCIE_CLK100M_GPUP
MAKE_BASE=TRUEPCIE_TBT_R2D_C_N<3..0>
MAKE_BASE=TRUEEDP_IG_BKL_ON
TP_PCIE_CLK100M_GPUN
MAKE_BASE=TRUEPCIE_TBT_R2D_C_P<3..0>MAKE_BASE=TRUEPCIE_TBT_D2R_N<3..0>
TP_DP_IG_A_AUXCHP
TP_DP_IG_A_MLN<3..0>
MAKE_BASE=TRUEEDP_IG_PANEL_PWR
XWA2021 2
XWA2031 2
RA2011 2
RA202
1 2
dvt
051-0675
6.0.0
102 OF 119
82 OF 94
48
81
81
80 86
5
12
52
52
81
28
12
11 82
12
12
14 79
14
12
14
12
11
12
22 23 24 86 89
22 25 26 86
22 23 24 86 89
21 59
14
22 25 26 86
11
21
11
14
14
566 68 86
68 86
68 86
5
28 86
68 83 88
68 83 88
79
579 94
79 94
79 94
12
12
12
12
12
12
12
7911 82
80 86
79
79
80 86
79
80
80
80
79
11 18
66
66 68 86
5
5
5
5
5
5
5
5
5
5
12
80 86
79 94
80
79
79
79
68 75
79
12
11
28 86
12
11
28 86
28 86
5
5
12
AA
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
J7000 - DC PWR
J4800 - ipd flex
Functional Test Points
2X
J8300 - eDP
J4002 - Camera
J6701 - audio flex
J6601 - mic
J6602 - L speaker
J6603 - R speaker
2X GND
2X
J4915 - kbd bklt
J4813 - keyboard
J9510 - rio flex
3X
5X
J6060 - right fan
J5150 - hall effect
J6050 - left fan
5X
3X
3X
5X
10X
19X
J9500 - rio coax
FUNC_TEST
2X GND
4X
4X
16X
3X
J7050 - battery
8X
8X
2X
2X
2X
2X
2X
FUNC_TEST J6100 - lpc + spiFUNC_TEST J3501 - airport
4X
4X
Power Rails
FUNC_TESTXDP
FUNC_TESTPower Sequence
I1918
I1919
I1920
I1921
I1922
I1923
I1924
I1925
I1927
I1928
I1929
I1930
I1931
I1932
I1934
I1935
I1936
I1938
I1939
I1940
I1941
I1942
I1943
I1944
I1948
I1949
I1950
I1951
I1952
I1953
I1954
I1955
I1956
I1957
I1958
I1959
I1960
I1961
I1962
I1963
I1965
I1966
I1967
I1968
I1969
I1970
I1971
I1972
I1973
I1974
TP-P6
TP-P6
Functional Test PointsSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
TRUE GND
GNDTRUE
TRUE GND
TRUE GND
TRUE GND
TRUE GND
GNDTRUE
TRUE GND
TRUE GND
TRUE GND
TRUE GND
GNDTRUE
TRUE GND
GNDTRUE
GNDTRUE
TRUE GND
GNDTRUE
GNDTRUE
TRUE GND
SMC_ROMBOOTTRUE
SPIROM_USE_MLBTRUE
TRUE WS_CONTROL_KBD
CPU_CFG<3>TRUE
PM_SYSRST_LTRUE
PM_RSMRST_LTRUE
PM_PCH_PWROKTRUE
XDP_PCH_TDOTRUE
TRUE AUD_HP_PORT_L
AUD_SPDIF_OUT_JACKTRUE
AUD_CONN_MIC_XWTRUE
PP3V3_S5_AVREF_SMCTRUE
PP3V3_S3TRUE
LED_RETURN_5TRUE
TRUE LED_RETURN_4
TRUE LED_RETURN_1TRUE LCD_HPD_CONN
TRUE DP_INT_ML_P<3>TRUE LCD_FSS
TRUE DP_INT_ML_P<2>TRUE DP_INT_ML_P<1>TRUE DP_INT_ML_P<0>
TRUE DP_INT_ML_N<2>TRUE DP_INT_ML_N<3>
DP_INT_ML_N<0>TRUEDP_INT_ML_N<1>TRUE
SMBUS_SMC_5_G3_SDATRUE
TRUE SMBUS_SMC_5_G3_SCL
PP20V_DCIN_FUSETRUE
ADAPTER_SENSETRUE
TRUE SPKRCONN_SR_OUT_PSPKRCONN_SR_OUT_NTRUE
SPKRCONN_R_OUT_PTRUE
SPKRCONN_R_OUT_NTRUE
SPKRCONN_R_IDTRUE
SPKRCONN_SL_OUT_PTRUE
DMIC_SDA2TRUE
TRUE WS_LEFT_OPTION_KBDWS_KBD_ONOFF_LTRUE
WS_KBD8TRUEWS_KBD9TRUE
WS_KBD7TRUE
TRUE WS_KBD3TRUE WS_KBD23
WS_KBD21TRUEWS_KBD22TRUE
WS_KBD20TRUE
WS_KBD2TRUE
WS_KBD19TRUE
WS_KBD17TRUEWS_KBD18TRUE
WS_KBD16_NUMTRUE
WS_KBD15_CAPTRUE
TRUE WS_KBD14
TRUE WS_KBD12WS_KBD13TRUE
WS_KBD11TRUE
WS_KBD10TRUE
WS_KBD1TRUE
PP3V42_G3HTRUE
TRUE SPI_ALT_CLK
SMC_TMSTRUE
SMC_TDOTRUE
SMC_TDITRUE
SMC_TCKTRUE
SMC_RESET_LTRUE
PP5V_S0TRUE
TRUE PM_CLKRUN_LLPC_SERIRQTRUE
TRUE LPC_PWRDWN_LLPC_FRAME_LTRUE
LPC_CLK33M_LPCPLUSTRUE
LPC_AD<2>TRUE
TRUE USB_BT_CONN_PUSB_BT_CONN_NTRUE
PCIE_AP_D2R_PI_NTRUE
AP_RESET_CONN_LTRUE
PPVOUT_S0_KBDBKLTTRUE
KBDBKLT_RETURN2TRUE
WS_LEFT_SHIFT_KBDTRUE
TRUE PPVTT_S0_DDR
TRUE LED_RETURN_6
PP1V35_S3TRUE
PP1V5_S0TRUE
TRUE XDP_CPU_TMS
TRUE XDP_PCH_TDITRUE XDP_PCH_TMS
TRUE XDP_CPU_TRST_LTRUE XDP_CPU_TDOTRUE XDP_CPU_TDITRUE XDP_PCH_TCK
XDP_CPU_TCKTRUE
PM_DSW_PWRGDTRUE
ALL_SYS_PWRGDTRUE
PM_PCH_SYS_PWROKTRUE
PLT_RESET_LTRUE
SMC_ONOFF_LTRUE
PCIE_AP_R2D_PTRUEPCIE_CLK100M_AP_CONN_NTRUE
PP3V3_WLANTRUE
MIPI_DATA_CONN_PTRUE
CAM_SENSOR_WAKE_L_CONNTRUE
SMC_LID_RTRUE
FAN_LT_PWMTRUE
PP5V_S0TRUE
=I2C_ALS_SDATRUE=I2C_ALS_SCLTRUE
PP5V_S3RS0_ALSCAM_FTRUE
I2C_CAM_SDATRUE
I2C_CAM_SCKTRUE
HDMI_DATA_N<2>TRUE
HDMI_DATA_P<2>TRUE
USB3_EXTB_D2R_PTRUEUSB3_EXTB_R2D_NTRUEUSB3_EXTB_R2D_PTRUE
TRUE USB3_SD_R2D_C_NTRUE USB3_SD_R2D_C_P
USB3_EXTB_D2R_NTRUE
USB_EXTB_OC_LTRUE
USB_EXTB_NTRUEUSB_EXTB_PTRUE
PP1V5R1V35_S0_RIOTRUE
SD_PWR_ENTRUE
TRUE HDMI_DDC_CLK
HDMI_HPD_LTRUE
TRUE HDMI_DDC_DATA
TRUE SMBUS_PCH_CLK
TRUE PM_SLP_S3_BUF_L
TRUE PP3V3_S3TRUE PM_SLP_S4_L
TRUE PP5V_S4TRUE PP3V3_S4
RIO_SDCONN_STATE_CHANGE_LTRUE
TRUE HDMI_DATA_P<1>HDMI_DATA_P<0>TRUE
HDMI_DATA_N<1>TRUE
HDMI_CLK_PTRUE
HDMI_CLK_NTRUE
HDMI_DATA_N<0>TRUE
TRUE PP3V3_S4
KBDBKLT_RETURN1TRUE
DMIC_SDA3TRUE
AUD_HP_PORT_RTRUE
AUD_TIPDET_INVTRUE
AUD_TYPEDETTRUE
AUD_CONN_SLEEVE_XWTRUE
DMIC_CLK3TRUE
SPKRCONN_SL_OUT_NTRUE
SPKRCONN_L_OUT_PTRUE
SPKRCONN_L_OUT_NTRUE
SPKRCONN_L_IDTRUE
US_HS_MICTRUE
PP3V3_S0TRUE
CH_HS_MICTRUE
XDP_CPU_PRDY_LTRUE
TRUE XDP_CPU_PREQ_L
PPVBAT_G3H_CONNTRUE
TRUE PP5V_S0
TRUE PCIE_WAKE_LPCIE_CLK100M_AP_CONN_PTRUE
PCIE_AP_D2R_PI_PTRUE
TRUE LPC_AD<0>LPCPLUS_RESET_LTRUE
TRUE LPC_AD<1>
LPC_AD<3>TRUE
PP1V05_S0TRUE
SMBUS_PCH_DATATRUE
PP3V42_G3HTRUE
FAN_RT_PWMTRUE
PP3V3_S0TRUE
TRUE USB3_SD_D2R_NTRUE USB3_SD_D2R_P
MIPI_DATA_CONN_NTRUE
TRUE MIPI_CLK_CONN_PMIPI_CLK_CONN_NTRUE
Z2_HOST_INTNTRUE
Z2_SCLKTRUE
TRUE WIFI_EVENT_L
FAN_LT_TACHTRUE
TRUE SYS_DETECT_L
TRUE SPI_ALT_MOSI
TRUE SPI_ALT_CS_L
TRUE SMC_TX_L
TRUE AP_CLKREQ_Q_L
PP5V_S3TRUE
PP3V42_G3HTRUE
PP3V3_S0TRUE
WS_KBD6TRUE
WS_KBD5TRUE
TRUE WS_KBD4
PP3V3_S0SW_SSDTRUE
PPVTTDDR_S3TRUE
TRUE PPVCC_S0_CPUPPDCIN_G3HTRUE
TRUE PPBUS_G3HPP5V_S5TRUE
PP5V_S0TRUE
PP3V3_S5TRUE
TRUE PM_SLP_S3_L
PPVOUT_S0_LCDBKLTTRUE
TRUE PP5VR3V3_SW_LCD
TRUE LED_RETURN_3TRUE LED_RETURN_2
Z2_CLKINTRUE
Z2_MISOTRUE
Z2_MOSITRUE
Z2_CS_LTRUE
=I2C_TPAD_SCLTRUE
TRUE =PP3V3_S4_TPAD=PP5V_S5_TPADTRUE
TRUE PICKB_LTRUE PSOC_F_CS_LTRUE Z2_KEY_ACT_L
PSOC_SCLKTRUE
SMC_T101_COM_1TRUE
TRUE SMC_LID=I2C_TPAD_SDATRUE
PSOC_MISOTRUE
PSOC_MOSITRUE
TP_SMC_TRST_LTRUE
TRUE SMC_RX_L
LPCPLUS_GPIOTRUE
TRUE TP_SMC_MD1
TRUE SPI_ALT_MISO
PP3V3_S3RS4_BT_FTRUE
PCIE_AP_R2D_NTRUE
FAN_RT_TACHTRUE
TRUE DP_INT_AUX_PTRUE DP_INT_AUX_N
LCD_PWR_ENTRUE
LCD_BKLT_ENTRUE
PEG_CLK100M_PPEG_CLK100M_NTPA4021
TPA4011
dvt
051-0675
6.0.0
104 OF 119
83 OF 94
41 49
14 49
38
6 18 86
12 19 40 88
12 65 88
12 19 88
11 18
50 54
40 41
81 83
62 67
62 67
62 67
67
67 86 94
62 67 79
67 86 94
67 86 94
67 86 94
67 86 94
67 86 94
67 86 94
67 86 94
40 43 92
40 43 92
55
55
52 54 93
52 54 93
52 54 93
52 54 93
51 54
52 54 93
54
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
81 83
49
40 41 49
40 41 49
40 41 49
40 41 49
40 41 49 56
81 83
12 40 49
13 40 49
12 20 40 49
13 40 49 79 88
19 49 88
13 40 49 79 88
33 87
33 87
33 88
33
39 62
39 62
38
81
62 67
81
81
6 18 86
11 18
11 18
6 18 86
6 18 86
6 18 86
11 18
6 18 86
12 40 88
18 19 40 65
12 18 19 40 88
12 18 20 21
38 40 41
33 88
33 88
33 41
36 91
36
42
48
81 83
36 43
36 43
36
35 36
35 36
86
86
13 78 87
78 87
78 87
20 78 88
20 78 88
13 78 87
18 78
13 78 87
13 78 87
78
13 18 78
13 43 88
50 64 65 78 79
81 83
12 21 33 37 40 65 78
81
81 83
20 78
86
86
86
86
86
86
81 83
39 62
51 54
50 54
50 54
53 54
51 54
52 54 93
52 54 93
52 54 93
51 54
81 83 93
6 18 86
6 18 86
55 56
81 83
12 33 35 88
33 88
33 88
13 40 49 79 88
20 49
13 40 49 79 88
13 40 49 79 88
81
13 43 88
81 83
48
81 83 93
20 78 88
20 78 88
36 91
36 91
36 91
38
38
33 40 41
48
55
49
49
40 41 49
33
81
81 83
81 83 93
38
38
38
81
81
81
81
81
81
81 83
81 93
12 21 40 65
62 67
67
62 67
62 67
38
38
38
38
38 43
38 81
38 81
38
38
38
38
38 40 41 42
38 43
38
38
49
40 41 49
14 49
49
49
33
33 88
48
67 86 94
67 86 94
67 79
62 79
68 82 88
68 82 88
TP
TP
TP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
MAKE_BASE
Thunderbolt
NC NO_TESTs
PLACEABLE BEAD-PROBES FOR TBTNO_TESTNO_TEST
PCHMAKE_BASE
NO_XNET_CONNECTION=TRUEBEAD-PROBESMNO_XNET_CONNECTION=TRUESM BEAD-PROBENO_XNET_CONNECTION=TRUESM BEAD-PROBE
I1975
I1976
I1977
I1978
NC & No TestSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
USB_EXTC_P
NC_USB_7NTRUETRUE
TRUE TRUE NC_USB_EXTDPTRUETRUE NC_USB_PSOCN
EDP_IG_BKL_PWM TRUE TRUE NC_EDP_IG_BKL_PWM
TP_USB_PSOCP
TP_HDA_SDIN3
TRUE NC_CLINK_RESET_LTRUETP_CLINK_RESET_L
TP_HDA_SDIN1NC_PCI_CLK33M_OUT3TRUETRUE
NC_PCI_CLK33M_OUT2TRUETRUE
ITPXDP_CLK100M_PITPXDP_CLK100M_N
USB_IR_N
TP_USB_7P
TP_USB_6PTP_USB_6N
TP_CLINK_DATA
TP_PCI_CLK33M_OUT2TP_PCI_CLK33M_OUT3
TP_HDA_SDIN2
TP_CLINK_CLK
DMI_N2S_P<3..1>TRUE
NC_PCIE_CLK100M_PE5PTRUETRUENC_PCIE_CLK100M_ENETSDNTRUETRUE
NC_PCIE_CLK100M_PEGBNTRUE TRUETP_PCIE_CLK100M_PEGBPTP_PCIE_CLK100M_SWN
TP_SATA_ODD_D2RPTP_SATA_ODD_R2D_CN
TP_SATA_D_R2D_CP
TP_USB_SDP
TRUETRUE NC_DP_IG_D_AUXCHP
TP_USB_7NNC_USB_6PTRUE TRUE
NC_SATA_D_R2D_CPTRUETRUE
TRUE TRUE NC_SATA_B_R2D_CN
TRUETRUE NC_USB3_SPARE_D2RN
TP_DP_IG_D_AUXCHP
TP_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5NTRUE TRUETP_PCIE_CLK100M_PE5P
TP_DP_IG_D_AUXCHN
NC_USB3_EXTC_D2RPTRUETRUE
NC_USB3_EXTD_D2RPTRUE TRUE
PCIE_CLK100M_ENETSD_P
TP_PCIE_CLK100M_PEGBNTP_PCIE_CLK100M_ENETPTP_PCIE_CLK100M_ENETN
TP_PCH_GPIO67_CLKOUTFLEX3
NC_USB_7PTRUETRUEUSB_EXTD_NUSB_EXTD_PTP_USB_PSOCN
TRUE NC_USB_WLANPTRUE
TP_PCIE_CLK100M_SWP
TP_PCH_GPIO64_CLKOUTFLEX0TP_PCH_GPIO65_CLKOUTFLEX1
TP_USB_4P
TRUETRUE NC_USB_PSOCPTRUE NC_USB_IRNTRUE
TRUE TRUE NC_USB_IRPUSB_IR_P
NC_USB_EXTDNTRUETRUE
TRUE NC_USB_6NTRUE
TRUE TRUE NC_USB_SDNNC_USB_EXTCPTRUETRUE
TRUE NC_USB_EXTCNTRUE
TRUETRUE NC_PCH_GPIO65_CLKOUTFLEX1TRUE TRUE NC_PCH_GPIO66_CLKOUTFLEX2TRUE TRUE NC_PCH_GPIO67_CLKOUTFLEX3
NC_PCIE_CLK100M_ENETSDPTRUETRUE
TRUETRUE NC_USB3_SPARE_R2D_CP
NC_USB3_EXTC_R2D_CPTRUETRUE
TP_PCH_GPIO66_CLKOUTFLEX2
TP_USB_4N
NC_SATA_F_D2RNTRUETRUE
TRUETRUE NC_SATA_D_R2D_CN
NC_SATA_ODD_R2D_CPTRUETRUE
TRUETRUE NC_SATA_ODD_R2D_CN
TRUE NC_SATA_ODD_D2RNTRUE
TRUETRUE NC_SATA_B_D2RP
TRUE TRUE NC_SATA_A_D2RP
TP_USB3_SPARE_D2RN
NC_USB3_EXTD_D2RNTRUETRUE
TP_SATA_ODD_D2RN
SATA_A_D2R_P
NC_PCIE_ENET_R2D_CNTRUE TRUE
NC_SATA_D_D2RPTRUE TRUE
TP_SATA_F_D2RPTP_SATA_F_R2D_CNTP_SATA_F_R2D_CP
USB_EXTC_N
TP_USB_SDN
TP_USB_WLANN
NC_PCIE_ENET_D2RPTRUE TRUE
TP_SATA_D_D2RN
TRUETRUE NC_HDA_SDIN3
TRUE TRUE NC_PCI_PME_L
TRUE TRUE NC_SATA_F_R2D_CP
TP_SATA_D_D2RP
TRUE NC_USB_4NTRUENC_USB_4PTRUE TRUE
NC_PCIE_CLK100M_ENETPTRUETRUE
TRUETRUE NC_PCIE_CLK100M_PEGBP
USB_SMC_PUSB_SMC_N
NC_ITPXDP_CLK100MPTRUE TRUE
USB3_EXTC_D2R_P
TRUETRUE NC_USB3_SPARE_D2RP
TRUETRUE NC_SMC_INTERFACE_2
TRUE TRUE NC_TBT_XTAL25OUT
NC_HDA_SDIN2TRUETRUE
TRUE TRUE NC_SATA_A_D2RN
TRUE TRUE NC_SATA_A_R2D_CN
NC_USB3_EXTC_R2D_CNTRUETRUE
NC_USB3_EXTD_R2D_CPTRUE TRUE
TRUE TRUE NC_SATA_A_R2D_CP
NC_SATA_B_R2D_CPTRUE TRUE
TRUETRUE NC_USB_SMCNTRUE NC_USB_SMCPTRUE
NC_CLINK_DATATRUETRUE
NC_CLINK_CLKTRUETRUE
TRUETRUE NC_LPC_DREQ0_L
TRUE NC_HDA_SDIN1TRUE
NC_ITPXDP_CLK100MNTRUETRUE
TRUE NC_USB_SDPTRUE
TRUE NC_USB_WLANNTRUE
TRUE TRUE NC_SATA_F_R2D_CN
TRUETRUE NC_SATA_D_D2RN
TRUETRUE NC_SATA_ODD_D2RP
NC_DP_TBTSRC_AUXCH_CNTRUETRUE
TRUETRUE NC_USB3_EXTC_D2RN
TRUE TRUE NC_PCH_GPIO64_CLKOUTFLEX0
NC_USB3_SPARE_R2D_CNTRUETRUE
NC_USB3_EXTD_R2D_CNTRUE TRUE
NC_DP_TBTSRC_AUXCH_CPTRUETRUE
TRUE TRUE NC_DP_TBTSRC_ML_CP<3..0>
TRUE PCIE_TBT_R2D_P<3..0>TRUE PCIE_TBT_R2D_N<3..0>TRUE PCIE_TBT_D2R_C_P<3..0>TRUE PCIE_TBT_D2R_C_N<3..0>
DMI_S2N_P<3..1>TRUEDMI_S2N_N<3..1>TRUE
DMI_N2S_N<3..1>TRUE
NC_PCIE_CLK100M_SWNTRUETRUE
TRUETRUE NC_SATA_F_D2RP
TP_SATA_D_R2D_CN
SMC_INTERFACE_2
TP_TBT_XTAL25OUT
TP_DP_TBTSRC_AUXCH_CNTP_DP_TBTSRC_AUXCH_CPTP_DP_TBTSRC_ML_CN<3..0>
PCIE_ENET_R2D_CP
PCIE_ENET_D2RPPCIE_ENET_D2RN
USB3_EXTD_R2D_C_PUSB3_EXTD_R2D_C_N
USB3_EXTD_D2R_NUSB3_EXTD_D2R_P
USB3_EXTC_R2D_C_P
USB3_EXTC_D2R_NTP_USB3_SPARE_R2D_CPTP_USB3_SPARE_R2D_CNTP_USB3_SPARE_D2RP
TBT_A_R2D_C_P<1>TBT_A_D2R_P<1>TBT_A_D2R_N<1>
TP_SATA_F_D2RN
TP_USB_WLANP
TP_PCI_PME_L
TP_LPC_DREQ0_L
SATA_B_R2D_C_NSATA_B_R2D_C_P
SATA_B_D2R_PSATA_B_D2R_NSATA_A_R2D_C_P
USB3_EXTC_R2D_C_N
SATA_A_R2D_C_N
SATA_A_D2R_N
PCIE_ENET_R2D_CN
TP_DP_TBTSRC_ML_CP<3..0>NC_DP_TBTSRC_ML_CN<3..0>TRUE TRUE
TRUE NC_PCIE_ENET_D2RNTRUE
NC_PCIE_ENET_R2D_CPTRUE TRUE
TP_SATA_ODD_R2D_CP
TRUE TRUE NC_SATA_B_D2RN
TRUE NC_DP_IG_D_AUXCHNTRUE
TRUE TRUE NC_PCIE_CLK100M_SWP
NC_PCIE_CLK100M_ENETNTRUE TRUE
PCIE_CLK100M_ENETSD_N
BPA5321BPA5311BPA5351
dvt
051-0675
6.0.0
105 OF 119
84 OF 94
13
87
87
12
13
11
13
11
11 86
11 86
13
13
13
13
13
11 20
11
11
13
5 12 86
11
11
11
11
11
13
13
87
87
12
11
11
12
87
87
11
11
11
11
11
87
13
13
13
11
11
11
13
87
8713
87
87
87
87
87
87
11
13
87
87
13
87
11
11
11
11
11
13
13
13
11
11
87
87
13
87
87
87
87
87
87
87
87
87
28 86
28 86
28 86
28 86
5 12 86
5 12 86
5 12 86
11
28
28
28
28
13
13
13
13
13
13
13
13
13
28 31 90
28 31 90
28 31 90
11
13
12
13
11
11
11
11
11
13
11
11
28
11
87
11
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_BOARD_INFO
VERSIONALLEGRO
(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
J15 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
Note: Outer dielectric is 0.058 mm nominal, Inner dielectric is 0.053 mm nominal.
Stackup-Defined Spacing Rules
0.116 MM0.116 MMYTOP,BOTTOM45_OHM_SE_ADJ
=STANDARD =STANDARDY* =STANDARD0.085 MM 0.085 MM45_OHM_SE_ADJ
=STANDARD* Y =STANDARD=STANDARD0.083 MM0.083 MM45_OHM_SE
TOP,BOTTOM45_OHM_SE Y 0.116 MM 0.116 MM
PCB Rule DefinitionsSYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
Y* =STANDARD=STANDARD =STANDARD0.090 MM0.102 MM40_OHM_SE
0.145 MM 0.095 MMYTOP,BOTTOM40_OHM_SE
0.186 MM =STANDARD0.1 MM* =STANDARD=STANDARDY27P4_OHM_SE
0.265 MM27P4_OHM_SE 0.095 MMYTOP,BOTTOM
YTOP,BOTTOM50_OHM_SE 0.095 MM0.095 MM
0.095 MMY 0.165 MM37_OHM_SE TOP,BOTTOM
0.090 MM* =STANDARD =STANDARD37_OHM_SE =STANDARDY 0.118 MM
0.066 MM =STANDARD=STANDARD=STANDARD*50_OHM_SE 0.066 MMY
0 MM0 MMYDEFAULT * =45_OHM_SE 10 MM=45_OHM_SE
?0.2 MM*BGA_P2MM
?STANDARD * =DEFAULT
?* 0.1 MMDEFAULT
=STANDARD72_OHM_DIFF =STANDARD* N =STANDARD=STANDARD=STANDARD
ISL2,ISL11 Y80_OHM_DIFF 0.126 MM0.126 MM0.096 MM 0.096 MM
0.080 MM0.080 MM85_OHM_DIFF 0.120 MM0.120 MMISL2,ISL11 Y
TOP,BOTTOM80_OHM_DIFF Y 0.120 MM 0.120 MM 0.160 MM 0.160 MM
=STANDARD=STANDARDN* =STANDARD=STANDARD80_OHM_DIFF =STANDARD
=STANDARD =STANDARD85_OHM_DIFF =STANDARDN =STANDARD* =STANDARD
Y85_OHM_DIFF 0.120 MMISL3,ISL4,ISL9,ISL10 0.080 MM0.080 MM 0.120 MM
0.105 MM0.105 MMY 0.125 MM85_OHM_DIFF TOP,BOTTOM 0.125 MM
=STANDARD=STANDARD =STANDARD =STANDARD=STANDARD* N90_OHM_DIFF
0.200 MM 0.200 MM0.078 MM 0.078 MM90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y
ISL3,ISL4,ISL9,ISL10 Y80_OHM_DIFF 0.126 MM0.096 MM 0.096 MM 0.126 MM
ISL2,ISL11 0.120 MM72_OHM_DIFF 0.120 MM0.105 MM0.105 MMY
0.105 MM0.105 MM 0.120 MM72_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.120 MM
0.200 MM0.078 MM0.078 MMISL2,ISL11 Y 0.200 MM90_OHM_DIFF
0.146 MM72_OHM_DIFF TOP,BOTTOM 0.120 MM0.120 MMY 0.146 MM
1x_DIELECTRIC ?0.053 MMISL3,ISL4,ISL9,ISL10
P65_BGA 0.126MM0.075MM* Y 0.071MM0.071MM
0.180 MM 0.180 MM0.101 MM0.101 MMYTOP,BOTTOM90_OHM_DIFF
=DEFAULT* =DEFAULTY =DEFAULT=DEFAULT 10 MMSTANDARD
16.2NO_TYPE,BGA,P65BGA MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
* 0.1 MM1:1_SPACING ?
?* 0.071 MMP072_SPACE
* ?0.1 MMBGA_P1MM
P075_SPACE** P65BGA
ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 ?0.101 MM1X_DIELECTRIC
* P65BGA P65_BGA
* ?0.075 MMP075_SPACE
0.058 MM ?TOP,BOTTOM1x_DIELECTRIC
BGA* * P072_SPACE
=STANDARD 0.1 MM 0.1 MM=STANDARD* Y1:1_DIFFPAIR =STANDARDdvt
051-0675
6.0.0
110 OF 119
85 OF 94
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DP / HDMI NET PROPERTIES
ELECTRICAL_CONSTRAINT_SET
Most CPU signals with impedance requirements are 50-ohm single-ended.
PEG - SSD & TBT
DIGITAL VIDEO SIGNAL CONSTRAINTS
NET_TYPE
SPACING
CPU Signal Constraints
Spacing Rule Sets
MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.
DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.
SOURCE: IVB PLATFORM DG , Tables 205-207
Some signals require 27.4-ohm single-ended impedance.
SPACING
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
PHYSICAL
CPU Net PropertiesNET_TYPE
PHYSICAL SPACINGELECTRICAL_CONSTRAINT_SET
DP AUX NET PROPERTIES
I125
I126
I130
I132
I133
I134
I135
I136
I140
I141
I144
I145
I146
I147
I150
I151
I152
I153
I154
I155
I156
I157
I158
I159
I166
I167
I170
I171
I210
I211
I212
I213
I223
I224
I225
I226
I227
I228
I229
I230
I231
I232
I233
I234
I235
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I247
I248
I249
I250
I251
I252
I253
I254
I255
I256
I257
I258
*PEG_* =SAME PEG_2SAME
PEG_R2D PEG_TXRX*PEG_D2R
PEG_* PEG_2OTHER**
HDMICLK_2CLKHDMI_CLK CLK_* *
CPU_8MIL ?* 8 MIL
CPU_COMP 20 MIL* ?
DMI_N2S DMI_TXRX*DMI_S2N
CPU_AGTL TOP,BOTTOM ?=2x_DIELECTRIC
CPU_VID 0.457 MM ?*
25 MILCPU_VCCSENSE * ?
=2:1_SPACING ?*CPU_ITP
* ?=6X_DIELECTRICDMICLK2N2S
DMI_TXRXDMI_N2S *DMI_S2N
CLK_DMI * DMICLK2OTHER*
PEG_2SAME * ?=3X_DIELECTRIC
TOP,BOTTOMPEG_2CLK ?=10X_DIELECTRIC?*PEG_2CLK =7X_DIELECTRIC
=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF*DP_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF
*DP_2OTHER ?=4x_DIELECTRIC
HDMICLK_2CLK * ?=7x_DIELECTRIC
* ?HDMICLK_2DP =4x_DIELECTRIC
DP_2SAME * ?=3x_DIELECTRIC
?HDMICLK_2OTHER * =7x_DIELECTRIC
PEG_* * PEG_2CLKCLK_*
PEG_2OTHER * ?=4X_DIELECTRIC
?*PEG_TXRX =6X_DIELECTRIC
DISPLAYPORT * HDMICLK_2DPHDMI_CLK
DP_2OTHER*DISPLAYPORT *
=SAME * DP_2SAMEDISPLAYPORT
?TOP,BOTTOM =10x_DIELECTRICHDMICLK_2OTHER
=6x_DIELECTRIC ?TOP,BOTTOMHDMICLK_2DP
*CPU_AGTL =STANDARD ?
DMI_N2SCLK_DMI * DMICLK2N2S
=10X_DIELECTRICDMI_TXRX ?TOP,BOTTOM
=50_OHM_SE =50_OHM_SECPU_50S =50_OHM_SE =50_OHM_SE =STANDARD* =STANDARD
=45_OHM_SE=45_OHM_SECPU_45S =STANDARD* =45_OHM_SE =45_OHM_SE =STANDARD
HDMICLK_2OTHER**HDMI_CLK
DMI_S2N * DMICLK2S2NCLK_DMI
?DMICLK2OTHER * =4X_DIELECTRIC
DMI_TXRX ?=6X_DIELECTRIC*
* ?DMI_2SAME =3X_DIELECTRIC
TOP,BOTTOM =10x_DIELECTRIC ?HDMICLK_2CLK
TOP,BOTTOM =6x_DIELECTRIC ?DP_2OTHER
DP_2SAME ?TOP,BOTTOM =4x_DIELECTRIC
PEG_2OTHER TOP,BOTTOM ?=6X_DIELECTRIC
PEG_2SAME TOP,BOTTOM =4X_DIELECTRIC ?
TOP,BOTTOM =10X_DIELECTRIC ?PEG_TXRX
=80_OHM_DIFFPEG_80D =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF
DMI_2SAME =4X_DIELECTRIC ?TOP,BOTTOM
CPU_VREF 12 MIL* ?
=27P4_OHM_SE=27P4_OHM_SECPU_27P4S =27P4_OHM_SE* 7 MIL=27P4_OHM_SE 7 MIL
CPU_85D =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF
* DMI_2SAME=SAMEDMI_*
TOP,BOTTOMDMICLK2N2S ?=10X_DIELECTRIC
DMICLK2S2N TOP,BOTTOM ?=6X_DIELECTRIC
DMICLK2OTHER TOP,BOTTOM =4X_DIELECTRIC ?
DMICLK2S2N * ?=3X_DIELECTRIC
SYNC_MASTER=CLEAN_J45
CPU ConstraintsSYNC_DATE=04/26/2013
PEG_R2D_C_P<7..0>PEG_R2DPEG_R2D PEG_80D
PCIE_TBT_R2D_C_P<3..0>CPU_85D PEG_R2D
PEG_D2RCPU_85D PCIE_TBT_D2R_C_P<3..0>
PEG_R2DPEG_80D PEG_R2D_P<7..0>
PEG_R2D_C_N<7..0>PEG_R2D PEG_R2DPEG_80D
PEG_80D PEG_R2D PEG_R2D_N<7..0>
PEG_D2RPEG_80D PEG_D2R_C_N<7..0>PEG_D2RPEG_80D PEG_D2R_C_P<7..0>PEG_D2RPEG_D2R PEG_80D PEG_D2R_N<7..0>PEG_D2RPEG_D2R PEG_80D PEG_D2R_P<7..0>
CPU_85D PCIE_TBT_D2R_P<3..0>PEG_D2R_TBT PEG_D2R
PEG_D2RCPU_85D PCIE_TBT_D2R_N<3..0>PEG_D2R_TBT
PEG_D2RCPU_85D PCIE_TBT_D2R_C_N<3..0>CPU_85DPEG_R2D_TBT PCIE_TBT_R2D_P<3..0>PEG_R2D
DISPLAYPORT DP_INT_AUX_PDP_85DDP_INT_AUXCH
DP_TBTSNK1_AUXCH_NDP_85DTBTSNK1_AUXCH1
DP_85D DP_TBTSNK1_AUXCH_PTBTSNK1_AUXCH1
DP_85D DISPLAYPORT DP_INT_ML_F_N<3..0>
CPU_PROCHOT_LCPU_AGTLCPU_45SCPU_PROCHOT_L
XDP_BDRESET_L XDP_DBRESET_LCPU_ITPCPU_45S
CPU_ITP XDP_BPM_L<3..0>CPU_45SXDP_BPMXDP_BPM_L<7..4>CPU_ITPCPU_45SXDP_BPM_L
DP_85D DISPLAYPORT DP_INT_ML_F_P<3..0>
CPU_PECICPU_PECI CPU_VIDCPU_45S
XDP_CPU_TMSXDP_TMS CPU_ITPCPU_45S
XDP_TCK XDP_CPU_TCKCPU_ITPCPU_45S
CPU_VCCSENSE CPU_VCCSENSE_PCPU_27P4S CPU_VCCSENSE
CPU_VID CPU_VIDALERT_LCPU_VIDCPU_45S
CPU_COMPCPU_SM_RCOMP CPU_27P4S CPU_SM_RCOMP<2..0>
CPU_45SPM_THRMTRIP_L PM_THRMTRIP_LCPU_8MIL
CPU_VIDSCLKCPU_VID CPU_VIDCPU_45S
DP_85D DP_TBTSNK1_ML_N<3..0>DISPLAYPORT
DP_TBTSNK0_AUXCH_PTBTSNK0_AUXCH DP_85D
DP_85DTBTSNK0_AUXCH DP_TBTSNK0_AUXCH_NDP_TBTSNK0_AUXCH_C_PDP_85DDP_TBTSNK0_AUXCH_C_NDP_85D
DP_85D DISPLAYPORT DP_TBTSNK1_ML_P<3..0>DP_TBT_ML1 DP_85D DISPLAYPORT DP_TBTSNK1_ML_C_N<3..0>
CPU_VCCSENSE CPU_VCCSENSECPU_27P4S CPU_VCCSENSE_N
CPU_CLK135M_DPLLREF_PCPU_CLK135_PLL CPU_85D CLK_PCIE
CLK_PCIE CPU_CLK135M_DPLLSS_PCPU_85DCPU_CLK135_PLL
DMI_CLK100M_CPU_PDMI_CLK CPU_85D CLK_DMI
FDI_CSYNC CPU_50S FDI_CSYNCCPU_AGTL
CPU_PWRGDCPU_AGTLCPU_45SCPU_PWRGD
XDP_CPU_PREQ_LXDP_PREQ_L CPU_ITPCPU_45S
CPU_85D PEG_R2D PCIE_TBT_R2D_C_N<3..0>
CPU_MEM_VREF CPU_VREF CPU_DIMMB_VREFDQ
DMI_S2N_N<3:0>DMI_S2N CPU_85D DMI_S2N
CPU_CFG<19..0>CPU_CFG CPU_ITPCPU_45S
XDP_TDO XDP_CPU_TDOCPU_ITPCPU_45S
XDP_CLK_PCH CLK_PCIE ITPXDP_CLK100M_NCLK_PCIE_85D
XDP_CLK_PCH ITPXDP_CLK100M_PCLK_PCIECLK_PCIE_85D
XDP_TRST_L CPU_ITPCPU_45S XDP_CPU_TRST_L
CPU_85DCPU_CLK135_PLL CLK_PCIE CPU_CLK135M_DPLLREF_N
PPVREF_S3_MEM_VREFCA_AMEM_PWRCPU_MEM_VREF
PCIE_TBT_R2D_N<3..0>CPU_85D PEG_R2DPEG_R2D_TBT
CPU_MEM_VREF PPVREF_S3_MEM_VREFDQ_BCPU_VREF
CPU_MEM_VREF CPU_VREF CPU_DIMMA_VREFDQ
PM_SYNCCPU_AGTLPM_SYNC CPU_45S
CPU_27P4S CPU_PEG_RCOMPCPU_PEG_COMP CPU_COMP
DMI_N2S CPU_85D DMI_N2S_N<3:0>DMI_N2S
CPU_85D CLK_DMI DMI_CLK100M_CPU_NDMI_CLK
CPU_AGTL PM_MEM_PWRGDPM_MEM_PWRGD CPU_45S
CLK_PCIE CPU_CLK135M_DPLLSS_NCPU_85DCPU_CLK135_PLL
PPVREF_S3_MEM_VREFCA_BCPU_MEM_VREF CPU_VREF
CPU_MEM_VREF MEM_PWR PPVREF_S3_MEM_VREFDQ_A
CPU_VIDSOUTCPU_VID CPU_VIDCPU_45S
HDMI_DATA_P<2..0>DP_85DHDMI_DATA DISPLAYPORT
DP_TBTSNK1_AUXCH_C_PDP_85D
HDMI_CLK DP_85D HDMI_CLK HDMI_CLK_N
DP_TBTSNK0_ML_N<3..0>DISPLAYPORTDP_85D
DP_TBTSNK1_AUXCH_C_NDP_85D
DP_85D HDMI_CLKHDMI_CLK HDMI_CLK_PDP_85DHDMI_DATA DISPLAYPORT HDMI_DATA_N<2..0>
DP_TBT_ML1 DISPLAYPORTDP_85D DP_TBTSNK1_ML_C_P<3..0>
DISPLAYPORTDP_85D DP_TBTSNK0_ML_P<3..0>DP_TBT_ML0 DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_N<3..0>DP_TBT_ML0 DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_P<3..0>
XDP_PRDY_L CPU_45S CPU_ITP XDP_CPU_PRDY_L
CPU_CATERR_LCPU_CATERR_L CPU_AGTLCPU_45S
FDI_INT CPU_50S FDI_INTCPU_AGTL
DMI_N2S CPU_85D DMI_N2S_P<3:0>DMI_N2S
CPU_85D DMI_S2NDMI_S2N DMI_S2N_P<3:0>
DP_INT_ML_P<3..0>DP_85D DISPLAYPORT
DISPLAYPORTDP_85D DP_INT_ML_C_P<3..0>DP_INT_IG_ML
DISPLAYPORT DP_INT_ML_C_N<3..0>DP_85DDP_INT_IG_ML
XDP_TDI XDP_CPU_TDICPU_ITPCPU_45S
CPU_COMP CPU_EDP_RCOMPCPU_27P4SCPU_EDP_COMP
DISPLAYPORT DP_INT_ML_N<3..0>DP_85D
DP_85D DISPLAYPORT DP_INT_ML_N<3..0>DP_85D DISPLAYPORT DP_INT_ML_P<3..0>
DP_INT_AUX_NDP_85D DISPLAYPORTDP_INT_AUXCH
DP_INT_AUXCH_C_PDP_INT_IG_AUX DP_85D DISPLAYPORT
DP_INT_IG_AUX DP_INT_AUXCH_C_NDP_85D DISPLAYPORT
DPB_IG_AUX_CH_NDP_85D DISPLAYPORTDP_INT_IG_AUX
DPB_IG_AUX_CH_PDP_INT_IG_AUX DISPLAYPORTDP_85D
DPA_IG_AUX_CH_NDP_INT_IG_AUX DISPLAYPORTDP_85D
DPA_IG_AUX_CH_PDISPLAYPORTDP_85DDP_INT_IG_AUX
dvt
051-0675
6.0.0
111 OF 119
86 OF 94
68 82
28 82
28 84
66 68
68 82
66 68
68
68
66 68 82
66 68 82
28 82
28 82
28 84
28 84
67 83 94
28 94
28 94
67 94
6 40 41 57
6 18 19
6 18
6 18
67 94
6 14 41
6 18 83
6 18 83
8 57
8 57
6
6 14 41
8 57
28 94
28 94
28 94
28 80 94
28 80 94
28 94
28 74 94
9 57
6 11
6 11
6 11
5 12
6 14 18
6 18 83
28 82
7 22
5 12 84
6 18 83
6 18 83
11 84
11 84
6 18 83
6 11
22 23 24 82 89
28 84
22 25 26 82
7 22
6 12
5
5 12 84
6 11
6 12 21
6 11
22 25 26 82
22 23 24 82 89
8 57
83
28 80 94
83
28 94
28 80 94
83
83
28 74 94
28 94
28 74 94
28 74 94
6 18 83
6 40
5 12
5 12 84
5 12 84
67 83 86 94
67 79 94
67 79 94
6 18 83
5
67 83 86 94
67 83 86 94
67 83 86 94
67 83 94
67 79 94
67 79 94
80 82
80 82
80 82
80 82
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
USB 3.0 INTERFACE CONSTRAINTS
USB 2.0 Interface Constraints
System Clock Signal Constraints
NOTE: 25MHz system clocks very sensitive to noise.
ELECTRICAL_CONSTRAINT_SET
Clock Net PropertiesNET_TYPE
PHYSICAL
PHYSICAL SPACING
NOTE: Latest Intel DG calls out 50ohms SE for sys clocks
ELECTRICAL_CONSTRAINT_SET SPACING
NET_TYPE
PCH Net Properties
SATA Interface Constraints
I213
I220
I221
I222
I223
I228
I229
I230
I231
I238
I239
I244
I245
I248
I249
I250
I251
I253
I254
I255
I256
I259
I260
I261
I262
I263
I264
I265
I266
I267
I268
I271
I272
I273
I274
I281
I282
I283
I284
I285
I286
I287
I288
I290
I291
I292
I293
I294
I295
I296
I297
I298
I299
I300
I301
I302
I303
=4X_DIELECTRIC ?BT_WAKE *
?*USB =4X_DIELECTRIC
?*USB_RBIAS =6X_DIELECTRIC
*USB3_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF
=10X_DIELECTRICTOP,BOTTOM ?SATA_TXRX
=6X_DIELECTRIC ?SATA_2OTHER TOP,BOTTOM
=6X_DIELECTRICUSB ?TOP,BOTTOM
TOP,BOTTOM ?=10X_DIELECTRICUSB_RBIAS
TOP,BOTTOM ?BT_WAKE =6X_DIELECTRIC
USB3_2SAME =3X_DIELECTRIC* ?
=6X_DIELECTRICUSB3_TXRX * ?
?=6X_DIELECTRICTOP,BOTTOMUSB3_2OTHER
TOP,BOTTOM ?USB3_TXRX =10X_DIELECTRIC
* =STANDARD=STANDARDCLK_SLOW_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE
* =STANDARDCLK_25M_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD=45_OHM_SE
USB3_2SAME=SAME *USB3_*
USB3_R2D USB3_D2R * USB3_TXRX
* *USB3_* USB3_2OTHER
TOP,BOTTOM ?=4x_DIELECTRICUSB3_2SAME
=5x_DIELECTRICCLK_25M * ?
=4x_DIELECTRICCLK_SLOW * ?
* =37_OHM_SE =37_OHM_SE=37_OHM_SE =37_OHM_SESATA_37SE =37_OHM_SE=37_OHM_SE
SATA_RCOMP =10X_DIELECTRICTOP,BOTTOM ?
* SATA_2OTHER*SATA_*
?*SATA_2SAME =3X_DIELECTRIC
=SAMESATA_* SATA_2SAME*
=6X_DIELECTRICSATA_RCOMP ?*
SATA_2OTHER ?* =4X_DIELECTRIC
=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFFUSB_85D * =85_OHM_DIFF
=STANDARD =STANDARD* =STANDARD=STANDARD =STANDARD =STANDARDPCH_USB_RBIAS
?*SATA_TXRX =6X_DIELECTRIC
* =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFFSATA_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF
SATA_TXRXSATA_R2D *SATA_D2R
*SATA_45SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE
=4x_DIELECTRICTOP,BOTTOMSATA_2SAME ?
* ?=4X_DIELECTRICUSB3_2OTHER
PCH Constraints 1SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
USB3_EXTA_R2D_C_PUSB3_R2DUSB_85D
USB_85D USB3_R2D USB3_EXTA_R2D_C_NUSB_85D USB3_D2RUSB3_EXTB_RX USB3_EXTB_D2R_P
USB3_EXTB_RX USB3_D2RUSB_85D USB3_EXTB_D2R_N
NC_USB3_EXTD_R2D_CNUSB3_R2DUSB_85D
USB_85D USB3_R2DUSB3_EXTA_TX USB3_EXTA_R2D_P
NC_USB_SDPUSB_NC USBUSB_85D
SYSCLK_CLK32K_RTCSYSCLK_CLK32K_RTC CLK_SLOWCLK_SLOW_45S
SYSCLK_CLK25M_SBSYSCLK_CLK25M_SB CLK_25MCLK_25M_45SSYSCLK_CLK25M_SB_RCLK_25MCLK_25M_45S
CLK_25M SYSCLK_CLK25M_CAMERASYSCLK_CLK25M_CAM CLK_25M_45S
NC_USB3 USB3_D2R NC_USB3_EXTD_D2RNUSB_85D
USB_85DUSB_NC USB NC_USB_6P
SYSCLK_CLK25M_TBT_RCLK_25MCLK_25M_45S
USB3_EXTB_TX USB3_EXTB_R2D_NUSB3_R2DUSB_85D
USB3_EXTA_RX USB_85D USB3_D2R USB3_EXTA_D2R_N
SYSCLK_CLK25M_TBT CLK_25M SYSCLK_CLK25M_TBTCLK_25M_45S
USB_85D USB3_EXTA_D2R_C_PUSB3_D2R
USB_85D USB3_R2D USB3_EXTB_R2D_C_N
USB_85DUSB3_EXTA_TX USB3_EXTA_R2D_NUSB3_R2D
USB_85D USB3_D2R USB3_EXTA_D2R_C_N
USB3_R2D NC_USB3_EXTD_R2D_CPUSB_85D
USB_85DNC_USB3 USB3_D2R NC_USB3_EXTD_D2RPUSB_85D USB3_R2D NC_USB3_EXTC_R2D_CN
USB3_R2D NC_USB3_EXTC_R2D_CPUSB_85D
USB_85D NC_USB3_EXTC_D2RNUSB3_D2RNC_USB3
USB_85DNC_USB3 USB3_D2R NC_USB3_EXTC_D2RP
USB_85D USB3_R2D USB3_EXTB_R2D_C_P
USB_85D USB3_D2R USB3_EXTB_D2R_C_P
USB3_EXTA_D2R_PUSB3_D2RUSB_85DUSB3_EXTA_RX
USB_BT USB USB_BT_PUSB_85D
USBUSB_85DUSB_NC NC_USB_EXTDN
USB_85D USB NC_USB_7NUSB_NC
PCH_USB_RBIAS PCH_USB_RBIAS USB_RBIAS PCH_USB_RBIAS
USB_85DUSB_NC USB NC_USB_IRP
USB_85DUSB_NC USB NC_USB_EXTDP
USB_85DUSB3_EXTB_TX USB3_R2D USB3_EXTB_R2D_PUSB3_D2R USB3_EXTB_D2R_C_NUSB_85D
USBUSB_85D USB_BT_CONN_NUSB USB_BT_CONN_PUSB_85D
USB_85D USBUSB_BT USB_BT_N
USB_85D USBUSB_SMC USB_SMC_N
NC_USB_EXTCNUSBUSB_85DUSB_NC
USB_SMC_PUSBUSB_SMC USB_85D
USBUSB_NC NC_USB_SDNUSB_85D
NC_SATA_A_D2RPSATA_85D SATA_D2R
NC_SATA_A_R2D_CPSATA_85D SATA_R2D
NC_SATA_B_D2RPSATA_D2RSATA_85D
NC_SATA_B_R2D_CNSATA_R2DSATA_85D
NC_SATA_A_D2RNSATA_85D SATA_D2R
NC_SATA_A_R2D_CNSATA_85D SATA_R2D
USB_EXTA USB_85D USB_EXTA_PUSBUSB_EXTA_NUSBUSB_EXTA USB_85D
CPU_45S SMC_DEBUGPRT_RX_LCPU_ITPSMC_DEBUGPRT_TX_LCPU_45S CPU_ITP
USB_EXTA USB_85D USB_EXTA_MUXED_NUSB
NC_SATA_B_R2D_CPSATA_R2DSATA_85D
USB_EXTA USB_LT1_NUSBUSB_85D
NC_SATA_B_D2RNSATA_D2RSATA_85D
SATA_RCOMP PCH_SATA_RCOMPSATA_45SEPCH_SATA_RCOMP
USB_EXTA USB_85D USB_EXTA_MUXED_PUSB
USB_EXTA USB_LT1_PUSBUSB_85D
USBUSB_NC NC_USB_EXTCPUSB_85D
USBUSB_85DUSB_NC NC_USB_IRN
USB_EXTB_PUSBUSB_85DUSB_EXTB
USB_EXTB USB_85D USB USB_EXTB_N
USB_85DUSB_NC USB NC_USB_7PNC_USB_6NUSB_85D USBUSB_NC
USB_85D USB USB_TPAD_NUSB_TPAD
USB_TPAD_PUSB_TPAD USBUSB_85D
USBUSB_85D USB_TPAD_R_NUSB_85D USB USB_TPAD_R_P
dvt
051-0675
6.0.0
112 OF 119
87 OF 94
13 37
13 37
13 78 83
13 78 83
84
37
84
11 19
11 19
11
19 36
84
84
28
78 83
13 37
19 28
13 78
37
84
84
84
84
84
84
13 78
13 37
13 33
84
84
13
84
84
78 83
33 83
33 83
13 33
84
84
84
84
84
84
84
84
84
84
13 37
13 37
37 40 41
37 40 41
37
84
37
84
11
37
37
84
84
13 78 83
13 78 83
84
84
13 38
13 38
38
38
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LPC Bus Constraints
HD Audio Interface Constraints
ELECTRICAL_CONSTRAINT_SET
PCI-Express
PCH Single Net Constraints
SPI Interface Constraints
ELECTRICAL_CONSTRAINT_SET SPACINGPHYSICAL
PCH Net PropertiesNET_TYPE
PHYSICAL
NET_TYPE
SPACING
PCH Net Properties
SMBus Interface Constraints
I253
I254
I255
I256
I257
I258
I259
I260
I261
I262
I275
I276
I281
I282
I293
I298
I299
I300
I303
I304
I307
I308
I313
I314
I315
I316
I317
I318
I319
I320
I321
I322
I323
I324
I325
I326
I327
I328
I329
I330
I331
I332
I333
I334
I335
I336
I337
I338
I339
I340
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/2013
PCH Constraints 2
=85_OHM_DIFF =85_OHM_DIFFCLK_PCIE_85D * =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF
=85_OHM_DIFF=85_OHM_DIFFPCIE_85D =85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF=85_OHM_DIFF
TOP,BOTTOM ?PCIE_2OTHER =6X_DIELECTRIC
TOP,BOTTOM ?PCIE_2CLK =10X_DIELECTRIC
* ?=2x_DIELECTRICHDA
=45_OHM_SE=45_OHM_SE=45_OHM_SE =STANDARD* =STANDARDSPI_45S =45_OHM_SE
=2X_DIELECTRIC* ?PCIE_2SAME
=6X_DIELECTRIC ?*PCIE_TXRX
PCIE_TXRXPCIE_R2D *PCIE_D2R
=STANDARD* =STANDARD=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SEHDA_45S
8 MIL*CLK_LPC ?
=STANDARD* =STANDARDLPC_45S =45_OHM_SE =45_OHM_SE=45_OHM_SE =45_OHM_SE
=45_OHM_SE =45_OHM_SE* =STANDARD =STANDARDPCH_45S =45_OHM_SE =45_OHM_SE
TOP,BOTTOM =3x_DIELECTRICPCH_SE ?=2x_DIELECTRIC ?*PCH_SE
TOP,BOTTOM ?=10X_DIELECTRICPCIE_TXRX
?=4X_DIELECTRICTOP,BOTTOMPCIE_2SAME
PCIE_2SAMEPCIE_* *=SAME
8 MIL ?SPI *
PCIE_2OTHERPCIE_* **
CLK_* *PCIE_* PCIE_2CLK
* *CLK_PCIE PCIECLK_2OTHER
PCIECLK_2OTHER ?* =7X_DIELECTRIC
?=7X_DIELECTRIC*PCIE_2CLK
=4X_DIELECTRICPCIE_2OTHER ?*
?TOP,BOTTOMPCIECLK_2OTHER =10X_DIELECTRIC
?=2x_DIELECTRIC*SMB
=45_OHM_SE =STANDARD* =STANDARD=45_OHM_SE =45_OHM_SE =45_OHM_SESMB_45S
LPC ?* 6 MIL
=45_OHM_SE* =STANDARD =STANDARD=45_OHM_SECLK_LPC_45S =45_OHM_SE =45_OHM_SE
SPI_CS0_R_LSPISPI_45S
CPU_45SPCIE_CLK100M PCH_CLK33M_PCIINCLK_PCIE
PCIE_CAMERA_R2D_NPCIE_R2DPCIE_85DPCIE_CAMERA_R2D
PEG_CLK100M PEG_80D PEG_CLK100M_NCLK_PCIE
PEG_80DPEG_CLK100M PEG_CLK100M_PCLK_PCIE
PCIE_CLK100M_TBT CLK_PCIE PCIE_CLK100M_TBT_NCLK_PCIE_85DPCH_CLK96M_DOT_PCLK_PCIE_85D CLK_PCIEPCIE_CLK100M_DOT
PCIE_CLK100M_SATA PCIE_85D CLK_PCIE PCH_CLK100M_SATA_PCLK_PCIEPCIE_CLK100M_SATA PCIE_85D PCH_CLK100M_SATA_N
CLK_PCIE PCIE_CLK100M_SSD_NCLK_PCIE_85D
CLK_PCIE PCIE_CLK100M_SSD_PPCIE_CLK100M_ENET PCIE_85D
SML_PCH_0_CLKSMBSMBUS_PCH_0_CLK SMB_45S
HDA_BIT_CLK_RHDAHDA_45S
PCH_PM_NET PCH_SRTCRST_LPCH_SEPCH_45S
PCH_PM_NET PCH_45S PM_RSMRST_LPCH_SE
PCH_PM_NET PCH_45S PM_SYSRST_LPCH_SE
PCH_PM_NET PCH_SEPCH_45S PM_PCH_APWROK
PCH_PM_NET PCH_45S PM_PCH_SYS_PWROKPCH_SE
PCH_45SPCH_PCIE_WAKE PCIE_WAKE_LPCH_SE
HDA_45S HDA_SYNC_RHDAHDA_RST_R_LHDAHDA_45S
HDA_SYNCHDA_SYNC HDAHDA_45S
HDA_BIT_CLKHDA_BIT_CLK HDAHDA_45S
SML_PCH_1_CLKSMBUS_PCH_1_CLK SMBSMB_45S
PCIE_D2RPCIE_85D PCIE_AP_D2R_PI_P
PCIE_R2DPCIE_85D PCIE_AP_R2D_PI_N
SMBUS_PCH_CLK SMBUS_PCH_CLKSMBSMB_45S
SPI_CS0_LSPI_CS0 SPISPI_45S
HDAHDA_45S CS4208_HDA_SDOUT0_RHDA_SDIN0_R
LPC_FRAME_LLPC_FRAME_L LPCLPC_45S
CPU_45SPCIE_CLK100M CLK_PCIE PCH_CLK33M_PCIOUT
PCIE_CLK100M_S2 CLK_PCIE_85D CLK_PCIE PCIE_CLK100M_CAMERA_N
PCIE_AP_D2R_PI_NPCIE_D2RPCIE_85D
LPC LPC_AD<3..0>LPC_AD LPC_45S
LPC_RESET_L LPC LPC_RESET_LLPC_45S
SPI_CLKSPISPI_45SSPI_CLK
PCIE_85D CLK_PCIE PCIE_CLK100M_AP_CONN_P
SPI_MISO SPI_MISOSPISPI_45S
USB3_D2RUSB3_SD_D2R USB3_85D USB3_SD_D2R_N
PCIE_CAMERA_R2D_PPCIE_R2DPCIE_85DPCIE_CAMERA_R2D
PCIE_R2D PCIE_AP_R2D_NPCIE_85DPCIE_AP_R2D
PCIE_85D PCIE_CAMERA_R2D_C_NPCIE_R2D
PCIE_CAMERA_D2R_C_NPCIE_D2RPCIE_85D
CLK_PCIEPCIE_CLK100M_PCH PCIE_CLK100M_PCH_NCLK_PCIE_85D
SPI_MOSI_RSPISPI_45S
HDA HDA_SDOUT_RHDA_45S
SPI_CLK_RSPISPI_45S
USB3_SD_R2D_C_NUSB3_SD_R2D USB3_R2DUSB3_85D
USB3_SD_R2D_C_PUSB3_R2DUSB3_85DUSB3_SD_R2D
PCIE_R2DPCIE_85D PCIE_AP_R2D_C_P
PCIE_CAMERA_D2R_NPCIE_D2RPCIE_CAMERA_D2R PCIE_85D
PCIE_CAMERA_D2R PCIE_85D PCIE_CAMERA_D2R_PPCIE_D2R
PCIE_R2D PCIE_CAMERA_R2D_C_PPCIE_85D
PCIE_D2RPCIE_85D PCIE_AP_D2R_NPCIE_AP_D2R
PCIE_AP_R2D_PI_PPCIE_R2DPCIE_85D
SPI_MOSISPISPI_MOSI SPI_45S
PCH_PM_NET PCH_45S PCH_INTVRMEN_LPCH_SE
PCH_PM_NET PCH_45S PCH_INTRUDER_LPCH_SE
PCH_PM_NET PCH_45S PM_DSW_PWRGDPCH_SE
PCH_45SPCH_PM_NET PCH_DSWVRMENPCH_SE
PCH_PM_NET PCH_45S PCH_SE PM_PCH_PWROK
PCH_PM_NET PCH_45S PM_PWRBTN_LPCH_SE
PCH_PM_NET PCH_45S PCH_SE PM_THRMTRIP_L_R
PCIE_D2RPCIE_85D PCIE_CAMERA_D2R_C_P
SMBUS_PCH_DATASMBUS_PCH_DATA SMBSMB_45S
SMBUS_PCH_0_DATA SMB_45S SML_PCH_0_DATASMB
SML_PCH_1_DATASMBSMBUS_PCH_1_DATA SMB_45S
HDAHDA_SDIN0 HDA_SDIN0HDA_45S
PCIE_85D PCIE_R2D PCIE_SSD_R2D_P<3..0>
PCH_45S PCH_SE PCH_RCIN_LPCH_PM_NET
PCIE_85DPCIE_R2D_SSD PCIE_SSD_R2D_C_N<3..0>PCIE_R2D
PCIE_85D PCIE_R2DPCIE_R2D_SSD PCIE_SSD_R2D_C_P<3..0>PCIE_85DPCIE_D2R_SSD PCIE_SSD_D2R_N<3..0>PCIE_D2R
PCIE_85D PCIE_R2D PCIE_SSD_R2D_N<3..0>
PCIE_85DPCIE_D2R_SSD PCIE_D2R PCIE_SSD_D2R_P<3..0>
CLK_PCIEPCIE_CLK100M_TBT CLK_PCIE_85D PCIE_CLK100M_TBT_P
HDA_RST_LHDAHDA_RST_L HDA_45S
HDAHDA_SDOUT HDA_SDOUTHDA_45S
PCIE_AP_R2D_C_NPCIE_R2DPCIE_85D
PCIE_D2RPCIE_85D PCIE_AP_D2R_PPCIE_AP_D2R
PCIE_AP_R2D_PPCIE_AP_R2D PCIE_85D PCIE_R2D
USB3_SD_D2R_PUSB3_D2RUSB3_SD_D2R USB3_85D
CLK_LPC_45S CLK_LPC LPC_CLK33M_SMC_R
CLK_PCIECLK_PCIE_85D PCIE_CLK100M_CAMERA_C_NCLK_PCIECLK_PCIE_85D PCIE_CLK100M_CAMERA_C_P
CLK_PCIE_85D CLK_PCIEPCIE_CLK100M_S2 PCIE_CLK100M_CAMERA_PPCIE_85D CLK_PCIE PCIE_CLK100M_AP_CONN_N
PCIE_CLK100M_AP PCIE_85D CLK_PCIE PCIE_CLK100M_AP_N
PCIE_CLK100M_DOT CLK_PCIECLK_PCIE_85D PCH_CLK96M_DOT_N
PCIE_CLK100M_PCH_PCLK_PCIEPCIE_CLK100M_PCH CLK_PCIE_85D
LPC_CLK33M_LPCPLUS_RCLK_LPC_45S CLK_LPC
PCH_LPC_CLK0 CLK_LPC_45S LPC_CLK33M_LPCPLUSCLK_LPC
CLK_LPC_45SPCH_LPC_CLK0 CLK_LPC LPC_CLK33M_SMC
PCIE_CLK100M_AP CLK_PCIE PCIE_CLK100M_AP_PPCIE_85D
CPU_45SPCIE_CLK100M PCH_CLK14P3M_REFCLKCLK_PCIE
dvt
051-0675
6.0.0
113 OF 119
88 OF 94
13 49
11 19
35 36
68 82 83
68 82 83
11 28
11
11
11
11 34
11 34
13 43
11
11
12 65 83
12 19 40 83
12 19
12 18 19 40 83
12 33 35 83
11
11
11 51
11 51
13 43
33 83
33
13 43 83
49
51
13 40 49 79 83
11 19
11 36
33 83
13 40 49 79 83
20
49
33 83
13 49
20 78 83
35 36
33 83
13 36
35 36
11
13 49
11 19
13 49
20 78 83
20 78 83
13 33
13 36
13 36
13 36
13 33
33
49
11
11
12 40 83
12
12 19 83
12 18 40
14 41
35 36
13 43 83
13 43
13 43
11 51
34
14
13 34
13 34
13 34
34
13 34
11 28
11 51
11 51
13 33
13 33
33 83
20 78 83
11 19
35 36
35 36
11 36
33 83
11 33
11
11
11 19
19 49 83
19 40
11 33
11
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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IV ALL RIGHTS RESERVED
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DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DQ signals should be matched within 0.508mm of associated DQS pair
DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
Memory Bus Spacing Group Assignments
Memory Bus ConstraintsELECTRICAL_CONSTRAINT_SET
Memory Net PropertiesSPACINGPHYSICAL
Spacing Rule Sets
Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.
SOURCE: Need to re-confirm CRW DG for memory down (Intel not yet provided)
A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.
NET_TYPE
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
SOURCE: Double checked with Doc#486985 Chief River SFF Platform DG: Memory Down
DDR3 (Memory Down):
Memory to Power Spacing
Memory to GND Spacing
I101
I103
I105
I106
I108
I109
I110
I111
I112
I113
I114
I115
I116
I117
I118
I119
I120
I121
I122
I123
I124
I125
I126
I127
I128
I129
I130
MEM_*_DATA_* ** MEM_2OTHER
MEM_*_DQS_* MEM_2OTHER**
MEM_CMD * MEM_2OTHER*
MEM_A_DATA_7MEM_A_DQS_7 MEM_DQS2OWNDATA*
MEM_B_DATA_1 * MEM_DQS2OWNDATAMEM_B_DQS_1
MEM_B_DATA_3MEM_B_DQS_3 MEM_DQS2OWNDATA*
MEM_DQS2OWNDATAMEM_B_DATA_5MEM_B_DQS_5 *
MEM_B_DATA_7MEM_B_DQS_7 MEM_DQS2OWNDATA*
MEM_CLK2CLKMEM_CLKMEM_CLK *
MEM_CMD MEM_CMD2CTRLMEM_CTRL *
=10x_DIELECTRIC ?MEM_2OTHER TOP,BOTTOM
=4x_DIELECTRIC ?TOP,BOTTOMMEM_2GND
=4x_DIELECTRIC ?MEM_2PWR TOP,BOTTOM
=5x_DIELECTRIC ?TOP,BOTTOMMEM_CMD2CTRL
=5x_DIELECTRIC ?TOP,BOTTOMMEM_DQS2OWNDATA
MEM_37S =37_OHM_SE=37_OHM_SE =STANDARD* =STANDARD=37_OHM_SE =37_OHM_SE
=72_OHM_DIFF=72_OHM_DIFF*MEM_72D =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF
=STANDARD=STANDARD* =45_OHM_SE =45_OHM_SE =45_OHM_SEMEM_45S =45_OHM_SE
=85_OHM_DIFFMEM_85D * =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF
* =STANDARDMEM_40S =40_OHM_SE=40_OHM_SE=40_OHM_SE =STANDARD=40_OHM_SE
MEM_2GND * =2x_DIELECTRIC ?
* ?=6x_DIELECTRICMEM_2OTHER
MEM_2OTHER*MEM_CLK *
MEM_A_DQS_3 MEM_A_DATA_3 * MEM_DQS2OWNDATA
MEM_CLK2CLK TOP,BOTTOM =8x_DIELECTRIC ?
MEM_CTRL2CTRL ?TOP,BOTTOM =5x_DIELECTRIC
MEM_DATA2SELF ?TOP,BOTTOM =5x_DIELECTRIC
=4x_DIELECTRIC ?*MEM_CLK2CLK
MEM_A_DQS_0 *MEM_A_DATA_0 MEM_DQS2OWNDATA
=5x_DIELECTRIC ?MEM_CMD2CMD TOP,BOTTOM
MEM_2OTHER*MEM_CTRL *
MEM_A_DQS_1 MEM_A_DATA_1 * MEM_DQS2OWNDATA
MEM_A_DQS_2 MEM_A_DATA_2 * MEM_DQS2OWNDATA
MEM_DQS2OWNDATAMEM_A_DATA_5MEM_A_DQS_5 *
MEM_A_DATA_4MEM_A_DQS_4 MEM_DQS2OWNDATA*
MEM_A_DATA_6 MEM_DQS2OWNDATA*MEM_A_DQS_6
MEM_B_DATA_0MEM_B_DQS_0 * MEM_DQS2OWNDATA
MEM_B_DQS_2 MEM_DQS2OWNDATA*MEM_B_DATA_2
MEM_DQS2OWNDATAMEM_B_DATA_4MEM_B_DQS_4 *
MEM_B_DATA_6MEM_B_DQS_6 MEM_DQS2OWNDATA*
MEM_CMD2CMDMEM_CMD MEM_CMD *
*MEM_*_DATA_* =SAME MEM_DATA2SELF
MEM_* MEM_* * MEM_2OTHERMEM
MEM_2PWR*MEM_*MEM_PWR
DEFAULTMEM_PWR **
MEM_2GNDMEM_* *GND
* ?MEM_CMD2CTRL =2x_DIELECTRIC
=2x_DIELECTRIC ?*MEM_CMD2CMD
MEM_CTRL2CTRL * ?=2x_DIELECTRIC
*MEM_2OTHERMEM ?=4x_DIELECTRIC
*MEM_DQS2OWNDATA =2x_DIELECTRIC ?
?* =2x_DIELECTRICMEM_DATA2SELF
MEM_2PWR ?* =2x_DIELECTRIC
MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL
MEM_2OTHERMEM TOP,BOTTOM =8x_DIELECTRIC ?
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
Memory Constraints
MEM_85DMEM_A_DQS2 MEM_A_DQS_N<2>MEM_A_DQS_2
MEM_85D MEM_A_DQS_N<4>MEM_A_DQS_4MEM_A_DQS4
MEM_85D MEM_A_DQS_N<7>MEM_A_DQS7 MEM_A_DQS_7
MEM_45S MEM_B_DATA_1 MEM_B_DQ<15..8>MEM_B_DATA_1
MEM_45S MEM_B_DQ<23..16>MEM_B_DATA_2MEM_B_DATA_2
MEM_B_DQ<39..32>MEM_B_DATA_4 MEM_B_DATA_4MEM_45S
MEM_45S MEM_B_DQ<47..40>MEM_B_DATA_5 MEM_B_DATA_5
MEM_85DMEM_A_DQS0 MEM_A_DQS_P<0>MEM_A_DQS_0
MEM_85D MEM_A_DQS_N<0>MEM_A_DQS0 MEM_A_DQS_0
MEM_B_CMD MEM_B_A<15..0>MEM_40S MEM_CMDMEM_B_BA<2..0>MEM_CMDMEM_B_CMD MEM_40S
MEM_B_DATA_0 MEM_B_DATA_0 MEM_B_DQ<7..0>MEM_45S
MEM_A_CLK0 MEM_A_CLK_P<0>MEM_CLKMEM_72D
MEM_A_CLK0 MEM_A_CLK_N<0>MEM_CLKMEM_72D
MEM_A_CLK1 MEM_A_CLK_P<1>MEM_CLKMEM_72D
MEM_A_CNTL0 MEM_A_CKE<0>MEM_CTRLMEM_40S
MEM_A_CNTL0 MEM_A_CS_L<0>MEM_40S MEM_CTRL
MEM_A_CMD MEM_A_A<15..0>MEM_40S MEM_CMD
MEM_40SMEM_A_CNTL1 MEM_A_ODT<1>MEM_CTRL
MEM_A_CNTL0 MEM_A_ODT<0>MEM_40S MEM_CTRL
MEM_A_CMD MEM_CMDMEM_40S MEM_A_BA<2..0>
MEM_A_CS_L<1>MEM_40S MEM_CTRLMEM_A_CNTL1
MEM_85D MEM_B_DQS_N<2>MEM_B_DQS2 MEM_B_DQS_2
MEM_85D MEM_B_DQS_P<4>MEM_B_DQS4 MEM_B_DQS_4
MEM_85D MEM_B_DQS_N<5>MEM_B_DQS5 MEM_B_DQS_5
MEM_85D MEM_B_DQS_N<7>MEM_B_DQS7 MEM_B_DQS_7
MEM_85DMEM_A_DQS5 MEM_A_DQS_P<5>MEM_A_DQS_5
MEM_A_DQS_N<3>MEM_85DMEM_A_DQS3 MEM_A_DQS_3
MEM_A_CKE<1>MEM_40S MEM_CTRLMEM_A_CNTL1
MEM_B_CLK0 MEM_B_CLK_P<0>MEM_72D MEM_CLK
MEM_85D MEM_B_DQS_P<7>MEM_B_DQS7 MEM_B_DQS_7
MEM_85D MEM_B_DQS_N<6>MEM_B_DQS_6MEM_B_DQS6
MEM_85D MEM_B_DQS_P<6>MEM_B_DQS_6MEM_B_DQS6
MEM_85D MEM_B_DQS_3 MEM_B_DQS_N<3>MEM_B_DQS3
MEM_85D MEM_B_DQS_P<3>MEM_B_DQS3 MEM_B_DQS_3
MEM_85D MEM_B_DQS_P<2>MEM_B_DQS_2MEM_B_DQS2
MEM_85D MEM_B_DQS_P<1>MEM_B_DQS_1MEM_B_DQS1
MEM_85D MEM_B_DQS_N<0>MEM_B_DQS_0MEM_B_DQS0
MEM_85D MEM_B_DQS_N<1>MEM_B_DQS1 MEM_B_DQS_1
MEM_85D MEM_B_DQS_P<0>MEM_B_DQS_0MEM_B_DQS0
MEM_B_CS_L<0>MEM_40SMEM_B_CNTL0 MEM_CTRL
MEM_B_CNTL0 MEM_B_ODT<0>MEM_40S MEM_CTRL
MEM_B_CLK_P<1>MEM_72D MEM_CLKMEM_B_CLK1
MEM_CLK MEM_B_CLK_N<0>MEM_B_CLK0 MEM_72D
MEM_A_CLK1 MEM_A_CLK_N<1>MEM_CLKMEM_72D
MEM_85DMEM_A_DQS7 MEM_A_DQS_P<7>MEM_A_DQS_7
MEM_85DMEM_A_DQS4 MEM_A_DQS_4 MEM_A_DQS_P<4>
MEM_45S MEM_A_DQ<39..32>MEM_A_DATA_4 MEM_A_DATA_4
MEM_85D MEM_A_DQS_N<1>MEM_A_DQS1 MEM_A_DQS_1
MEM_45SMEM_A_DATA_7 MEM_A_DQ<63..56>MEM_A_DATA_7
MEM_45S MEM_A_DQ<47..40>MEM_A_DATA_5 MEM_A_DATA_5
MEM_A_DQS3 MEM_85D MEM_A_DQS_P<3>MEM_A_DQS_3
MEM_85D MEM_A_DQS_N<5>MEM_A_DQS_5MEM_A_DQS5
MEM_85D MEM_A_DQS_P<6>MEM_A_DQS6 MEM_A_DQS_6
MEM_45S MEM_B_DATA_6MEM_B_DATA_6 MEM_B_DQ<55..48>MEM_45S MEM_B_DQ<63..56>MEM_B_DATA_7MEM_B_DATA_7
MEM_85D MEM_B_DQS_N<4>MEM_B_DQS4 MEM_B_DQS_4
MEM_85D MEM_B_DQS_P<5>MEM_B_DQS_5MEM_B_DQS5
PP1V35_S3_MEMMEM_PWRMEM_PWR PPVREF_S3_MEM_VREFCA_AMEM_PWR PPVREF_S3_MEM_VREFDQ_A
MEM_85DMEM_A_DQS1 MEM_A_DQS_P<1>MEM_A_DQS_1
MEM_40SMEM_A_CMD MEM_A_CAS_LMEM_CMD
MEM_40SMEM_A_CMD MEM_CMD MEM_A_RAS_L
MEM_40S MEM_A_WE_LMEM_A_CMD MEM_CMD
MEM_45S MEM_A_DQ<7..0>MEM_A_DATA_0 MEM_A_DATA_0
MEM_45S MEM_A_DQ<15..8>MEM_A_DATA_1 MEM_A_DATA_1
MEM_45S MEM_A_DQ<23..16>MEM_A_DATA_2 MEM_A_DATA_2
MEM_45S MEM_A_DQ<31..24>MEM_A_DATA_3 MEM_A_DATA_3
MEM_45S MEM_A_DQ<55..48>MEM_A_DATA_6 MEM_A_DATA_6
MEM_85D MEM_A_DQS_P<2>MEM_A_DQS2 MEM_A_DQS_2
MEM_85D MEM_A_DQS_N<6>MEM_A_DQS6 MEM_A_DQS_6
MEM_B_CS_L<1>MEM_40SMEM_B_CNTL1 MEM_CTRL
MEM_B_RAS_LMEM_CMDMEM_B_CMD MEM_40SMEM_B_CAS_LMEM_CMDMEM_B_CMD MEM_40SMEM_B_WE_LMEM_B_CMD MEM_CMDMEM_40S
MEM_B_DATA_3 MEM_B_DQ<31..24>MEM_B_DATA_3 MEM_45S
MEM_B_ODT<1>MEM_40SMEM_B_CNTL1 MEM_CTRL
MEM_B_CKE<1>MEM_40SMEM_B_CNTL1 MEM_CTRL
MEM_B_CKE<0>MEM_CTRLMEM_40SMEM_B_CNTL0
MEM_B_CLK_N<1>MEM_CLKMEM_72DMEM_B_CLK1
dvt
051-0675
6.0.0
114 OF 119
89 OF 94
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LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Only used on dual-port hosts.
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL SPACING
Thunderbolt IC Net Properties
Only used on hosts supporting Thunderbolt video-in
SPACING
Thunderbolt SPI Signal Constraints
TBT_DP Interface Constraints
NET_TYPE
SOURCE: Bill Cornelius’s Thunderbolt Routing Notes
Thunderbolt/DP Connector Signal Constraints
DisplayPort Signal ConstraintsNOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
ELECTRICAL_CONSTRAINT_SET PHYSICAL
Thunderbolt/DP Net Properties
I308
I309
I310
I311
I312
I313
I314
I315
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I321
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=STANDARD =STANDARD*TBT_SPI_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE
?TOP,BOTTOMTBTDP_TXRX =10X_DIELECTRIC
TBTDP_2SAME*=SAMETBTDP_*
=4x_DIELECTRIC ?TBTDP_2SAME TOP,BOTTOM
TBTDP_85D =85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF
TBTDP_2OTHER TOP,BOTTOM ?=6X_DIELECTRIC
* *TBTDP_* TBTDP_2OTHER
*TBTDP_R2D TBTDP_D2R TBTDP_TXRX
=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFFTBTDP_85D
TBT_SPI =2x_DIELECTRIC* ?
=3X_DIELECTRIC*TBTDP_2SAME ?
=6X_DIELECTRIC* ?TBTDP_TXRX
TBTDP_2OTHER ?* =4X_DIELECTRIC
Thunderbolt ConstraintsSYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
DP_TBTPA_ML_P<3>DP_TBTPA_ML DP_85D DISPLAYPORT
TBT_A_AUXCH DP_TBTPA_AUXCH_NDP_85D
TBTDP_85D TBTDP_R2D TBT_B_R2D_C_P<1..0>TBT_B_R2D
TBTDP_85D TBTDP_R2D TBT_B_R2D_N<1..0>TBT_B_R2D
TBTDP_D2RTBTDP_85D TBT_B_D2R_C_N<0>TBT_B_D2R0
TBTDP_85D TBTDP_R2D TBT_B_R2D_P<1..0>TBT_B_R2D
DP_B_LSX_ML DP_85D DISPLAYPORT DP_TBTPB_ML_C_P<1>
DP_85D DP_TBTPB_AUXCH_NTBT_B_AUXCH
DP_85D DP_TBTPB_AUXCH_PTBT_B_AUXCH
DP_85D DP_TBTPB_AUXCH_C_NTBT_B_AUXCH
DP_85D DP_TBTPB_AUXCH_C_PTBT_B_AUXCH
TBTDP_D2RTBTDP_85D TBT_B_D2R1_AUXDDC_NTBT_B_D2R1
TBTDP_D2RTBTDP_85D TBT_B_D2R1_AUXDDC_PTBT_B_D2R1
TBTDP_85D TBTDP_D2R TBT_B_D2R_N<1>TBT_B_D2R1
TBTDP_85D TBTDP_D2R TBT_B_D2R_P<1>TBT_B_D2R1
TBTDP_85D TBTDP_R2D TBT_B_R2D_C_N<1..0>TBT_B_R2D
TBTDP_D2RTBTDP_85D TBT_B_D2R_C_P<1>TBT_B_D2R1
TBTDP_D2RTBTDP_85D TBT_B_D2R_C_N<1>TBT_B_D2R1
TBTDP_85D TBTDP_D2R TBT_B_D2R_N<0>TBT_B_D2R0
TBTDP_85D TBTDP_D2R TBT_B_D2R_P<0>TBT_B_D2R0
DP_85D DISPLAYPORT DP_TBTPB_ML_N<3>DP_TBTPB_ML
TBTDP_D2RTBTDP_85D TBT_B_D2R_C_P<0>TBT_B_D2R0
DP_85D DISPLAYPORT DP_TBTPB_ML_P<3>DP_TBTPB_ML
DP_85D DISPLAYPORT DP_TBTPB_ML_C_N<3>DP_TBTPB_ML
DP_85D DISPLAYPORT DP_TBTPB_ML_C_P<3>DP_TBTPB_ML
DP_B_LSX_ML DP_85D DISPLAYPORT DP_B_LSX_ML_N<1>DP_B_LSX_ML DP_85D DISPLAYPORT DP_B_LSX_ML_P<1>DP_B_LSX_ML DP_85D DISPLAYPORT DP_TBTPB_ML_N<1>DP_B_LSX_ML DP_85D DISPLAYPORT DP_TBTPB_ML_P<1>DP_B_LSX_ML DP_85D DISPLAYPORT DP_TBTPB_ML_C_N<1>
DP_A_LSX_ML DP_A_LSX_ML_N<1>DISPLAYPORTDP_85D
TBT_A_D2R0 TBTDP_85D TBTDP_D2R TBT_A_D2R_C_P<0>
TBT_A_D2R0 TBT_A_D2R_N<0>TBTDP_D2RTBTDP_85D
TBT_A_D2R1 TBTDP_85D TBTDP_D2R TBT_A_D2R_P<1>
TBT_SPI_45S TBT_SPITBT_SPI_MISO TBT_SPI_MISOTBT_SPI_45STBT_SPI_CS_L TBT_SPI_CS_LTBT_SPI
TBT_SPI_45S TBT_SPITBT_SPI_MOSI TBT_SPI_MOSITBT_SPI_45STBT_SPI_CLK TBT_SPI_CLKTBT_SPI
DP_85D DP_TBTSRC_AUXCH_C_NDISPLAYPORT
DP_85D DISPLAYPORT DP_TBTSRC_AUXCH_C_PDP_85D DISPLAYPORT DP_TBTSRC_ML_C_N<3..0>DP_85D DP_TBTSRC_ML_C_P<3..0>DISPLAYPORT
TBT_A_D2R1 TBT_A_D2R_C_N<1>TBTDP_85D TBTDP_D2R
TBTDP_85DTBT_A_D2R1 TBT_A_D2R_N<1>TBTDP_D2R
TBTDP_85DTBT_A_D2R1 TBT_A_D2R1_AUXDDC_PTBTDP_D2R
TBT_A_D2R1 TBTDP_85D TBT_A_D2R1_AUXDDC_NTBTDP_D2R
TBT_A_AUXCH DP_TBTPA_AUXCH_C_PDP_85D
TBT_A_D2R1 TBT_A_D2R_C_P<1>TBTDP_85D TBTDP_D2R
DP_TBTPA_ML_C_P<3>DP_TBTPA_ML DISPLAYPORTDP_85D
TBTDP_85DTBT_A_R2D TBT_A_R2D_C_P<1..0>TBTDP_R2D
DP_A_LSX_ML DISPLAYPORTDP_85D DP_TBTPA_ML_C_P<1>
DP_A_LSX_ML DISPLAYPORTDP_85D DP_A_LSX_ML_P<1>DP_A_LSX_ML DISPLAYPORTDP_85D DP_TBTPA_ML_N<1>DP_A_LSX_ML DP_85D DISPLAYPORT DP_TBTPA_ML_P<1>
TBTDP_85DTBT_A_R2D TBT_A_R2D_C_N<1..0>TBTDP_R2D
DP_A_LSX_ML DP_85D DISPLAYPORT DP_TBTPA_ML_C_N<1>
DP_TBTPA_ML_C_N<3>DP_TBTPA_ML DISPLAYPORTDP_85D
DP_TBTPA_ML DP_85D DISPLAYPORT DP_TBTPA_ML_N<3>
TBTDP_D2RTBT_A_D2R0 TBT_A_D2R_C_N<0>TBTDP_85D
TBT_A_D2R0 TBT_A_D2R_P<0>TBTDP_D2RTBTDP_85D
TBT_A_AUXCH DP_TBTPA_AUXCH_C_NDP_85D
TBT_A_AUXCH DP_TBTPA_AUXCH_PDP_85D
TBTDP_85D TBTDP_R2D TBT_A_R2D_P<1..0>TBT_A_R2D
TBTDP_85DTBT_A_R2D TBT_A_R2D_N<1..0>TBTDP_R2D
dvt
051-0675
6.0.0
115 OF 119
90 OF 94
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32
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31
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Memory Bus Constraints
NET_TYPE
PHYSICAL SPACING
Memory to GND Spacing
Memory to Power Spacing
Spacing Rule Sets
ELECTRICAL_CONSTRAINT_SET
MIPI Interface Constraints
Memory Bus Spacing Group Assignments
Camera Net Properties
I101
I102
I103
I104
I106
I107
I108
I109
I110
I127
I128
I129
I130
I131
I132
I133
I134
I145
I146
I147
I148
I149
TOP,BOTTOM =10x_DIELECTRIC ?S2MEM_2OTHER
TOP,BOTTOM ?S2MEM_2PWR =4x_DIELECTRIC
=4x_DIELECTRICS2_CMD2CTRL ?TOP,BOTTOM
MIPICLK_2OTHER =10X_DIELECTRICTOP,BOTTOM ?
MIPI_2CLK =8X_DIELECTRIC ?TOP,BOTTOM
=6X_DIELECTRIC ?TOP,BOTTOMMIPI_2OTHER
S2_DATA2SELF ?=4x_DIELECTRICTOP,BOTTOM
=4x_DIELECTRICS2_DQS2OWNDATA ?TOP,BOTTOM
S2_CMD2CMD ?TOP,BOTTOM =4x_DIELECTRIC
TOP,BOTTOM =6x_DIELECTRIC ?S2_2OTHERMEM
?=4x_DIELECTRICTOP,BOTTOMS2MEM_2GND
S2_CTRL2CTRL ?TOP,BOTTOM =4x_DIELECTRIC
S2_CMD2CMD * ?=2x_DIELECTRIC
=2x_DIELECTRICS2_CTRL2CTRL * ?
=2x_DIELECTRICS2_CMD2CTRL ?*
?* =4x_DIELECTRICS2_2OTHERMEM
S2_DQS2OWNDATA * ?=2x_DIELECTRIC
S2MEM_2PWR =2x_DIELECTRIC* ?
* ?S2_DATA2SELF =2x_DIELECTRIC
* S2_CMD2CTRLS2_MEM_CTRLS2_MEM_CMD
S2MEM_2OTHER* *S2_MEM_DQS*
**S2_MEM_DATA* S2MEM_2OTHER
S2_MEM_DATA* S2_DATA2SELF*=SAME
*S2_MEM_PWR S2_MEM_* S2MEM_2PWR
DEFAULT* *S2_MEM_PWR
*S2_MEM_DATA0 S2_DQS2OWNDATAS2_MEM_DQS0
S2_MEM_CMD * * S2MEM_2OTHER
**S2_MEM_CTRL S2MEM_2OTHER
* S2MEM_2OTHER*S2_MEM_CLK
*S2_MEM_CMD S2_CMD2CMDS2_MEM_CMD
* S2_CTRL2CTRLS2_MEM_CTRLS2_MEM_CTRL
S2_MEM_* S2_MEM_* * S2_2OTHERMEM
*S2_MEM_* S2MEM_2GNDGND
=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFFMIPI_85D *
S2_MEM_85D =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF*
=45_OHM_SES2_MEM_45S * =45_OHM_SE =STANDARD=45_OHM_SE =STANDARD=45_OHM_SE
MIPICLK_2OTHER*CLK_MIPI *
MIPI_DATA CLK_MIPI MIPI_2CLK*
MIPI_DATA MIPI_2OTHER**
?=7X_DIELECTRIC*MIPICLK_2OTHER
?=6X_DIELECTRIC*MIPI_2CLK
=4X_DIELECTRIC* ?MIPI_2OTHER
=2x_DIELECTRICS2MEM_2GND * ?
=6x_DIELECTRIC ?*S2MEM_2OTHER
*S2_MEM_DATA1 S2_DQS2OWNDATAS2_MEM_DQS1
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
Camera Constraints
MEM_CAM_DM<1>S2_MEM_DATA1S2_MEM_DATA_1 S2_MEM_45S
MEM_CAM_DQS_N<0>S2_MEM_DQS0 S2_MEM_85D S2_MEM_DQS0
MEM_CAM_DM<0>S2_MEM_45SS2_MEM_DATA_0 S2_MEM_DATA0
S2_MEM_CMD MEM_CAM_WE_LS2_MEM_45S S2_MEM_CMD
MEM_CAM_DQS_N<1>S2_MEM_DQS1 S2_MEM_DQS1S2_MEM_85D
MEM_CAM_DQ<7..0>S2_MEM_DATA_0 S2_MEM_45S S2_MEM_DATA0
PP1V35_CAMS2_MEM_PWR
S2_MEM_PWR PP0V675_MEM_CAM_VREFDQ
MIPI_85D MIPI_CLK_CONN_PCLK_MIPI
S2_MEM_DQS0S2_MEM_85DS2_MEM_DQS0 MEM_CAM_DQS_P<0>
MEM_CAM_A<14..0>S2_MEM_45SS2_MEM_A S2_MEM_CMD
S2_MEM_PWR PP0V675_CAM_VREF
S2_MEM_45SS2_MEM_CMD MEM_CAM_BA<1>S2_MEM_CMD
CLK_MIPIMIPI_85D MIPI_CLK_CONN_N
MEM_CAM_CLK_PS2_MEM_85D S2_MEM_CLKS2_MEM_CLK
MEM_CAM_ODTS2_MEM_45S S2_MEM_CTRLMEM_CAM_CAS_LS2_MEM_CMD S2_MEM_CTRLS2_MEM_45S
S2_MEM_CNTL S2_MEM_45S MEM_CAM_CKES2_MEM_CTRL
MEM_CAM_RAS_LS2_MEM_CMD S2_MEM_45S S2_MEM_CTRL
MIPI_85DMIPI_CLK_S2 CLK_MIPI MIPI_CLK_P
MEM_CAM_CLK_NS2_MEM_CLKS2_MEM_85DS2_MEM_CLK
MEM_CAM_CS_LS2_MEM_CNTL S2_MEM_CTRLS2_MEM_45S
MEM_CAM_BA<0>S2_MEM_45SS2_MEM_CMD S2_MEM_CMD
S2_MEM_CMDS2_MEM_CMD S2_MEM_45S MEM_CAM_BA<2>
MIPI_85DMIPI_CLK_S2 MIPI_CLK_NCLK_MIPI
S2_MEM_PWR PP0V675_MEM_CAM_VREFCA
MEM_CAM_DQ<15..8>S2_MEM_DATA_1 S2_MEM_45S S2_MEM_DATA1
MEM_CAM_DQS_P<1>S2_MEM_DQS1 S2_MEM_DQS1S2_MEM_85D
MIPI_85D MIPI_DATA MIPI_DATA_CONN_NMIPI_85D MIPI_DATA MIPI_DATA_CONN_PMIPI_85DMIPI_DATA_S2 MIPI_DATA MIPI_DATA_NMIPI_85D MIPI_DATA_PMIPI_DATAMIPI_DATA_S2
dvt
051-0675
6.0.0
116 OF 119
91 OF 94
35 36
35 36
35 36
35 36
35 36
35 36
35 36
36
36 83
35 36
35 36
35 36
35 36
36 83
35 36
36
35 36
35 36
35 36
35 36
35 36
35 36
35 36
35 36
35 36
36
35 36
35 36
36 83
36 83
35 36
35 36
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
NET_TYPE
PHYSICAL
PHYSICAL
NET_TYPE
SMBus Charger Net Properties
SPACING
SPACINGELECTRICAL_CONSTRAINT_SET
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET
SYNC_DATE=04/26/2013SYNC_MASTER=CLEAN_J45
SMC Constraints
CHGR_CSO_N1TO1_DIFFPAIR
CHGR_CSO_PCHGR_CSO 1TO1_DIFFPAIR
CHGR_CSI_PCHGR_CSI 1TO1_DIFFPAIRCHGR_CSI_N1TO1_DIFFPAIR
SMBUS_SMC_5_g3_SCLSMBUS_SMC_5_SCL SMBSMB_45S
SMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SDA SMBSMB_45S
SMBUS_SMC_2_S3_SDASMBSMBUS_SMC_2_S3_SDA SMB_45S
SMB SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL SMB_45S
SMBUS_SMC_3_SDASMBUS_SMC_3_SDA SMBSMB_45S
SMBUS_SMC_3_SCLSMBUS_SMC_3_SCL SMBSMB_45S
SMBUS_SMC_5_G3_SDASMBUS_SMC_5_SDA SMBSMB_45S
SMBUS_SMC_1_S0_SDA SMB SMBUS_SMC_1_S0_SDASMB_45S
SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SCLSMBSMB_45S
SMBUS_SMC_2_S3_SCLSMBSMBUS_SMC_2_S3_SCL SMB_45S
dvt
051-0675
6.0.0
117 OF 119
92 OF 94
56
56
56
56
40 43 83
40 43
40 43
40 43
40 42
40 42
40 43 83
40 43
40 43
40 43
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEMLINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL
NET_TYPE
SPACING
NET_TYPE
PHYSICAL SPACING
J15 Specific Net Properties
ELECTRICAL_CONSTRAINT_SETELECTRICAL_CONSTRAINT_SET
J15 Specific Net Properties
I357
I358
I359
I360
I361
I362
I405
I406
I407
I408
I419
I420
I421
I422
I423
I424
I425
I426
I429
I430
I431
I432
I433
I434
I435
I436
I440
I441
I442
I445
I446
I447
I448
I449
I450
I451
I452
I453
I454
I455
I456
I457
I458
I459
I460
I461
I462
I463
I480
I481
I482
I483
I484
I485
I486
I487
I488
I489
I490
I491
I492
I493
I494
I495
I510
I511
I514
I515
I516
I517
I518
I519
I520
I521
I522
I523
I524
I525
I526
I527
I528
I529
I530
I531
I532
I533
I534
I535
I536
I537
=1:1_DIFFPAIR =1:1_DIFFPAIR=1:1_DIFFPAIR*THERM_1TO1_50S =50_OHM_SE =50_OHM_SE =50_OHM_SE
GND_P2MMCLK_PCIE GND *
SATA_*GND GND_P2MM*
GND_P2MM * 0.20 MM 1000
0.20 MM 1000*PWR_P2MM
* 0.09 MM 100 MILMEM_85D
CPU_27P4S BOTTOM 0.23 MM 100 MIL
* 0.2 MM=1:1_DIFFPAIR =45_OHM_SE =45_OHM_SE =45_OHM_SETHERM_45S_CPUVRISNS1 0.2 MM
=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR*THERM_1TO1_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE
* =1:1_DIFFPAIRSENSE_1TO1_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE =1:1_DIFFPAIR=1:1_DIFFPAIR
0.1 MMTOPUSB_85D 500 MIL
=1:1_DIFFPAIR* =1:1_DIFFPAIR =1:1_DIFFPAIRDIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR=1:1_DIFFPAIR* =50_OHM_SE =50_OHM_SE =50_OHM_SESENSE_1TO1_50S
SENSE ?* =2X_DIELECTRIC
GND ?* =STANDARD
*GNDUSB GND_P2MM
* PWR_P2MMSB_POWERCLK_PCIE
PWR_P2MM*SB_POWERUSB
?*THERM =2X_DIELECTRIC
GND_P2MMPCIE_* *GND
0.075 MM 0.090 MMISL10USB3_85D
1:1_DIFFPAIR1TO1_DIFFPAIR *
AUDIO * ?=2X_DIELECTRIC
500 MILUSB3_85D TOP 0.1 MM
GND *CPU_VCCSENSE GND_P2MM
GND *CPU_COMP GND_P2MM
SB_POWER * PWR_P2MMSATA_*
SYNC_DATE=04/26/2013
Project Specific ConstraintsSYNC_MASTER=CLEAN_J45
MEM_72D * 0.09 MM 100 MIL
* 0.09 MMMEM_40S 100 MIL
0.1 MMAUDIODIFF * 0.1 MM10 MM0.1 MM0.1 MM=1:1_DIFFPAIR
* 0.09 MM 100 MILMEM_37S
0.075 MMISL9 0.090 MMDP_85D
10 MM* 0.09 MMPCIE_85D
0.090 MM0.075 MMISL10PCIE_85D
SENSE_DIFFPAIR CPUVR_ISNS3_NTHERMTHERM_45S_CPUVRISNS1
SENSE_DIFFPAIR THERM_45S_CPUVRISNS1 THERM CPUVR_ISNS2_NSENSE_DIFFPAIR THERM_45S_CPUVRISNS1 THERM CPUVR_ISNS3_P
SENSESENSE_DIFFPAIR ISNS_S2_R_NSENSE_1TO1_45S
THERMSENSE_DIFFPAIR THERM_1TO1_45S P1V05S0_CS_P
CHGR_CSO_R_NAUDIODIFF AUDIO
THERM ISNS_CPU_DDR_R_PTHERM_1TO1_45SISNS_CPU_DDR_R_NTHERMTHERM_1TO1_45S
SENSESENSE_DIFFPAIR SENSE_1TO1_45S ISNS_AIRPORT_N
SENSESENSE_1TO1_45S ISNS_HS_OTHER5V_PSENSE_DIFFPAIR
SENSESENSE_1TO1_45S ISNS_HS_OTHER3V3_PSENSE_DIFFPAIR
THERMSENSE_DIFFPAIR THERM_1TO1_45S DDR3THMSNS_D1_N
AUDIOAUDIO_DIFFPAIR AUD_LO2_L_PAUDIODIFF
AUDIODIFF AUDIO LSUBIN_PAUDIODIFF RSUBIN_NAUDIO
AUDIO SPKRCONN_L_OUT_PDIFFPAIRAUDIO_DIFFPAIR
AUDIOAUDIODIFF LSUBIN_N
AUDIO_DIFFPAIR AUDIO SPKRCONN_L_OUT_NDIFFPAIRSPKRCONN_R_OUT_PAUDIODIFFPAIRAUDIO_DIFFPAIR
AUDIO AUD_HS_MIC_PDIFFPAIR
AUDIODIFFPAIR AUD_MIC_IN1_L_N
SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_LCDBKLT_N
SENSESENSE_DIFFPAIR ISNS_S2_R_PSENSE_1TO1_45S
SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_AIRPORT_P
SENSESENSE_1TO1_45S ISNS_AIRPORT_R_P
SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_LCDBKLT_P
SENSE_DIFFPAIR THERM DDR3THMSNS_D1_PTHERM_1TO1_45S
AUDIODIFFPAIR CODEC_HS_MIC_NAUDIO_DIFFPAIR
AUDIO ISNS_TBT_R_PAUDIODIFF
SENSE_DIFFPAIR ISNS_HS_COMPUTING_NSENSESENSE_1TO1_45S
THERMSENSE_DIFFPAIR TBT_THERMD_PTHERM_1TO1_45S
AUDIOAUDIO_DIFFPAIR CHGR_CSI_R_PAUDIODIFF
THERM ISNS_SSD_PTHERM_1TO1_45SSENSE_DIFFPAIR
THERM P1V05S0_SENSE_PTHERM_1TO1_45SSENSE_DIFFPAIR
THERMTHERM_1TO1_45S TBT_THERMD_N
AUDIODIFF AUDIO AUD_SPKRAMP_RSUBIN_P
AUDIO CHGR_CSI_R_NAUDIODIFF
AUD_SPKRAMP_LSUBIN_NAUDIODIFF AUDIO
AUDIO AUD_SPKRAMP_LIN_PAUDIODIFF
AUDIOAUDIO_DIFFPAIR AUDIODIFF CHGR_CSO_R_P
SB_POWER PP3V3_S0PP3V3_S5SB_POWER
P1V05S0_SENSE_NTHERMTHERM_1TO1_45S
AUDIODIFF AUDIO SPKRAMP_LIN_P
AUDIODIFF AUDIO RSUBIN_P
AUD_SPKRAMP_LSUBIN_PAUDIODIFF AUDIO
AUDIODIFF AUDIO AUD_SPKRAMP_RSUBIN_N
AUDIO AUD_LO2_R_NAUDIODIFFAUDIO_DIFFPAIR
AUD_SPKRAMP_RIN_NAUDIOAUDIODIFF
AUDIO SPKRAMP_LIN_NAUDIODIFF
AUD_LO3_L_PAUDIO_DIFFPAIR AUDIODIFF AUDIO
ISNS_CPUDDR_PSENSE_DIFFPAIR THERMTHERM_1TO1_45S
SENSE_DIFFPAIR THERM ISNS_CPUDDR_NTHERM_1TO1_45S
SENSE_DIFFPAIR THERMTHERM_1TO1_45S CPUTHMSNS_D2_P
CPUVR_ISNS_PSENSE_1TO1_45S SENSE
AUDIODIFFPAIR SPKRCONN_SR_OUT_NAUDIO_DIFFPAIR
DIFFPAIR SPKRCONN_SL_OUT_PAUDIOAUDIO_DIFFPAIR
SPKRAMP_RIN_PAUDIOAUDIODIFF
AUDIODIFFPAIR AUD_HS_MIC_NAUDIO HS_MIC_PDIFFPAIR
AUDIO AUD_LO3_L_NAUDIO_DIFFPAIR AUDIODIFF
AUDIODIFFPAIR AUD_MIC_IN1_L_PAUDIO_DIFFPAIR
AUD_MIC_IN1_R_NAUDIOAUDIO_DIFFPAIR DIFFPAIR
SENSESENSE_1TO1_45S ISNS_AIRPORT_R_N
THERMTHERM_1TO1_45S ISNS_LCD_PANEL_NSENSE_DIFFPAIR
THERMTHERM_1TO1_45S ISNS_LCD_PANEL_PSENSE_DIFFPAIR
THERMTHERM_1TO1_45S CPUTHMSNS_D2_NSENSE_DIFFPAIR
AUDIOAUDIODIFF AUD_LO2_R_PAUDIO_DIFFPAIR
SENSE_1TO1_45S ISNS_1V35_MEM_R_NSENSE
SENSESENSE_1TO1_45S ISNS_1V35_MEM_R_PSENSE_DIFFPAIR ISNS_1V35_MEM_NSENSE_1TO1_45S SENSE
SENSE_DIFFPAIR ISNS_1V35_MEM_PSENSE_1TO1_45S SENSE
THERMSENSE_DIFFPAIR THERM_1TO1_45S GPUTHMSNS_D_NSENSE_DIFFPAIR THERMTHERM_1TO1_45S GPUTHMSNS_D_P
SENSESENSE_1TO1_55S GPUFB_CS_PSENSE_DIFFPAIR
SENSE_1TO1_55S SENSE ISNS_GPUFB_R_NSENSE_DIFFPAIR
SENSESENSE_1TO1_55SSENSE_DIFFPAIR ISNS_GPUFB_R_P
ISNS_HS_OTHER3V3_NSENSE_DIFFPAIR SENSESENSE_1TO1_45S
SENSESENSE_1TO1_45S ISNS_HS_COMPUTING_PSENSE_DIFFPAIR
AUDIOAUDIO_DIFFPAIR DIFFPAIR CODEC_HS_MIC_PSENSE_1TO1_55S P1V05_GPU_CS_PSENSESENSE_DIFFPAIR
SENSE_DIFFPAIR SENSESENSE_1TO1_55S P1V05_GPU_CS_N
SENSE_DIFFPAIR THERM_45S_CPUVRISNS1 CPUVR_ISNS2_PTHERM
SENSE_DIFFPAIR CPUVR_ISUM_R_PTHERMTHERM_1TO1_45S
SENSE_1TO1_55SSENSE_DIFFPAIR SENSE ISNS_HS_GPU_N
ISNS_HS_OTHER5V_NSENSESENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_55S SENSE GPUFB_CS_NSENSE_DIFFPAIR
SB_POWER PP1V35_S3RS0_CPUDDR
AUD_SPKRAMP_LIN_NAUDIOAUDIODIFF
AUD_SPKRAMP_RIN_PAUDIODIFF AUDIO
AUDIO AUD_LO2_L_NAUDIO_DIFFPAIR AUDIODIFF
AUDIO SPKRAMP_RIN_NAUDIODIFF
AUDIO SPKRCONN_SL_OUT_NDIFFPAIRAUDIO_DIFFPAIR
DIFFPAIR AUDIO SPKRCONN_SR_OUT_PAUDIO_DIFFPAIR
DIFFPAIR AUDIO SPKRCONN_R_OUT_NAUDIO_DIFFPAIR
AUDIO AUD_MIC_IN1_R_PDIFFPAIRAUDIO_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S ISNS_HS_GPU_PSENSE
CPUVR_ISNS_NSENSESENSE_1TO1_45S
SENSE ISNS_PP1V0_S0GPU_R_PSENSE_DIFFPAIR SENSE_1TO1_55S
SENSESENSE_DIFFPAIR SENSE_1TO1_55S ISNS_PP1V0_S0GPU_R_NTHERMSENSE_DIFFPAIR THERM_1TO1_45S P1V05_GPU_PEX_IOVDD_SNS_P
SENSE_DIFFPAIR THERMTHERM_1TO1_45S P1V05_GPU_PEX_IOVDD_SNS_NTHERM CPUVR_ISNS1_PTHERM_45S_CPUVRISNS1SENSE_DIFFPAIR
THERMSENSE_DIFFPAIR CPUVR_ISNS1_NTHERM_45S_CPUVRISNS1AUDIO_DIFFPAIR AUD_LO3_R_NAUDIOAUDIODIFF
AUDIO_DIFFPAIR AUD_LO3_R_PAUDIODIFF AUDIO
AUDIO AUD_CONN_HS_MIC_NDIFFPAIR
AUDIODIFFPAIR AUD_CONN_HS_MIC_PHS_MIC_NAUDIODIFFPAIR
AUDIODIFFAUDIO_DIFFPAIR ISNS_TBT_NAUDIO
THERMSENSE_DIFFPAIR THERM_1TO1_45S CPUVR_ISUM_R_N
ISNS_SSD_R_PSENSE_DIFFPAIR THERMTHERM_1TO1_45S
SENSESENSE_DIFFPAIR ISNS_S2_PSENSE_1TO1_45S
SENSE ISNS_S2_NSENSE_1TO1_45SSENSE_DIFFPAIR
THERM ISNS_SSD_R_NTHERM_1TO1_45S
ISNS_SSD_NTHERMTHERM_1TO1_45S
SENSE_DIFFPAIR THERM GPU_TDIODE_NTHERM_1TO1_55S
THERM_1TO1_55S GFXIMVP_ISNS2_PSENSE_DIFFPAIR THERM
THERM_1TO1_55S THERMSENSE_DIFFPAIR GFXIMVP_ISNS1_PGFXIMVP_ISNS2_NSENSE_DIFFPAIR THERMTHERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S GPU_TDIODE_PTHERM
GFXIMVP_ISNS1_NTHERMTHERM_1TO1_55SSENSE_DIFFPAIR
SENSE_DIFFPAIR GPUVCORE_SENSE_NTHERM40_OHM_SE
GPUVCORE_SENSE_PSENSE_DIFFPAIR THERM40_OHM_SE
ISNS_TBT_PAUDIOAUDIODIFFAUDIO_DIFFPAIR
THERMTHERM_1TO1_45S P1V05S0_CS_N
AUDIO ISNS_TBT_R_NAUDIODIFF
GND GND
dvt
051-0675
6.0.0
118 OF 119
93 OF 94
45 58
45 58
45 58
46
61
56
46
46
44
44
47
50 52
52
52
52 54 83
52
52 54 83
52 54 83
53 54
46 62
46
46
46 62
47
50
45
44
47
56
45
61
47
52
56
52
52
56
81 83
81 83
61
52
52
52
52
50 52
52
52
50 52
47
45
52 54 83
52 54 83
52
53 54
50 53
50 52
46
47
50 52
45
45
45
45
47
47
45 71
45
45
44
44
5046 71
46 71
45 58
45
44
44
45 71
81
52
52
50 52
52
52 54 83
52 54 83
52 54 83
44
45
46
46
71 76
71 76
45 58
45 58 50 52
50 52
50 53
45
45
45
45
45
47 74
77
77
77
47 74
77
76 77
76 77
45
61
45
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
ELECTRICAL_CONSTRAINT_SET
MUXGFX & DP AUX MUX NET PROPERTIES
PHYSICAL
NET_TYPE
SPACING
PHYSICAL
GDDR5 FB A Net PropertiesNET_TYPE
SPACING
GDDR5 FB B Net Properties
PHYSICAL
NET_TYPE
SPACINGELECTRICAL_CONSTRAINT_SET
Kepler Net Properties
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
ELECTRICAL_CONSTRAINT_SET
GDDR5 Frame Buffer Signal Constraints
PHYSICAL
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=STANDARD =STANDARD=45_OHM_SE_ADJ =45_OHM_SE_ADJ* =45_OHM_SE_ADJGDDR5_45SE =45_OHM_SE_ADJ
*GDDR5_EDC ?=5x_DIELECTRIC
=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFF=80_OHM_DIFFGDDR5_80D
* ?GDDR5_CMD =3x_DIELECTRIC
?* =3x_DIELECTRICGDDR5_DATA TOP,BOTTOM ?=5x_DIELECTRICGDDR5_DATA
?* =5x_DIELECTRICGDDR5_CLK
=STANDARD* 12.7 MM=50_OHM_SE =STANDARD=50_OHM_SEGDDR5_45R50SE =50_OHM_SE
?TOP,BOTTOM =5x_DIELECTRICGDDR5_CLK
GDDR5_CMD TOP,BOTTOM ?=4x_DIELECTRIC
TOP,BOTTOM ?GDDR5_EDC =5x_DIELECTRIC
SYNC_DATE=09/02/2012
GPU (Kepler) Constraints
SYNC_MASTER=SIDLE_J15
DP_INT_ML_C_N<3..0>DP_85D DISPLAYPORT
DP_INT_ML_C_P<3..0>DP_85D DISPLAYPORT
DP_85D DP_INT_ML_F_P<3..0>DISPLAYPORT
DP_85D DISPLAYPORT DP_INT_ML_F_N<3..0>
DP_INT_AUXCH_C_NDISPLAYPORTDP_85DDP_INT_AUX_PDISPLAYPORTDP_85DDP_INT_AUXCH
DP_85D DISPLAYPORT DP_INT_IG_AUX_NDP_85D DISPLAYPORT DP_INT_IG_AUX_PDP_INT_IG_AUX
DP_85D DISPLAYPORT DP_INT_IG_ML_N<3..0>DP_85D DISPLAYPORT DP_INT_IG_ML_P<3..0>DP_INT_IG_ML
DP_85DDP_INT_EG_ML DISPLAYPORT DP_INT_EG_ML_P<3..0>DISPLAYPORT DP_INT_EG_ML_N<3..0>DP_85D
DP_85D DP_INT_EG_AUX_NDISPLAYPORT
DP_85DDP_INT_EG_AUX DP_INT_EG_AUX_PDISPLAYPORT
DISPLAYPORT DP_TBTSNK0_EG_AUXCH_PDP_85DDP_INT_EG_AUX
DP_INT_EG_AUX DP_85D DISPLAYPORT DP_TBTSNK0_EG_AUXCH_N
FB_A0_DQ<23..16>GDDR5_45SE GDDR5_DATAFB_A0_DQ_BYTE2
GDDR5_DATAFB_A0_DQ_BYTE1 FB_A0_DQ<15..8>GDDR5_45SE
FB_A0_DQ<7..0>GDDR5_45SEFB_A0_DQ_BYTE0 GDDR5_DATA
FB_A1_WCLK_N<0>GDDR5_CMDFB_A1_WCLK0 GDDR5_80D
GDDR5_80D FB_A1_WCLK_P<0>GDDR5_CMDFB_A1_WCLK0
DP_INT_EG_AUX1 DP_85D DISPLAYPORT DP_TBTSNK1_EG_AUXCH_P
DP_85D DISPLAYPORT DP_TBTSNK0_AUXCH_C_N
HDMI_CLK HDMI_EG_CLK_C_PHDMI_CLKDP_85D
PEX_TSTCLK_O_N1TO1_DIFFPAIR
PEX_TSTCLK_O_P1TO1_DIFFPAIR
GPU_OSC_27M_XTAL_BUFFOUT_RCLK_SLOWGPU_CLK27M CLK_SLOW_50S
FB_A1_CKE_LGDDR5_45SE GDDR5_CMDFB_A1_CMD_R
GDDR5_45SEFB_A0_CMD FB_A0_WE_LGDDR5_CMD
FB_B0_DBI_L0 GDDR5_45SE GDDR5_DATA FB_B0_DBI_L<0>
GDDR5_80D GDDR5_CMD FB_B1_WCLK_P<1>FB_B1_WCLK1FB_B1_WCLK_N<1>GDDR5_80D GDDR5_CMDFB_B1_WCLK1GDDR5_80D GDDR5_CMD FB_A1_WCLK_N<1>FB_A1_WCLK1
GDDR5_45SEFB_A1_DQ_BYTE0 GDDR5_DATA FB_A1_DQ<7..0>
GDDR5_CMDGDDR5_45SE FB_B0_RESET_LFB_B0_CMD_R
FB_B1_WCLK0 FB_B1_WCLK_N<0>GDDR5_CMDGDDR5_80D
FB_A0_DBI_L<1>GDDR5_45SE GDDR5_DATAFB_A0_DBI_L1
GDDR5_45SE GDDR5_DATAFB_B1_DBI_L1 FB_B1_DBI_L<1>
FB_A1_DBI_L3 GDDR5_45SE GDDR5_DATA FB_A1_DBI_L<3>GDDR5_80D GDDR5_CMDFB_A0_WCLK0 FB_A0_WCLK_P<0>
FB_A1_DBI_L1 FB_A1_DBI_L<1>GDDR5_45SE GDDR5_DATA
GDDR5_45SE GDDR5_CMDFB_B0_CMD FB_B0_CAS_L
FB_B1_DQ<23..16>GDDR5_DATAGDDR5_45SEFB_B1_DQ_BYTE2
GDDR5_45SE GDDR5_DATAFB_B1_DBI_L3 FB_B1_DBI_L<3>GDDR5_80D FB_B0_WCLK_P<0>FB_B0_WCLK0 GDDR5_CMD
GDDR5_CMDGDDR5_45SEFB_B1_CMD FB_B1_CS_L
GDDR5_45SE GDDR5_CMD FB_B1_RESET_LFB_B1_CMD_R
FB_A0_DBI_L<3>GDDR5_45SE GDDR5_DATAFB_A0_DBI_L3
FB_A0_DBI_L<0>FB_A0_DBI_L0 GDDR5_DATAGDDR5_45SE
GDDR5_45SE GDDR5_EDC FB_A1_EDC<3>FB_A1_EDC3
GDDR5_45SE GDDR5_CMDFB_B0_CMD_R FB_B0_CKE_LGDDR5_45SE GDDR5_CMDFB_B1_CMD_R FB_B1_CKE_LGDDR5_45SE GDDR5_CMDFB_B0_CMD FB_B0_CS_L
GDDR5_45SE GDDR5_EDCFB_B0_EDC0 FB_B0_EDC<0>
GDDR5_45SE GDDR5_CMDFB_B1_CMD FB_B1_WE_L
GDDR5_45SE FB_B1_EDC<0>GDDR5_EDCFB_B1_EDC0
GDDR5_45SE GDDR5_EDCFB_B0_EDC3 FB_B0_EDC<3>
GDDR5_45SE GDDR5_CMDFB_B0_CMD FB_B0_WE_L
GDDR5_45SE GDDR5_DATA FB_B0_DBI_L<2>FB_B0_DBI_L2
FB_B1_DBI_L2 GDDR5_45SE GDDR5_DATA FB_B1_DBI_L<2>
GDDR5_45SE GDDR5_EDCFB_B1_EDC1 FB_B1_EDC<1>
GDDR5_45SE GDDR5_DATAFB_B0_DBI_L1 FB_B0_DBI_L<1>
FB_B0_WCLK1 GDDR5_80D GDDR5_CMD FB_B0_WCLK_P<1>
GDDR5_45SE GDDR5_CMDFB_B1_CMD FB_B1_ABI_LGDDR5_45SE GDDR5_CMDFB_B0_CMD FB_B0_ABI_L
GDDR5_45SE GDDR5_CMDFB_B0_CMD FB_B0_RAS_LGDDR5_45SE GDDR5_CMDFB_B1_CMD FB_B1_RAS_L
GDDR5_80D GDDR5_CLKFB_B0_CLK FB_B0_CLK_PGDDR5_80D GDDR5_CLKFB_B0_CLK FB_B0_CLK_NGDDR5_80D GDDR5_CLKFB_B1_CLK FB_B1_CLK_PGDDR5_80D GDDR5_CLKFB_B1_CLK FB_B1_CLK_N
GDDR5_45SE GDDR5_CMDFB_B1_CMD FB_B1_A<8..0>GDDR5_45SE GDDR5_CMDFB_B0_CMD FB_B0_A<8..0>
GDDR5_45SE GDDR5_CMDFB_B1_CMD FB_B1_CAS_L
GDDR5_45SE GDDR5_EDCFB_B0_EDC1 FB_B0_EDC<1>
GDDR5_45SEFB_B1_DBI_L0 FB_B1_DBI_L<0>GDDR5_DATA
GDDR5_45SE GDDR5_CMD FB_A0_CAS_LFB_A0_CMD
GDDR5_45SE GDDR5_CMDFB_A0_CMD FB_A0_RAS_L
GDDR5_45SE GDDR5_CMD FB_A1_WE_LFB_A1_CMD
GDDR5_80D GDDR5_CLK FB_A1_CLK_PFB_A1_CLK
GDDR5_80D GDDR5_CLK FB_A0_CLK_NFB_A0_CLK
FB_A1_CLK GDDR5_80D GDDR5_CLK FB_A1_CLK_NGDDR5_45SE GDDR5_CMD FB_A0_A<8..0>FB_A0_CMD
GDDR5_45SE GDDR5_CMD FB_A0_ABI_LFB_A0_CMD
GDDR5_45SE GDDR5_CMD FB_A1_A<8..0>FB_A1_CMD
FB_A0_WCLK_N<0>GDDR5_CMDGDDR5_80DFB_A0_WCLK0
GDDR5_45SE GDDR5_EDC FB_B1_EDC<2>FB_B1_EDC2
FB_B0_DBI_L3 GDDR5_45SE FB_B0_DBI_L<3>GDDR5_DATA
GDDR5_45SE GDDR5_EDCFB_B0_EDC2 FB_B0_EDC<2>
FB_B0_WCLK0 GDDR5_80D GDDR5_CMD FB_B0_WCLK_N<0>
FB_A0_DQ_BYTE3 FB_A0_DQ<31..24>GDDR5_45SE GDDR5_DATA
FB_A1_DQ_BYTE1 GDDR5_45SE GDDR5_DATA FB_A1_DQ<15..8>
GPU_CLK27M GPU_OSC_27M_XTALINCLK_SLOWCLK_SLOW_50S
FB_B1_DQ<31..24>GDDR5_DATAGDDR5_45SEFB_B1_DQ_BYTE3
FB_B1_WCLK0 GDDR5_CMD FB_B1_WCLK_P<0>GDDR5_80D
FB_B0_WCLK1 GDDR5_80D GDDR5_CMD FB_B0_WCLK_N<1>
GDDR5_45SE GDDR5_EDC FB_A1_EDC<0>FB_A1_EDC0
GDDR5_EDCFB_A1_EDC2 FB_A1_EDC<2>GDDR5_45SE
GDDR5_EDCGDDR5_45SE FB_A1_EDC<1>FB_A1_EDC1
FB_A1_WCLK_P<1>GDDR5_CMDGDDR5_80DFB_A1_WCLK1
GDDR5_45SE GDDR5_CMD FB_A0_CKE_LFB_A0_CMD_R
GDDR5_80D GDDR5_CMDFB_A0_WCLK1 FB_A0_WCLK_N<1>
GDDR5_45SE GDDR5_DATA FB_A1_DBI_L<2>FB_A1_DBI_L2
GDDR5_45SE FB_A0_DBI_L<2>GDDR5_DATAFB_A0_DBI_L2
GDDR5_45SE GDDR5_CMDFB_A0_CMD_R FB_A0_RESET_L
GDDR5_45SE GDDR5_DATA FB_A1_DQ<23..16>FB_A1_DQ_BYTE2
GDDR5_45SE GDDR5_CMDFB_A1_CMD FB_A1_CS_LGDDR5_45SE FB_A0_EDC<0>GDDR5_EDCFB_A0_EDC0
FB_B1_EDC3 GDDR5_45SE FB_B1_EDC<3>GDDR5_EDC
FB_A0_EDC<3>GDDR5_EDCGDDR5_45SEFB_A0_EDC3
FB_A0_EDC2 GDDR5_45SE FB_A0_EDC<2>GDDR5_EDC
GDDR5_45SE GDDR5_DATA FB_B0_DQ<31..24>FB_B0_DQ_BYTE3FB_B1_DQ<7..0>GDDR5_45SE GDDR5_DATAFB_B1_DQ_BYTE0
GPU_OSC_27M_XTALOUTCLK_SLOWGPU_CLK27M CLK_SLOW_50S
GDDR5_DATAGDDR5_45SE FB_B1_DQ<15..8>FB_B1_DQ_BYTE1
FB_B0_DQ<23..16>GDDR5_45SE GDDR5_DATAFB_B0_DQ_BYTE2
GDDR5_45SE GDDR5_DATA FB_B0_DQ<15..8>FB_B0_DQ_BYTE1
FB_B0_DQ_BYTE0 GDDR5_45SE GDDR5_DATA FB_B0_DQ<7..0>
GDDR5_80D GDDR5_CLK FB_A0_CLK_PFB_A0_CLK
FB_A0_EDC1 GDDR5_45SE GDDR5_EDC FB_A0_EDC<1>
GDDR5_45SE GDDR5_CMDFB_A1_CMD FB_A1_ABI_L
DISPLAYPORTDP_85D DP_TBTSNK1_AUXCH_C_P
GDDR5_80DFB_A0_WCLK1 FB_A0_WCLK_P<1>GDDR5_CMD
FB_A1_DBI_L<0>GDDR5_DATAGDDR5_45SEFB_A1_DBI_L0
GDDR5_45SE GDDR5_CMD FB_A0_CS_LFB_A0_CMD
DISPLAYPORT DP_INT_AUXCH_C_PDP_85D
GDDR5_45SEFB_A1_DQ_BYTE3 FB_A1_DQ<31..24>GDDR5_DATA
DISPLAYPORTDP_85DTBTSNK1_AUXCH1 DP_TBTSNK1_AUXCH_N
GDDR5_45SEFB_A1_CMD FB_A1_CAS_LGDDR5_CMD
GDDR5_45SE GDDR5_CMD FB_A1_RAS_LFB_A1_CMD
DISPLAYPORT DP_INT_ML_N<3..0>DP_INT_ML DP_85D
DISPLAYPORTDP_85DDP_INT_ML DP_INT_ML_P<3..0>
GPU_CLK27M CLK_SLOW_50S GPU_OSC_27M_SSINCLK_SLOW
HDMI_CLKHDMI_CLK HDMI_EG_CLK_C_NDP_85D
HDMI_DATA HDMI_EG_DATA_C_N<2..0>DISPLAYPORTDP_85D
HDMI_EG_DATA_C_P<2..0>HDMI_DATA DISPLAYPORTDP_85D
DP_85D DISPLAYPORTTBTSNK0_AUXCH DP_TBTSNK0_AUXCH_P
DP_85D DP_TBTSNK1_ML_C_N<3..0>DISPLAYPORT
DP_85D DISPLAYPORT DP_TBTSNK1_ML_C_P<3..0>
DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_P<3..0>DISPLAYPORTDP_85DDP_TBT_ML DP_TBTSNK0_ML_N<3..0>
DISPLAYPORTDP_85DDP_TBT_ML1 DP_TBTSNK1_ML_N<3..0>DISPLAYPORTDP_TBT_ML1 DP_85D DP_TBTSNK1_ML_P<3..0>
DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_N<3..0>
DISPLAYPORTDP_TBT_ML DP_85D DP_TBTSNK0_ML_P<3..0>DISPLAYPORTDP_85D DP_TBTSNK1_AUXCH_C_N
DP_85D DISPLAYPORTTBTSNK1_AUXCH1 DP_TBTSNK1_AUXCH_P
DISPLAYPORTDP_85D DP_TBTSNK0_AUXCH_C_PDISPLAYPORTDP_85DTBTSNK0_AUXCH DP_TBTSNK0_AUXCH_N
DP_INT_EG_AUX1 DP_85D DISPLAYPORT DP_TBTSNK1_EG_AUXCH_N
DP_INT_AUX_NDISPLAYPORTDP_INT_AUXCH DP_85D
GDDR5_45SE GDDR5_CMD FB_A1_RESET_LFB_A1_CMD_R
dvt
051-0675
6.0.0
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28 80 86
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68
68
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74 75
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28 80 86
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28 86
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67 83 86
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74
74 78
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74 78
28 86
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28 86
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28 86
74 80
67 83 86
70 72