sc filters

8/14/2019 SC Filters

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F. Maloberti

: Switched Capacitor Filters 1

Switched Capacitor Filters

Franco Maloberti


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F. Maloberti


OUTLINE

Switched capacitor technique

Biquadratic SC filters

SC N-path filters

Finite gain and bandwidth effects

Layout consideration

Noise


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F. Maloberti


Simple SC structures

Q = C

1

(V

1

- V

2

) every

t = T

1

2

1 2

I

1

2

C1

C1

I

T

T

V1 V2

V1 V2


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F. Maloberti


The two SC structures are

(on average) equivalent to a resistor

If the SC structures are used to get an equivalent time constant

eq

= R

eq

C

2

it results:

IV1 V2 Tt

I

Q itV1 V2

R-------------------T= =

ReqT

C1

-------=

eq T

C2

C1-------

=


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F. Maloberti


SC INTEGRATOR

Starting from the continuous-time circuit of the Integrator, we can ob-tain a SC integrator by replacing the continuous-time resistor with the

equivalent resistances.

+

_

R1

C2


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F. Maloberti


1 2

+

_

C1

C2

+

_

C1

C2

+

_

C2

C1

1

1

1

2

2

2

2

1

1

1


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F. Maloberti: Switched Capacitor Filters 10

We consider the samples of the input and of the output taken at

the same times nT (the end of the sampling period).

Structure 1:

taking the z-transform:

Structure 2:


Vout n 1+( )T[ ] Vout nT( )

C1

C2-------Vin nT( )=

Vout

z( )

Vin z( )-------------------

C1C2-------

1z 1------------=

Vout n 1+( )T[ ] Vout nT( )C1C2-------Vin n( 1 )T ]+=


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Structure 3:


Remember that for the continuous-time integrator:

Comparing the sampled-data and continuous-time transfer functions we get:

Vout z( )

Vin z( )-------------------

C1C2-------

z

z 1------------=

Vout

n 1+( )T[ ] Vout

nT( )C1

C2------- V

inn 1+( )T[ ] V

innT( )+{ }=

Vout z( )

Vin z( )-------------------

C1

C2-------

z 1+

z 1------------=

Vout s( )Vin s( )-------------------

1sR1C2------------------=


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Structure 1:

FE approximation

Structure 2:

BE approximation

Structure 3:

Bilinear approximation

It does not exist a simple SC integrator which implement the LD

approximation.

Note: the cascade of a FE integrator and a BE integrator is

equivalent to the cascade of two LD integrators.

R1

T

C1-------

s

1

T---

z 1( )

R1T

C1------- s

1

T

---

z 1( )

z

-----------------

R1T

2C1

---------- s2

T---

z 1( )z 1+( )

-----------------


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The key point is to introduce a full period delay from the input to

the output

1

2

+

_

21+

_

C2

C1

C1

C2'

'


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The same result is got with:

1 2

+

_2 1

+

_

C2

C1

C2

'

'

C1


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STRAY INSENSITIVE STRUCTURE

The considered SC integrators are sensitive to parasitics.

Toggle structure:

The top plate parasitic capacitance Ct,1 isin parallel with C1

It is not negligible with respect to C1 and

it is non linear The top plate parasitic capacitance Ct,1

acts as a toggle structure

Bilinear resistor:

1 2C1

Ct,1 Cb,1

1

2C1

Ct,1 Cb,1


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Both the parasiticcapacitances Ct,1, Cb,1 act

as toggle structures. Theirvalues are different (of afactor 10) and they are nonlinear.

Stray insensitivity can be gotfor the first two structures ifone terminal is switchedbetween points at the same

voltage.

The right-side parasiticcapacitor is switchedbetween the virtual groundand ground (note: even inDC Vv.g. must equal Vground)

1

1

2

2

C1

Ct,1

Cb,1

C1

12

12

Virtual

ground

C1

1

2

Virtualground

2

1


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The left side capacitor is connected, during phase 1, to a voltage(or equivalent) source.

The charge injected into virtual ground is important, not the onefurnished by the input source.

Structure A is equivalent to the toggle structure, but the injected

charge has opposite sign. Equivalent negative resistance allows to implement non inverting

integrators.

It is possible to easily realize a stray insensitive bilinear resistorwith fully differential configuration.


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SC BIQUADRATIC FILTERS

Consider a (continuous-time) biquadratic transfer function

If the bilinear transformation is applied, it results a z-biquadratic trans-fer function

where the coefficients are:

H s( )p0 sp1 s

2p2+ +

s2

s0

Q0-------

0

2+ +

----------------------------------------=

H s( )a0 za1 z

2a2+ +

b0 zb1 z2b2+ +

----------------------------------------=

a0 p02

T---p1

4

T2

------p2+=


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a1 2p08

T2

------p2=

a2 p02

T---p1

4

T2

------p2+ +=

b0 02 2

T---

0Q------

4

T2

------+=

b1 202 8

T2------

=

b2 02 2

T---

0

Q------

4

T2------

+ +=


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All the stable z-biquadratic transfer functions are realized by the topology:

+

-

+

-

G

D

E

C

A

B

F

I

J

H

1

F1

F2

Vin

t

V01V02


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Features:

Loop of two integrators one inverting and the other noninverting.

Damping around the loop provided by capacitor F or (and)

capacitor E (usually only E or F are included in the network).

Two outputs available V0,1 V0,2.

Denominator of the transfer function determined by the capacitors

along the loop (A, B, C, D, E, F).Transmission zeros (numerator) realized by the capacitors (G, H,

I, J).

Input signal sampled during 1 and held for a full clock period

Charge injected into the virtual ground during 1.


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Charge conservation equations:

DV0,1(n+1) = DV0,1(n) - GVin(n+1) + HVin(n) - CV0,2(n+1) - E[V0,2(n+1) - V0,2(n)]

(B + F)V0,2(n+1) = BV0,2(n) + AV0,1(n) - IVin(n+1) + JVin(n)

Taking the z-transform and solving, it results:

10 Capacitors

6 Equations a0, a1, a2, b0, b1, b2

Dynamic range optimization

H1V0 1,Vin-----------

IC IE GF GB+( )z2

FH BH BG JC JE IE+ +( )z EJ BH( )+ +

DB DF+( )z2

AC AE 2DB DF+( )z DB AE( )+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------= =

H2V

0 2,Vin-----------

DIz

2

AG DI DJ( )z DJ AH( )+ +DB DF+( )z

2AC AE 2DB DF+( )z DB AE( )+ +

-------------------------------------------------------------------------------------------------------------------------------------------= =


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Scaling for minimum total capacitance in the groups of capacitorsconnected to the virtual ground of the op-amp1 and the op-amp2.

Since there are 9 conditions, one capacitor can be set equal tozero

E = 0 F type

F = 0 E type

Firstly the 6 equations are satisfied. Later capacitors D and A

are adjusted in order to optimize the dynamic range. Finally all

the capacitor connected to the virtual ground of the op-amp arenormalized to the smaller of the group.


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Scaling for minimum total capacitance

Assume that C3 is the smallest capacitance of the group. In order to makeminimum the total capacitance C3 must be reduced to the smallest value al-lowed by the technology (Cmin)

Multiply all the capacitors of the group by

+

_

C2

C1

C3

C4

Cn

kCminC3

------------=


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SC LADDER FILTERS

Orchards observationDoubly-terminated LC ladder network that are designed to effect max-

imum power transfer from source to load over the filter passband fea-

ture very low sensitivities to value component variation.

Syntesis of SC Ladder Filters:

Symple approach

Replace every resistance Ri in an active ladder structure with aswitched capacitor Ci = T/Ri.

Use a full clock period delay along all the two integrator loop (itresults automatically verified in single ended schemes).

It results an LD equivalent, except for the terminations.


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Quasi LD transformation:

Prewarp the specifications using sin(T/2)

Attenuation wwsbwpbApb Asb DESIRED SPECIFICATION Attenuationw

ww

Apb

Asb

PREWARPED SPECIFICATION

sin( pb T/2) sin( sb T/2)


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Effect of the terminations:

if R1 = T/ C1 and R3 = T/C3 we get:

+

_

R1

R

C2_

+

_

C2C1

C3

HDI s( )R3

sC2

R1

R3

R1

+---------------------------------------= HDI s( )

C1sTC

2

C3

+----------------------------=

Vout n 1+( ) C2 C3+( ) Vout n( )C2 C1Vin n( )+=


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Taking the z-transform we get:

along the unity circle z=ejT

The half clock period delay will be used in the cascaded integrator in

order to get the LD transformation

The termination is complex and frequency dependent.

The integrating capacitor C2 must be replaced by C2 + C3/2.

zVout C2 C3+( ) C2Vout C1Vin+=

HDI z( )C1

C2 z 1( ) zC3+-----------------------------------------

C1z1 2

C2 z1 2

z1 2

( ) z1 2

C3+---------------------------------------------------------------------= =

HDI ejT

( )C1e

j T 2

C2 ejT 2

ej T 2

( ) ejT 2

C3+-------------------------------------------------------------------------------------

C1ej T 2

2j C2

C3

+( )T

2-------- C

3

T

2--------cos+sin

---------------------------------------------------------------------------------= =


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Complex termination:

Note: the output voltage changes during

Taking the z-transform:

+

_

C2C

1

C3

F1

Vout n 1+( )C2 Vout n( )C2

2

C2 C3+-------------------- C1Vin n( )+=

zVoutC2 Vout C2C2C3

C2 C3+--------------------

C1Vin+=


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along the unity circle z=ejT

The imaginary part of the contribution of the termination isnegative

The integrating capacitor must be replaced by

HDI z( )C1

C2 z 1( )C

2

C3

C2 C3+--------------------+

----------------------------------------------------

C1z1 2

C2 z1 2

z 1 2

( ) z 1 2

C2

C3

C2 C3+--------------------+

-------------------------------------------------------------------------------------= =

HDI ejT( ) C1e

j T 2

2j C21

2---

C2C3C2 C3+--------------------

T2

--------

C2C3C2 C3+--------------------

T2

--------cos+sin

----------------------------------------------------------------------------------------------------------------=

C2 C21

2---

C2C3C2 C3+--------------------


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FINITE GAIN AND BANDWIDTH EFFECT

If the op-amp has finite gain A0 the virtual ground voltage is V0/A0

z-transforming:

+

_

C2

C1

C2V0 n 1+( ) 11

A0------+

C2V0 n( ) 11

A0------+

C1 Vin n 1+( )V0 n 1+( )

A0-------------------------+=

H z( )Vo z( )

Vin z( )----------------

C1z

C2 11

A0------+

z 1( )C1A0-------z+

----------------------------------------------------------------= =


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Comparing H(z) with the transfer function with

Substituting z = esT, on the imaginary axis

Magnitude error

Phase error

A0

Hid z( )

C1z

C2 z 1( )------------------------=

H z( )H

idz( )

11

A0

-------+

C

1

C2A0

---------------

z

z 1

------------+

----------------------------------------------------------

Hid

z( )

11

A0

-------+

C

1

C2A0

---------------

1

z 1

------------

1

2

---

1

2

---+ +

+

-----------------------------------------------------------------------------------

Hid

z( )

11

A0

-------

1

2

---

C1

C2A0

---------------+ +

C1

2C2A0

-------------------

z 1+

z 1------------+

----------------------------------------------------------------------------------------= = =

H ejT

( )H

idejT

( )

11

A0

-------

C1

2C2A0------------------- j

C1

2C2

A0

T 2( )tan---------------------------------------------------+ +

-----------------------------------------------------------------------------------------------------

Hid

ejT

( )

1 m ( ) j ( )-------------------------------------------= =

m ( )1

A0------ 1

C1

2C2-----------+

=

( )C1

2C2

A0

T 2( )tan------------------------------------------------

C1C

2A

0T

-----------------------=


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For the noninverting integrator

z-transforming and solving

Same magnitude and phase error result

+

_

C2

C1

C2V0 n 1+( ) 11

A0

------+ C2V0 n( ) 1

1

A0

------+ C1 Vin n( )

V0 n 1+( )

A0

-------------------------++=

H z( )Vo z( )

Vin z( )----------------

C1

C2 1

1

A0------

+

z 1( )

C1

A0-------

z+

----------------------------------------------------------------= =


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FULLY DIFFERENTIAL CIRCUITS

Fully differential configurations reduce the clock feedthroughnoise and increase the dynamic range.

They allow an increase design flexibility

Simple integrator (inverting and non inverting)

+

_

C2

C1

1

2

2

12

(2)

(1)


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Immediate sampling (inverting and non inverting) integrator:

Delayed sampling (inverting and non inverting) integrator:

1

+

_

122

1

1 22

Vin

-Vin

-Vin

Vin

1

1

1

+

_

122

1122

Vin

-Vin

-Vin

Vin2

2


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The peaking in the frequency response due to the phase error is

strongly reduced

It is easy to realize bilinear integrators

1

+

1

2

1

1

2

Vin

Vin

2

2

C2C1

C2

C1

_

_

NOISE IN SC CIRCUITS


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NOISE IN SC CIRCUITS

The noise sources in a SC network are: Clock feedthrough noise

Noise coupled from power supply lines and substrate

kT/C noise Noise generators of the op-amp

The first two sources are the same as in mixed analog-digital circuits.

kT/C noise:

C id th i l t k


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Consider the simple network:

In the on state the switch can bemodeled with a noisy resitor

Noise equivalent circuit:

The white spectrum of the on resistance is shaped by the low pass

vin

CS1

4kTR fC

S1

on

Ron

ti f th R C filt


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action of the RonC filter.The noise voltage across the capacitor C has spectrum:

When the switch is turned off the noise voltage vn,c is sampled andheld onto C

Sn,c vn c,2

4kTRon H f( )2

f4kTRonf

1 2fRonC( )2

+-----------------------------------------= = =

f

S

The folding of the spectrum in band base gives a white spectrum


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The folding of the spectrum in band-base gives a white spectrum.

It power (the dashed area) is equal to the integral of Sn,c

Procedure for the noise calculation in SC networks:

f

v n,c

fCK/2

*

vn c,2 4kTRonf

1 2fRonC( )2

+-----------------------------------------

0

df4kT

2C----------- xatan( )0

kT

C-------= = =

sc filters

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