Department of Electrical and Computer Engineering

Vishal Saxena -1-

SAR, Algorithmic and Integrating ADCs

Vishal Saxena, Boise State University(vishalsaxena@boisestate.edu)

Vishal Saxena -2-– 2 –

Successive Approximation ADC

Vishal Saxena -3-

Successive Approximation ADC

– 3 –

• Binary search algorithm → N*Tclk to complete N bits

• Conversion speed is limited by comparator, DAC, and digital logic (successive approximation register or SAR)

Vishal Saxena -4-

Binary Search Algorithm

– 4 –

• DAC output gradually approaches the input voltage

• Comparator differential input gradually approaches zero

Vishal Saxena -5-

Charge Redistribution SA ADC

– 5 –

• 4-bit binary-weighted capacitor array DAC (aka charge scaling DAC)

• Capacitor array samples input when Φ1 is asserted (bottom-plate)

• Comparator acts as a zero crossing detector

Vishal Saxena -6-

Charge Redistribution (MSB)

– 6 –

R i R

i R X 4 X 3 2 1 0 X iV 8C- V 16C VV 16C = V - V C - V C +C +C +C V - V

16C 2

• Start with C4 connected to VR and others to 0 (i.e. SAR=1000)

Vishal Saxena -7-

Comparison (MSB)

– 7 –

• If VX < 0, then Vi > VR/2, and MSB = 1, C4 remains connected to VR

• If VX > 0, then Vi < VR/2, and MSB = 0, C4 is switched to ground

X

iR

X V2

V V:TEST MSB

Vishal Saxena -8-

Charge Redistribution (MSB–1)

– 8 –

R i

i R X X X R iV 12C V 16C 3V 16C V V 12C V 4C V V V

16C 4

• SAR=1100

Vishal Saxena -9-

Comparison (MSB–1)

– 9 –

• If VX < 0, then Vi > 3VR/4, and MSB-1 = 1, C3 remains connected to VR

• If VX > 0, then Vi < 3VR/4, and MSB-1 = 0, C3 is switched to ground

X R i3MSB -1 TEST : V V V4

X

Vishal Saxena -10-

Charge Redistribution (Other Bits)

– 10 –

Test completes when all four bits are determined w/ four charge redistributions and comparisons

• SAR=1010, and so on…

Vishal Saxena -11-

After Four Clock Cycles…

– 11 –

• Usually, half Tclk is allocated for charge redistribution and half for comparison + digital logic

• VX always converges to 0 (Vos if comparator has nonzero offset)

X

Vishal Saxena -12-

Summing-Node Parasitics

– 12 –

• If Vos = 0, CP has no effect eventually; otherwise, CP attenuates VX

• Auto-zeroing can be applied to the comparator to reduce offset

Vishal Saxena -13-

SAR ADC Summary

– 13 –

• High accuracy achievable (12+ Bits) • Low power and linear as no Opamp is required

• Relies on highly accurate comparator • Moderate speed (10 MHz) • Regaining interest in scaled CMOS processes

Vishal Saxena -14-

SAR ADC Limitations

– 14 –

•Conversion rate typically limited by finite bandwidth of RC network during sampling and bit-tests•For high resolution, the binary weighted capacitor array can become quite large

•E.g. 16-bit resolution, Ctotal~100pF for reasonable kT/C noise contribution•If matching is an issue, an even larger value may be needed

•E.g. if matching dictates Cmin=10fF, then 216Cmin=655pF•Commonly used techniques

•Implement "two-stage" or "multi-stage" capacitor network to reduce array size [Yee, JSSC 8/79]

•Split DAC or C-2C network•Calibrate capacitor array to obtain precision beyond raw technology matching [Lee, JSSC 12/84]

Vishal Saxena -15-– 15 –

Algorithmic (Cyclic) ADC

Vishal Saxena -16-

Algorithmic (Cyclic) ADC

– 16 –

•Essentially same as pipeline•But a single MDAC stage is used in a cyclic fashion for all operations•Need many clock cycles per conversion

Vishal Saxena -17-

Algorithmic (Cyclic) ADC

– 17 –

• Input is sampled first, then circulates in the loop for N clock cycles

• Conversion takes N cycles with one bit resolved in each Tclk

Samplemode

Vishal Saxena -18-

Modified Binary Search

– 18 –

• If VX < VFS/2, then bj = 0, and Vo = 2*VX

• If VX > VFS/2, then bj = 1, and Vo = 2*(VX-VFS/2)

• Vo is called conversion “residue”

• RA = residue amplifier

Conversionmode

Vishal Saxena -19-

Modified Binary Search

– 19 –

• Constant threshold (VFS/2) is used for each comparison

• Residue experiences 2X gain each time it circulates the loop

X

i

FS

clk

FS

Vishal Saxena -20-

Loop Transfer Function

– 20 –

• Comparison → if VX < VFS/2, then bj = 0; otherwise, bj = 1

• Residue generation → Vo = 2*(VX - bj*VFS/2)

VX

Vo

VFS/20 VFS

VFSbj=0 bj=1

Vishal Saxena -21-

Algorithmic ADC

– 21 –

• Hardware-efficient, but relatively low conversion speed (bit-per-step)

• Modified binary search algorithm

• Loop-gain (2X) requires the use of a residue amplifier, but greatly simplifies theDAC → 1-bit, inherently linear (why?)

• Residue gets amplified in each circulation; the gain accumulated makes the later conversion steps insensitive to circuit noise and distortion

• Conversion errors (residue error due to comparator offset and/or loop-gain non-idealities) made in earlier conversion cycles also get amplified again and again – overall accuracy is usually limited by the MSB conversion step

• Redundancy is often employed to tolerate comparator/loop offsets

• Trimming/calibration/ratio-independent techniques are often used to treat loop-gain error, nonlinearity, etc.

Vishal Saxena -22-

Offset Errors

– 22 –

Ideal RA offset CMP offset

Vo = 2*(Vi - bj*VFS/2) → Vi = bj*VFS/2 + Vo/2

Vi

Vo

VFS/20 VFS

VFSb=0 b=1

Vi

Vo

VFS/20 VFS

VFSb=0 b=1

Vi

Vo

VFS/20 VFS

VFSb=0 b=1Vos

Vos

Vi

Do

VFS/20 VFS Vi

Do

VFS/20 VFS Vi

Do

VFS/20 VFS

Vishal Saxena -23-

Redundancy (DEC, RSD)

– 23 –

Vi

Vo

VFS/20 VFS

VFSbj=0 bj=1

VFS/2Bj+1=0

Bj+1=1

Vi

Do

VFS/20 VFS00011011

Vi

Vo

VFS/20 VFS

VFSbj=0 bj=1

VFS/2Bj+1=0

Bj+1=1

Bj+1=-1

Bj+1=2

Vi

Do

VFS/20 VFS00011011

1 CMP 3 CMPs

• RSD= Redundant Signed Digit

Vishal Saxena -24-

Loop Transfer Function

– 24 –

Original w/ Redundancy

• Subtraction/addition both required to compute final sum

• 4-level (2-bit) DAC required instead of 2-level (1-bit) DAC

Vi

Vo

VFS/20 VFS

VFSb=0 b=1

Vi

Vo

VFS/20 VFS

b=0 b=1b=-1 b=2

Vishal Saxena -25-

Comparator Offset

– 25 –

• Max tolerance of comparator offset is ±VFS/4 → simple comparators

• Similar tolerance also applies to RA offset

• Key to understand digital redundancy:

jo

o

i

j

FSVV = +2

b2V

V

b

Vishal Saxena -26-

Modified 1-Bit Architecture

– 26 –

1-b/s RA transfer curvew/ no redundancy

One extra CMPadded at VR/2

0

VR/2

-VR/2

Vi

Vo

-VR/2 VR/2-VR

VR

VR

0

VR/2

-VR/2

Vi

-VR/2 VR/2-VR

VR

VR

b=0 b=1 b=0 b=1b=0.5

Vishal Saxena -27-

From 1-Bit to 1.5-Bit Architecture

– 27 –

-VR/4 VR/4

0

VR/2

-VR/2

Vi

-VR

VR

VR

b=0 b=1b=0.5

-VR/4 VR/4

0

VR/2

-VR/2

Vi

-VR

VR

VR

b=0 b=2b=1

Vo

A systematic offset –VR/4introduced to both CMPs

A 2X scaling is performedon all output bits

Vishal Saxena -28-

The 1.5-Bit Architecture

– 28 –

• 3 decision levels → ENOB = log23 = 1.58

• Max tolerance of comparator offset is ±VR/4

• An implementation of the Sweeny-Robertson-Tocher (SRT) division principle

• The conversion accuracy solely relies on the loop-gain error, i.e., the gain error and nonlinearity

• A 3-level DAC is required o i RV = 2 V - b -1 V

Vishal Saxena -29-

The Multiplier DAC (MDAC)

– 29 –

• 2X gain + 3-level DAC + subtraction all integrated

• A 3-level DAC is perfectly linear in fully-differential form

• Can be generalized to n.5-b/stage architectures

Vo

Vi

0-VR

VR

Decoder

Φ1 C1

Φ1 C2

Φ2

Φ1e

A

Φ2

-VR/4

VR/4

R1

2i

1

21o V

CC1bV

CCCV

o i RV = 2 V - b -1 V

Vishal Saxena -30-

A Linear 3-Level DAC

– 30 –

b = 0 b = 1 b = 2

Ri

TB1

2i

1

21

ooo

VV2

VVCCV

CCC

VVV

i

CMCM1

2i

1

21

ooo

V2

VVCCV

CCC

VVV

Ri

BT1

2i

1

21

ooo

VV2

VVCCV

CCC

VVV

Vo-

C1

C2

Vo+

C1

C2

AVT

VBVo-

C1

C2

Vo+

C1

C2

AVCM

VCM Vo-

C1

C2

Vo+

C1

C2

AVT

VB

Vishal Saxena -31-

Alternative 1.5-Bit Architecture

– 31 –

Ref: E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully digital correction of monolithic pipelined ADC’s,” IEEE Trans. on Circuits and Systems II, vol. 42, issue 3, pp. 143-153, 1995.

-VR/2 VR/2

0 Vi

-VR

VR

VR

b=0 b=2b=1

Vo

How does this work?

Vishal Saxena -32-

Error Mechanisms of RA

– 32 –

• Capacitor mismatch

• Op-amp finite-gain error and nonlinearity

• Charge injection and clock feedthrough (S/H)

• Finite circuit bandwidth

o i RV = 2 V - b -1 V

1 2 2o S/H i R

1 2 1 21 1

o o

C C CV t f V b 1 VC C C CC CA V A V

Vo

Vi

0-VR

VR

Decoder

Φ1 C1

Φ1 C2

Φ2

Φ1e

A

Φ2

-VR/4

VR/4

Vishal Saxena -33-

RA Gain Error and Nonlinearity

– 33 –

Raw accuracy is usually limited to 10-12 bits w/o error correction

R R

R

R

i

R

R

R

o

iR R

o

Vishal Saxena -34-

Static Gain-Error Correction

– 34 –

1 2 2o i R i R

1 2 1 21 1

1 2C C CV V b V V -b VC C ka kaC CC C

A A

1 2

1 21

oi 2i o

R 1 2 R 1 2

C CC VV CA b D = D + bV C C V C C

kd kd

Analog-domain method:

Digital-domain method:

Do we need to correct for kd2 error?

Vishal Saxena -35-

RA Gain Trimming

– 35 –

• Precise gain-of-two is achieved by adjustment of the trim array

• Finite-gain error of op-amp is also compensated (not nonlinearity)

C1/C2 = 1 nominally

1 2o i

1 21

2R

1 21

C CV VC CC

AC b 1 VC CC

A

Vo-

Vo+

i+

i-

X+

X-

12

12

Vishal Saxena -36-

Split-Array Trimming DAC

– 36 –

• Successive approximation utilized to find the correct gain setting

• Coupling cap is slightly increased to ensure segmental overlap

2C1.2C

8C4C2CC8C4C2CC

2C1.2C

8C4C2CC8C4C2CC

VX+

VX-

Vi+

Vi-

8-bit gain1-bit sign

Vishal Saxena -37-

Digital Radix Correction

– 37 –

2 1

2 1 2 1

2 1

j j j+1

j j+1 j+2

2j j+1 j+2

2 3j j+1 j+2 j+3

2 3j j+1 j+2

2 1

2 1 2 1 2 1

2 1 j+32 1 2 1 2

kd kd

kd kd kd kd

kd kd kd kd

kd kd kd kd kd kd

kd kd kd kd

D = b + D

= b + b + D

= b + b + D

= b + b + b + D

= b + b + bkd kd kd+ b +...

1 2

1 21

oi 2i o

R 1 2 R 1 2

C CC VV CA b D = D + bV C C V C C

kd kd

Unroll this:

Vishal Saxena -38-– 38 –

Integrating ADC

Vishal Saxena -39-

Single-Slope Integration ADC

– 39 –

• Sampled-and-held input (Vi)

• Counter keeps counting until comparator output toggles

• Simple, inherently monotonic, but very slow (2N*Tclk/sample)

i

fclk oX

Y

Vishal Saxena -40-

Single-Slope Integration ADC

– 40 –

• INL depends on the linearity of the ramp signal

• Precision capacitor (C), current source (I), and clock (Tclk) required

• Comparator must handle wide input range of [0, VFS]

1i 1 o

clk

io

clk

clk

tIV = t , D =C T

V D = ,I TC

I T LSB =C

Vishal Saxena -41-

Dual-Slope Integration ADC

– 41 –

• RC integrator replaces the I-C integrator

• Input and reference voltages undergo the same signal path

• Comparator only detects zero crossing

i

fclk

o

XR

Vishal Saxena -42-

Dual-Slope Integration ADC

– 42 –

• Exact values of R, C, and Tclk are not required

• Comparator offset doesn’t matter (what about its delay?)

• Op-amp offset introduces gain error and offset (why?)

• Op-amp nonlinearity introduces INL error

i Rm 1 2

i 2 2o

R 1 1

o 2 1

V VV = t = tRC RC

V t ND = = =V t N

or D =N for fixed N

X 1 2

m

os

Vishal Saxena -43-

Op-Amp Offset

– 43 –

Vi = 0 Vi = VR

N2 ≠ 0 → Offset Longer integration time!

Vi

Do

0 VR

Actual

IdealDos

Vishal Saxena -44-

Subranging Dual-Slope ADC

– 44 –

• MSB discharging stops at the immediate next integer count past Vt

• Much faster conversion speed compared to dual-slope• Two current sources (matched) and two comparators required

Vi

ControlLogic

SHA

Cnt 1(8 bits) MSB’s

VX

Cmp2

I

CS

I256

Cmp1Vt

Cnt 2(8 bits)

LSB’s

fclk Carry

Vishal Saxena -45-

Subranging Dual-Slope ADC

– 45 –

• Precise Vt is not required if carry is propagated

• Matching between the current sources is critical

→ if I1 = I, I2 = (1+δ)·I/256, then |δ| ≤ 0.5/256

• It’d be nice if CMP 1 can be eliminated → ZX detector!

X

X

dV 1 I ,dt C

dV 2 Idt 256C

21o NWND

X

1 2

t

Vishal Saxena -46-

Subranging Dual-Slope ADC

– 46 –

• CMP 1 response time is not critical• Delay from CNT 1 to MSB current shut-off is not critical

→ constant delay results in an offset (why?)• CMP 2 response time is critical, but relaxed due to subranging

Vishal Saxena -47-

Subranging Multi-Slope ADC

– 47 –

i

XS

fclk

Ref: J.-G. Chern and A. A. Abidi, “An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique,” in Proceedings of IEEE Custom Integrated Circuits Conference, 1989, pp. 6.2/1-6.2/4.

Vishal Saxena -48-

Subranging Multi-Slope ADC

– 48 –

• Single comparator detects zero-crossing

• Comparator response time greatly relaxed

• Matching between the current sources still critical

X

X

X

dV 1 I ,dt C

dV 2 I ,dt 16C

dV 3 Idt 256C

32211o NWNWND

Vishal Saxena -49-

Subranging Multi-Slope ADC

– 49 –

• Comparator response time is not critical except the last one• Delays from CNTs to current sources shut-off are not critical

→ constant delays only result in offsets• Last comparator response time is critical, but relaxed due to multi-

step subranging

Vishal Saxena -50-

References1. Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog

Converters,” 2nd Ed., Springer, 2005..2. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.3. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.