RISC5: Implementing the RISC-V ISA in gem5

Alec Roelke (ar4jc@virginia.edu)Mircea R. Stan (mircea@virginia.edu)

Introduction

n Increasing complexities of designs increases simulation overhead

n Proprietary libraries and architectures impede research and collaboration

n Solution: gem5—fast, flexible, freen Useful for RISC-V hardware development

2

RISC-V Simulation Platforms

3

Binary Translation

RTL

Sim

ulat

ion

Sim

ulat

ion

Acc

urac

y

Simulator Speed

spike

C++

QEMU

gem5Detailed CPU

gem5Atomic CPU

FS

SE

Gem5 Execution Modes

Verilog

Outline

n Implementation of RISC-V in gem5n Comparison with Other RISC-V Simulatorsn Performance and Validationn Example Simulation Flown Future Work

4

Implementation of RISC-V in gem5

n Includes 64-bit base ISA + standard extensions (RV64G)

n Supports single-threaded execution in SE mode

n No support for privileged ISA yet

5

Integer and Multiply Instructions

n Most instructions based on MIPSq e.g. fence (RISC-V) : sync (MIPS)

n Internal behaviors mostly copied from MIPS and Alpha

n Nearly all instructions implementedq Only eret has no implementationq fence does not support ordering flags

6

Atomic Instructions

n Release Consistency: acquire an address to see changes after earlier release

n LR/SC and atomic RMW instructionsn Mark instructions with ACQUIRE or RELEASEn RMW needs two memory operations—not

supported with memory timing!n Split into two micro-ops and add intermediate

register

7

Floating-Point Instructions

n Development machine missing max magnitude round mode

n Verified against spike and a hardware designq Invalid computation results (NaN, ∞, 0)q Floating point exceptions

8

Simulation Features

Feature gem5 Chisel spike QEMUBinary Translation ✔ ✔ ✔

Checkpoints ✔ ✔

Multicore Simulation ✔† ✔ ✔ ✔

Performance Statistics ✔ ✔‡

RTL Simulation ✔

System Call Emulation ✔ ✔§ ✔§

9

†Requires m5threads, which does not support RISC-V yet‡Only with support from design and/or software§System call emulation is supported via the RISC-V proxy kernel

Chisel: Bachrach et al., DAC 2012spike: https://github.com/riscv/riscv-isa-simQEMU: Bellard, ATEC 2005

Performance and Validation

n Configure gem5 to resemble Rocket Chipn Compare with FPGA and C++ simulatorn Run several SPEC CPU2006 benchmarks

10

Performance Results

11

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

bzip2 milc namd dealII soplex libquantum specrand

Run

time

(s)

Benchmark

Simulation Performance

gem5

FPGA

C++

Validation Results

12

00.20.40.60.8

11.21.4

bzip2 soplex libquantum specrand Average

Nor

mal

ized

Cou

ntgem5 to C++

cycleinstfetchinstretmemorybranch

0

0.5

1

1.5

bzip2 milc namd dealII soplex libquantum specrand Average

Nor

mal

ized

Cou

nt

gem5 to FPGA

Example Flow

13

gem5(RISC5)

Performance

Area

Floorplan

Power

Appl

icat

ion

Phase

SimPoint

McPAT

ArchFP

HotSpot

VoltSpot

n Simulate a section of the libquantum SPEC CPU2006 benchmarkn Exclude VoltSpot due to cycle-by-cycle input requirement

SimPoint: Sherwood et al., ASPLOS 2002 ArchFP: Faust et al., VLSI-SoC 2012 VoltSpot: Zhang et al., ISCA 2014McPAT: Li et al., MICRO 2009 HotSpot: Huang et al., TVLSI vol. 14 no. 5

Example Results

14

L2$

I$ D$

Register Files Pipeline

Rocket Chip

EXE

Ren

ame/

Issu

e

D$

I$

Register File

L2$

L2$

BOOM

Area: 4.175 mm2

Power: 1.0215 WArea: 1.367 mm2

Power: 5.1114 WProcess Size: 45 nmFrequency: 1.5 GHzVDD: 1.0 V

Rocket Chip: https://github.com/freechipsproject/rocket-chipBOOM: Celio et al., UCB/EECS-2015-167

Future Work

n Full support for all of gem5’s featuresq Multithreaded workloads in SE modeq Full-system modeq Correct minor differences (e.g. floating-point

rounding)n Improve modeling accuracyn Explore ISA effects on power/performance

15

Acknowledgments

n Pradip Bose, Schuyler Eldridge, and the rest of the IBM VELVET Team

n Members of the HPLP research groupn The gem5 community

16

Conclusion

n Implemented RISC-V in gem5n Compared with and validated against

Chisel C++ simulation and FPGAn Executed an example simulation flown Significant work left until full supportn RISC5 is available as part of the main

gem5 release at www.gem5.org

17

Version Information

18

Component Versiongem5 ffc29f2d9a5a†

User-level ISA 2.1Privileged ISA N/ARocket Chip 73e9508

Chisel b18e98b

†Refers to a Mercurial changeset hash; gem5 has since moved to git