rfp test bench development for mixed signal cmos imager · any new photonic devices such as optical...

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RFP

Test Bench Development for mixed

signal CMOS Imager

February, 2019

SPACE APPLICATIONS CENTRE

INDIAN SPACE RESEARCH ORGANISATION

DEPARTMENT OF SPACE

GOVERNMENT OF INDIA

AHMEDABAD 380015

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Contents Introduction 3

Section 1: Test Set-up configuration 3

Section 2: Scope of work 5

Section 3: Description of hardware and software development work 8

Section 4: Mechanical configuration 16

Section 5: Test and measurement 17

Section 6: Wire harness requirement for ambient and thermo-vacuum test conditions 18

Section 7: Vendor selection criteria 19

Section 8: Hardware and firmware acceptance criteria 19

Section 9: Deliverables: 20

Section 10: Delivery Schedule: 21

Section 11: Warranty: 22

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Introduction Testing, characterization and electrical stimuli optimization are integral part of development of

any new photonic devices such as Optical image sensor array (Device under test, DUT).

Dedicated test bench is developed to support evaluation of DUT with respect to electro-optical

parameters. To enable DUT evaluation, bias, clock, video processing, data acquisition and data

processing test boards/software modules are required. Mechanical structure is also required to

support these test boards and mount DUT in front of the optical stimuli. Thermal control system

is required to closely monitor and control DUT temperature during its operation in Laboratory

and vacuum conditions. Two types of test benches (type-1 & type-2) required to be

developed for evaluation two different types of DUTs.

Proposals are invited from reputed vendors having experience in developing electro-optical

test set-up for characterization of multi-line CMOS detector and evaluation of detector

performance. This document gives requirement of test set-up and also brings out briefly scope

of work, requirements from vendors, documentation from SAC, delivery schedule and

responsibilities.

Manufacturers are requested to submit their technical and commercial offers separately.

Commercial bid without price information shall be attached along with the Technical

offer.

Proposals are invited from vendors having experience in hardware and software development.

This document gives details of the development in the following sections:

Section-1: Test set-up configuration

Section-2: Scope of the Work

Section-3: Description of work

Section-4: Mechanical and thermal configuration

Section-5: Test and measurement

Section-6: Harness and mechanical fixture requirement

Section-7: Assembly, Integration, testing and DUT characterization

Section-8: Vendor selection criteria

Section-9 Board level and integrated testing / assembly / performance validation

Section-10 Hardware and firmware acceptance criteria

Section-11: Deliverables

Section-12: Delivery Schedules

Section-13: Warranty

Section 1: Test Set-up configuration Test setup configuration discussed the major blocks with in the test bench and associated responsibility

distribution between vendor and SAC. Following figure 1 shows basic block diagram of sensor

characterization test bench. Block with blue colour is vendor’s responsibility and green colour is SAC

responsibility.

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Figure 1: Electro-optical Test Bench Block Diagram for TB1 and TB2

1.1 SAC Responsibility:

1. Scene simulator: To generate uniform flat fields and desired test patterns depending

on type of measurements.

2. Power Supplies: To supply RAW power for test setup electronics.

3. Image Sensor: It is the DUT to be characterized. Two different test benches uses (1)

Four Band CMOS Imager (2) Two staggered array CMOS Imager

4. Instruments: Measuring instruments like Oscilloscope and multi-meter which can be

used with monitoring unit.

1.2 Vendor Responsibility [Development/Activity under Purchase Order]:

1. Detector Temperature Control Mechanism: Design and development of H/W &

S/W to maintain and monitor DUT temperature during Electro-optical characterization

and in laboratory environment and in vacuum environment (10-5 to 10-7 mbar). Vendor

to maintain the DUT temperature within ±0.5°C over the set temperature range of

15°C to 35°C in laboratory and 10 to 30°C for Vacuum.

2. System monitoring unit shall have the necessary H/W & S/W to monitor various

operating conditions and health parameters for drive electronics boards.

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3. Bias and Timing control board shall generate required biases, timing sequence and

control signal for image sensor operation.

4. Detector electronics board houses image sensor and interfaces with power supply,

Bias and timing and control board, Data-acquisition card and detector temperature

control mechanism.

5. Data acquisition cards is PCI/PCIe based digital acquisition cards for acquiring the

digital data from sensor output.

6. Host computer and storage is a PCI/PCIe slot based computer having interface with

digital acquisition cards along with software for data analysis, storage and archival.

7. Data analysis and archival S/W shall incorporate commanding & controlling of test

setup electronics and instruments during DUT characterization with provision for

DUT’s video data processing, analysis and data archival.

8. Optical Test Targets: These targets include test patterns for MTF measurement and

Electrical coupling measurement. Targets for MTF shall consists at least three bar

targets having spatial frequency Nq, Nq/2 and Nq/4. Where Nyquist frequency(Nq)

would be 62.5lp/mm.

Section 2: Scope of work This development of test bench involves design, fabrication and testing in the field of

electronics and thermo-mechanical H/w design. This section discusses in brief about the

activities which shall be carried out during the execution of this project. Workflow diagram for

the project is shown in figure 2. Blocks with blue colour is vendor’s responsibility and green

colour is SAC team’s responsibility. Blocks marked with orange colour symbols shall be

executed in SAC under supervision of SAC team. This work flow diagram will be identical

and executed in parallel for development of both the test benches.

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Figure :2 Tentative Work Flow for the Test Bench Development (TB1 and TB2)

vendor scope of work for different developments in two test benches is as follows:

2.1 Electrical development: Development of three different card fall in this category for

operation in ambient condition and vacuum: 1) Bias and Timing control board, 2) Detector

board, 3) Thermal control board. SAC is responsible for all the design inputs and vendor shall

generate PCB schematic and layout, component procurement, PCB fabrication, component

mounting, PCB testing and firmware development. Work details for both the test bench (TB1

and TB2) is provided below:

Schematic entry as per SAC designer’s inputs: Vendor shall make schematic as per

SAC design and need to take SAC designer’s approval before proceeding for layout. It

includes, Bias and timing control board, detector board, DAQ interface board and

temperature controller circuit.

PCB layout design: Vendor shall make multilayer PCB layout as per designer/ ISRO

guidelines and shall carry out the signal integrity analysis. PCB shall be designed from

testability point of view also.

Bare PCB fabrication: Vendor shall be responsible for bare PCB fabrication. Six sets

of multilayered PCB shall be fabricated for each card.

Components procurement: Components shall be procured by vendor as per SAC bill

of material.

PCB population: Soldering and wiring of minimum six sets of MLBs as per mounting

and fabrication sequence provided by SAC.

SoC microcontroller firmware development for creating necessary interface b/w (a)

Host PC and microcontroller (b) FPGA and microcontroller (C) Dynamic monitoring

of critical biases over USB interface

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FPGA firmware development for (a) Detector readout clocks generation, (b)

Selection of different operating mode options, (c) LVDS to CMOS TTL translation and

Digital data formatting.

Electrical testing: Vendor shall perform detailed electrical testing and functionality

verification on all the developed electrical hardware in presence of SAC personal before

delivering the hardware’s.

High Temperature burn-in@: Vendor shall carry out powered burn-in of

electrically/functionally tested and accepted PCBs (fully integrated) at 70oC at vendor

premises.

The vendor shall be responsible for supplying ZIF socket compatible with sensor

package with necessary thermal control interface.

2.2 Thermal control development: Vendor shall carry out the design and development of

close loop thermal control system. It will ensure DUT temperature during operation within the

accepted tolerance limit (see section 1.2.1). Detailed description of work is specified in later

section of this document.

2.3 Mechanical Development:

Vendor shall be responsible for design and fabrication of mechanical fixtures and enclosures

for fabricated PCBs. The mechanical fixtures ensure PCB assembly with DUT and ensures all

interfaces in upright orientation enabling uniform optical stimuli over the DUT plane. Apart

from fixtures, fabrication of optical test targets and thermos-vacuum flanges with suitable

connector interface is also the part of mechanical development.

Integration and Test: Vendor shall carry out the assembly and integration of the electrical,

mechanical and thermal H/Ws. He should also carry out the verification of the integrated test

bench (electrical + thermal + mechanical) with respect to functionality and specification.

Vendor shall also perform the necessary electro-optical tests on SAC DUT’s with functionally

verified and accepted E-O test bench. Vendor shall depute one dedicated engineer (minimum

educational qualification should be B.E. in electronics) per test bench for DUT

characterization. Estimated man-hour required for DUT characterization activity would be

3600 hrs during the period of 1.5 year/ per test bench. Vendor shall be solely responsible for

arranging logistics of person deputed for DUT characterization and for the persons visiting

SAC during project development.

As system will be used to evaluate performance of flight grade sensor, it has to undergo 168

hrs burn-in in vacuum at 70°C at vendor premises. Hence sub-system design, component

selection, assembly, integration, testing and overall system level performance evaluation plan

shall be presented by the vendor along with quotation.

Note: IP rights of the complete development will be SAC property.

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Section 3: Description of hardware and software development work 3.1 Electronics H/W Realization:

Image sensor drive electronics as shown in block diagram (figure-1), shall consist of detector

board, bias and timing control board, and thermal control board. Following are the list of

activities for the vendor to develop and deliver the above three types of electrical boards.

Quantity of each type of board is Qty:4+2 Nos. (Ambient + vacuum operation)

1. Schematic entry in consultation with SAC team.

2. Footprint design for all the components including socket as per SAC/ISRO guidelines

and component placement approval from SAC prior to layout design.

3. Layout of PCB boards in consultation with SAC. Vendor shall conduct necessary

simulations for SI and cross talk and ground bounce related issues. Analysis files shall

be provided to SAC for review.

4. Vendor to provide schematic and layout files compatible to Cadstar version 15 or less.

5. SAC shall approve Gerber data prior to fabrication of PCBs.

6. Fabrication of PCB boards.

7. Component procurement as mentioned in table 1 and 4 for fabrication of PCB.

8. Mounting and soldering of identified components on PCBs as per component mounting

and fabrication sequence provided by SAC.

9. Electrical testing of PCBs as per SAC guidelines.

10. SAC personal will review the PCB boards performance as mentioned in acceptance

criteria section and shall give clearance for the dispatch.

Requirements and component lists given in this section are tentative and may change slightly

depending upon the design changes. Final requirements shall be provided during schematic

entry stage after PO placement. Vendor has to report (documentation to be provided) any

deviation/failure happened during development phase and actions taken against the

deviation/failure.

The below section gives the brief details about the each of the electrical H/w with respect to

their functionality and interface with the rest of the cards, tentative card sizes, component types

and their tentative counts.

3.2 Detector Board:

Detector board houses DUT and its proximity electronics. DUT is SAC element, which

shall be provided during integration and characterization at SAC. This board houses

mainly bias filter and clock termination network.

This card will receive necessary clocks and biases from bias and timing control board

through D-sub (typical) connector interfaces.

DUT shall be mounted on zero insertion force (ZIF) socket for stress free mounting

and removal, there shall be cut out for thermal interface in ZIF socket such that thermal

control system can effectively take out heat from detector package and maintain it at

set temperature. SAC shall share typical design of ZIF socket along with PO. The

vendor shall be responsible for design and fabrication of the socket maintaining

thermal, mechanical and electrical requirements.

Tentative pin counts for each DUT is ~400(TB1) and ~300 (TB2) respectively.

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Tentative card size of Detector board will be: 200mm X 150mm

Tentative Controlled impedance on: 600 nets

Tentative Total No. of solder joints: 1200

Table1: Component list of Detector board (six sets of PCBs)

Component Type TB1

Qty

TB2

Qty

Operating

conditions of

components

Resistor from 2 Ω to 600

Ω (values shall be

finalized at the time of

schematic design)

tolerance: 1%,

1206 720 720 Industrial grade

vacuum

compatible

components

Resistor from 1k Ω to 300

kΩ (values shall be


schematic design)

tolerance: 1%,

1206 720 720

Capacitor (values shall be


schematic design,

tentative values: 1pF,

10pF, F 1000pF, 0.1uF)

Voltage: > 50V

Tolerance: 5%

Dielectric: x7r

0603 720 720

Polarized Capacitor

(values shall be finalized

at the time of schematic

design, tentative values

1uF, 4.7uF,10uF,20uF

Voltage: > 25V or > 50V

(depending on maximum

rating available in that

capacitance value)

Tolerance: 10%

CWR06H 360 360

37 pin connector (plug,

PCB mountable straight,

gold plated pin)

D sub 8 8

High density connector

(plug/socket)

(104 pins or more)

- 8 8

Vendor shall keep provision for extra components for replacement in case of failure.

3.3 Bias and Timing control board:

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Bias and timing control board shall consist of voltage regulators, SoC controller and FPGAs.

Bias and timing control board will serve the following functionality.

1. This board will generate DC biases for CMOS Imager, SoC controller and FPGAs.

Detector biases and clocks shall be interfaced to detector board through D sub

connector.

2. It will generate required timing logics for the detector including power ON and OFF

sequences, image sensor gain selection, exposure control and bias control.

3. Board will have provision for monitoring DC biases generated for the detector. These

biases will be logged using USB interface for recording and analysis purpose.

4. This boards shall have interface with the detector boards through LVDS connectors.

LVDS output from imager will be converted into CMOS TTL level in board FPGAs.

CMOS output from FPGAs will be sent for acquisition through VHDCI interface.

Table 2 shows bias requirement and RMS noise on bias Line

Table 2: Bias details per card (Type 1 & 2 Test Benches)

Sr. No. Bias (V) Current Tolerance Block RMS noise

1. 3.3 (10 nos) 400mA ±0.2V PSoC(1), FPGA(2),

DUT(7)

≤200μV at

1MHz

2. 2.5 (2 nos) 50mA ±0.2V FPGA(2)

3. 1.5 (2 nos.) 50mA ±0.1V FPGA(2)

4. 5 (2 nos.) 10mA ±0.2V PSoC(1) ,DUT(1)

5. 1.8 (4 nos.) 100mA ±0.2V FPGA(2), DUT(2)

6. 2 -3.3 (2 no’s)

100mA ±0.2V DUT (Vdd_pix,

vdd_tx)

Table 3: Input /Output Signal Details for TB 1 and TB 2

Sr.

No.

Input Signal No. of pins Level Input/Output Frequency

(TB1/TB2) TB1 TB2

1 LVDS input CLK

4 2 350mV

swing with

1.2V VCM

Input ~50MHz

2 SCLK 4 2 0-3.3V

CMOS TTL

Input ~4MHz

3 SSB 4 2 0-3.3V

CMOS TTL

Input ~4MHz

4 MISO 4 2 0-3.3V

CMOS TTL

Input ~4MHz

5 MOSI 4 2 0-3.3V

CMOS TTL

Input ~4MHz

6. RSTB 4 2 0-3.3V

CMOS TTL

Input -

7. Lsync 4 2 0-3.3V

CMOS TTL

Input ~4KHz

8. ExpCtrl 4 2 0-3.3V

CMOS TTL

Input ~4KHz

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9. BGReset 4 2 0-3.3V

CMOS TTL

Input -

10. DataValid 4 2 0-3.3V

CMOS TTL

Output -

11. Lsync_out 4 2 0-3.3V

CMOS TTL

Output ~4KHz

12. LVDS_P <11:0>

48 48 350mV

swing with

1.2V VCM

Output ~50MHz

13. LVDS_N<11:0>

48 48 350mV

swing with

1.2V VCM

Output ~50MHz

14. LVDS_CLKP

4 2 350mV

swing with

1.2V VCM

Output ~50MHz

15. LVDS_CLKN

4

2 350mV

swing with

1.2V VCM

Output ~50MHz

Tentative card size of Bias and Timing control board: 200mm X 200mm

Tentative No. of nets: 1250

Tentative Total No. of solder joints: 2500

Table 4: Bias and Timing control board Component List (six set of card)

Component Type Qty

( TB1)

Qty

( TB2)

Operating

conditions of

components

ADP 3336 regulator MSOP 120 120 Industrial

grade

vacuum

compatible

components

FPGA A3PE1500 (208pin

TQFN)

15 15

XTAL OSC AE CXO 255FG 15 15

FPGA JTAG

programmer

Flash pro 3 / 4 6 6

FPGA JTAG connector JTAG_NEW_FTSH

(10 PIN)

15 15

PSoC -3

100 PIN TQFP

CyC3866AXA-039

8 8

PSOC J-TAG

FTSH-103-01-L-

DV

8 8

USB socket USB Conn_Type

B_Molex_67068-

7041

8 8

Resistor from 2 Ω to 600

Ω (values shall be


1206 1500 1500

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schematic design)

tolerance: 1%

Resistor from 1k Ω to

300 kΩ (values shall be


schematic design)

tolerance: 1%

1206 1500 1500

Decoupling Capacitors



design tentative values:

1pf, 10pf, 100pf 1000pf,

0.1uf, 1uf, 1)

Voltage: > 50V

Tolerance: 5%

Dielectric: x7r

0603 1500 1500

Polarized Capacitors



design tentative values:

10uf, 22uf, 47uf)

Voltage: > 25V or > 50V

(depending on maximum

rating available in that

capacitance value)

Tolerance: 10%

CWR06H 1500 1500

15 Pin Socket Connector

(PCB mountable

straight, gold plated pin)

D SUB 12 12

15 Pin Plug Connector

(PCB mountable

straight, gold plated pin)

D Sub

12 12

37 Pin socket Connector

(PCB mountable

straight, gold plated pin

compatible with detector

board )

D SUB 12 12

LVDS buffer ( N no.

channel)

300/N 300/N

DDC connector 8 8

VHDCI cable (1.5 m) 8 8

High density connector

(plug/socket)

(104 pins or more)

- 8 8

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3.4 Thermal control board:

Thermal control board is a closed loop control system which control the DUT temperature

during operation within the allowed error band. Below table gives the details about the

requirement for the thermal control system.

Table: 5 Thermal Control Board Requirement

S.No Parameter Value

1. DUT power dissipation 6W (type -1)

4 W (type-2)

2. DUT accessible surface area ~ 80 x 30mm (type -1)

~ 80 x 15 mm (type-2)

3. Temperature range 15°C to 35°C (laboratory)

10°C to 30°C (vacuum 10-5 to 10-7

mbar)

4. Set temperature error band ±0.5°C ( During testing phase of

typically two hours )

The design and development for the thermal control system is vendor responsibility. He shall

propose the suitable thermal scheme for the required thermal stability and cooling/heating

mechanism.

Work details for above requirement is as follows:

SAC shall provide configuration design to vendor. It would be vendor responsibility to

design the control system and meet overall requirements.

Vendor shall propose the TEC base or / Cu cold finger/ chiller and heat pipe based

control system.

Based on the proposed method vendor should procure components e.g. chiller, Cu

finger, interface plate, and heat pipe.

Design, fabrication, wiring and testing of PCBs required in temperature control system.

Integrate the sub system.

Test and validation of thermal control system with load simulator and submission of

detailed test report to SAC.

Delivery of complete thermal control system at SAC after review of test results by SAC

team.

Validation of temperature control with actual load.

Accessories or materials like thermal glue or thermal grease shall not be used in temperature

control mechanism.

3.5 System command/control and monitoring

Vendor shall provide system monitoring and data logging unit with display. This unit shall

have the necessary H/W & S/W to monitor and log data under various operating conditions

which shall include at least the following:

1. Control and Monitor/logging light power & scene simulator settings

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2. Control and Monitoring/logging of detector settings including operating mode, bias

voltage setting

3. Control and Monitor/logging detector temperature

4. Control and Monitor/logging regulated power supplies and currents

5. Perform diagnostics and monitor test bench health and safety (overvoltage / over

current) parameters

The logged parameters shall provide necessary feedback for correction or recording set-up

configuration. Logged data shall be recorded in data logger memory in standard format like

MS Word/ Excel. Interface with instruments is through USB, LAN and RS232. Following are

the major instrument, which requires control:

Table: 6 Test Instrument Details

S.No Instruments Model No. Interface

1. Agilent power supply N6700B USB

2 Keithley Multimeter 2700 GPIB

3 New Port Power meter 2936-C USB

5 Lamda power supply GEN 150-10 LAN/USB

6 Keithley power supply 2230-30-1 USB

3.6 Firmware/ Software development

Vendor shall develop firmware for the following activities:

1. FPGA firmware: Vendor shall develop VHDL/verilog FPGA timing logic as per SAC

requirement to generate the required timings for imaging sensor. Imaging sensor ON

and OFF sequence shall also be incorporated in the firmware. FPGA shall have

interface with SoC controller for variability in the timings. Timing details and power

ON and OFF sequence details will be provided to the vendor along with PO.

FPGA core utilization for A3p1500 Actel is expected to be ≤50%.

2. SoC controller firmware: Vendor shall develop firmware for (a) monitoring DC biases

of the detectors as per SAC requirements. (b) Firmware for creating necessary interface

b/w (a) Host PC and microcontroller (b) FPGA and PSoC controller.

3.7 Host Computer Requirement:

Table: 7 Host System Specification

S.No. Specification Value

1. No. of Host systems 2 units per test bench

2. Processor 2.3 GHz or more

3. No. of Cores 8 core or above

4. Installed RAM 8 GB or more

5. HD drive 2TB HDD drive or more

6. Operating system* Licensed version of Window 10

or above

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7. Accessories Monitor (27 inch or more),

Keyboard, Mouse

8. PCI slots 2 or more

9. S/W development Tool* Licensed version of

LabVIEW2016 professional or

above preinstalled with system

10 Microsoft office* Licensed version of MS office

2016 or above pre-installed

11. USB ports 5 or more

12. CD/ DVD writer Required

13. Display port Compatible with Monitor

14. Power Supply 230±10 V 50Hz (Indian Standard)

*Vendor must deliver the CD/DVD of the third party software installed in the system.

3.8 Digital Acquisition Cards Specification:

CMOS output from the Bias and timing control board will be acquired using digital acquisition

cards. Vendor has to procure and configure the digital acquisition cards for sensor data

acquisition and processing. Table 9 shows the specification for the digital acquisition card.

Table: 8 Digital Acquisition Card Specification

S.No. Specification Value

1. No. of acquisition cards 2 cards per test bench

2. Acquisition Voltage

levels

1.8, 3.3 and 5 V Compatible

3. Input Data rate 10MHz to 100MHz

4. Number of parallel

channel/ card

≥32

5. Card Memory ≥64Mb/channel

6. Input impedance of

digital channel

≥10KΩ

7. No. Sample clock 4 or more

8. Maximum internal skew

allowed b/w data

channels

≤±1.25ns

9. Sample clock duty cycle

variation allowed

45%≤ Duty cycle ≤ 55%

10. Sampling mode Rising edge,

Falling edge,

Delayed mode

11. Compatibility Compatible with

PCI slot of Host PC of table 8

12. Operating Temperature 0 - 55 °C

3.9 Data Acquisition, Analysis and archival S/W:

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Vendor shall develop the necessary S/W for acquisition of the digital data over the VHDCI

interface on compatible s/w tool. The s/w must also carry out the pre-processing and formatting

on the acquired data. In addition, s/w must have provision for raw/formatted data storage,

archival and analysis. Following are the minimum requirements for acquisition and processing

S/W.

GUI based acquisition and processing acquired data

Processing of data as per SAC definition

Storing and archival of acquired data

Report generation

Automatic Test Procedures for Linearity, Dynamic Range, Signal to Noise, PRNU,

Saturation, Dark Offset, Dark Noise, Crosstalk, Responsively, Quantum Efficiency,

Spectral response, SWR, etc.

Statistical analysis like pixel/ port wise histogram, standard deviation, averaging on

region of interest.

The software must be compatible with windows operating system. All development tools shall

be upgradeable. Copy of source code of software shall be delivered to SAC. All software

functions and test procedures shall be adequately described and documented.

Section 4: Mechanical configuration 4.1 Mechanical Fixtures:

(Requirement is similar for TB1 and TB2.)

Manufacturer shall design the mechanical fixtures for mounting the detector drive electronics

boards. Mechanical configuration must ensure the cards, DUT and electrical/thermal interface

placement to be such that (a) it allows uniform optical stimuli over the DUT plane (b) clamp

the whole assembly steady, stable and upright position (c) Maximally accessible for debugging

and physical monitoring. (d) Must avoid secondary optical path over DUT.

Figure 3. shows the tentative representation of mechanical configuration. Vendor must keep

the following points while designing the mechanical configuration.

(a) All PCBs board shall have suitable mounting holes on the four corners in order to

facilitate mounting of the cards.

(b) Detector board shall have necessary cut out to make provision for thermal

implementation.

(c) Vendor has to provide ten sets of black anodized Aluminum mechanical fixtures

compatible to PCB size (type-1: 5sets type-2: 5 sets).

(d) Vendor must also provide mechanical enclosures/ packages for the developed PCBs.

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Figure 3 Tentative Mechanical Configuration

4.2 Optical Test Targets


Vendor has to design and fabricate different types of BAR targets. These targets include test

patterns for MTF measurement and Electrical coupling measurement. Targets for MTF shall

consists at least three bar targets having spatial frequency Nq, Nq/2 and Nq/4. Where Nyquist

frequency(Nq) would be 62.5lp/mm. Target for electrical coupling shall be design such that it

illuminates the few pixels of the imager or any particular line/section of imager.

Preferred base material for a target is glass. Elaborated details for targets design (both for

MTF/electrical coupling) will be provided after PO placement.

4.3 Thermovacuum Flange


Vendor has to design and fabricate mechanical flange (Qty.2) with following connector

interfaces.

Connectors interface for interfacing detector input signals with bias and timing control

board.

Connector interface for interfacing detector LVDS output signal with Bias and timing

control board.

S.No. Parameter Value

1. Flange diameter ~255mm

2. Flange Thickness 10mm

3. Flange material Tentatively stainless steel

Section 5: Test and measurement EO Measurements shall be categorised in four different categories:

1. LTC measurement:

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This measurement shall be done at twenty different aperture settings of uniform light source

covering detector output from dark to saturation. This measurement cover processing of

following EO parameters:

Dark Counts

Dark noise

Conversion gain

Signal to noise ratio

Saturation count

Bad pixel Map

2. MTF measurement:

Collimated light shall fall on the detector. Measurement is done by projecting targets of

different frequencies (ηc, ηc/2 and ηc/4) on detector. Vendor has to design and fabricate these

targets.

3. QE measurement:

In this measurement monochromatic light covering wavelength range from 350nm to 1050nm

shall fall on detector. Detector data shall be acquired at each wavelength and QE shall be

processed as per formula/procedure defined at the time of purchase order.

4. Inter array coupling measurement:

Device under test is multiline CMOS linear array integrated with strip filter. There is possibility

of electrical as well as optical coupling because of device architecture or overlaid filters. To

measure this parameter different targets are required such that few pixels of any one array, any

two arrays, any three arrays, and any four arrays can be illuminated.

Section 6: Wire harness requirement for ambient and thermo-vacuum

test conditions Wire harness is required for providing power to the PCB boards or for interconnecting different

PCB boards during operation of test bench in laboratory and vacuum chambers. Vendor shall

provide necessary wire harness for TB1 and TB2 meeting following typical requirements.

Harness Requirement for laboratory Testing

Six sets of (tentative length: two meter) fabricated harness for test bench operation in ambient

condition as per following.

Six sets of LVDS cable (gore cable/ equivalent) with 105 or more plug pins connector

on one side and 105 or more socket pins connector on another side

Six sets of Twisted pair shielded two core 26 AWG (2A rating) with one side 37 pin D

sub plug and on another side 37 pin D sub socket connector.

Six sets of Twisted pair shielded two core 26 AWG (2A rating) with one side 15 pin D

sub plug and on another side 15 pin D sub socket connector.

Harness requirement for thermos-vacuum flange:

Two sets of (tentative length: two meter) fabricated harness for test bench operation in thermo-

vacuum condition as per following.

Two sets LVDS cable (gore cable/ equivalent) with 104 plug pins connector on one

side and 104 socket pins connector on another side

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Two sets of Twisted pair shielded two core 26 AWG (2A rating) with one side 37 pin

D sub plug and on another side 37 pin D sub socket connector.

Section 7: Vendor selection criteria Following are the vendor selection criteria for development of test bench

1. Vendor shall submit necessary document along with technical offer showing his capabilities of

developing test bench or camera systems for CCD/CMOS imaging sensors along with thermal

control system.

2. Vendor shall provide references of similar development carried out in the past. In the absence of

such details the offer shall be rejected.

3. Vendor shall have PCB development tool (Cadstar 15.1or less is preferable, if vendor choose to

design PCB schematic and layout in different version than he must translate designs into Cadstar

15.1).

4. Vendor shall have at least following pre-requisite hardware in his premises:

Tunable DC Power supply units generating DC voltages in the range of 0 to 40V with at least

1A current capacity

CRO/DSO with probes having minimum 500MHz bandwidth

At least 6 and ½ digit precision multi-meter

Soldering station capable to solder fine pitch surface mount components (mentioned in

component list)

ESD safe soldering and testing tables

FPGA and SoC evaluation kits

5. Vendor has to provide point by point compliance of RFP requirement and shall submit sufficient

information meeting above requirements with the technical offer for the evaluation of vendor

capabilities. SAC reserves right to reject the offer having lack of information.

Section 8: Hardware and firmware acceptance criteria Detector card

Compatibility of designed foot prints with actual components

Electrical test checks of bare PCB with Gerber data at vendor premises (pre dispatch)

Compatibility check of PCB with mechanical enclosure/fixture at vendor premises (pre

dispatch)

Electrical test at lab conditions initially and after powered burn-in at +70°C /168 hrs at vendor

premises. Deviation between initial and after powered burn-in measurement values shall not

more than ±10%.

Firmware shall be considered accepted only if the integrated performance is acceptable post-

dispatch.

Bias and Timing control board:

Compatibility of designed foot prints with actual components (Pre-dispatch)

Electrical test checks of bare PCB with Gerber data(Pre-dispatch)

Timing logic generation with jitter tolerance of ≤1% (Pre-dispatch)

Rise and fall time ≤25ns with capacitive load of 25 pF at Voltage swing of 3.3V (Pre-dispatch)

Timing measurement at lab conditions initially and after powered burn-in at

+70°C /168 hrs. This activity shall be carried out at SAC (after dispatch). Deviation between

initial and after powered burn-in measurement values shall not more than ±10%.

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Detector temperature and control mechanism

Detector temperature within ±0.5°C in the set temperature range from 15°C to 35°C in ambient

and 10°C to 30°C vacuum for two hours’ operation.

Firmware acceptance criteria

SoC Firmware Acceptance: Vendor shall demonstrate the SoC controller functionality in terms

of (a) Verify SoC interface with FPGA and USB (b) Critical bias measurement of DUT with

≤5mV error.

FPGA Firmware Acceptance: Vendor shall demonstrate the (a) required timing relation for

DUT (b) verify the SPI interface via reading and writing the SPI registers of DUT (C) Verify

LVDS to single ended conversion for all LVDS channels.

Firmware shall be considered accepted only if the integrated performance (SoC +FPGA +DUT

+digital acquisition) is acceptable post-dispatch.

At SAC, vendor shall demonstrate above parameters initially at lab conditions and after

completion of powered burn-in of delivered hardware.

Integrated performance validation

Vendor shall validate performance of individual sub systems at integrated level in loaded (dummy load

and or/ DUT load) condition with respect to sub system level acceptance criteria of section 8.1 catering

following points:

1. Bias generating board: Bias voltage, noise

2. Timing and control board: Timing relationship, Clock jitter, Control signal generation

3. Detector board integrated with bias generating board and timing and control board: clock

parameters and bias parameter verification at DUT pins.

4. DAQ Interface Card: With LVDS input of 70% eye opening measuring the valid CMOS output

for all LVDS channels.

5. Thermal control validation (DUT load)

6. Software validation (DUT load): Data acquisition, processing software

Section 9: Deliverables: Table :9 Deliverables

Sr.No Deliverable Quantity

(Type -1TB )

Quantity

(Type -2 TB)

1 Populated detector board 6 6

2 Populated Bias and timing control card 6 6

3 Thermal control H/w design and

fabrication * (ambient + vacuum)

6 (4+2 ) 6 (4+2)

4 Digital Acquisition Cards# 4 4

5 Host computer + accessories (monitor +

keyboard + mouse)

2 2

6 Compatible VHDCI cable 8 8

7 Targets for MTF 3 3

8 Targets for inter array coupling 3 3

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9 Mechanical fixtures(Detector board +

Bias-timing + thermal control board)

6 for each

type of card

6 for each

type of card

10 Mechanical Enclosure (Detector board +

Bias-timing + thermal control board)

6 for each

type of card

6 for each

type of card

11 Thermo-vacuum flange with compatible

connector

2 2

12 Data Analysis, data archival and data

display software

1 1

13 Harness sets for thermos-vacuum 2 2

14 Harness sets for ambient condition 6 6

15 Assembly, Integration, testing and

characterization of DUT at SAC for 7200

hours within the period of one year and

half year

- -

16 Documents: Test report, PCB gerber file,

PCB Schematic, s/w source code

1 1

17 Software Manual 1 1

18 Firmware 1 1

19 ZIF sockets 12 12

20 Spare Components’ set (as used in

deliverable no.1,2,3, for replacement post

warranty)

2 sets 2 sets

21 Testing and characterization of DUT at

SAC for 3600 hours within the period of 1.5

year

1$ 1$

* For thermal control design and fabrication four unit shall be used for laboratory environment

and other two shall be used in vacuum environment, hence necessary modification should

be incorporated for vacuum compatible thermal control system.

# Point 4 of the above tables assumes vendor develop the digital acquisition chain with 32

channels digital acquisition cards. If he chooses to use higher channel digital acquisition the

card quantity will reduce accordingly.

$ Quantity here refers to no. of dedicated engineers to be deputed for DUT testing after

delivery and acceptance of complete test bench.

Section 10: Delivery Schedule:

Table :10 Delivery Schedule

Activity Time Schedule ( type-1 and type-2 Test bench)

SAC responsibility Vendor responsibility

Design for different PCBs to be provided to vendor

T0

Schematic entry for different PCBs

T1: T0+10days

SAC clearance on schematic entry

T2:T1+2 day

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PCB layout design for different PCBs

T3: T2+30 days

SAC clearance on PCB layout

T4: T3+7days

Bare PCB fabrication T5: T4+ 15days

PCB population, Firmware development and electrical tested PCB delivery (all types and each quantity 5 No.)

T6: T5+30days

Software delivery T7:T0+100 days

Temperature control mechanism design

T8:T0+40 days

Development and delivery of tested temperature control mechanism

T9: T8+65 days

ZIF socket delivery T10: T0+120 days

Mechanical fixtures and targets delivery

T11: T0+120 days

Assembly, integration and testing at SAC

T12:T11+ 450 working days

T0: Purchase order placement Delivery schedule for both type of test bench is parallel. Only T0 time can be different.

Section 11: Warranty: Vendor shall provide warranty for 1 year from the date of acceptance. During warranty period,

vendor shall provide support for free of cost repair of hardware deliverables and bug-fixing of

software deliverables. For off-the-shelf hardware, vendor shall provide free replacement/repair

within warranty period of that hardware. Vendor shall give the details of the approach to

support during warranty.

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Compliance matrix table

Vendor has to submit fully filled compliance matrix table with technical proposal. In absence

of fully filled compliance matrix table, vendor’s proposal shall be rejected.

Sr.

No.

Requirement Compliance

(YES/NO)

Remarks

1. Vendor has understood his responsibilities

detailed in section 1 of this RFP and agrees to

comply with it.

2. Vendor agrees to work as per work flow

diagram and carry out all the work falling

under his scope of work as per section 2 of this

RFP.

3. Vendor has submitted a Technical proposal

including sub-system design, component

selection, assembly, integration, testing and

overall system level performance evaluation

plan meeting RFP requirements.

4. Vendor agrees to do high temperature burn-in

of tested electronic PCBs after integration as

per RFP requirement.

5. Vendor has provided temperature controlling

scheme in its Technical proposal.

6. Vendor agrees to provide ZIF socket as per

final design requirement of Detector board.

7. Vendor agrees to meet all the specification

requirements of detector boards as per section

3.2

8. Vendor agrees to procure and use components

required for detector board meeting operating

condition requirement as per Table 1.


requirements of Bias and Timing Control

board as per section 3.3.

10. Vendor agrees to procure and use components

required for Bias and Timing Control meeting

operating condition requirement as per Table

4.


requirements of Thermal control board as per

section 3.4 of RFP

12. Temperature controlling scheme provided by

vendor meets specification requirement as per

table:5 of RFP

13. Vendor agrees to procure and use the required

component for thermal control scheme

implementation.

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14. Vendor agrees to develop the control,

acquisition and monitoring S/W as per section

3.5 and 3.9 of RFP

15. Vendor agrees to develop the Firmware for

PSoC and FPGA as per section 3.6 of RFP

16. Vendor agrees to supply the host computers

and accessories as per specification of table 7

of RFP

17. Vendor agrees to supply the digital acquisition

cards as per specification of table 8 of RFP

18. Vendor agrees to develop the mechanical

fixtures, test targets and Thermovacuum

flange as per section 4.1,4.2 and 4.3 of RFP

19. Vendor agrees to perform the test and

measurement as per the section 5 of RFP

20. Vendor agrees to supply the necessary harness

as per section 6 of the RFP.

21. Vender agrees to H/W S/W acceptance criteria

as per section 8 of RFP.

22. Vendor agrees to deliverables for both the test

benches as per table 9 of RFP.

23. Vendor agrees to delivery schedule as per

section 10.

24. Vendor agrees to warranty terms as per section

11.