Project Number: JKM-1A03

RF APPLICATIONS

A Major Qualifying Project Report:

submitted to the Faculty

of the

WORCESTER POLYTECHNIC INSTITUTE

in partial fulfillment of the requirements for the

Degree of Bachelor of Science

By

________________________

Pavlo Fedorenko

________________________

Christopher J. Huber

________________________

John G. Kauffman

Date: March 15, 2004

Approved:

__________________________________

Professor John A. McNeill, Advisor

ii

Abstract

An increased demand for wireless communications is driving semiconductor

companies to provide chipset solutions to manufacturers. By providing chipsets, time to

market and design responsibilities are reduced for manufacturers. This project

investigated a wireless transceiver design based upon Analog Devices products.

This paper presents mathematical models of various data transmission schemes,

examining their bandwidth efficiency, phase walk, and noise tolerance. Various

hardware interfacing solutions are described. Characterization measurements evaluating

the system performance confirmed the mathematical modeling results.

iii

Acknowledgments

We would like to thank the following people for helping make this project a success:

− John A McNeill − Donald Brown − Yuping Toh − Steve Laverty − Ben Woodacre − Eamon Nash − Eric Newman − Sergey Makarov

iv

Table of Contents Abstract_______________________________________________________________ ii

Acknowledgments_______________________________________________________ iii

List of Figures _________________________________________________________ vi

1 Introduction _______________________________________________________ 1

2 Background Research _______________________________________________ 3 2.1 Modulation Schemes__________________________________________________ 3

2.1.1 Modulation Scheme Comparison Criteria _______________________________________ 7 2.2 Direction Conversion Vs. Superheterodyne _______________________________ 9 2.3 Synchronization_____________________________________________________ 11

2.3.1 Synchronization from Transmitter to Receiver __________________________________ 11 2.3.2 Synchronization within the Receiver__________________________________________ 12

2.4 Filtering ___________________________________________________________ 14 2.4.1 Sampling Frequency ______________________________________________________ 14

2.5 Group Delay _______________________________________________________ 15 2.5.1 Summary of Design Choices ________________________________________________ 17

3 Hardware Implementation___________________________________________ 18 3.1 Transmitter ________________________________________________________ 18

3.1.1 DAC Inputs and Data Generation ____________________________________________ 19 3.1.2 DAC Output Resistor Network ______________________________________________ 20 3.1.3 DAC Output Filters _______________________________________________________ 22 3.1.4 AD8349 Direct Conversion Modulator ________________________________________ 23

3.2 Wireless Link_______________________________________________________ 24 3.2.1 Matching _______________________________________________________________ 26

3.3 Receiver ___________________________________________________________ 31 3.3.1 ADF4212 Dual IF/RF PLL Frequency Synthesizer_______________________________ 32 3.3.2 Passive Mixer ___________________________________________________________ 33 3.3.3 190MHz SAW Filter ______________________________________________________ 34 3.3.4 AD8348 IF Quadrature Demodulator _________________________________________ 37 3.3.5 AD9862 12-bit Dual ADC__________________________________________________ 38

4 Mathematical Modeling_____________________________________________ 39 4.1 Pulse Shaping of Baseband Data _______________________________________ 39

4.1.1 Shaped Waveform Construction _____________________________________________ 41 4.1.2 Shape Properties _________________________________________________________ 41 4.1.3 Comparison of Sigmoidal Pulse Shaping and Shaping Windows Used in Industry ______ 45

4.2 Data Encoding ______________________________________________________ 48 4.3 Data Reconstruction _________________________________________________ 51

4.3.1 Matched Filter ___________________________________________________________ 54 4.3.2 Downsampling Process ____________________________________________________ 54 4.3.3 Detection _______________________________________________________________ 55

5 Results___________________________________________________________ 56 5.1 Measured DAC Output Results ________________________________________ 56 5.2 Phase Walk Characterization _________________________________________ 57

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5.3 Frequency Mismatch Limitations ______________________________________ 59 5.4 Wireless Link Limitations ____________________________________________ 62

6 Conclusions and Future Work _______________________________________ 65 6.1 Recommendations ___________________________________________________ 66

6.1.1 PLL Frequency Generation _________________________________________________ 66 6.1.2 DAC/ADC Control _______________________________________________________ 67

7 References _______________________________________________________ 70

8 Appendices _______________________________________________________ 71 8.1 Appendix A – MATLAB Code_________________________________________ 71

8.1.1 Exportpattrighalf.m _______________________________________________________ 71 8.1.2 Iqinit.m ________________________________________________________________ 73 8.1.3 Listread.m ______________________________________________________________ 76 8.1.4 Received_detection.m _____________________________________________________ 77 8.1.5 Shapedata.m_____________________________________________________________ 81

8.2 Appendix B – Absolute QPSK Detection Schemes_________________________ 87 8.2.1 Downsampling Process ____________________________________________________ 88 8.2.2 Magnitude Dependent and Independent Reconstruction ___________________________ 89

8.3 Derotation Schemes__________________________________________________ 92 8.3.1 Derotation by Abrupt Changes ______________________________________________ 92 8.3.2 Derotation by Average Changes Stored in a Finite Array __________________________ 94 8.3.3 Derotation by Delta Change. ________________________________________________ 96

8.4 Appendix C – Product Datasheets______________________________________ 97

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List of Figures Figure 1.1 - System Block Diagram. _______________________________________________________ 1 Figure 2.1 - BPSK Constellation. _________________________________________________________ 4 Figure 2.2 - Inphase and Quadrature Waveforms [2]. _________________________________________ 5 Figure 2.3 - Modulated In-phase and Quadrature Components. _________________________________ 6 Figure 2.4 - QPSK Constellation. _________________________________________________________ 7 Figure 2.5 - Error Dependence on the Number of Symbols in M-QPSK [12]. _______________________ 8 Figure 2.6 - Problems with Direct Down Conversion [8]. _____________________________________ 10 Figure 2.7 - (A) Stable Constellation, (B) Rotating Constellation. _______________________________ 12 Figure 2.8 - Receiver Synchronization. ____________________________________________________ 13 Figure 2.9 - Sampling Frequency.________________________________________________________ 14 Figure 2.10 - Low Group Delay. _________________________________________________________ 16 Figure 2.11 - High Group Delay. ________________________________________________________ 16 Figure 3.1 - Transmitter Block Diagram. __________________________________________________ 18 Figure 3.2 - Timing Diagram. ___________________________________________________________ 20 Figure 3.3 - AD9862 Output Resistor and Filter Network. ____________________________________ 21 Figure 3.4 - Filter Response with Signal Spectrum. __________________________________________ 22 Figure 3.5 - AD8349 Detailed Block Diagram (Analog Devices). _______________________________ 24 Figure 3.6 - Quarter Wavelength Monopole Antenna. ________________________________________ 25 Figure 3.7 - Return Loss of a Quarter Wavelength Monopole Antenna ___________________________ 26 Figure 3.8 - Antenna Impedance on the Smith Chart. _________________________________________ 28 Figure 3.9 - Input impedance of the Antenna with a Matching Network. __________________________ 30 Figure 3.10 - Return Loss at the Matching Network Interface Looking into the Antenna______________ 31 Figure 3.11 - Receiver Block Diagram.____________________________________________________ 32 Figure 3.12 - ADF4212 IF/RF Configuration (Analog Devices). ________________________________ 33 Figure 3.13 - Delay and Summation Filter [7]. _____________________________________________ 35 Figure 3.14 - Weighting Coefficients [7]. __________________________________________________ 35 Figure 3.15 - Filter Frequency Response [7]._______________________________________________ 36 Figure 3.16 - Physical Filter Layout [7]. __________________________________________________ 37 Figure 4.1 - Baseband Data Constructed out of Square Steps. __________________________________ 40 Figure 4.2 - Fuzzy Logic Waveforms. _____________________________________________________ 43 Figure 4.3 - Frequency Content of the Fuzzy Logic Waveforms. ________________________________ 44 Figure 4.4 - Bandwidth Accumulation by Fuzzy Logic Functions. _______________________________ 45 Figure 4.5 - Industry Standards in Comparison with Sigmoidal. ________________________________ 46 Figure 4.6 - Frequency Content of Chebyshev, Hann and Sigmoidal Waveforms. ___________________ 47 Figure 4.7 - Comparison of Bandwidth Accumulation by Chebyshev, Hann and Sigmoidal Windows. ___ 48 Figure 4.8 - Differential QPSK Constellation. ______________________________________________ 49 Figure 4.9 - Circular Array. ____________________________________________________________ 50 Figure 4.10 - Conceptual View of Circular Array Data Encoding. ______________________________ 51 Figure 4.11 - Transmitted I and Q Sigmoidal Signals. ________________________________________ 52 Figure 4.12 - Received Signal Corrupted by Noise and Walk. __________________________________ 53 Figure 4.13 - Matched Filter Processing. __________________________________________________ 54 Figure 5.1 - DAC Output Frequency Response. _____________________________________________ 57 Figure 5.2 - Measured Phase Walk. ______________________________________________________ 59 Figure 5.3 - Created I and Q Data._______________________________________________________ 60 Figure 5.4 - Transmitted I and Q Data.____________________________________________________ 60 Figure 5.5 - Received Constellations at Different Frequency Mismatches. ________________________ 61 Figure 5.6 - Received I and Q Data. ______________________________________________________ 62 Figure 5.7 - Constellation of Received Data at 58cm Transmission. _____________________________ 63 Figure 5.8 - Constellation of Received Data at More 58cm Transmission. ________________________ 64 Figure 6.1 - Software Display for PLL Frequency Generator. __________________________________ 66 Figure 6.2 - Software Display of DAC/ADC. _______________________________________________ 69 Figure 8.1 - Magnitude and Phase of the Received Signal Difference.____________________________ 88 Figure 8.2 - Magnitude Independent Reconstructions. ________________________________________ 90 Figure 8.3 - Magnitude Dependent Reconstruction. __________________________________________ 91 Figure 8.4 - QPSK plane. ______________________________________________________________ 93

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Figure 8.5 - Removing Walk by Abrupt Change._____________________________________________ 94 Figure 8.6 - Construction of Finite Array. _________________________________________________ 95 Figure 8.7 - Visual Diagram of Delta Change Derotation._____________________________________ 96 Figure 8.8 - An Example of the Convergence of Magic N. _____________________________________ 96

1 Introduction Due to the increase in demand for wireless applications such as cell phones, Internet

communications, and computer peripherals, semiconductor companies are being forced to

provide entire chipset solutions to manufacturers. By providing chipsets, time to market

and design responsibilities are reduced for manufacturers. This Major Qualifying Project

(MQP) highlights Analog Devices (ADI) digital to analog converters (DAC), analog to

digital converters (ADC), modulators, demodulators, and phase locked loop frequency

generators in a wireless transceiver application.

The project is a proof of concept and will transfer data from the transmitter to the

receiver. The wireless transceiver could be used for many applications such as

transmitting voice, raw data transfer, video conferencing, etc., however these applications

will not be explored. The main goals of the project are to establish a wireless link and

optimize the system in terms of bandwidth efficiency, signal to noise ratio, and bit error

rate.

Figure 1.1 is a high-level block diagram for the entire system.

Figure 1.1 - System Block Diagram.

One of ADI’s goals is to increase awareness their products. This project will give

their products more exposure in the form of application notes and journal articles. It will

show to their customers what their products are capable of, and what to expect in terms of

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performance. Additionally, ADI will gain knowledge of new applications of their chips

that were previously unexplored.

This MQP report is organized into six chapters. The first is the introduction and goals

of the project. Chapter two contains all the necessary background research conducted on

the theory of digital modulation, demodulation, and synchronization. Chapter three

discusses the hardware implementation of the project. Chapter four presents the

mathematical modeling performed in MATLAB to generate bandwidth efficient signals,

to encode transmitted data, and to process received data. Chapter five presents the results

and performance of the wireless transceiver. Chapter six proposes future work for a

continuation of the project and conclusions for the work completed.

2 Background Research

The following background research contains all of the relevant theoretical

information that was found when researching the necessary areas for this project. The

background research is broken down into the main topics of digital modulation theory,

comparison of direct conversion versus superheterodyne demodulation, transmitter to

receiver synchronization, filtering, and group delay.

2.1 Modulation Schemes

The digital modulation scheme used for this project is quadrature phase shift keying

(QPSK). This scheme was chosen for its relative simplicity of implementation and the

ability to extend results to higher levels of phase shift keying schemes. The following

section explores the theoretical background for generation and comparison of different

digital modulation schemes.

Phase shift keying (PSK) utilizes principles used in analog phase modulation. The

baseband signal is encoded into the phase of the modulated signal, usually a sinusoid,

which is then recovered by the receiver. We chose binary phase shift keying (BPSK) as

the first modulation scheme to investigate, because it is the easiest to understand and

implement.

In BPSK, digital information is encoded into the phase of a cosine carrier: a “1” is

represented by 0° (0 rad), while “0” is represented by a 180° (π rad) phase-shift. The

amplitude of the signal stays constant throughout any PSK scheme [2].

In the case of )cos( tcω being used as a carrier, if a “1” is transmitted then the

modulated signal would be )0cos( +tcω , or if a “0” is transmitted, then )cos( πω +tc

3

would be the modulated signal. In the complex plane, modulated signals are represented

as phasors )cos( tcω = and 01∠ )cos( πω +tc = π∠1 as seen in Figure 2.1. In system

implementation, phase conversion is accomplished by multiplying the carrier by a

positive or negative scalar depending on the “1” or “0” inputs, respectively [2].

Seen in Figure 2.1, BPSK can only send one bit per symbol transmitted, each phase

shift corresponds to one symbol. A symbol is point on a constellation. Therefore, the

maximum bandwidth efficiency of BPSK is 1 bit per second per Hertz.

0 1 Inphase

Figure 2.1 - BPSK Constellation.

QPSK and other high level M-PSK schemes use similar principles of phase

modulation. QPSK splits the complex plane into four regions, instead of two like BPSK,

and therefore uses four phases of a cosine carrier to transmit the encoded signal [2].

4

To produce a cosine wave with four phases separated by π/2, we need an in-phase

carrier signal )cos( tcω and quadrature carrier signal )2

cos( πω +tc . These sinusoids

represent a set of orthogonal signals, which could be used to construct sinusoids with any

phase. Both carriers have baseband digital data signals that are represented by negative

and positive voltages as can be seen in the Figure 2.2. Similar to BPSK baseband data, a

“1” is represented by a positive voltage (0 rad phase) and a “0” is represented by a

negative voltage of the same magnitude (π rad phase). However, in this case one

baseband signal used in BPSK is replaced by in-phase and quadrature (I and Q) baseband

signals bp(t) and bq(t), each could be “0” or “1” [2].

Figure 2.2 - Inphase and Quadrature Waveforms [2].

Following Figure 2.2 from left to right, signals representing each of the carriers

multiplied by positive or negative values of the baseband signals lie on the axes of the

complex plane. This complex plane is shown below in Figure 2.3.

5

)cos( tcω)cos( tcω−

)2

cos( πω +tc

)2

cos( πω +− tc

Figure 2.3 - Modulated In-phase and Quadrature Components.

The next step is to add two adjacent signals, an I and Q component with both negative

and positive baseband data, to obtain parts of the modulated signal, as shown in the right

part of Figure 2.2.

• First Quarter, bp(t)= “1”, bq(t)= “1”

)4

cos(2)2

cos()cos( πωπωω +=++ ttt ccc

• Second Quarter, bp(t)= “0”, bq(t)= “1”

)4

3cos(2)cos()2

cos( πωωπω +=−+ ttt ccc

• Third Quarter, bp(t)= “0”, bq(t)= “0”

)4

5cos(2)2

cos()cos( πωπωω +=+−− ttt ccc

• Fourth Quarter, bp(t)= “1”, bq(t)= “0”

)4

7cos(2)cos()2

cos( πωωπω +=++− ttt ccc

6

From the calculations above, the modulated signal is a cosine of the same amplitude

and four phases π/4, 3π/4, 5π/4 and 7π/4. Note that the phase of the output cosine depends

on the baseband input signals bp(t) and bq(t). If the calculated results are represented

graphically on a complex plane, the QPSK constellation signature is created, Figure 2.4.

42 π∠

432 π

∠

452 π

∠4

72 π∠

Figure 2.4 - QPSK Constellation.

2.1.1 Modulation Scheme Comparison Criteria

In order to pick the most appropriate modulation, several criteria such as power

efficiency, bandwidth efficiency, and bit error rate are used for evaluation. Bandwidth

efficiency is described by the number of bits sent per symbol. For example, while BPSK

allows a maximum of one bit transmitted per symbol, QPSK can send up to 2 bits per

symbol, which means that the bandwidth efficiency of QPSK is twice that of BPSK. The

higher order of M-PSK modulation scheme yields higher bandwidth efficiency. However,

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once we go past QPSK, we have to make a trade off between bit error ratio versus power

efficiency.

Power efficiency is determined by the distance the constellation points are from the

origin. Theoretically, all the QPSK schemes could have the same power efficiency

because all the schemes could have points located equally far away from the origin. In the

meantime, the bit error ratio depends directly on how far the constellation points are

away from each other. The closer the constellation points are together, the more error

prone the scheme is. In Figure 2.5 each symbol has a predefined area in the complex

plane. If the symbol is received incorrectly, it will not occupy this predefined area. The

farther the symbols are away from each other (vector n), the more error resistant the

scheme is.

Figure 2.5 - Error Dependence on the Number of Symbols in M-QPSK [12].

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When using M-PSK, it is possible to put symbols farther away from each other,

however by doing that the radius of the constellation circle would have to be increased.

As a result, increased transmitted power will reduce power efficiency [12].

2.2 Direction Conversion Vs. Superheterodyne

The superheterodyne receiver is the most widely used and best understood receiver

technology. After being filtered, the received RF signal is down-converted to an

intermediate frequency (IF) using a frequency mixer. The signal is then amplified and

filtered again. Then the signal at the IF is down-converted to baseband by using another

mixer or demodulator.

One of the largest tradeoffs associated with superheterodyne is the very strict filtering

requirement due to the images created by the mixers. When filtering at lower frequency,

high quality value filters are required to have sharp attenuation dropoffs and relatively

small passbands. Surface acoustical wave (SAW) filters solve this problem; however they

introduce problems such as, the need for matching networks, attenuation in the passband,

linearity, and added system cost and size. The higher the IF used the more relaxed the

filtering requirements become. Additionally, dual IFs can be used to allow flexibility with

filter selection [8].

The main alternative to superheterodyne is direct down-conversion (DDC), which

eliminates the need for IF altogether. In a DDC receiver system, the RF signal is mixed

with a local oscillator (LO) of the same exact frequency; the result is an image centered at

DC. Since the IF is zero and the image created from down-conversion is the baseband

data itself, simple low pass filtering methods can be used instead of expensive SAW

bandpass filters. The low pass filter can be implemented on the chip, which drastically

reduces the overall system size. Additionally, there is no need for a second LO, which

further reduces cost and size [8].

Until recently, products based on DDC technology have had consistent performance

issues that prevented them from becoming widely used and accepted. DDC receivers

typically have large I/Q channel phase and magnitude mismatches and a relatively large

DC offset because of LO leakage into the RF signal. This can be seen in Figure 2.6.

Additionally, because there is no longer an IF stage, signal amplification and filtering

must be performed at either RF or baseband. This can limit design options since

narrowband high frequency filters can be very expensive [10].

Figure 2.6 - Problems with Direct Down Conversion [8].

In both superheterodyne and DDC receivers, some of the LO will show up on the RF

signal. This is not a problem when using superheterodyne, since it will be filtered out in

the IF stage, however remains a problem for DDC. The DC offset at the output can cause

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the baseband signal to saturate and hit the rails of the system. Also, the DC offset is

frequency dependent making a simple offset compensation circuit difficult to implement

[10].

Design breakthroughs at companies such as Analog Devices have eliminated the

typical poor performance figures for I/Q phase and magnitude mismatch and DC offset.

To do so, active mixers are used, which allows for the LO to be set quite low. Also, more

advanced DC offset averaging circuitry is used to minimize LO leakage even more [10].

2.3 Synchronization

When dealing with high frequencies, communication between circuits can be

extremely troublesome and synchronization needs to be taken into account. What it

means to be synchronized is to have signals with matched frequencies and phase, or to

have signals generated from the same frequency reference. If the frequency and phase are

not closely matched, problems may occur with signal demodulation or other operations.

Synchronization issues will need to be addressed in our project with communication from

transmitter to receiver [12].

2.3.1 Synchronization from Transmitter to Receiver

When receiving a modulated signal, synchronization is needed so that the data can be

properly recovered. Most systems would use symbol lock or frame lock synchronization.

Through research, we have found that high levels of synchronization, like symbol and

frame, are not needed because low phase mismatch of our system can be removed by

digital processing in MATLAB [12].

Mismatch in frequency caused by an absence of synchronization in the system results

in a rotating constellation; this will be later referred to as phase walk. By processing the

received data in MATLAB, the incoming signal will be decoded. Processing of the

received signal in MATLAB requires the receiver to be internally synchronized.

When the receiver is synchronized and the MATLAB detection has been performed,

at perfectly matched transmission and receiving frequencies, only four constellation

points will appear on the constellation, Figure 2.7(A). When the receiver is not

synchronized, four constellation points will rotate as shown in Figure 2.7(B).

Figure 2.7 - (A) Stable Constellation, (B) Rotating Constellation.

2.3.2 Synchronization within the Receiver

In the receiver, the inputs of the passive mixer and the IF demodulator have to be

synchronized. The signal is down-converted to 190MHz using a passive mixer and a

SAW filter. The passive mixer inputs are a 2.4GHz RF signal and a 2.21GHz LO, and

output is a signal that contains terms at the sum and difference of the input frequencies

(4.61GHz and 190MHz respectively). The SAW filter filters out the high frequency

component, leaving the 190MHz signal undistorted. This signal is then fed into the

AD8348 demodulator.

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The AD8348 demodulator requires a LO twice that of the signal frequency in order to

generate signals for inphase and quadrature data. To synchronize the receiver, the

frequency of the input signal should not vary more then 1MHz compared to the 190MHz

reference in the demodulator. If it varies more than 1MHz, it is not guaranteed that the

constellation points will be able to be properly decoded in MATLAB.

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Figure 2.8 - Receiver Synchronization.

To ensure synchronization of the two LO references (for 2.21GHz and 380MHz), the

ADL4212 Phase Locked Loop (PLL) frequency generator will be used. The ADL4212

generates an RF and IF signal from the same crystal oscillator. This will ensure that the

frequency of the demodulator input signal wouldn’t vary by more than 1MHz from its

desired value.

2.4 Filtering

When dealing with filtering both magnitude and phase need to be taken into account.

]To ensure the signal passing through with minimal attenuation and removal of all

unwanted noise, the magnitude response should be considered. To ensure minimal signal

delay, phase should be considered [5].

In the system, signals will be filtered in four important areas: the DAC outputs,

modulator output, receiver input, and the passive mixer output.

2.4.1 Sampling Frequency

Initially, data was sampled at 50MHz, which caused signal harmonics at multiples of

the sampling frequency to appear. Figure 2.9 shows the frequency spectrum of the DAC

output signal. A low pass filter will be used here to remove the sampling frequency. A

first order RC filter with a 1MHz cutoff frequency and 20dB/decade drop will be

sufficient in order to remove the sampling frequency and its harmonics [5].

Figure

Sampling Frequency Spike

2.9 - Sampling Frequency.

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2.5 Group Delay

In order to have a distortionless filter, its phase should be linear in the passband. If the

phase response of the filter is not linear, different frequencies of the signal will be

delayed by different amounts of time which will cause distortion. Group delay is the

change of phase with respect to frequency.

ωφ

∂∂−

=GroupDelay

If phase and frequency both change at the same rate the group delay will be linear, but if

phase changes at a different rate compared to the change in frequency, a nonlinear delay

will ensue. It is not necessary to look at the phase changes after the cutoff frequency

because this part of the signal is being filtered out. The only way to make phase constant

over the desired range is by moving poles and zeros, which requires higher order filters

[13].

Seen below in Figure 2.10, is the frequency response of a low pass filter. The phase is

almost linear, thus the group delay would be very small. When looking at Figure 2.11, the

phase changes nonlinearly which will make the group delay large. This change in delay

would then distort the output by causing a different delay on different frequency

components of the signal.

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Figure 2.10 - Low Group Delay.

Figure 2.11 - High Group Delay.

In our project, we only had to deal with group delay when we built the filters for the

DAC outputs. All of the purchased filters have linear phase in the passband of the filter. 16

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2.5.1 Summary of Design Choices

Based on the background research, design choices could be made. Because of its

simplicity, bit error ratio, and spectral efficiency, QPSK modulation will be implemented

in the design. A superheterodyne architecture will be used for the receiver because they

are the most widely used and because direct conversion systems are still in the adoption

phase. Additionally, a superheterodyne design gives more opportunities for filtering and

amplification. Synchronization will only be performed on the receiver between the RF

and IF LO’s. The software created in MATLAB eliminates the need for complicated

analog hardware synchronization solutions.

3 Hardware Implementation

The hardware implementation is one of the main sections of the project. The three

major parts of the hardware include the transmitter, the wireless link, and the receiver.

The following sections describe these parts in detail.

3.1 Transmitter

The transmitter has six main elements: data generation, signal generation, digital to

analog conversion, biasing, filtering, and modulation. The output of the transmitter is a

2.4 GHz modulated signal containing all of the baseband data. Figure 3.1 outlines all the

parts of the transmitter design and the signal flow.

Figure 3.1 - Transmitter Block Diagram.

The first step is to generate a bit stream with MATLAB to input into the HP 16500C

pattern generator as a text file. The generated bit stream contains interleaved I and Q data

for sigmoidal pulse shaping. Using the HP pattern generator, digital signals containing

the information for pulse shaping are sent to the DAC. The DAC clock signal is being 18

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generated by the pattern generator to ensure proper setup and hold time as well as data

synchronization. Interleaved data is required since there are only 14 pins for the dual

DAC input interface on the AD9862. The MATLAB code for this operation can be seen

in Appendix A, under the name of exportpattrighalf.m.

The AD9862 dual DACs generate analog waveforms for both the I and Q channels

for QPSK modulation. There are two outputs per channel: the signal and its complement,

which make up a 20mA differential current signal. A resistor network is needed to bias

the signal to appropriate voltage levels for the AD8349 modulator. A low pass filter is

desired to remove the sampling frequency. The AD8349 direct conversion modulator up-

converts the baseband data directly to the LO frequency of 2.4GHz that is generated by a

HP 8648D signal generator.

The transmission range of the system will be relatively limited without the use of a

power amplifier, however will be sufficient for lab measurement.

3.1.1 DAC Inputs and Data Generation

The AD9862 Mixed Signal Front End Processor has two 14-bit DACs on chip that are

used in the transmitter to implement baseband QPSK pulse shaped data signals. To

reduce the amount of physical space required for the transmit interface, the AD9862 uses

a 14-pin input and requires interleaved data to be used with both DACs. In addition to

data bits, a transmit sync bit is included to distinguish the interleaved data. By default,

this bit must be high when sending I data and low for Q data, however these can be

reversed using the serial port interface. By default, the rising clock edge must appear in

the middle of valid data bits, allowing 3ns for setup time and 3ns for hold time. Other

requirements are described in the AD9862 datasheet in Appendix C.

MATLAB was used to generate clock, transmit sync and data bits for the signal

generator to be sent into the DAC. In order to use both DACs for generation of pulse-

shaped data, I and Q digital data had to be interleaved in MATLAB. Digital pulse

shaping techniques were used to provide adequate signals for all 14 bits.

The system timing diagram is in Figure 3.2 below.

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Figure 3.2 - Timing Diagram.

3.1.2 DAC Output Resistor Network

Before sending the DAC output signals to the AD8349 modulator, they must be

biased correctly. The biasing network raises the signal to the optimal level for the

modulator input as specified in its data sheet.

Both DAC outputs of AD9862 have complimentary programmable full-scale current

outputs. The full-scale output current (Ifsout) can be programmed to source 2mA through

20mA using the external resistor Rset. The relationship between the output current and

Rset is:

⎥⎦⎤

⎢⎣⎡×=

RsetVIfsout 23.167

By setting Rset equal to 4kΩ, Ifsout equals its optimal setting of 20mA. The output is

differential, meaning that when one output is 20mA, the other is 0mA and vice versa.

Common mode output is defined when both output are equal and in this case, 10mA

each.

To generate biased voltage inputs for the AD8349 modulator from the current outputs

of the AD9862, a resistor network must be implemented. The AD8349 wants to see a DC

bias level of 0.4V with a full-scale swing of 1.2V or 600mV per channel.

Figure 3.3 - AD9862 Output Resistor and Filter Network.

To set up the DC bias level, the common mode DAC output must be examined.

Common mode operation is when the DAC output current is balanced at 10mA for each

channel. To create the 0.4V DC bias that the AD8349 requires, 40Ω resistors are used.

In Figure 3.3, each DAC output sees an impedance of 35Ω (40Ω || (40Ω + 240Ω)).

When IoutA is in full-scale operation it is sourcing 20mA of current, thus creating a 21

700mV peak signal (600mVp-p centered at 0.4V bias level) at IBBP. A similar situation

occurs at IBBN when IoutB is sourcing 20mA of current. This creates a full-scale swing

of 1.2V in the I and Q channels.

3.1.3 DAC Output Filters

When designing the DAC filters, the sampling frequency at 50MHz and unwanted

noise had to be removed from the signal before going into the modulator. A first order

filter was chosen because of the simplicity of not having to deal with multiple poles and

zeros as well as loosened requirements caused by pulse shaping and use of DAC

interpolation filters. Seen below in Figure 3.4, is the filter response superimposed with

the signal spectrum.

Figure 3.4 - Filter Response with Signal Spectrum.

The sampling frequency at 50MHz will be attenuated by -30dB by the filter. This is

enough attenuation to remove the sampling frequency so that it does not affect the

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transmitted data. Group delay will not be an issue because the phase is mostly linear

during the passband of the magnitude, thus making group delay very small.

3.1.4 AD8349 Direct Conversion Modulator

The AD8349 is a direct conversion modulator capable of producing an output

frequency of 700 MHz to 2.7 GHz. The baseband data can be in the frequency range of

DC to 200 MHz. The benefit of using direct conversion is the elimination of dealing with

intermediate frequencies. It is capable of modulating GSM, CDMA, W-CDMA, QPSK,

QAM, and other signals.

The AD8349 has five main sections to its design: LO interface, mixer, voltage to

current converter, differential to single ended converter, and bias. All of these sections

are shown in Figure 3.5.

The LO interface splits the input LO into I and Q signals to drive two mixers. The

four baseband data inputs are each fed into voltage to current converters, which then

input into the mixers as well. There are two mixers on chip, one for the I data and one for

the Q data. Each mixer utilizes a Gilbert-cell mixer design with four cross-connected

transistors each. The outputs of the mixers are combined using a differential to single

ended conversion to produce the output, which is designed to drive a 50Ω load. More

information can be obtained from the datasheet in Appendix C.

Figure 3.5 - AD8349 Detailed Block Diagram (Analog Devices).

3.2 Wireless Link

In order to establish wireless link, two linear wire antennas were used. This type of

antenna was chosen because of its simple implementation. By using a linear wire

antenna, we can ensure relatively uniform distribution of electric field in every direction,

except for the direction along the z-axis. Conveniently, linear wire antennas can be used

for both transmitting and receiving. This property enabled us to design one antenna and

duplicate it.

The initial design of the transceiver required bandpass filters at the input and output

of the antennas. Due to logistical problems and price constraints, we were not able to

obtain filters for the signal at 2.4GHz. Instead, we decided to use a matching network

with high nodal quality factor Qn. This design solution would enable us to match the

24

antennas to the rest of the circuit and at the same time filter noise at the frequencies

outside of 2.4Ghz.

A quarter wavelength monopole antenna on a conducting ground plane is used in the

project. This is a version of a half wavelength dipole, well described in antenna design

literature. A picture of the antenna can be seen in Figure 3.6.

Figure 3.6 - Quarter Wavelength Monopole Antenna.

After construction, both antennas were tested and tuned using a network analyzer.

Theoretically, the return loss of a quarter wavelength antenna should be the smallest at

the resonance frequency. While looking at the return loss on the network analyzer, the

length of the monopoles was adjusted until the magnitude of the return loss reached its

minimum for 2.4GHz, Figure 3.7.

25

Figure 3.7 - Return Loss of a Quarter Wavelength Monopole Antenna

3.2.1 Matching

To ensure optimum RF power transfer between the antennas and the rest of the

circuitry, two matching networks had to be constructed. The circuits that had to be

matched to the antennas were the AD8349 modulator on the transmitter side and AD8354

amplifier on the receiver side. Both of these circuits have 50Ω input and output

impedance at the operating frequency of 2.4GHz. To properly design a matching network

the input impedance of the antennas at the frequency of 2.4 GHz had to be determined.

Literature sources on antenna design provide multiple formulas for finding the input

impedance of dipole and monopole antennas. The actual impedance of antennas however

26

27

varies highly with the surroundings, positioning, materials and physical construction. In

order to account for all of these factors, a network analyzer was used to directly measure

the impedance of the antennas in similar surroundings.

Even though the antennas are physically almost identical, one of them was identified

as the transmitter antenna and another one as the receiver antenna. Measurements of the

S11 parameter of the transmitter antenna yielded the input impedance to be 36.15 +

j37.45Ω. This measurement also includes the transmission line effect of the antenna

connectors. The input impedance of the receiver antenna under analogous conditions was

determined to be 35.74 + j38.06Ω. The location of the antenna impedance on the Smith

Chart can be seen in Figure 3.8.

Figure 3.8 - Antenna Impedance on the Smith Chart.

Matching networks can be designed and built using discrete components, open and

short circuit stubs with transmission lines, and the combination of both. Initially, L-type

discrete component matching networks made of fixed inductors and variable capacitors

were used. Calculations were done graphically using a Smith Chart and simulations were

performed in ADS. Pre-made attenuator boards were used to mount the matching

network, however due to the high operating frequency and transmission line effect of the

board, the matching network did not work. Even though transmission line effect of the

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29

board could be predicted, there was no acceptable technique for modeling connector

effects.

Following the design guidelines for matching networks operating at mid-gigahertz

frequencies, the matching network was built out of two distributed elements and one

lumped element in parallel. Also, new boards were built for matching networks using

FR4 material with a dielectric constant of 4.7. The trace was cut to be approximately

114mils wide, which would produce characteristic impedance of 50Ω. Due to the lack of

tools and information for modeling connector effects, the method of trial and error was

implemented. A variable capacitor was moved along the trace, while the response of the

system was constantly observed on the network analyzer. This technique also did not

produce desired results.

Using an LCR meter, it was determined that the connectors on the FR4 board had a

small capacitive effect. Based on this observation, boards with half wavelength traces

were designed. The capacitance of the input connector reduced the inductance of the

antenna, the half wavelength transmission line caused full rotation of the Smith Chart,

and the second connector brought the impedance even closer to 50Ω. The final input

impedance of the antenna with the matching network can be seen in Figure 3.9. By

comparing Figure 3.8 and Figure 3.9, the standing wave ratio at the antenna interface is

significantly reduced.

Figure 3.9 - Input impedance of the Antenna with a Matching Network.

Although not perfect, the half wavelength transformer reduced the return loss of the

antennas from -7dB to -14 dB. This can be observed by comparing return loss

measurements shown in Figure 3.7 and Figure 3.10.

30

Figure 3.10 - Return Loss at the Matching Network Interface Looking into the Antenna

The conclusion was drawn that GHz range matching networks should be designed

with distributed rather than lumped elements. Also, the physical board should be built

professionally in order to ensure that proper distances between circuit elements are

observed. Theoretically, this could be performed manually, but realistically it is very

difficult to measure distances as small as 1mil and cut traces with a knife.

3.3 Receiver

The receiver is responsible for downconverting the signal back to baseband

frequencies and demodulating QPSK back into I and Q components. By Analog Devices’

request, a superheterodyne architecture was chosen over direct conversion designs. This 31

decision was made because because supheterodyne designs are still the most widely used

and direct conversion systems are in the adoption phase. Figure 3.11 shows the functional

block diagram of the receiver system.

32

Figure 3.11 - Receiver Block Diagram.

3.3.1 ADF4212 Dual IF/RF PLL Frequency Synthesizer

The purpose of the ADF4212 is to generate LOs for the passive mixer and the

AD8348 quadrature demodulator from the same reference oscillator. This chip was

chosen because of its ability to generate two synchronized signals. Without this

synchronization, there would be a large amount of phase walk present on the outputs of

the AD8348 demodulator.

The ADF4212 cannot generate LO signals alone and must be combined with two

voltage controlled oscillators (VCO) and a loop filter as seen in Figure 3.12. The two

VCOs provided by Varil can generate frequencies over a certain bandwidth. To specify

the exact desired frequency the ADF4212 must be controlled by software via the serial

port. The power level of both IF and RF generated signals is –7 dBm, which is ideal to

drive both the passive mixer and the AD8348 demodulator. The VCO190-370T is

configured to generate exactly 380MHz to input into the demodulator and the VCO190-

2250T is configured to generate 2210MHz to input into the passive mixer. The 370T can

produce 340-400MHz and the 2250T can produce 2200-2300MHz. Please refer to the

Future Work section for software instructions.

For a more detailed explanation of the internal chip functionality of the ADF4212

review the datasheet in Appendix C.

Figure 3.12 - ADF4212 IF/RF Configuration (Analog Devices).

3.3.2 Passive Mixer

The purpose of the passive mixer in the receiver is to down-convert the 2.4GHz RF

signal down to 190MHz IF. The mixer is ‘passive’ because it is designed from all 33

34

passive components and does not require biasing. There are two inputs, which are for the

RF and LO signals, and one output for the IF signal. Because an IF of 190MHz is being

used, the LO frequency must be 2210MHz. The output of the passive mixer contains the

summation and difference of the RF and LO frequencies. Since we are only interested in

the difference between them, a filter is needed at 190MHz.

The recommended LO power levels specified by Mini-Circuits is 7 dBm, however the

maximum power output of the ADF4212 frequency generator is only –7 dBm. To fix this,

an amplification stage for the LO is necessary. The AD8354 can provide up to 20 dB of

gain, however cannot amplify signals above +4 dBm. Adding this gain block amplifies

the LO to about 4 dBm, which is sufficient to drive the mixer. The passive mixer that is

used in the receiver is the Mini-Circuits ZAM-42.

3.3.3 190MHz SAW Filter

Conventional filters are usually realized in the frequency domain, where certain

frequencies allow signals to pass and other attenuate. These filters consist of lumped

elements such as inductors and capacitors to achieve a specific frequency response.

Varying the values of these lumped elements will adjust the filter characteristics.

SAW filters do not operate on the same fundamentals as typical lumped element

filters. Filtering is accomplished by physical designs in the time domain. The incoming

signal is passed through many delay paths that are summed and weighted at each delay

point. Each point can be added constructively when in the passband, or destructively

when in the stopband depending on the signal content. This is illustrated in Figure 3.13

below.

Figure 3.13 - Delay and Summation Filter [7].

The weighting coefficients an are shown in the time domain in Figure 3.14. It is

desirable for bandpass applications to shape the coefficients to a sinc(t) function in the

time domain to create a rectangular response in the frequency domain. By utilizing this

Fourier transform relationship, SAW filter design has been made simpler.

Figure 3.14 - Weighting Coefficients [7].

35

Figure 3.15 - Filter Frequency Response [7].

Figure 3.15 shows the rectangular frequency response when the weighting functions

are arranged in a sinc(t) layout. The number of taps and the total time delay of the filter

can change the filter characteristics. A physical filter layout can be seen in Figure 3.16

below. The summation function is performed by the large sidebars and the weighted

samples are performed by the small metal bars in the center [7].

36

Figure 3.16 - Physical Filter Layout [7].

3.3.4 AD8348 IF Quadrature Demodulator

The AD8348 quadrature demodulator is responsible for converting the IF signal down

to baseband differential I and Q components. The chip not only provides accurate

demodulation performance, but also has a built in 44 dB variable gain amplifier (VGA).

The inputs to the demodulator include the IF input signal and the LO that is being

generated by the ADF4212 at 380MHz. The LO is required to be double the frequency of

the IF input signal to provide 190MHz for both I and Q mixers. It is possible to bypass

the VGA by using the MXIP and MXIN inputs, however for our design, the amplification

is used. The input impedance of the chip is 200Ω, however the matching network on the

evaluation board allows for a 50Ω input. Setting the VGIN pin to 0.2V with the onboard

potentiometer sets the gain of the VGA to ensure proper signal levels at the input of the

demodulator.

The demodulator’s differential baseband outputs are connected to a differential

amplifier in a buffer configuration located on the ADC evaluation board. Because of this,

all DC bias applied to the VCMO pin of the demodulator will not have an effect on the

37

38

signal. Additionally, the buffer provides the high impedance (>2kΩ) that is required by

the demodulator for optimal performance.

Please refer to the AD8348 datasheet for more detailed information on the

functionality and pin descriptions in Appendix C.

3.3.5 AD9862 12-bit Dual ADC

The role of the dual analog to digital converter portion of the AD9862 is to convert

the analog waveforms provided by the demodulator to digital 12-bit words. The input to

the ADC is AC coupled because of the differential amplifier on the evaluation board. The

optimal 2V DC bias point is set by the internal circuitry of the chip. The HP 16500C

logic analyzer is used to read in the digital bits from the ADC and store them to file,

which can then be imported into MATLAB. The code written in MATLAB is able to

reconstruct the original signal as described later in the following mathematical modeling

section.

39

4 Mathematical Modeling

Before physically implementing project design ideas, MATLAB was used to

mathematically model and evaluate their performance. We modeled various pulse

shaping techniques in order to choose one for implementation. Additionally, MATLAB

was used to encode transmitted data and perform signal processing on the received data

to remove noise and phase walk.

4.1 Pulse Shaping of Baseband Data

The first step in generating a QPSK signal is to generate its baseband I and Q

components. In Figure 4.1, baseband QPSK signals look like digital bit stream signals. In

theory, they could be generated directly with the signal generator module of the logic

analyzer. However, deeper investigation of the problem uncovered the fact that the logic

analyzer could not generate voltage signals that would be compatible with the modulator

input. In order to solve this problem, it was decided to use a digital to analog converter

(DAC) to generate baseband data.

Figure 4.1 - Baseband Data Constructed out of Square Steps.

The DAC allowed the flexibility of producing the desired signal with a specific

voltage offset and swing range. According to the specifications of the AD8349

modulator, a 1.2Vp-p signal centered on a 0.4V DC operating point was needed. The

most logical first step to obtain a baseband bit stream signal was to construct it out of

square steps. An example of I and Q signals generated in this form is shown in Figure

4.1. Initially, it was decided to allocate 2us for every bit in the time domain to meet the

1Msymbol/sec design requirement.

A square step baseband signal is the easiest to construct, however the signal exhibits

unsatisfactory behavior in the frequency domain. The Fast Fourier Transform (FFT)

analysis of the signal shows that the signal occupies too much bandwidth. Sharp

transitions in the time domain require more bandwidth [5].

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41

Smoothing out edges of the baseband signal could help reduce the spread of the

spectrum. Having a compact signal in the frequency domain would loosen requirements

on the filters. Instead of building precision multiple order filters, a simple resistor

capacitor (RC) pair could be used.

4.1.1 Shaped Waveform Construction

Pulse shaping is the technique widely used for minimizing frequency spread of the

signal. Usually pulse shaping is implemented by running the baseband signal comprised

out of square steps through a low-pass filter with desired frequency characteristics.

Using MATLAB as a tool for signal processing, we have an option to directly

generate shaped waveforms. From a theoretical standpoint, both filtering and direct

generation yield equivalent results. For direct generation, single pulse in the time domain

is convolved with a positive and negative impulse train representing zeros and ones in the

bitstream. The result of this operation is a shaped waveform [5].

4.1.2 Shape Properties

Having identified the scheme of waveform construction, a pulse shaping technique

with the most compact frequency spectrum needed to be chosen. In the course of the

project, several functions were analyzed that are traditionally used for pulse shaping, such

as Hann, Chebyshev, and Gaussian Bell. In addition to the widely used pulse shapes, the

performance of functions in the Fuzzy Logic Toolbox of MATLAB was investigated.

The Fuzzy Logic Toolbox allowed us to easily generate linear, Gaussian, Pi, and

Sigmoidal pulse shaping techniques. All of these functions are defined in the MATLAB

Fuzzy Logic Toolbox documentation.

42

Choosing adequate pulse shaping functions required setting criteria for selection. In

our case, the biggest indicator was the frequency spread, so we looked at how fast

functions accumulated 95% of the bandwidth with respect to each other. We also paid

attention at the shape of the signal’s FFT, specifically at the level of the high frequency

content.

The time domain signals generated through the Fuzzy Logic Toolbox can be seen in

Figure 4.2. To fully compare the frequency performance of different shaping schemes,

we have to look at the waveform FFTs in Figure 4.3.

Figure 4.2 - Fuzzy Logic Waveforms.

When comparing the frequency content of different pulse shaping methods, the signal

with no pulse shaping has the greatest level of high frequency content, while Sigmoidal

has the lowest.

43

Figure 4.3 - Frequency Content of the Fuzzy Logic Waveforms.

Figure 4.4 shows how fast the bandwidth of each function is accumulated. The figure

was obtained by running empirical cumulative distribution function on the FFTs of the

signals. The benefit of pulse shaping can be instantly seen in Figure 4.4 since the signals

with pulse shaping accumulate bandwidth faster than unshaped signals. By analyzing

frequency content and bandwidth accumulation graphs of the Fuzzy Logic waveforms, it

can be said that Sigmoidal pulse shaping has the least amount of high frequency and

accumulates bandwidth the fastest.

44

Figure 4.4 - Bandwidth Accumulation by Fuzzy Logic Functions.

4.1.3 Comparison of Sigmoidal Pulse Shaping and Shaping Windows

Used in Industry

To properly estimate the performance of Sigmoidal pulse shaping, it was decided to

compare it to several pulse shaping windows used in the industry. Using the Window

Design and Analysis Tool in MATLAB three windows were visually selected that best

suited the established criteria. The criteria for selection were low levels of high frequency

content and the shape in time domain that would not cause intersymbol interference.

From the visual analysis, Gaussian, Hann, and a version of the Chebyshev window with

60dB of sidelobe attenuation were chosen. The waveforms were constructed in

MATLAB by time shifting and adding positive and negative shapes in order to represent

ones and zeros, respectively, in the bit pattern [5]. 45

A time domain representation of the shaped waveforms can be seen in Figure 4.5.

Unlike Sigmoidal, signals shaped using Chebyshev and Hann windows do not form a

straight line when several ones or zeros are located next to each other.

Figure 4.5 - Industry Standards in Comparison with Sigmoidal.

In order to compare Chebyshev, Hann and Sigmoidal pulse shaping techniques, FFTs

were plotted in Figure 4.6. From visual analysis, Chebyshev has more high frequency

content than Sigmoidal and Hann. This is not necessarily a prediction of actual

performance, but rather a limitation of computation. In order to make a waveform out of

Chebyshev windows, the endpoints should be truncated because of the discontinuity of

the function at the first and last samples. Combining the truncated Chebyshev windows

46

resulted in sharp transitions from one window to another thus creating relatively large

high frequency content.

Figure 4.6 - Frequency Content of Chebyshev, Hann and Sigmoidal Waveforms.

The graphs in Figure 4.7 indicate that Hann, Chebyshev and Sigmoidal shaping

schemes accumulate bandwidth almost at the same rate. Both Hann and Chebyshev have

very similar characteristics and are slightly more compact in frequency domain than the

Sigmoidal window.

47

Figure 4.7 - Comparison of Bandwidth Accumulation by Chebyshev, Hann and Sigmoidal Windows.

Even though our comparison showed that the pulse-shaping functions used in the

industry performed slightly better than the ones from the Fuzzy Logic Toolbox,

Sigmoidal pulse-shaping will still be used for the rest of the project.

4.2 Data Encoding

In the initial stages of the project, the data was sent directly through the wireless link

without encoding. Initially, ones and zeros of the original data were represented directly

by high and low levels of the baseband signals as described in Section 2.1. This method

will be later referred to as absolute QPSK. By having the information encoded in the

absolute values of the phase, an absolute reference of the initial phase is needed on the

receiving end to reconstruct the signal. Given the fact that our system does not have any

48

analog synchronization block, the presence of reference signal at the receiving end cannot

be ensured. Regardless of this fact, we developed several detection schemes that could be

employed with absolute QPSK. The description of these schemes is given in Appendix B.

In order to overcome the limitation of absolute QPSK, we approached the problem

differently. Instead of encoding the bits in the absolute phases of the modulated signal,

the bits were encoded in the differences in phase of the modulated signal. Such encoding

scheme will be referred to as differential QPSK. As can be seen from Figure 4.8, a

clockwise shift around the constellation represents I=0 and Q=1, counterclockwise

represents I=1, Q=0, jumping across the constellation represents I=1, Q=1 and staying at

the same point represents I=0. Q=0.

Figure 4.8 - Differential QPSK Constellation.

When the bits are encoded in transitions, the initial phase and the accumulated walk

of the received signal does not impact detection. Such a benefit, however, comes at a

certain price: the data has to be encoded. Because the exact location of the symbols does

not matter, I and Q have to be looked at simultaneously while encoding.

49

To generate the signal for transmission the circular array scheme is used. The array

has four cells. The first and second cells are filled with ones, while the rest are filled with

zeros as seen in Figure 4.9. The I component of the transmission signal is the value in the

third position, the Q component of the transmission signal is the value in the fourth

position.

Figure 4.9 - Circular Array.

When (0,0) is to be transmitted, the array stays at the current position, therefore the

constellation symbol stays at the same point. When (1,0) is to be transmitted, the array is

shifted one position to the right, at the same time the constellation symbol moves

counterclockwise to the next position on the constellation plot. When (0,1) is to be

transmitted, the array is shifted one position to the left, at the same time the constellation

symbol moves clockwise to the next position on the constellation plot. When (1,1) is to

be transmitted the array is shifted two positions in either direction. On the absolute QPSK

constellation plot this shift represents transition across the constellation. This information

is summarized in Table 4.1.

Table 4.1 - Encoding Summary.

Original I and Q Data Array Action Constellation Action

(0,0) Staying the same Staying the same

(1,0) Right Hand Shift Counterclockwise Shift

(0,1) Left Hand Shift Clockwise Shift

(1,1) 2 Position Shift Transition Across

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Because the array is circular, when the symbol is pushed out of the array after

shifting, it immediately enters the vacant location from the other side. As long as the

relative position of bits in the array is preserved, any initial position could be used to

generate the transmission data.

Given the initial position of the transmission data is (1,0), Figure 4.10 shows the

positions of the array when the original data is (0,0), (1,0), (0,1) and (1,1). By looking at

the constellation plots in Figure 4.10, we can see that the original data is represented by

no transition, counterclockwise transition, clockwise transition and transition across,

respectively. For convenience of understanding original data on the constellation plots is

shown in red, while the transmitted data is shown in black.

Figure 4.10 - Conceptual View of Circular Array Data Encoding.

MATLAB implementation of the down-sampling algorithm can be found in

Appendix A - Iqinit.m.

4.3 Data Reconstruction

Just like all communication systems, our project is prone to error due to noise and

phase walk. Phase walk is usually compensated for by having an analog synchronization

51

block, such as a PLL or a Costa’s loop that matches up transmission and receiving

frequencies, thus eliminating phase walk in the received signal. Our system does not have

an analog synchronization block by design, therefore a digital signal-processing scheme

needs to be implemented in order to recover the bit stream from the received signal.

The impact of phase walk and noise on the system can be seen from comparing

Figure 4.11 and Figure 4.12.

Figure 4.11 - Transmitted I and Q Sigmoidal Signals.

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Figure 4.12 - Received Signal Corrupted by Noise and Walk.

Figure 4.11 shows the transmitted I and Q component signals, where we can clearly

see the bits described in Table 4.2.

Table 4.2 - Bit Pattern.

Transmitted Bits

I Component 1 0 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 0 0

Q Component 0 1 0 1 1 0 1 1 1 0 1 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1

The signal in Figure 4.12 is the received signal that is corrupted by noise and phase

walk to the point that the exact location and value of the bits cannot be recognized. The

location of ‘x’ signs in Figure 4.12 shows the location of the transmitted bits. By

53

comparing ‘x’ marks and the waveform trace, it can be seen how the received signal

becomes less and less recognizable as it accumulates more phase walk with time.

4.3.1 Matched Filter

When receiving data, noise may affect detection accuracy. Using a matched filter can

solve this problem. The impulse response of the matched filter is an exact copy of the

shape of the transmitted shaped data. The filter is used to compute the time-

autocorrelation of the signal. This is seen below in Figure 4.13. Doing this will then

remove most of the noise from received data [3], [4], [11].

Figure 4.13 - Matched Filter Processing.

4.3.2 Downsampling Process

As mentioned earlier, the shaped bitstream is obtained by generating a sampled

waveform using digital to analog converters. The shaping algorithm defines the number

of samples per symbol; usually 100 samples per transmitted symbol are used. Having 100

samples per symbol ensures relatively smooth transitions from one sample to another. At

the same time, the transmitted bit information is encoded only in one of these 100

samples. This sample is located in the middle of the symbol (usually sample number 50).

When working with the received signal, it makes more sense to down-sample the

waveform and just work with the points that contain actual bit information.

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55

The implemented down-sampling algorithm operates on the phase of the received

signal. Besides the phase waveform, the algorithm needs to know the number of samples

per received symbol. This can be determined by knowing the sampling rate of the analog

to digital converter (ADC) on the receiver side and the symbol transmission speed of the

system.

The phase of the received signal is constantly changing. Large jumps in phase usually

occur when the constellation point switches to its next position. The down-sampling

algorithm finds large abrupt change in phase and fills in the rest of the list according to

the number of samples per symbol. Now that we know the tentative locations of all the

bit transitions we locate the bits themselves by sampling in between the transitions.

MATLAB implementation of the down-sampling algorithm can be found in

Appendix A - Received_detection.m.

4.3.3 Detection

The detection algorithm by itself is relatively simple. By having downsampled phase

data the location of points on the constellation plot can be determined. Changes in phase

are easily found by subtracting the phase of a point in the array from the phase of the next

point. These changes are then used to directly reconstruct original I and Q data. The

guide table for reconstruction is shown below.

Table 4.3 - Symbol Reconstruction from Phase Difference.

Intended Phase Difference Phase Difference Window Original I and Q Data

0˚ -45˚≤θ<45˚ (0,0)

+90˚ 45˚≤θ<135˚ (1,0)

-90˚ -135˚≤θ<-45˚ (0,1)

±180˚ 135˚≤θ<-135˚ (1,1)

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5 Results

This section contains all the real world results from the transmitter and receiver over

the wireless link. Tests that were conducted to determine phase walk over the wireless

link, signal detection limit due to high phase walk, and signal to noise ratio. By varying

the carrier frequency, a frequency mismatch was artificially created to simulate an

unsynchronized system. The purpose of the tests is to find how much phase walk can be

tolerated in the physical hardware and the data reconstruction software written in

MATLAB.

5.1 Measured DAC Output Results

In addition to running simulations, we measured the spectrum of the AD9862 output

and compared no pulse shaping versus sigmoidal pulse shaping. The results can be seen

in Figure 5.1. This goes to further prove our conclusions drawn from the pulse shaping

simulations. The measured results confirm that pulse shaping drastically reduces the

bandwidth of our signal to about 1 MHz.

Figure 5.1 - DAC Output Frequency Response.

5.2 Phase Walk Characterization

Tests were run to determine the real system phase walk when the system was

unsynchronized. The four different frequency settings tested were 0Hz, 3kHz, 6kHz, and

12kHz mismatch. Phase walk should be linear over time and proportional to the

frequency mismatch.

Calculating phase walk can be done by measuring the phase around the constellation

when I and Q and assigned ( )θcos and ( )θsin respectively. When doing this theta is the

walk of both I and Q. Seen below are the calculations of walk at a 3kHz mismatch.

( )sec

08.118010130002* 6

µππωθ DegreestWalk =⋅⋅⋅⋅⋅=== −

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Table 5.1 - Calculated and Measured Phase Walk

Frequency Mismatch

Calculated Phase Walk (Degree/us)

Measured Phase Walk (Degree/us)

Zero 0 ≈ 0 3kHz 1.08 1.16 6kHz 2.16 2.19 12kHz 4.32 4.37

To measure the phase walk over time, the transmitted signal contains constant I and Q

values to ensure that phase is only changed by the frequency mismatch. Figure 5.2 shows

the phase walk for the examined frequency mismatches. The reason why the phase is at a

constant 45 degrees when the frequency is matched is because I and Q are both set to one.

As predicted, the observed phase walk is linearly proportional to the amount of frequency

mismatch added to the carrier frequency. The recorded phase walk values are in Table

5.1.

Figure 5.2 - Measured Phase Walk.

5.3 Frequency Mismatch Limitations

In order to test the detection capabilities of the system, random I and Q data was

transmitted and received over the wireless link. These tests were performed at a

frequency mismatch of 300Hz, 500Hz, 1000Hz, 1500Hz, 2000Hz, 2500Hz, 3000Hz, and

at matched.

59

Figure 5.3 below is the original I and Q data. The bit stream is then encoded into

transitions and pulse shaped using the algorithms explained the mathematical modeling

section. The transmitted waveform can be seen in Figure 5.4.

Figure 5.3 - Created I and Q Data.

Figure 5.4 - Transmitted I and Q Data.

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A frequency match indicates that the carrier frequency is set to 2.4GHz. This carrier

frequency will ensure that the IF signal going into the AD8348 demodulator is exactly

190MHz. If the carrier frequency has a slight mismatch, the IF will not be exactly at

190MHz and will result in a noticeable phase walk on the baseband data. Because the

transmitted data is encoded into transitions, a reasonable amount of phase walk is

tolerable. The goal of these tests is to find exactly how much phase walk can be present

while still reconstructing the correct symbols. Figure 5.5 shows the received constellation

with zero, 300Hz, 2500Hz, and 3000Hz of frequency mismatch.

Figure 5.5 - Received Constellations at Different Frequency Mismatches.

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Figure 5.6 - Received I and Q Data.

With 3000Hz of mismatch, there is too much phase walk per symbol to be detected.

At all mismatch frequencies below 3000Hz, the recovered signal appears to be a repeated

identical version to the original data before it was encoded into transitions. The received

data is shown in Figure 5.6. Running this test proves complete functionality of both the

hardware and software. The reconstruction limitation was expected and simply identifies

when the phase walk per symbol forces the received bit into the incorrect quadrant. One

of the major reasons leading to reconstruction limitation is the down-sampling algorithm.

The algorithm should be improved in order to track all the large phase changes in the

received signal.

5.4 Wireless Link Limitations

Since the transmitter does not incorporate a power amplifier, the range of the wireless

link will be relatively poor. The purpose of the project was never to create a long-range

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transmission link, but for characterization purposes, the maximum transmission length

was determined.

Figure 5.7 - Constellation of Received Data at 58cm Transmission.

Figure 5.7 shows the received constellation at a transmission length of 58cm and

under. If the link is increased to anything more than 58cm, the power level of the

received signal is attenuated too much and cannot be received correctly. All tests were

run using the maximum RF transmit power of 5dBm specified in the AD8349 modulator

datasheet. Figure 5.8 below shows the incorrectly received constellation.

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Figure 5.8 - Constellation of Received Data at More 58cm Transmission.

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6 Conclusions and Future Work

The result of this project is a fully functional QPSK data link that operates at 2.4GHz

and can transmit up to a rate of 1Msymbol/sec. The system is robust and can tolerate up

to 3000Hz of carrier frequency mismatch in the case of an unsynchronized system. The

original project description included plans to measure bit error ratio (BER) tests over

different modulation schemes, power levels, and symbol rates. Due to time and budget

limitations, designing and building a real time BER test system was an unrealistic goal.

While the system itself is fully functional, the current MATLAB software analysis

technique limits the ability to characterize system performance. It is recommended that

future work on this project include a real time DSP/FPGA characterization solution to

replace the HP16500C logic analyzer and MATLAB code. A real time system would

allow for extremely accurate BER tests with relative ease.

Other suggestions for future work include implementation of a direct down-

conversion receiver system. In doing so, the system size would be reduced and testing

could be conducted to compare superheterodyne and direct conversion systems in the real

world. If the superheterodyne solution is left in place, replacing the passive mixer with an

active mixer (possibly from Analog Devices) would reduce LO power level requirements.

Also, it would be possible to include an ADI power amplifier on the output of the

transmitter to increase the range of the wireless link.

The range of the wireless link could be significantly improved by redesigning the

matching network. We recommend the new matching network to be designed using

distributed elements and built professionally.

6.1 Recommendations

Throughout the course of the project we have gained certain knowledge about the

system’s operation by carefully reviewing chip datasheets as well as trial and error. In

order to spare next group the agony and prepare them for a quick start of the project we

are including several tips on operating the system in this section.

6.1.1 PLL Frequency Generation

ADF4212 PLL generator is controlled by the serial interface through software

supplied by Analog Devices, Inc. Seen below in Figure 6.1 is the GUI of the control

software for the PLL chip. The values below ensure optimum performance of the system

in terms of frequency mismatch as well as I and Q levels.

Figure 6.1 - Software Display for PLL Frequency Generator.

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The control values for the optimum frequency generation that were determined in the

course of the project can be seen in Table 6.1. 2.4GHz transmission frequency is

assumed.

Table 6.1 - PLL Frequency Generator Input Settings.

RF IF

VCO Output Frequency 2207.79 MHz 380MHz

PFD Frequency 30 kHz 50kHz

REF In Frequency 10MHz 10MHz

Prescaler 32/33 32/33

Charge Pump Current Setting 1.875mA 3.125mA

6.1.2 DAC/ADC Control

AD9862 DAC/ADC chip is controlled by the serial port interface through the

LabView software supplied by Analog Devices, Inc. The software sets the gain of an

internal amplifier, determines DAC interpolation and performs other functions, described

in the datasheet that can be found in Appendix C.

A GUI display with the optimal settings that were used for the project is shown in

Figure 6.2. Most of the settings are clearly explained in the product datasheet, however

there are several settings that we discovered by trial and error.

The DAC can use either edge of the clock for waveform generation. By design of the

project the rising edge of the clock should be used, however we found out that the

software should be set to have the DAC trigger at the falling edge of the clock instead.

Otherwise, the clock violates setup and hold time. This setting can be changed by setting

bit 2 in register 18 high.

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Sometimes PLL and DAC/ADC chips stop performing their functions. This can be

fixed by reprogramming them through the serial interface again.

Figure 6.2 - Software Display of DAC/ADC.

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70

7 References [1] Balanis, Constantine A. Antenna Theory, Analysis and Design. 2nd ed. New York:

John Wiley & Sons, Inc., 1997. [2] Burr, Alister. Modulation and Coding for Wireless Communication. New Jersey:

Prentice Hall, 2001, pp.17-20. [3] Haykin, Simon. Communication Systems. 4th ed. New York: John Wiley and

Sons, Inc., 2001, pp. 251. [4] Lathi, B.P. Modern Digital and Analog Communication Systems. 2nd ed. Florida:

The Dryden Press Saunders College Publishing, 1989, pp. 515. [5] Lathi, B.P. Signal Processing and Linear Systems. 2nd ed. Carmichael, CA:

Berkeley-Cambridge Press, 1998, pp. 265, 471, 765, 771. [6] Ludwig, Reinhold. RF Circuit Design. New Jersey: Prentice Hall, 2000. [7] Matthews, Herbert. Surface Wave Filters: Design, Construction, and Use. New

York: John Wiley & Sons, Inc., 1977. [8] McClymont, Donald. Solving the Challenges of Direct Conversion:

Advancements in Direct-Conversion Receivers Enable Enhanced-Feature Sets and Lower-Cost Handsets. Oct. 2001. <http://www.electronicproducts.com/ShowPage.asp?SECTION=

3700&PRIMID=&FileName=octcox1.oct2001> [9] Milligan, Thomas A. Modern Antenna Design. New York: McGraw-Hill Inc,

1985. [10] Nash, Eamon, Yuping Toh, and Gray Hendrickson. Single Chip Realizes Direct-

Conversion Rx. Oct. 2002. <http://www.mwrf.com/Articles/Index.cfm?ArticleID=5524&pg=2>

[11] Proakis, John G. Communication Systems Engineering. 2nd ed. New Jersey:

Prentice Hall, 2002. [12] Sklar, B. Digital Communications. New Jersey: Prentice Hall, 1988, pp. 170, 430. [13] Smith, Julius O. Group Delay. Stanford University. Jan. 2004.

<http://ccrmawww.stanford.edu/~jos/filters/Group_Delay.html> [14] Wolaver, Dan H. Phase-Locked Loop Circuit Design. New Jersey: Prentice Hall,

1991. [15] Ziemer, R, and R. Peterson. Introduction to Digital Communication. New Jersey:

Prentice Hall, 2001.

8 Appendices

8.1 Appendix A – MATLAB Code

8.1.1 Exportpattrighalf.m

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8.1.2 Iqinit.m

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74

75

8.1.3 Listread.m

76

8.1.4 Received_detection.m

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78

79

80

8.1.5 Shapedata.m

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82

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84

85

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8.2 Appendix B – Absolute QPSK Detection Schemes

In order to extract the bitstream from the received signal of absolute QPSK scheme

without encoding, we looked at the polar (magnitude and phase) representation of the

differential signal, as opposed to the Cartesian (I and Q). The graphs representing

magnitude and phase of the transmitted signal can be seen in Figure 8.1. They were

mathematically modeled in MATLAB assuming a uniform 2˚ walk per symbol.

The magnitude and phase representation of the signal will prove very beneficial later

on when we have to restore the original bit transitions from the received signal.

Figure 8.1 - Magnitude and Phase of the Received Signal Difference.

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8.2.1 Downsampling Process

As mentioned earlier, the shaped bitstream is obtained by generating a sampled

waveform using digital to analog converters. The shaping algorithm defines the number

of samples per symbol; usually 100 samples per transmitted symbol are used. Having 100

89

samples per symbol ensures relatively smooth transitions from one sample to another. At

the same time, the transmitted bit information is encoded only in one of these 100

samples. This sample is located in the middle of the symbol (usually sample number 50).

When working with the received signal, it makes more sense to down-sample the

waveform and just work with the points that contain actual bit information.

The implemented down-sampling algorithm operates on the phase of the received

signal. Besides the phase waveform, the algorithm needs to know the number of samples

per received symbol. This can be determined by knowing the sampling rate of the analog

to digital converter (ADC) on the receiver side and the symbol transmission speed of the

system.

The phase of the received signal is constantly changing. Large jumps in phase usually

occur when the constellation point switches to its next position. The down-sampling

algorithm finds large abrupt change in phase and fills in the rest of the list according to

the number of samples per symbol. Now that we know the tentative locations of all the

bit transitions we locate the bits themselves by sampling in between the transitions.

8.2.2 Magnitude Dependent and Independent Reconstruction

After presenting the received signal as magnitude and phase, the differentiated I and

Q bit patterns can be reconstructed. As a reminder, the differentiated I or Q patterns could

take three possible values of -1, 0 or 1. Therefore, the combined differentiated I and Q

chart would have nine constellation points: eight are depicted on the constellation plot of

Figure 8.2 and the ninth is at the origin.

The polar representation of the differentiated I and Q shows that every constellation

point has a defined phase, except for (0,0). The angle of (0,0) is an arctan(0/0), which is

undefined. This can be seen in the phase oscillations in Figure 8.1 in time spots when the

magnitude of the signal is close to zero (8-9us and 27-28us). Even though the phase of

the signal at the point (0,0) is undefined, the magnitude is very close to zero. Therefore,

every time we find a point where the magnitude is zero, we can say it is (0,0) regardless

of the phase that the point exhibits.

In order to assign the rest of the points in the constellation appropriately, we will

consider two different reconstruction schemes, one of which relies on the magnitude of

the signal and the other one does not.

Figure 8.2 - Magnitude Independent Reconstructions.

The constellation representing magnitude-independent reconstruction is shown in

Figure 8.2. The phase of the downsampled signal is the only criterion that determines

what constellation region the symbol belongs to. For example, if the symbol’s phase

ranges from 22.5º to 77.5º we assign it the value of 45º which corresponds to a (1,1). By

using the magnitude independent reconstruction scheme we do not rely on possibly

unstable magnitude of the received signal. This makes the scheme more noise resistant.

At the same time we limit our phase deviation range to only 45º (±22.5º from the

90

assigned location). More narrow phase deviation range makes the scheme more prone to

error due to high walk values.

Another option of assigning transition bits to constellation points is to use a

magnitude-dependent reconstruction scheme. By looking at the magnitude part in Figure

8.1, three distinct levels of signal magnitude can be identified. For example, the first level

of magnitude lies around zero, the second – from 1.5 to 2 and the third around 2.5.

Figure 8.3 - Magnitude Dependent Reconstruction.

The first level of magnitude around zero has been already discussed, it is used to

detect points where I and Q are both zero. The second magnitude level corresponds to the

points that contain a 1 or -1 and a 0, such as (0,1), (0,-1), (1,0), (-1,0). We can identify

that these differentiated I and Q points correspond to the constellation points with angles

of 0º, 180º, 90º, and -90º, respectively. The third magnitude level corresponds to the

points that contain ones or minus ones, such as (1,1), (-1,1), (-1,-1), (1,-1). We can also

identify that these differentiated I and Q points correspond to the constellation points

with angles of 45º, 135º, -135º, and -45º, respectively.

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Instead of looking at the constellation points on one plot seen in Figure 8.2, we can

split them according to their magnitude levels and get two constellation plots as shown in

Figure 8.3. Such a split allows us to increase the phase deviation range by a factor of 2.

Now we can tolerate up to 90º of deviation for every constellation point, as opposed to

45º with magnitude-independent scheme. Such an improvement increases the robustness

of reconstruction process against phase walk. The tradeoff is the dependence on

magnitude, which could vary more significantly at higher noise levels.

8.3 Derotation Schemes

With our two detection choices described earlier, magnitude dependent and

magnitude independent, three different derotation schemes can be chosen. The three

schemes are abrupt change, average change by finite array, and delta change. All three of

these derotation schemes will remove the walk from our received data, but in different

ways.

8.3.1 Derotation by Abrupt Changes

Derotating by an abrupt change is the simplest of the three schemes, but may be the

most inaccurate. Derotation works by choosing a constellation point and comparing its

phase to the closest expected constellation angle. This will be later referred to as the

presumed angle. The next step would be to find the difference between the presumed and

measured angles, which can be seen below in Figure 8.5.

Figure 8.4 - QPSK plane.

The difference found would then be considered the walk of that constellation point.

Once the walk of the current constellation point is established we can then re-center the

constellation by subtracting the established walk from all future points. Subtracting the

walk of one point from the rest of the array is considered an abrupt change. This process

can be seen below in Figure 8.5, between parts (A) and (B).

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Figure 8.5 - Removing Walk by Abrupt Change.

The next step in the derotation process is to look at the next point and its closest

presumed angle, Figure 8.5 part (B). The difference between the presumed and measured

angles is used to re-center the constellation once again. By repeating the process of re-

centering for every constellation point, we slowly deal with the accumulation of walk of

future points. This process is demonstrated above in Figure 8.5, parts (B)-(D).

The abrupt derotation scheme places a high emphasis on the current walk compared

to the previous walk estimates. This high emphasis makes abrupt change derotation more

prone to error due to noise.

8.3.2 Derotation by Average Changes Stored in a Finite Array

Since phase walk is not always uniform, emphasis on a current walk should be

reduced. This can be done by subtracting the average of the differences instead of the

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differences themselves. When doing this we would be giving equal weight to a chosen

number of previous samples, making the derotation more accurate. This average is found

by entering the differences in a finite array and taking the average. The finite array size

allows the average to change relatively quickly.

Seen below in Figure 8.6 is the construction of the finite array. The first difference is

entered into the first location, which then gets averaged and used to re-center the system.

The next difference is entered into the second location and the average of the two points

is taken. When the array becomes full, the old entries are removed to make room for the

new ones. This allows the average of the finite array to adjust accordingly if the phase

walk changes over time.u

Diff.1

Diff.2

Diff.1

Diff.1 Diff.2

Diff.1 Diff.2 Diff.3

Diff.2 Diff.3 Diff.4

Diff.3 Diff.4 Diff.5

Average(Diff.1)

Average(Diff.1&Diff.2)

Average(Diff.1&Diff.2&Diff.3)

Average(Diff.2&Diff.3&Diff.4)

Average(Diff.3&Diff.4&Diff.5)

Finite Array

Figure 8.6 - Construction of Finite Array.

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8.3.3 Derotation by Delta Change.

Another derotation scheme employs a feedback system visualized below in Figure

8.7. The system uses a feedback loop, which forces Magic N correction factor to

converge on average walk. This Magic N is then subtracted from the array to re-center

our data.

Figure 8.7 - Visual Diagram of Delta Change Derotation.

Seen below in Figure 8.8 is an example of how Magic N is being created and

converges on the average of phase differences.

∆×

+ +

∆× ∆× ∆×

+ +−− − −

1.0=∆

Figure 8.8 - An Example of the Convergence of Magic N.

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8.4 Appendix C – Product Datasheets