rev 6.5€¦ · page(.csa)contents syncdate 46 lpc+spi debug connector 04/02/2013 j41_mlb 61...

TABLE_TABLEOFCONTENTS_ITEM










































































TABLE_TABLEOFCONTENTS_HEAD


DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL


DRAWING

TABLE_TABLEOFCONTENTS_HEAD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

IV ALL RIGHTS RESERVED

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPDCK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISIONREV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILESchematic / PCB #’sPRODUCT SAFETY REQUIREMENTS:

J43 MLB SCHEMATIC DVTREV 6.5.0

4/09/13

ALIASES RESOLVED

1 OF 76

<PART_DESCRIPTION>

<SCH_NUM>

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Fan J41_MLB4560 02/06/2013

Thermal Sensors J41_MLB4458 02/06/2013

Debug Sensors 1 J41_MLB4356 03/28/2013

Voltage & Load Side Current Sensing J41_MLB4255 03/28/2013

High Side Current Sensing J41_MLB4154 03/28/2013

SMBus Connections J41_MLB4053 02/06/2013

SMC Project Support J41_MLB3952 02/06/2013

SMC Shared Support J41_MLB3851 02/06/2013

SMC J41_MLB3750 02/06/2013

IPD Connector J41_MLB3648 02/12/2013

External A USB3 Connector J41_MLB3546 02/07/2013

SD CONTROLLER (GL3219) MASTER3445 10/11/2010

SD READER CONNECTOR MASTER3344 07/01/2011

Camera 2 of 2 J41_MLB3240 03/20/2013

Camera 1 of 2 J41_MLB3139 04/02/2013

SSD Connector J41_MLB3037 04/09/2013

Wireless Connector J41_MLB2935 02/06/2013

Thunderbolt Connector A J41_MLB2832 02/07/2013

TBT Power Support J41_MLB2730 02/06/2013

Thunderbolt Host (2 of 2) J41_MLB2629 02/06/2013

Thunderbolt Host (1 of 2) J41_MLB2528 02/06/2013

LPDDR3 DRAM Termination J41_MLB2427 02/06/2013

LPDDR3 DRAM Channel B (32-63) J41_MLB2326 02/06/2013

LPDDR3 DRAM Channel B (0-31) J41_MLB2225 02/06/2013

LPDDR3 DRAM Channel A (32-63) J41_MLB2124 02/06/2013

LPDDR3 DRAM Channel A (0-31) J41_MLB2023 02/06/2013

DDR3 VREF MARGINING J41_MLB1922 02/12/2013

Project Chipset Support J41_MLB1820 02/15/2013

Chipset Support J41_MLB1719 02/06/2013

CPU/PCH Merged XDP J41_MLB1618 02/06/2013

PCH GPIO/MISC/LPIO J41_MLB1516 04/02/2013

PCH PCIe/USB/LPC/SPI/SMBus J41_MLB1415 02/06/2013

PCH PM/PCI/GFX J41_MLB1314 02/06/2013

PCH Audio/JTAG/SATA/CLK J41_MLB1213 02/06/2013

PCH Decoupling J41_MLB1112 02/07/2013

CPU Decoupling WILL_J431010 01/08/2013

CPU/PCH GROUNDS J41_MLB99 02/06/2013

CPU/PCH POWER J41_MLB88 04/09/2013

CPU DDR3/LPDDR3 Interfaces J41_MLB77 02/06/2013

CPU Misc/JTAG/CFG/RSVD J41_MLB66 04/02/2013

CPU GFX/NCTF/RSVD J41_MLB55 02/06/2013

PD PARTS MASTER44 MASTER

BOM Variants K21_MLB33 11/16/2010

BOM Configuration J41_MLB22 04/09/2013

Reference7607/03/2012

J41_MLB

121

Project Specific Constraints7509/25/2012

CONSTRAINTS

119

Project Specific Constraints7412/07/2012

J41_MLB

118

SMC Constraints7309/25/2012

CONSTRAINTS

117

Camera Constraints7201/30/2013

J41_MLB

116

Thunderbolt Constraints7109/25/2012

CONSTRAINTS

115

Memory Constraints7009/25/2012

CONSTRAINTS

114

PCH Constraints 26912/14/2012

J41_MLB

113

PCH Constraints 16811/13/2012

CLEAN_J43

112

CPU Constraints6709/25/2012

CONSTRAINTS

111

PCB Rule Definitions6610/24/2012

CONSTRAINTS

110

Project FCT/NC/Aliases6509/13/2012

J41_MLB

105

Func Test / No Test6402/01/2013

J41_MLB

104

Signal Aliases6308/30/2012

J41_MLB

102

Power Aliases6201/30/2013

J41_MLB

100

Left I/O (LIO) Connector6111/13/2012

CLEAN_J43

95

Internal DisplayPort Connector6002/06/2013

J41_MLB

83

Power Control5902/06/2013

J41_MLB

81

Power FETs5802/06/2013

J41_MLB

80

Misc Power Supplies5702/06/2013

J41_MLB

78

LCD/KBD Backlight Driver5602/06/2013

J41_MLB

77

1.05V S0 Power Supply5503/28/2013

J41_MLB

76

5V S4RS3 / 3.3V S5 Power Supply5409/17/2012

J41_MLB

75

LPDDR3 Supply5302/09/2013

J41_MLB

74

CPU VR12.5 VCC Power Stage5204/09/2013

J41_MLB

73

CPU VR12.6 VCC Regulator IC5104/09/2013

J41_MLB

72

PBus Supply & Battery Charger5002/09/2013

J41_MLB

71

DC-In & G3H Supply4902/06/2013

J41_MLB

70

Battery Connector48MASTER

MASTER

69

Audio: Speaker Amp4702/06/2013

J41_MLB

64

Date

Page Sync(.csa)

ContentsLPC+SPI Debug Connector46

04/02/2013

J41_MLB

61

PCBF,MLB,J43820-3437 CRITICALPCB1

SCHSCHEM,MLB,J43051-9800 CRITICAL1

Table of Contents MASTER11 MASTER

LAST_MODIFIED=Tue Apr 9 20:06:04 2013

TITLE=MLB

ABBREV=DRAWING

Contents(.csa)

Page SyncDate

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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM


Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

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TABLE_BOMGROUP_ITEM

DRAM Parts

CFG 0

00

1 0

CFG 1

CPU DRAM CFG Chart

HYNIX

VENDOR

SAMSUNG

1 1

0

0

1

1

0

1

CFG 2

CFG 3

ELPIDA

SIZE

4GB

8GB

MICRON

B

A

DIE REV

BOM Groups Alternate Parts

Current Sensor Configuration

Module Parts

Programmable Parts

CPU DRAM SPD Straps

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GBDDR3:SAMSUNG_8GB

TBTROM:BLANK335S0865 EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN CRITICAL1 U2890

341S3802 IC,EEPROM,C/R (V23.4) EVT,J41/J41 CRITICAL1 TBTROM:PROGU2890

335S0809 1 64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8 BOOTROM_MAC:BLANKCRITICALU6100

SYNC_DATE=04/09/2013SYNC_MASTER=J41_MLB

BOM Configuration

DDR3:SAMSUNG_4GB RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8 BOOTROM_NUM:BLANKCRITICAL1335S0803 U6100

IC,EFI ROM (V0071) DVT,J41/J43341S3809 1 BOOTROM:PROGCRITICALU6100

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA338S1159 1 SMC:BLANKU5000 CRITICAL

CPU:1.4GHZHSW,SR16L,PRQ,C0,1.4,15W,2+3,1.1,3M,BGA U0500 CRITICAL1337S4526

DDR3:MICRON_4GB RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB

IC,TBT,CR-4C,B1,PRQ,CIO,288,12X12 FC-CSP338S1113 U2800 CRITICAL1

HSW,SR16M,PRQ,C0,1.3,15W,2+3,1.0,3M,BGA U0500 CRITICAL1 CPU:1.3GHZ337S4525

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YESISNS:ENG

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NOISNS:PROD

DDR3:HYNIX_4GB RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:ENG,MLB_PROGPARTSMLB_COMMON

XDP_CONNMLB_DEVEL:PVT

DEVEL_BOM,XDP,LPCPLUSMLB_DEBUG:ENG

MLB_MISC PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS

138S0638 Murata alt to Samsung138S0841 ALL

376S1180 Renesas alt to Vishay376S0761 ALL

152S1804 ALL TDK alt to Toko152S1876

107S0240 ALL107S0255 Cyntec alt to TFT

ALL107S0248 Cyntec alt to TFT107S0250

Epson alt to TXCALL197S0545 197S0544

ALL377S0104377S0155 OnSemi alt to Infineon

197S0343197S0481 Epson crystal alt to TXCALL

Cyntec sense R alt to TFT107S0254 ALL107S0241

353S3452 353S1286 ALL Maxim alt to Microchip

128S0325128S0397 Kemet alt to SanyoALL

197S0542 197S0544 NDK alt to TXCALL

DDR3:HYNIX_8GB RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

ALL197S0478197S0479 200uW Epson alt to NDK

ALL128S0371 128S0376 Kemet alt to Sanyo

128S0394 ALL NEC alt to Sanyo128S0415

197S0480 NDK crystal alt to TXCALL197S0343

ALL Taiyo alt to Samsung138S0681 138S0638

152S1821 ALL Cyntec alt to NEC152S1757

Kemet alt to Sanyo128S0398 128S0220 ALL

376S0855 ALL NXP alt for Diodes dual376S1129

138S0703 138S0648 Murata alt to Taiyo YudenALL

152S0586 ALL Dale/Vishay alt to Cyntec152S1301

372S0186 372S0185 NXP alt to DiodesALL

Murata alt to Taiyo Yuden138S0684 ALL138S0660

376S1032 376S0855 Toshiba alt for Diodes dualALL

371S0558371S0713 ALL Diodes alt to ST Micro

128S0386 Kemet alt to Sanyo128S0284 ALL

376S0604376S1053 ALL Diodes alt to Fairchild

ALL376S1089 NXP alt for Diodes single376S1128

1 CRITICALIC,BCM15700A2,S2 PCIE CAMERA PROCESSOR U3900338S1186

ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENGMLB_DEVEL:ENG

MLB_DEBUG:PVT DEVEL_BOM,BKLT:PROD,XDP,LPCPLUS,ISNS:PROD

BKLT:PROD,LPCPLUS,XDP,ISNS:PRODMLB_DEBUG:PROD

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GBDDR3:ELPIDA_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GBDDR3:ELPIDA_4GB

CRITICAL J41_MLBJ69551 ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99607-6811

HSW,SR16H,PRQ,C0,1.7,15W,2+3,1.1,4M,BGA U0500 CRITICAL1 CPU:1.7GHZ337S4528

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL4 DRAM_TYPE:HYNIX_4GB333S0677

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA333S0681 U2300,U2400,U2500,U2600 DRAM_TYPE:HYNIX_8GBCRITICAL4

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA333S0676 U2300,U2400,U2500,U2600 CRITICAL4 DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 DRAM_TYPE:MICRON_4GB333S0679 4 CRITICAL

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA CRITICAL4 U2300,U2400,U2500,U2600 DRAM_TYPE:ELPIDA_4GB333S0678

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600333S0666 CRITICAL4 DRAM_TYPE:ELPIDA_8GB

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA4 CRITICALU2300,U2400,U2500,U2600 DRAM_TYPE:SAMSUNG_8GB333S0680

VCORE_FET:VSHY2 CRITICALMOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN Q7311,Q7321376S1174

1 LABEL825-7670 LABEL,TEXT,MLB,K21/K78

VCORE_FET:REN2 Q7310,Q7320 CRITICAL376S0964 MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN

VCORE_FET:RENQ7311,Q7321 CRITICAL2376S1104 MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN

VCORE_FET:VSHYMOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN2 Q7310,Q7320 CRITICAL376S1173

CRITICAL1 SOLDERPASTE900-0090

1 GLUE946-3892 J11/J13 MLB DYMAX ADHESIVE 29993-SC 0.4G CRITICAL

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BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM



TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM


PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD


BOM Variants NOTE: All the "GOOD" BOM Configs have been de-activated

Sub-BOMs

Alternate Parts

Programmable Parts

Module Parts

BOM Groups

VCORE_FETSVCOREFETSVCORE FET,VSHY,J43685-0065 1 CRITICAL

CRITICAL1 CMNPTS685-0025 CMN PTS,PCBA,MLB,J43 MLB_CMNPTS

J43 MLB DEVELOPMENT BOM985-0018 CRITICALDEVEL1 DEVEL_BOM

U45001 CRITICAL338S1215 IC,GL3219,USB3 SD CARD READER,46P,LQFN

BOOTROM:PROG,SMC:PROG,TBTROM:PROGMLB_PROGPARTS

ALL333S0700333S0704 Elpida CAM DRAM alt to Hynix

Renesas alt for VishayALL685-0065685-0064

VCORE FET,VSHY,J43 VCORE_FET:VSHY685-0065

MLB_CMNPTS,CPU:1.7GHZ,DDR3:MICRON_4GB639-4759 PCBA,MLB,BEST,MI-4GB,J43

MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_8GBPCBA,MLB,BEST,EL-8GB,J43639-4758

MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_8GBPCBA,MLB,BEST,HY-8GB,J43639-4756

MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_4GBPCBA,MLB,BEST,HY-4GB,J43639-4755

PCBA,MLB,GOOD,MI-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:MICRON_4GB639-4745

PCBA,MLB,BETTER,HY-4GB,J43639-4445 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_4GB

PCBA,MLB,BETTER,HY-8GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_8GB639-4446

PCBA,MLB,BETTER,EL-8GB,J43639-4448 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_8GB

VCORE_FET:RENVCORE FET,REN,J43685-0064

PCBA,MLB,GOOD,EL-8GB,J43639-4295 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_8GB

PCBA,MLB,BETTER,EL-4GB,J43639-4447 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_4GB

MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_4GBPCBA,MLB,BEST,EL-4GB,J43639-4757

U5000 CRITICAL SMC:PROG1341S3758 IC,SMC-A3 SCPL,EXT,V22.12a19,PROTO 1,J43

J43 MLB DEVELOPMENT BOM MLB_DEVEL:ENG985-0018

MLB_COMMONCMN PTS,PCBA,MLB,J43685-0025

PCBA,MLB,BETTER,MI-4GB,J43639-4746 MLB_CMNPTS,CPU:1.3GHZ,DDR3:MICRON_4GB

639-4146 PCBA,MLB,GOOD,HY-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_4GB

PCBA,MLB,GOOD,EL-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_4GB639-4294

639-4293 PCBA,MLB,GOOD,HY-8GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_8GB

BOM VariantsSYNC_DATE=11/16/2010SYNC_MASTER=K21_MLB

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Plated Board Slot

CPU Heat Sink Mounting Bosses

4x 860-1327

860-1327

SSD Boss

870-1938

X21 Boss

860-1327

Fan Boss

860-1327

870-1938

DisplayPort Pogo

2x TBT chip

2x USB Connector

2x MDP Connector

2x TBT pin diodes

Can Slots

USB/SD Card PogoEMI I/O Pogo Pins

PD Module Parts

1

Z0410STDOFF-4.5OD1.8H-SM

1

ZS0406CRITICAL

POGO-2.0OD-3.6H-K86-K87SM

1


1


1

ZS0405SM

CRITICAL

POGO-2.0OD-3.6H-K86-K87

1

SL0402

SL-1.1X0.4-1.4X0.7

TH-NSP

1

SL0406

SL-1.1X0.4-1.4X0.7

TH-NSP1


1

SL0401

SL-1.1X0.4-1.4X0.7

TH-NSP

1

SL0403TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0407TH-NSP

SL-1.1X0.45-1.4X0.75

1

SL0408TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0400

SL-2.3X3.9-2.9X4.5

TH-NSP

1

SL0405

SL-1.1X0.45-1.4X0.75

TH-NSP

1

SL0404

SL-1.1X0.4-1.4X0.7

TH-NSP

1


1


1


CRITICAL1 INSULATOR,CPU,J41/J43 CPU_INSULATOR725-1792

1 CRITICAL806-3083 SHLD,USB,MLB,J11/J13 USBCAN

1 CRITICAL806-3216 CAN,MDP,J11/J13 MDPCAN

1 CRITICALCAN,COVER,TBT,J11/J13 TBTCOVER806-3215

1 CRITICALTBTFENCECAN,TBT,J11/J13806-3142

1 CRITICALCAN,TOPSIDE,COVER,ALT,J41/J43 TBTTOPSIDE_2P_COVER806-5108

1 CRITICAL806-5107 CAN,TOPSIDE,ALT,J41/J43 TBTTOPSIDE_2P_FENCE

PD PARTSSYNC_DATE=MASTERSYNC_MASTER=MASTER

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OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN

EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

DDI

EDP

SYM 1 OF 19

SYM 17 OF 19

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

SPARE

SYM 18 OF 19

TP

TP

TP

TP

TP

TP

TP

TP

NC NCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNCNC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

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Other corner test signals connected in

MCP Daisy-Chain Strategy:Each corner of CPU has two testpoints.

NO_TESTNO_TEST

daisy-chain fashion. Continuity shouldexist between both TP’s on each corner.

eDP Port Assignment:

Internal panel

DDI Port Assignments:

TBT Sink 0

TBT Sink 1(MUXed with HDMI if necessary)

18 25 67

18 25 67

60 67

60 67

64

64

64

64

64

64

60 67

60 67

B49

C46

B47

B46

A49

C47

A47

C45

D20

A43

B45

A45

B53

B50

B54

C50

A53

C49

C53

C51

B57

A55

C58

C55

A57

B55

B58

C54

U0500

CRITICAL

HASWELL-ULT

BGA-TSP

OMIT_TABLE

2C+GT2

C2

C1

B63

B62

B61

B3

B2

AY62

AY61

AY60

AY3

AY2

AW63

AW62

AW61

AW3

AW2

AW1

AV1

A62

A61

A60

A4

A3

U0500

2C+GT2HASWELL-ULT

BGA-TSP

OMIT_TABLECRITICAL

U10

T23

R23

N23

J21

H22

F22

D15

AY14

AW14

AV44

AU44

AU15

AU10

AT2

AP7

AM11

AL1

U0500HASWELL-ULT

OMIT_TABLECRITICAL

2C+GT2BGA-TSP

1TP0531TP-P6

1 TP0500TP-P61 TP0510TP-P6

1TP0501TP-P6

1 TP0511TP-P61 TP0520TP-P61 TP0521TP-P6

1 TP0530TP-P6

2

1R053024.91%

MF201

1/20W

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

18 25 67

18 25 67

18 25 67

18 25 67

18 25 67

18 25 67

CPU GFX/NCTF/RSVDSYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB

TP_EDP_DISP_UTIL

MCP_DC_AV1

MCP_DC_AW3_AY3TRUE

MCP_DC_AW63

TRUEMCP_DC_AW3_AY3

MCP_DC_A60

MCP_DC_B2

TRUEMCP_DC_AW2_AY2

MCP_DC_AY60MCP_DC_AW61_AY61 TRUE

MCP_DC_B62_B63 TRUE

MCP_DC_A3_B3 TRUE

TRUEMCP_DC_A61_B61

MCP_DC_AW62_AY62 TRUE

TRUE MCP_DC_AW62_AY62MCP_DC_AW61_AY61TRUE

TRUE MCP_DC_AW2_AY2MCP_DC_AW1

TRUE MCP_DC_A61_B61MCP_DC_A62

MCP_DC_A4MCP_DC_A3_B3TRUE

MCP_DC_C1_C2 TRUE

DP_INT_AUXCH_C_PDP_INT_AUXCH_C_N

NC_INT_ML_CN<3>NC_INT_ML_CP<2>NC_INT_ML_CN<2>

NC_INT_ML_CN<1>DP_INT_ML_C_P<0>DP_INT_ML_C_N<0>

PPVCOMP_S0_CPU

DP_TBTSNK0_ML_C_N<3>


DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<1>DP_TBTSNK1_ML_C_P<0>DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>DP_TBTSNK0_ML_C_N<1>DP_TBTSNK0_ML_C_P<1>





DP_TBTSNK1_ML_C_N<3>DP_TBTSNK1_ML_C_P<2>DP_TBTSNK1_ML_C_N<2>

NC_INT_ML_CP<1>

MCP_EDP_RCOMP

NC_INT_ML_CP<3>

5 OF 121

<E4LABEL>

<SCH_NUM>

<BRANCH>

5 OF 76

5

5

5

5

5

5

5

5

5

5

5

5

8

www.vinafix.vn

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1

SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*PROC_DETECT*SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNC

NC

BI

BI

OUT

NC

BI

BI

BI

BI

BI

BI

BI

BI

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

VSS

VSS

RSVD

RSVD

CFG_RCOMP

RSVD

RSVD

RSVD

TD_IREF

CFG0

CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17

CFG19

RSVD

RSVD

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

EDP_SPARE

RSVD_TP

RSVD_TP

RSVD_TP

RSVD

RSVD

RSVD

PROC_OPI_COMP

RSVD

RSVD

RESERVED

SYM 19 OF 19

NC

NCNCNCNC

NCNC

NCNC

NC

Apple Inc.


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6 3



CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVIDCFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

and are only for debug accessThese can be placed close to J1800

(IPU)

(IPD)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCKCFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODECFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

(IPU)

(IPU)

AU61

AV60

AU60

AV61

AV15

C61

K63

E59

E61

F62

F63

E60

D61

K62

J62

N62

K61

J61

K60

H63

K59

H62

H61

H60

J60

U0500

BGA-TSP2C+GT2

HASWELL-ULT

OMIT_TABLECRITICAL

2

1R0640NOSTUFF

1K5%

201

1/20WMF

2

1R0639HSW_PRE_ES2

1K5%

201

1/20WMF

2

1R0638

MF1/20W

201

5%1K

NOSTUFF

2

1R0631

MF1/20W

201

5%1K

NOSTUFF

2

1R0630NOSTUFF

1K5%

201

1/20WMF

6 16 67

6 16 67

16 64 67

16 67

16 67

6 16 67

16 67

16 67

6 16 67

6 16 67

16 67

6 16 67

16 67

16 67

16 67

16 67

16

16

16

16

37 38 51 67

2

1R06105%

1/20WMF201

62

2 1

R0611

201

5%

MF

56

1/20W

38 67

37 67

2

1R0620

PLACE_NEAR=U0500.C61:12.7mm

201MF

1/20W5%

10K

16 67

16 67

16 67

16 67

16 67

16 67

16 67

16 67

16 64 67

16 64 67

12 16 64 67

16 64 67

16 64 67

16 64 67

16 64 67

2

1R0652

MF1/20W

201

1001%

PLACE_NEAR=U0500.AU61:12.7mm

2

1R0651

MF1/20W

201

1%

PLACE_NEAR=U0500.AV60:12.7mm

121

2

1R06501%

200

201

1/20WMF


18

17

2

1R06801%

1/20W

201MF

49.9

P22

N21

B12

Y22

W23

L60

C63

C62

B51

AV63

AU63

A51

R20

P20

N60

J20

H18

E1

D58

D1

AV62

A5

AY15

B43

V63

V61

V62

Y60

Y61

Y62

AA60

AA63

AC63

U62

U63

AA61

AA62

T60

T61

T62

T63

U60

V60

AC62

AC60

U0500

CRITICALOMIT_TABLE

HASWELL-ULT2C+GT2BGA-TSP

2

1R0690

201MF1/20W1%49.9

2

1R0685

1/20WMF201

1%8.25K

2

1R06341K5%

201

1/20WMF

EDP


CPU Misc/JTAG/CFG/RSVD

CPU_SM_RCOMP<0>

PP1V05_S0

CPU_SM_RCOMP<2>

CPU_CATERR_L

CPU_CFG<9> TP_MCP_RSVD_B51

CPU_CFG<0>CPU_CFG<1>

CPU_CFG<5>CPU_CFG<4>CPU_CFG<3>CPU_CFG<2>

CPU_CFG<6>

CPU_CFG<10>


CPU_CFG<11>

CPU_CFG<15>CPU_CFG<14>CPU_CFG<13>



TP_MCP_RSVD_AV63TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63TP_MCP_RSVD_C62

TP_MCP_RSVD_A51

CPU_OPI_RCOMP

CPU_CFG<4>

XDP_CPU_PRDY_LXDP_CPU_PREQ_L

XDP_CPU_TCKXDP_CPU_TMSXDP_CPUPCH_TRST_L

XDP_CPU_TDIXDP_CPU_TDO

XDP_BPM_L<0>XDP_BPM_L<1>XDP_BPM_L<2>XDP_BPM_L<3>XDP_BPM_L<4>XDP_BPM_L<5>XDP_BPM_L<6>XDP_BPM_L<7>

TP_MCP_RSVD_L60

CPU_CFG_RCOMP

CPU_CFG<12>

CPU_PWRGD

CPU_SM_RCOMP<1>

TP_CPU_MEM_RESET_L

CPU_MEMVTT_PWR_EN_LSVDDQ

CPU_PECI

CPU_PROCHOT_R_LCPU_PROCHOT_L

CPU_CFG<0>

CPU_CFG<10>CPU_CFG<9>CPU_CFG<8>CPU_CFG<1>

PCH_TD_IREF

<BRANCH>

<SCH_NUM>

<E4LABEL>

6 OF 121

6 OF 76

67

8 11 15 16 17 27 38 42 51 55 58 59 62 64

67

6 16 67

67

67

6 16 67

6 16 67

6 16 67

6 16 67

6 16 67

www.vinafix.vn

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55

SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45

SA_DQ46

SA_DQ42

SA_DQ43

SA_DQ44

SA_DQ40

SA_DQ41

SA_DQ39

SA_DQ37

SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32

SA_DQ33

SA_DQ29

SA_DQ30

SA_DQ31

SA_DQ27

SA_DQ28

SA_DQ24

SA_DQ25

SA_DQ22

SA_DQ23

SA_DQ21

SA_DQ19

SA_DQ20

SA_DQ17

SA_DQ18

SA_DQ16

SA_DQ14

SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7

SA_DQ8

SA_DQ6

SA_DQ4

SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0*

SA_CS1*

SA_CKE0

SA_CKE1

SA_CKE2

SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3

SA_MA4

SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13

SA_MA14

SA_MA15

SA_BA2

SA_BA0

SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3

SA_DQSP4

SA_DQSP5

SA_DQSP6

SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5

SA_DQSN6

SA_DQSN7

SYM 3 OF 19

MEMORY CHANNEL A

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

SB_DQ0

SB_DQ1

SB_DQ2

SB_DQ3

SB_DQ4

SB_DQ5 SB_CKE0

SB_DQ6 SB_CKE1

SB_DQ7 SB_CKE2

SB_DQ8 SB_CKE3

SB_DQ9

SB_DQ10 SB_CS0*

SB_DQ11 SB_CS1*

SB_DQ12

SB_DQ13 SB_ODT0

SB_DQ14

SB_DQ15 SB_RAS*

SB_DQ16 SB_WE*

SB_DQ17 SB_CAS*

SB_DQ18

SB_DQ19 SB_BA0

SB_DQ20 SB_BA1

SB_DQ21 SB_BA2

SB_DQ22

SB_DQ23 SB_MA0

SB_DQ24 SB_MA1

SB_DQ25 SB_MA2

SB_DQ26 SB_MA3

SB_DQ27 SB_MA4

SB_DQ28 SB_MA5

SB_DQ29 SB_MA6

SB_DQ30 SB_MA7

SB_DQ31 SB_MA8

SB_DQ32 SB_MA9

SB_DQ33 SB_MA10

SB_DQ34 SB_MA11

SB_DQ35 SB_MA12

SB_MA13

SB_DQ37 SB_MA14

SB_DQ38 SB_MA15

SB_DQ39

SB_DQ40 SB_DQSN0

SB_DQ41 SB_DQSN1

SB_DQ42 SB_DQSN2

SB_DQ43 SB_DQSN3

SB_DQ44 SB_DQSN4

SB_DQ45 SB_DQSN5

SB_DQ46 SB_DQSN6

SB_DQ47 SB_DQSN7

SB_DQ48

SB_DQ49 SB_DQSP0

SB_DQ50 SB_DQSP1

SB_DQ51 SB_DQSP2

SB_DQ52 SB_DQSP3

SB_DQ53 SB_DQSP4

SB_DQ54 SB_DQSP5

SB_DQ55 SB_DQSP6

SB_DQ56 SB_DQSP7

SB_DQ57

SB_DQ58

SB_DQ59

SB_DQ60

SB_DQ61

SB_DQ62

SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1SYM 4 OF 19

MEMORY CHANNEL B

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

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CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

CAA5

CAB9

CAB8

CAB5

RSVD1

RSVD2

CAA0

CAA2

CAA4

CAB3

CAB2

CAB1

CAB4

CAB6

LPDDR3

CAA5

CAB9

CAB8

CAB5

CAB3

CAB2

CAB1

CAB4

CAB6

LPDDR3

CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

CAA0

CAA2

CAA4

RSVD3

RSVD4

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

21 63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

21 63 70

63 70

63 70

63 70

63 70

63 70

63

63

20 21 24 63 70

20 21 24 70

20 21 24 70

20 24 70

21 24 70

21 24 70

20 24 70

20 24 70

20 24 70

63

21 24 63 70

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

20 24 63 70

63

63 70

63 70

63 70

63 70

63 70

21 63 70

63 70

63 70

AP51

AR51

AP49

AW34

AY34

AP32

AU40

AY39

AW39

AV40

AR36

AU39

AP36

AR38

AU42

AV42

AR35

AU41

AW41

AP35

AY37

AU36

AL49

AL42

AW53

AW57

AN55

AN58

AN61

AJ62

AL48

AL43

AV53

AV57

AM55

AM58

AN62

AJ61

AM62

AM63

AK60

AK51

AM51

AK48

AM48

AK61

AK49

AM49

AK46

AM46

AM42

AM40

AK43

AK45

AM45

AM43

AH60

AK42

AK40

AU52

AV52

AU54

AV54

AW52

AY52

AW54

AY54

AH61

AU56

AV56

AU58

AV58

AW56

AY56

AW58

AY58

AN54

AR54

AK62

AK55

AL55

AK54

AM54

AR55

AP55

AN57

AR57

AK58

AL58

AK63

AK57

AM57

AR58

AP58

AP60

AP61

AM60

AM61

AP62

AP63

AH62

AH63

AR32

AP33

AW36

AY36

AU37

AV37

AY43

AY42

AW43

AU43

AU34

AY41

AV35

AU35

U0500

2C+GT2

CRITICALOMIT_TABLE

BGA-TSP

HASWELL-ULT

21 24 70

21 24 70

19

19

19

22 24 70

22 24 70

23 24 70

23 24 70

22 24 70

22 24 70

23 24 70

23 24 70

22 23 24 70

22 23 24 70

22 23 24 63 70

63

63

63

63

23 24 63 70

63

63

63

63

63

63

63

63

63

63

63

63

63

22 24 63 70

63

63

63

63 70

63 70

63 70

63 70

63 70

63 70

23 63 70

63 70

63 70

63 70

63 70

63 70

63 70

23 63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

AK35

AM35

AL32

AU46

AY47

AY46

AW46

AP45

AR45

AR42

AP42

AP46

AR46

AK33

AU47

AV47

AK36

AR40

AP40

AM18

AM21

AW18

AV22

AM25

AM28

AW26

AV30

AN18

AN21

AV18

AW22

AN25

AN28

AV26

AW30

AW27

AY27

AU29

AP18

AR18

AM20

AK20

AV29

AL18

AK18

AR20

AN20

AK22

AK21

AP21

AN22

AM22

AL21

AU31

AR22

AR21

AU17

AV17

AU19

AV19

AW17

AY17

AW19

AY19

AV31

AU21

AV21

AU23

AV23

AW21

AY21

AW23

AY23

AL25

AK25

AW29

AM26

AK26

AP25

AR25

AR26

AN26

AP28

AR28

AN29

AR29

AY29

AK28

AL28

AK29

AM29

AU25

AV25

AU27

AV27

AW25

AY25

AW31

AY31

AK32

AM32

AV50

AW49

AU50

AY49

AK38

AL38

AM38

AN38

AM33

AU49

AM36

AL35

U0500OMIT_TABLECRITICAL


63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

23 63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70

63 70


CPU DDR3/LPDDR3 Interfaces

=MEM_B_RAS_L

MEM_B_DQS_P<2>

MEM_B_DQS_P<0>

=MEM_B_BA<2>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_CLK_P<1>

MEM_B_CKE<2>

CPU_DIMMB_VREFDQ

CPU_DIMMA_VREFDQ

CPU_DIMM_VREFCA

MEM_A_DQS_P<2>

MEM_A_DQS_P<4>MEM_A_DQS_P<3>


MEM_A_DQS_N<5>MEM_A_DQS_N<6>

MEM_A_DQS_N<4>MEM_A_DQS_N<3>MEM_A_DQS_N<2>MEM_A_DQS_N<1>


MEM_A_DQS_N<0>

=MEM_A_A<13>MEM_A_CAA<6>=MEM_A_A<11>

=MEM_A_A<9>=MEM_A_A<10>

=MEM_A_A<8>



TP_LPDDR3_RSVD2=MEM_A_A<5>

=MEM_A_A<1>=MEM_A_A<2>TP_LPDDR3_RSVD1

=MEM_A_A<0>

=MEM_A_BA<2>MEM_A_CAB<6>

=MEM_A_RAS_L=MEM_A_WE_L=MEM_A_CAS_L

=MEM_A_BA<0>

MEM_A_CS_L<1>MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CKE<3>MEM_A_CKE<2>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_CLK_P<1>MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_B_DQS_P<7>

MEM_B_DQS_P<5>MEM_B_DQS_P<6>

MEM_B_DQS_P<3>MEM_B_DQS_P<4>

MEM_B_DQS_P<1>

MEM_B_DQS_N<7>MEM_B_DQS_N<6>


MEM_B_DQS_N<3>


MEM_B_DQS_N<0>

=MEM_B_A<15>=MEM_B_A<14>=MEM_B_A<13>MEM_B_CAA<6>=MEM_B_A<11>=MEM_B_A<10>

=MEM_B_A<8>=MEM_B_A<9>

=MEM_B_A<7>=MEM_B_A<6>=MEM_B_A<5>TP_LPDDR3_RSVD4TP_LPDDR3_RSVD3=MEM_B_A<2>=MEM_B_A<1>=MEM_B_A<0>

MEM_B_CAB<6>=MEM_B_BA<0>

=MEM_B_CAS_L=MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CKE<3>

MEM_B_CKE<0>

MEM_B_CLK_N<1>

MEM_B_CLK_N<0>MEM_B_CLK_P<0>

MEM_B_DQ<17>

MEM_B_DQ<37>

MEM_B_DQ<49>MEM_B_DQ<50>

MEM_B_DQ<44>

MEM_B_DQ<30>MEM_B_DQ<29>MEM_B_DQ<28>

MEM_B_DQ<0>MEM_B_DQ<1>MEM_B_DQ<2>MEM_B_DQ<3>MEM_B_DQ<4>MEM_B_DQ<5>MEM_B_DQ<6>MEM_B_DQ<7>MEM_B_DQ<8>MEM_B_DQ<9>MEM_B_DQ<10>MEM_B_DQ<11>MEM_B_DQ<12>MEM_B_DQ<13>MEM_B_DQ<14>MEM_B_DQ<15>MEM_B_DQ<16>

MEM_B_DQ<18>MEM_B_DQ<19>MEM_B_DQ<20>MEM_B_DQ<21>MEM_B_DQ<22>MEM_B_DQ<23>MEM_B_DQ<24>MEM_B_DQ<25>MEM_B_DQ<26>MEM_B_DQ<27>

MEM_B_DQ<31>MEM_B_DQ<32>MEM_B_DQ<33>MEM_B_DQ<34>MEM_B_DQ<35>

MEM_B_DQ<38>MEM_B_DQ<39>MEM_B_DQ<40>MEM_B_DQ<41>MEM_B_DQ<42>MEM_B_DQ<43>

MEM_B_DQ<45>MEM_B_DQ<46>MEM_B_DQ<47>MEM_B_DQ<48>

MEM_B_DQ<51>MEM_B_DQ<52>MEM_B_DQ<53>MEM_B_DQ<54>MEM_B_DQ<55>MEM_B_DQ<56>MEM_B_DQ<57>MEM_B_DQ<58>MEM_B_DQ<59>MEM_B_DQ<60>

MEM_B_DQ<36>

MEM_A_DQ<2>

MEM_A_DQ<12>

MEM_A_DQ<0>MEM_A_DQ<1>

MEM_A_DQ<3>


MEM_A_DQ<6>



MEM_A_DQ<13>

MEM_A_DQ<11>


MEM_A_DQ<16>



MEM_A_DQ<26>

MEM_A_DQ<35>

MEM_A_DQ<21>




MEM_A_DQ<31>MEM_A_DQ<30>MEM_A_DQ<29>


MEM_A_DQ<36>

MEM_A_DQ<34>


MEM_A_DQ<39>


MEM_A_DQ<44>MEM_A_DQ<43>MEM_A_DQ<42>


MEM_A_DQ<47>MEM_A_DQ<48>MEM_A_DQ<49>MEM_A_DQ<50>MEM_A_DQ<51>MEM_A_DQ<52>MEM_A_DQ<53>MEM_A_DQ<54>


MEM_A_DQ<57>MEM_A_DQ<58>MEM_A_DQ<59>MEM_A_DQ<60>MEM_A_DQ<61>MEM_A_DQ<62>MEM_A_DQ<63>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_B_DQ<61>

MEM_B_DQ<63>MEM_B_DQ<62>

7 OF 76

7 OF 121

<E4LABEL>

<SCH_NUM>

<BRANCH>

www.vinafix.vn

VCC

VCC

VCC

VCC

VCC

VCC

VCCST

VCCST

VCCST

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC

RSVD

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

RSVD

RSVD

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VDDQ

VCCIOA_OUT

RSVD

RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

HSW ULT POWER

SYM 12 OF 19

OUT

IN

NCNC

NC

NC

VCCHSIO

VCCHSIO

VCCHSIO

VCCIO

VCCIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL

VCCAPLL

VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3

VCCSUS3

VCC3

VCC3

VCCDSW3_3

VCC1P05

VCC1P05

VCCCLK

VCCCLK

VCCCLK

VCCCLK

VCCCLK

VCCCLK

VCCACLKPLL

VCCSUS3

VCCSUS3

VCCIO

VCCIO

VCCAPLL

DCPSUS4

VCCSUS3

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCCASW

VCC1P05

VCC1P05

VCC1P05

VCC1P05

VCC1P05

DCPSUSBYP

DCPSUSBYP

VCCASW

VCCASW

VCCASW

DCPSUS1

DCPSUS1

VCC3

VCC3

VCCTS1_5

VCCSDIO

VCCSDIO

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI

RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

NC

NCNC

NCNC

NCNC

NC

BI

NCNC

IN

OUT

IN

NCNCNC

NC

NC

OUT

NC

NCNC

NCNCNCNC

IN

NC

Apple Inc.


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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



114mA Max

Max load: 300mA

42mA Max

17mA Max

3mA Max

31mA Max

Powered in DeepSx11mA Max

18mA Max

???mA Max

32A Max

1.4A Max (DDR3: 1.5-1.35V)1.1A Max (LPDDR3: 1.2V)

213mA Max[1]3.3mA Max[1]

1mA Max[1]

40mA Max[1]

473mA Max[1]

185mA Max[1]

29mA Max[1]

0.3mA Max[1]

59mA Max[1]

41mA Max

WF: RSVD on Sawtooth Peak rev 1.0

WF: RSVD on Sawtooth Peak rev 1.0WF: RSVD on Sawtooth Peak rev 1.0

1838mA Max

57mA Max

VCCCLK: 200mA Max

1499mA Max[1]

VCCCLK: 200mA Max

Max load: 300mA

R0802.2:

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

R0800.2:

R0810.2:

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0.Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.

P62

D63

C59

F60

L63

N63

L62

AY50

AY44

AY40

AY35

AR48

AP43

AN33

AJ37

AJ33

AJ31

AH26

B59

AE23

AE22

AC22

E20

A59

W57

U57

E63

P57

M57

M23

L22

K57

K23

J23

H23

G57

G55

G53

G51

G49

G47

G45

G43

G41

G39

G37

G35

G33

G31

G29

G27

G25

G23

F56

F52

F48

F44

F40

F36

F32

F28

F24

E57

E55

E53

E51

E49

E47

E45

E43

E41

E39

E37

E35

E33

E31

E29

E27

E25

E23

C56

C52

C48

C44

C40

C36

C32

C28

C24

AG57

AD57

AB57

F59

V59

U59

P61

P60

N61

N59

T59

N58

L59

J58

AG58

AE60

AE59

AD60

AD59

AD23

AC59

AC58

AB23

AA59

AA23

H59

U0500OMIT_TABLE

2C+GT2HASWELL-ULT

BGA-TSP

CRITICAL

2

1R0802

PLACE_NEAR=U0500.L63:2.54mm

1/20W1%130

MF201

51 67

16

2

1R0860

1/20W

100PLACE_NEAR=U0500.C50:50.8mm

MF201

5%

B18

J15

AH11

AE21

AE20

AC9

AA9

Y8

U8

T9

B11

AG10

P9

N8

AG17

AG16

M9

L10

K9

AH14

AH10

V21

T21

R21

M20

K18

J17

AG8

AG14

AG13

AF9

AE9

Y20

W21

AC20

AA21

A20

W9

V8

K16

K14

K19

J18

J11

H15

H11

AF22

AE8

AG20

AG19

AB8

J13

AH13

AD8

AD10

AE7

U0500

CRITICALOMIT_TABLE


51 67

16 17

17 51

17 51

51 67

2

1 C0899

BYPASS=R0899:U0500:2.54mm402CERM

1UF10%6.3V

21

R0899

1%

MF-LF

5.11

PLACE_NEAR=U0500.AG19:2.54mm

1/20W

201

51 67

2

1 C08950.1UF

CERM402

10V20%

BYPASS=U0500.AE7:6.35mm

2

1C0892

402CERM10V20%

0.1UF

BYPASS=U0500.AG10:6.35mm

2

1C0891


0.1UF

402CERM10V20%

2

1 C0890


1UF

402CERM6.3V10%

21

R0811

MF1/20W

0201

0

5%

21

R0812

MF1/20W

0201

0

5%

21

R0810

201

1/20W

PLACE_NEAR=U0500.L62:38.1mm

43

5%

MF

2

1R0800

PLACE_NEAR=R0810.1:2.54mm

751/20W

MF

1%

201

SYNC_MASTER=J41_MLB SYNC_DATE=04/09/2013

CPU/PCH POWER

CPU_VIDSOUT_RCPU_VIDSCLK_R

CPU_VR_READY

CPU_VIDALERT_R_L

TP_PPVCCIO_S0_CPU

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

CPU_VCCST_PWRGD

PP1V05_S0

CPU_VR_EN

PP1V05_S0

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

PPVCOMP_S0_CPU

PPVMEMIO_S0_CPU

PPVCC_S0_CPU

PPVCC_S0_CPU

CPU_VCCSENSE_P

CPU_PWR_DEBUG

TP_CPU_RSVD_P60TP_CPU_RSVD_P61TP_CPU_RSVD_N59TP_CPU_RSVD_N61

CPU_VIDSCLK

CPU_VIDALERT_L

CPU_VIDSOUT

PP1V05_S0_PCH_VCC_ICC

PP1V05_S0

PP3V3_S5

PP1V05_S0SW_PCH_HSIO

PP1V05_S0_PCH_VCCAPLL_OPI

PP1V05_S0_PCH_VCCACLKPLL

PP1V5_S0SW_AUDIO_HDA

PP3V3_S0

PP1V05_S0

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0SW_PCH_VCCSATA3PLL

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mmPPVOUT_S5_PCH_DCPSUSBYP

PPVRTC_G3H

PP1V05_S0

PP1V05_S0

PP3V3_SUS

PP1V5_S0

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP3V3_S0

PPVOUT_S0_PCH_DCPRTC


PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

8 OF 76

8 OF 121

<E4LABEL>

<SCH_NUM>

<BRANCH>

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

5

10 42

8 10 42 52 62 64

8 10 42 52 62 64

11

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

11 58 62

11

11 12

11 17 58

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44

45 56 59 61 62 64 65 74

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

11 14

11 12

12 13 17 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 14 18 46 57 58 59 62 64

57 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

www.vinafix.vn

SYM 14 OF 19

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

OUT

SYM 15 OF 19

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SYM 16 OF 19

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS_SENSE

VSS

VSS

VSS

Apple Inc.


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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



AP20

AP17

AP10

AN7

AN63

AN60

AN52

AN51

AN49

AN48

AN46

AN45

AN43

AN42

AN40

AN39

AN36

AN35

AN32

AN31

AN23

AN17

AM52

AM31

AM23

AM17

AM1

AL61

AL60

AL57

AL54

AL52

AL51

AL46

AL45

AL40

AL39

AL36

AL33

AL31

AL29

AL26

AL23

AL22

AL20

AL17

AL13

AL10

AK52

AK3

AK23

AJ63

AJ60

AJ58

AJ56

AJ54

AJ52

AJ50

AJ47

AJ45

AJ43

AJ41

AJ39

AJ35

AJ29

AJ27

AJ25

AJ23

AJ14

AJ13

AH57

AH55

AH53

AH51

AH49

AH44

AH42

AH40

AH38

AH36

AH34

AH32

AH30

AH28

AH24

AH22

AH20

AH19

AH17

AG63

AG62

AG61

AG60

AG23

AG21

AG11

AG1

AF18

AF17

AF15

AF14

AF12

AF11

AE58

AE5

AE10

AD63

AD3

AD21

AC61

AB7

AB22

AB20

AB10

AA58

AA1

A56

A52

A48

A44

A40

A36

A32

A28

A24

A18

A14

A11

U0500

CRITICALOMIT_TABLE

HASWELL-ULT

BGA-TSP2C+GT2

2

1R0960PLACE_NEAR=U0500.E62:50.8mm5%

1001/20WMF201

51 67

D31

D30

D29

D27

D26

D25

D23

D21

D2

D18

D14

D12

C57

C39

C38

C27

C25

C20

C18

C14

C11

B60

B56

B52

B48

B44

B40

B4

B36

B32

B28

B26

B24

B20

AY6

AY59

AY57

AY53

AY51

AY4

AY33

AY30

AY26

AY24

AY22

AY18

AY16

AY11

AW60

AW59

AW51

AW50

AW47

AW44

AW42

AW40

AW4

AW37

AW35

AW33

AW24

AW16

AV8

AV59

AV55

AV51

AV49

AV46

AV43

AV41

AV39

AV36

AV34

AV33

AV28

AV24

AV20

AV16

AV14

AU59

AU57

AU55

AU53

AU51

AU33

AU30

AU28

AU26

AU24

AU22

AU20

AU18

AU16

AU1

AT63

AT62

AT61

AT49

AT46

AT43

AT42

AT40

AT37

AT35

AT13

AR52

AR5

AR49

AR43

AR39

AR33

AR31

AR23

AR17

AR15

AR11

AP57

AP54

AP52

AP48

AP39

AP38

AP31

AP3

AP29

AP26

AP23

AP22

U0500

CRITICALOMIT_TABLE

HASWELL-ULT

BGA-TSP2C+GT2

Y63

Y59

Y10

W22

W20

V7

V58

V3

V23

V10

U9

U61

U22

U20

T58

T1

E62

R8

R22

R10

P63

P59

N3

N10

M22

L7

L61

L58

L20

L18

L17

L15

L13

K12

K1

J63

J59

J22

J10

H57

H17

H13

G8

G6

G5

G3

G22

G18

F61

F58

F54

F50

F46

F42

F38

F34

F30

F26

F20

E17

E11

D8

D62

D59

D57

D55

D54

D53

D51

D50

D5

D49

D47

D46

D45

D43

D42

D41

D39

D38

D37

D35

D34

D33

AH46

AH16

U0500

CRITICALOMIT_TABLE

HASWELL-ULT

BGA-TSP2C+GT2


CPU/PCH GROUNDS

CPU_VCCSENSE_N

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Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuffApple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff

2x Bulk nostuff per Harris Beach v1.0 schematic

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603 CPU VDDQ DECOUPLING

CPU VCC Decoupling

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

2

1 C1000CRITICAL

4VX6S0402

20%10UF

2

1 C105010UF

0402-1CERM-X5R6.3V20%

2

1 C105110UF

CERM-X5R6.3V20%

0402-12

1 C1052

CERM-X5R0402-1

10UF6.3V20%

2

1 C105310UF

0402-1CERM-X5R6.3V20%

2

1 C1054

CERM-X5R

20%

0402-1

10UF6.3V 2

1 C105510UF

0402-1CERM-X5R6.3V20%

2

1 C1040

6.3VCERM402-LF

2.2UF20%

2

1 C1041

402-LF

6.3VCERM

2.2UF20%

2

1 C1042

6.3VCERM402-LF

20%2.2UF

2

1 C1043

6.3V20%2.2UF

402-LFCERM

2

1 C1060

TANT2V20%270UF

CASE-B2-SM

2

1 C1061NO STUFF

CASE-B2-SMTANT2V20%270UF

2

1 C1001CRITICAL

20%4VX6S0402

10UF

2

1 C1002CRITICAL

4VX6S

10UF20%

04022

1 C1003

0402

4VX6S

10UF20%

NO STUFF

2

1 C1004CRITICAL

0402

4VX6S

10UF20%

2

1 C1005NO STUFF

10UF

0402

4VX6S

20%2

1 C1006

0402

4VX6S

10UF20%

NO STUFF

2

1 C1007CRITICAL

10UF

0402

4VX6S

20%2

1 C1008

0402

4VX6S

10UF20%

NO STUFF

2

1 C1009NO STUFF

20%

0402

4VX6S

10UF

2

1 C1010CRITICAL

0402

4VX6S

10UF20%

2

1 C1011

0402

4VX6S

10UF20%

NO STUFF

2

1 C1012CRITICAL

0402

4VX6S

10UF20%

2

1 C101310UF

0402

4VX6S

20%

NO STUFF

2

1 C1014CRITICAL

0402

4VX6S

10UF20%

2

1 C1015

4VX6S

20%10UF

0402

NO STUFF

2

1 C1016CRITICAL

4V20%

0402X6S

10UF

2

1 C1017CRITICAL

20%10UF

X6S4V

04022

1 C1018CRITICAL

4V20%

0402X6S

10UF

2

1 C101920%4VX6S

10UF

0402

NO STUFF

2

1 C102020%

X6S4V

10UF

0402

NO STUFF

2

1 C1021CRITICAL

0402

4VX6S

10UF20%

2

1 C1084CRITICAL

4VX6S

20%10UF

04022

1 C1083CRITICAL

4VX6S

20%10UF

04022

1 C1082

4VX6S

20%10UF

0402

NO STUFF

2

1 C108120%

0402X6S4V

10UF

NO STUFF

2

1 C1080NO STUFF

4VX6S

10UF20%

04022

1 C1079

4VX6S

20%10UF

0402

NO STUFF

2

1 C1078NO STUFF

10UF20%

X6S4V

04022

1 C1077CRITICAL

20%

X6S4V

10UF

04022

1 C1076CRITICAL

4VX6S

10UF20%

04022

1 C1075NO STUFF

4VX6S

10UF20%

04022

1 C107410UF20%4VX6S0402

NO STUFF

2

1 C1073NO STUFF

X6S4V20%

0402

10UF

2

1 C107210UF

X6S4V20%

0402

NO STUFF

2

1 C1071NO STUFF

4VX6S

10UF20%

04022

1 C1070NO STUFF

20%

0402

10UF

X6S4V

2

1 C1097NO STUFF

0402

20%10UF

X6S4V2

1 C1096

0402

4VX6S

20%10UF

NO STUFF

2

1 C1095

0402

20%10UF

X6S4V

NO STUFF

2

1 C1094

0402

20%10UF

X6S4V

NO STUFF

2

1 C109310UF

0402

20%

X6S4V

NO STUFF

2

1 C1092NO STUFF

0402

10UF20%

X6S4V2

1 C1091NO STUFF

0402

4V20%

X6S

10UF

2

1 C1090NO STUFF

0402

20%10UF

X6S4V2

1 C1089CRITICAL

0402

20%10UF

X6S4V2

1 C1088CRITICAL

0402

20%10UF

X6S4V2

1 C1087NO STUFF

0402

20%10UF

X6S4V2

1 C1086NO STUFF

10UF

0402

20%4VX6S2

1 C1085NO STUFF

10UF

0402

20%

X6S4V

2

1 C1038NO STUFF

0402

10UF20%4VX6S2

1 C1037NO STUFF

0402

4VX6S

10UF20%

2

1 C1036NO STUFF

4V

0402X6S

20%10UF

2

1 C1035NO STUFF

0402

20%10UF4VX6S2

1 C1034NO STUFF

X6S0402

20%4V

10UF

2

1 C1033NO STUFF

0402

20%4VX6S

10UF

2

1 C1032

0402

10UF20%

X6S4V

NO STUFF

2

1 C1029

0402

20%4VX6S

NO STUFF

10UF

2

1 C109A

0402

10UF20%4VX6S

NO STUFF

2

1 C1099NO STUFF

0402X6S

20%10UF4V2

1 C1098NO STUFF

0402

4VX6S

20%10UF

2

1 C107BNO STUFF

20%

X6S4V

10UF

04022

1 C107A

4V20%10UF

X6S0402

NO STUFF

2

1 C1069NO STUFF

10UF

X6S4V20%

04022

1 C1068NO STUFF

0402X6S4V

10UF20%

2

1 C108FNO STUFF

20%4VX6S0402

10UF

2

1 C1067NO STUFF

0402

4VX6S

20%10UF

2

1 C108ENO STUFF

20%4VX6S

10UF

0402

2

1 C1066NO STUFF

0402

10UF20%4VX6S

2

1 C108DNO STUFF

X6S4V20%

0402

10UF

2

1 C108CNO STUFF

X6S4V20%10UF

0402

2

1 C1065NO STUFF

0402

10UF4V20%

X6S

2

1 C1028NO STUFF

10UF

0402

4VX6S

20%2

1 C102710UF

0402

4VX6S

20%

NO STUFF

2

1 C1049

0402

NO STUFF

4V20%

X6S

10UF

2

1 C1048

0402

4V20%

X6S

10UF

NO STUFF

2

1 C102610UF4VX6S0402

20%

NO STUFF

2

1 C1047

0402X6S

10UF4V20%

NO STUFF

2

1 C1025NO STUFF

10UF20%4VX6S0402

2

1 C1024NO STUFF

10UF

0402

4VX6S

20%

2

1 C1046NO STUFF

0402X6S

10UF4V20%

2

1 C1045NO STUFF

0402

10UF4V20%

X6S

2

1 C1023NO STUFF

0402

4VX6S

10UF20%

2

1 C1022NO STUFF

10UF

0402

20%4VX6S

2

1 C1044NO STUFF

0402

20%

X6S4V

10UF

2

1 C1039NO STUFF

0402

10UF

X6S4V20%

2

1 C1064NO STUFF

X6S0402

10UF20%4V

2

1 C108B

X6S

20%4V

0402

10UF

NO STUFF

2

1 C1063

0402X6S4V

10UF20%

NO STUFF

2

1 C108ANO STUFF

20%

X6S4V

10UF

0402

2

1 C106210UF20%4VX6S

NO STUFF

0402

2

1 C109FNO STUFF

X6S

10UF4V20%

04022

1 C109ENO STUFF

X6S4V20%10UF

0402

2

1 C1059NO STUFF

10UF

0402

20%4VX6S2

1 C1058NO STUFF

0402

10UF4VX6S

20%

2

1 C109DNO STUFF

10UF20%4VX6S0402

2

1 C1057

0402

20%

NO STUFF

4VX6S

10UF

2

1 C109CNO STUFF

X6S

10UF20%4V

0402

2

1 C1056NO STUFF

0402

10UF4VX6S

20%

2

1 C109BNO STUFF

X6S4V

0402

10UF20%

3 2

1 C1031CRITICAL

470UF-0.0045OHM

SM

2.5VPOLY-TANT

20%

2

1 C1030

0402

4VX6S

10UF20%

NO STUFF

2

1 C104CNO STUFF

10UF

0402

4VX6S

20%2

1 C104D

4V

NO STUFF

20%

X6S

10UF

04022

1 C104E20%10UF

X6S4V

0402

NO STUFF

2

1 C104FNO STUFF

20%10UF

X6S4V

04022

1 C106ANO STUFF

20%10UF

X6S4V

04022

1 C106B20%10UF

X6S4V

0402

NO STUFF

2

1 C106C20%10UF

X6S4V

0402

NO STUFF

2

1 C106D

0402

4VX6S

10UF20%

NO STUFF

2

1 C106E

0402

4VX6S

10UF20%

NO STUFF

2

1 C105ANO STUFF

20%10UF

X6S4V

04022

1 C105BNO STUFF

20%10UF

X6S4V

04022

1 C105CNO STUFF

4V20%10UF

X6S0402

2

1 C105D20%10UF

X6S4V

0402

NO STUFF

2

1 C105E

0402

4VX6S

10UF20%

NO STUFF

2

1 C105FNO STUFF

0402

4VX6S

10UF20%

2

1 C104ANO STUFF

10UF

0402

4VX6S

20%2

1 C104BNO STUFF

0402

4VX6S

10UF20%

SYNC_DATE=01/08/2013SYNC_MASTER=WILL_J43

CPU Decoupling

PPVMEMIO_S0_CPU

PPVCC_S0_CPU

10 OF 121

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<SCH_NUM>

<E4LABEL>

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8 42

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(PCH 1.05V CORE PWR)PCH VCC BYPASS

(PCH 1.05V SATA3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS(PCH 1.05V USB3 PLL PWR)

PCH VCCSATA3PLL FILTER/BYPASS

as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0

PCH VCCSUSHDA BYPASS

(PCH 3.3V/1.8V SDIO PWR)PCH VCCSDIO BYPASS

(PCH 3.3V/1.5V HDA PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 3.3V SPI PWR)PCH VCCSPI BYPASS

(PCH 3.3V SUSPEND PWR)PCH VCCSUS3_3 BYPASS

(PCH 3.3V DSW PWR)

(PCH 1.05V ACLK PLL PWR)PCH VCCACLKPLL FILTER/BYPASS

PCH VCCCLK FILTER/BYPASS(PCH 1.05V VCCCLK PWR)

PCH VCCIO BYPASS(PCH 1.05V USB2 PWR)

(PCH 3.3V THERMAL PWR)PCH VCC3_3 BYPASS

(PCH 3.3V GPIO/LPC PWR)PCH VCC3_3 BYPASS

PCH VCCCLK BYPASS(PCH 1.05V CLK PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V ME CORE PWR)PCH VCCASW BYPASS

PCH VCCHSIO BYPASS(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCDSW3_3 BYPASS

41mA Max

83mA Max 42mA Max

??mA Max

31mA Max

57mA Max

PCH OPI VCCAPLL FILTER/BYPASS

??mA Max

2

1C1202

BYPASS=U0500.Y8:6.35mm

CERM402

0.1UF20%10V

NO STUFF

21

L1280

0603

2.2UH-240MA-0.221OHM

CRITICALNO STUFF

21

R12800

MF-LF402

5%1/16W

2

1C1295

0805-1

47UF20%4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

2

1C1296

0805-1

47UF20%4V

CERM-X5R


NO STUFF

2

1C1290


CERM-X5R4V20%

47UF

0805-12

1C1291

0805-1

47UF20%4V

CERM-X5R


NO STUFF

2

1C1280

BYPASS=U0500.AA21:12.7mm

0805-1

47UF20%4V

CERM-X5R

NO STUFF

2

1C1281

CERM-X5R4V20%

47UF


0805-1

NO STUFF

2

1C1275

BYPASS=U0500.J18:12.7mm

4V20%

47UF

0805-1CERM-X5R 2

1C1276

0805-1

47UF20%4V

CERM-X5R


2

1C1270

CERM-X5R

BYPASS=U0500.A20:12.7mm

0805-1

47UF20%4V

2

1C1271

CERM-X5R4V20%

47UF

0805-1


2

1C1200

6.3V10%

402CERM

1UF

BYPASS=U0500.AH10:6.35mm

NO STUFF

2

1C1210

BYPASS=U0500.AH14:6.35mm

6.3V10%1UF

CERM402

2

1C1214

BYPASS=U0500.K14:6.35mm

CERM402

10V20%

0.1UF

2

1C1206

BYPASS=U0500.AH11:6.35mm402

CERM6.3V

1UF10%

2

1C1264

402CERM


1UF10%

6.3V

2

1C12611UF

CERM402

10%6.3V

BYPASS=U0500.L10:6.35mm

2

1 C1262

0402-1

20%10UF

CERM-X5R

BYPASS=U0500.M9:6.35mm

6.3V

2

1C1266

6.3VCERM402

1UF10%


2

1C1255


6.3V20%

603X5R

10UF

2

1C1250


X5R-CERM-16.3V20%

22UF

603

NO STUFF

2

1 C1256


6.3V

402

10%1UF

CERM 2

1 C12571UF


6.3V10%

402CERM

2

1 C1251


6.3V10%

402CERM

1UF

2

1C1267

6.3VCERM402

1UF10%

BYPASS=U0500.R21:6.35mm

2

1C1204

X5R-CERM-16.3V20%

22UF

603BYPASS=U0500.AC9:12.7mm

2

1C121222UF

20%6.3V

X5R-CERM-1

BYPASS=U0500.V8:12.7mm603

2

1C1208

BYPASS=U0500.U8:6.35mm402

CERM6.3V

1UF10%

2

1C1260

BYPASS=U0500.K9:6.35mm

1UF

402

10%6.3VCERM

2

1 C1277

10V10%

402X5R

1UF


21

L12752.2UH-240MA-0.221OHM

0603

CRITICAL

2

1 C1297

10V10%

402X5R

1UF


21

L1295CRITICAL

0603

2.2UH-240MA-0.221OHM

2

1 C1292

10V10%

402X5R

1UF


21

L12902.2UH-240MA-0.221OHM

CRITICAL

0603

21

R12750

1/16W5%

402MF-LF

2

1 C12721UF

X5R402

10%10V


21

L1270

0603

CRITICAL

2.2UH-240MA-0.221OHM21

R1270

5%

402MF-LF1/16W

0

2

1 C12821UF

X5R402

10%10V



PCH Decoupling

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05VMIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

MIN_NECK_WIDTH=0.075 MMVOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCC_ICC


MIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCCACLKPLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCC_ICC_RMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05VMIN_NECK_WIDTH=0.075 MMMIN_LINE_WIDTH=0.2 MMPP1V05_S0SW_PCH_VCCSATA3PLL


PP1V05_S0

VOLTAGE=1.05VMIN_NECK_WIDTH=0.075 MMMIN_LINE_WIDTH=0.2 MMPP1V05_S0SW_PCH_VCCUSB3PLL


PP1V05_S0

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MMPP1V05_S0_PCH_VCCACLKPLL_R

PP1V05_S0PP3V3_S0

PP3V3_S0 PP1V05_S0

PP3V3_SUS

PP3V3_SUS

PP3V3_S5


PP3V3_S0

PP3V3_SUS

PP1V05_S0

<BRANCH>

<SCH_NUM>

<E4LABEL>

12 OF 121

11 OF 76

8

8

8 12

8 12

8 11 58 62

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 14

8 11 58 62

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74 6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

8 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 17 58

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8 11 14 18 46 57 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

www.vinafix.vn

IN IN

IN

IN

IN

IN

IN

OUT

BI

OUT

OUT

OUT

IN

IN

NC

NC

NC

IN

OUT

RSVD

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1

RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD

HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34

SATA1GP/GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

OUT

IN

IN

OUT

OUT

IN

IN

NC

NC

OUT

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

TESTLOW

TESTLOW

TESTLOW

DIFFCLK_BIASREF

RSVD

RSVD

SYM 6 OF 19

CLOCK SIGNALS

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

NCNC

OUT

OUT

OUT

IN

OUT

Apple Inc.


124578

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A


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

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6 3



(IPD)

SSD Lane 0

SSD Lane 2

PCIe Port assignments:

SSD Lane 3

(IPD-PWROK)

(IPD-PLTRST#)

(IPU)

(IPD)

Secondary HDD/SSD

Unused

Primary HDD/SSD

Reserved: ODD

SATA Port assignments:

SSD Lane 1

(IPD-PLTRST#)

(IPU)

(IPU)

16 64 69

21R1345MF 2015% 1/20W

100K

21R1375 100KMF5% 1/20W 201

16

16

16

16

21R13431/20W MF 2015%

100K

16 64 69

16 64 69

16 64 69

16

61 65 69

61 65 69

61 65 69

21R1312PLACE_NEAR=U0500.AU8:1.27mm

1/20W5% MF33

201

21R1311201

PLACE_NEAR=U0500.AV11:1.27mmMF5% 1/20W

33

61 65 69

21R1310PLACE_NEAR=U0500.AW8:1.27mm

1/20W5% 201MF33

17

2

1R1302

MF201

5%1/20W

330K

2

1R13011M

MF201

5%1/20W

2

1C1300

10V10%

402X5R

1UF

2

1R1300

1/20W5%

201MF

20K

2

1 C1303

10V10%1UF

402X5R

2

1R13035%

201

20K1/20WMF

6 16 64 67

2

1R1370


1%1/20W

3.01K

MF201

30 67

AV6

U3

D17

C15

B17

A15

C17

B14

A17

B15

E5

H6

H8

H5

F5

J6

J8

J5

C12

A12

AC1

V6

U1

V1

AY5

AW5

AU7

L11

K10

AV2

AL11

AC4

AU62

AD62

AE61

AD61

AE62

AE63

AV7

AU6

AY8

AV11

AU11

AU12

AY10

AU8

AV10

AW10

AW8

U0500

BGA-TSP

HASWELL-ULT2C+GT2

OMIT_TABLECRITICAL

30 67

30 64 67

30 64 67

30 67

30 67

30 64 67

30 64 67

30 67

B25

A25

C35

C34

AL8

AK8

M21

K21

T2

U5

N1

AD1

Y5

U2

C26

A37

B39

C37

B42

A41

C42

B37

A39

B38

C41

B41

C43

AP15

AN15

A35

B35

U0500

BGA-TSP

HASWELL-ULT2C+GT2

CRITICALOMIT_TABLE

30 67

30 67

30 67

30 64 67

30 64 67

30 64 67

30 64 67

12 29

29 64 69

29 64 69

61 65 69

12 31

32 69

32 69

25 69

25 69

12 27

30 64 67

30 64 67

12 30

2

1R1380

1/20W


1%

201MF

3.01K

17 69

17 69

21R1390 10KMF1/20W5% 20121R1391MF 2011/20W

10K5%21R1392

201MF1/20W10K

5%21R13935%

10K1/20W MF 201

17

17

17

21R1313201


331/20W5% MF

21R13411/20W5% 201MF

100K

21R1344 100KMF 2015% 1/20W

21R13401/20W5% 201MF

100K

21R13425% MF 2011/20W

100K

PCH Audio/JTAG/SATA/CLKSYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB

SSD_CLKREQ_L

PCIE_CLK100M_SSD_PPCIE_CLK100M_SSD_N

TBT_CLKREQ_L

PCIE_CLK100M_TBT_PPCIE_CLK100M_TBT_N

PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_AP_N

CAMERA_CLKREQ_L

PCIE_CLK100M_CAMERA_PPCIE_CLK100M_CAMERA_N

ENETSD_CLKREQ_L

TP_PCIE_CLK100M_ENETSDPTP_PCIE_CLK100M_ENETSDN

NC_PCIE_CLK100M_FWN

FW_CLKREQ_L

NC_PCIE_CLK100M_FWP

PCH_SATA_RCOMP

PCH_CLK24M_XTALOUTPCH_CLK24M_XTALIN

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_SDIN0

NC_RTC_CLK32K_RTCX2

TP_PCH_I2S1_TXDTP_PCH_I2S1_SFRM

XDP_PCH_TCK

TP_PCH_I2S1_SCLK

XDP_CPUPCH_TRST_L

SSD_CLKREQ_LTBT_CLKREQ_L

AP_CLKREQ_LFW_CLKREQ_L

CAMERA_CLKREQ_LENETSD_CLKREQ_L

PCH_SATALED_L

NC_HDA_SDIN1

XDP_SSD_PCIE0_SEL_L

PCH_INTRUDER_L

PCIE_SSD_D2R_P<0>PCIE_SSD_D2R_N<0>

PCH_TESTLOW_C34

HDA_SDOUT_R

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_N<3>PCIE_SSD_R2D_C_P<3>



PCIE_SSD_R2D_C_P<1>PCIE_SSD_R2D_C_N<1>

TP_ITPXDP_CLK100MNTP_ITPXDP_CLK100MP

LPC_CLK24M_SMC_R

PCH_TESTLOW_AK8PCH_TESTLOW_AL8

PCH_CLK32K_RTCX1

PCIE_SSD_R2D_C_P<0>

PCH_TESTLOW_C35

HDA_RST_R_L

PP3V3_S0

LPC_CLK24M_LPCPLUS_R

PCH_DIFFCLK_BIASREF

PCH_SATALED_L

PP1V05_S0_PCH_VCCACLKPLL

PPVRTC_G3H

PCH_INTVRMEN

PCH_SRTCRST_L

XDP_PCH_TDO

XDP_PCH_TMS

XDP_PCH_TDI

PCIE_SSD_R2D_C_N<0>

PP1V05_S0SW_PCH_VCCSATA3PLL

PCIE_SSD_D2R_N<2>PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_P<2>

XDP_SSD_PCIE3_SEL_LXDP_SSD_PCIE2_SEL_LXDP_SSD_PCIE1_SEL_L

PCH_JTAGX

HDA_SYNC

HDA_BIT_CLK

RTC_RESET_L

HDA_SDOUT

HDA_RST_L

12 OF 76

<BRANCH>

<SCH_NUM>

<E4LABEL>

13 OF 121

12

64

12

64

69

69

12 30

12 27

12 29

12

12 31

12

12

64

17 69

69

8 11 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61 62

64 65 74

12

8 11

8 13 17 62 64

8 11

www.vinafix.vn

IN

OUT

IN

OUT

OUT

IN

IN

IN

IN

OUT

OUT

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

OUT

OUT

OUT

OUT

BI

IN

IN

OUT

OUT

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79

PIRQD*/GPIO80

PIRQA*/GPIO77

PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN

DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

OUT

BI

BI

BI

BI

BI

BI

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

NC

08

NC

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



R1400 kept for debug purposes.

(IPU)

(IPD-PLTRST#)

(IPD-DeepSx)

(IPD-DeepSx)

(IPU)

(IPU)

(IPD-PLTRST#)

U1420 ensures signal will only be high in S0.SLP_S0# can be driven high outside of S0

SLP_S0# Isolation

59 64

13 18 37

39

39

15 16 18

13 17

13 17

16 17 37

17 37 64

13 42 59

13 17 18 37 59

AJ5

AC3

AG2

AV4

AE6

AK2

AG4

AM5

AP4

AP5

AJ6

AT4

AF3 AJ7

AL5

AW6

AL7

AG7

AY7

AW7

AV5

V5

AN4

AB5

AJ8

U0500

BGA-TSP2C+GT2

HASWELL-ULT

CRITICALOMIT_TABLE

13 18 29 36 37 59

13 37 59

38 69

37 46 64

13 37 46 64

13 29 31 64

2

1R14515%

201

1/20WMF

100K

37

2

1R14505%

201

1/20WMF

330K

13 56

56

AD4

N2

N4

P4

U6

U7

L3

L4

L1

R5

C6

D6

A9

B8

A8

D11

D9

A6

B6

C8

C9

B9

B5

C5

U0500HASWELL-ULT

OMIT_TABLECRITICAL

BGA-TSP2C+GT2

13 60

25 67

18 25 67

18 25 67

25 67

18 28

18

18

18 28

25

18 25

60

21R14465% 2011/20W MF

100K21R1445

5% 2011/20W MF100K

21R14425% 2011/20W MF

100K21R1443

5% 2011/20W MF100K

21R14415% 2011/20W MF

10K

2

1R14005%0

0201

1/20WMF

NO STUFF

21R14405% 2011/20W MF

100K

13 25 27

13 37

13 64

13 64

13 64

13 28

13 64

13 64

13 37

21R14555% 2011/20W MF

10K

21R14105% 2011/20W MF

10K

21R14475% 2011/20W MF

100K21R1448

5% 2011/20W MF100K

21R14495% 2011/20W MF

100K

21R14315% 2011/20W MF

100K21R1430

5% 2011/20W MF100K

37 38

13 59 61 65

21R14055% 2011/20W MF

1K

21R14525% 2011/20W MF

10K

21R14605% 2011/20W MF

100K21R1461

5% 2011/20W MF100K

21R14625% 2011/20W MF

100K

21R14645% 2011/20W MF

100K21R1463

5% 2011/20W MF100K

13 16 37

4

6

53

1

2

U1420

CRITICAL74LVC1G08SOT891

2

1 C1420

0201X5R-CERM

10%10V

0.1UF

PCH PM/PCI/GFXSYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB

PP3V3_S0

PM_SLP_SUS_L

EDP_BKLT_ENEDP_PANEL_PWR

AUD_IP_PERIPHERAL_DET

PM_SLP_S0_LPM_SLP_S3_LPM_SLP_S4_L

EDP_BKLT_EN

PM_SLP_S0_LPCH_PM_SLP_S0_L

PP3V3_S0

EDP_BKLT_PWM

TP_PCH_SLP_WLAN_L

PM_BATLOW_L

PM_PWRBTN_L

PP3V3_S5

AUD_PWR_ENAUD_IPHS_SWITCH_EN

ENET_LOW_PWRDP_AUXCH_ISOL_LODD_PWR_EN_L

AUD_I2C_INT_L

TBT_EN_CIO_PWR_LSMC_RUNTIME_SCI_L

PM_SLP_S5_L

PM_CLKRUN_L

PCIE_WAKE_L

EDP_PANEL_PWR

PCH_DSWVRMEN

PM_DSW_PWRGD

PM_CLKRUN_L

LPC_PWRDWN_L

PM_SYSRST_L

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PM_PCH_PWROK

PLT_RESET_L

PM_RSMRST_L

PM_PWRBTN_L

SMC_ADAPTER_EN

PM_BATLOW_L

ODD_PWR_EN_L

AUD_PWR_ENAUD_IPHS_SWITCH_EN

ENET_LOW_PWRDP_AUXCH_ISOL_L

AUD_I2C_INT_LAUD_IP_PERIPHERAL_DETSMC_RUNTIME_SCI_LTBT_EN_CIO_PWR_L

NC_PCI_PME_L

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_DDC_DATA

PCIE_WAKE_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

PM_SLP_S4_L

PM_SLP_S3_L

PPVRTC_G3H

DP_INT_HPD

DP_TBTSNK0_HPD

DP_TBTSNK1_DDC_CLK

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P


TP_PM_SLP_A_L


DP_TBTSNK1_HPD

PCH_SUSACK_L

PCH_SUSWARN_L

14 OF 121

<E4LABEL>

<SCH_NUM>

<BRANCH>

13 OF 76

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

13 42 59

13 56

13 60

13 64

13 18 37

13 17 18 37 59

13 18 29 36 37 59

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

13 37

13 16 37

8 11 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

13 59 61 65

13 64

13 64

13 28

13 64

13 64

13 25 27

13 37

13 37 59

13 37 46 64

13 29 31 64

64

8 12 17 62 64

www.vinafix.vn

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2

LAD3

LAD1

SPI_CLK

LAD0 SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

OUT

IN

IN

IN

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

PCIE_RCOMP

PCIE_IREF

RSVD

RSVD

PETP1/USB3TP2

PETN1/USB3TN2

PERP1/USB3RP2

PERN1/USB3RN2

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

PERN2/USB3RN3

PERP2/USB3RP3

PETN2/USB3TN3

PETP2/USB3TP3

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42

OC3*/GPIO43

RSVD

RSVD

USBRBIAS*

USBRBIAS

USB3TP1

USB3TN1

USB3RP1

USB3RN1

USB3TP0

USB3TN0

USB3RP0

USB3RN0

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB

PCI-E

SYM 11 OF 19

IN

IN

NCNC

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

NCNC

BI

BI

BI

IN

BI

BI

BI

BI

BIOUT

BI

BI

OUT

BI

BI

BI

BI

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

BI

OUT

BI

BI

IN

BI

BI

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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPU)

Otherwise, 100k pull-up to 3.3V SUS required.

Ext A (SS)

SD Card Reader

(IPD)

Reserved: Camera

Trackpad

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU/IPD)

(IPU/IPD)

(IPU)

(IPU/IPD)

Reserved: SD (HS)

IR

BT

Ext B (LS/FS/HS)

Ext A (LS/FS/HS)

USB Port Assignments:

Ext B (SS)

Camera

AirPort

Reserved: FireWire

Thunderbolt lane 0

USB3 Port Assignments:

PCIe Port Assignments:

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

(& Ethernet if combo)

Unused

SML1ALERT# pull-up not provided on thispage, may be wire-ORed into other signals.

AA2

AA4

AF1

Y6

AC2

Y4

Y7

AA3

AH3

AU3

AU4

AK1

AN1

AL2

AH1

AP2

AN2

AV12

AW11

AY12

AW12

AU14

AF4

AD2

AF2

U0500HASWELL-ULT

OMIT_TABLE

BGA-TSP2C+GT2

CRITICAL

25 69

21R15802011/20W MF5%

100K21R1581

201MF1/20W5%100K

14 16 35

14 16 61 65

14 16

39

14 16

25 69

14 64

25 69

25 69

25 69

25 69

25 69

25 69

25 69

25 69

34 65 68

34 65 68

34 65 68

34 65 68

32 69

32 69

32 69

32 69

29 69

29 69

AJ10

AJ11

A33

B34

B33

C33

F18

H20

E18

G20

AP13

AN11

AN13

AL15

AT10

AP8

AT7

AM8

AR13

AP11

AM13

AM15

AR10

AR8

AR7

AN8

E15

E13

AN10

AM10

A21

C21

A23

C22

A29

B30

A31

C31

B22

B21

B23

C23

B29

C29

B31

C30

F6

G10

E8

E10

G13

F11

G15

F17

E6

H10

F8

F10

F13

G11

F15

G17

A27

B27 AV3

AH2

AT1

AL3

U0500

CRITICAL

HASWELL-ULT

BGA-TSP2C+GT2

OMIT_TABLE

29 64 69

29 64 69

2

1R1500

1/20W

PLACE_NEAR=U0500.A27:2.54mm

1%

MF201

3.01K

61 65 68

61 65 68

61 65 68

61 65 68

35 68

25 69

35 68

35 68

35 68

2

1R1570PLACE_NEAR=U0500.AJ10:2.54mm

MF1/20W1%

201

22.6

36 64 68

36 64 68

64

25 69

64

29 68

29 68

61 65 68

61 65 68 25 69

35 68

35 68

37 46 64 69

37 46 64 69

37 46 64 69

37 46 64 69

37 46 64 69

21R1543 33MF 2015% 1/20W

21R1542 335% MF1/20W 201

25 69

21R15441/20W5% 201MF

33

21R1540 33MF 2011/20W5%21R1541 33MF 2015% 1/20W

46 69

46 69

32 37 40 43 44 64 69 73

25 69

32 37 40 43 44 64 69 73

40 69

40 69

16 19 25 40 56 69

16 19 25 40 56 69

46 69

46 69

25 69

14

14

21R1591 100K5% MF1/20W 201

21R15492011/20W MF5%

1K

21R1590201MF1/20W5%

100K

21R15482011/20W MF5%

1K

21R1582201MF1/20W5%

100K21R1583

1/20W5% MF 201100K

PCH PCIe/USB/LPC/SPI/SMBusSYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013

LPC_FRAME_L

SML_PCH_0_DATA

SMBUS_SMC_1_S0_SCLSMBUS_SMC_1_S0_SDA

XDP_USB_EXTD_OC_LXDP_USB_EXTC_OC_LXDP_USB_EXTB_OC_LXDP_USB_EXTA_OC_L

SPI_IO<2>

SPI_IO<3>

SPI_MISO

SPI_MOSI_R

LPC_AD_R<3>

LPC_FRAME_R_L

PCIE_CAMERA_R2D_C_P

SPI_CS0_R_L

TP_SPI_CS1_L

TP_SPI_CS2_L

PCH_USB_RBIAS

PCIE_TBT_D2R_N<0>

NC_CLINK_CLK

NC_CLINK_RESET_L

NC_CLINK_DATA

SMBUS_PCH_CLKSMBUS_PCH_DATA

SML_PCH_0_CLK

LPC_AD<3>

LPC_AD<1>LPC_AD<0>

SPI_CLK_R

USB3_SD_R2D_C_P

NC_PCIE_FW_D2RN

PCIE_AP_R2D_C_P

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<3>PCIE_TBT_D2R_P<3>

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_PPCIE_CAMERA_D2R_N


PCIE_TBT_R2D_C_N<1>PCIE_TBT_R2D_C_P<1>




PCIE_AP_D2R_P

PCIE_AP_R2D_C_N

NC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CP

USB3_SD_D2R_NUSB3_SD_D2R_P

USB3_SD_R2D_C_N

USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_PUSB3_EXTA_R2D_C_N

USB3_EXTB_D2R_NUSB3_EXTB_D2R_P

USB3_EXTB_R2D_C_N

USB_EXTA_N

NC_USB_SDNNC_USB_SDP

NC_USB_CAMERAPNC_USB_CAMERAN

TP_USB_5P

PCH_SMBALERT_L

PCIE_AP_D2R_N

USB3_EXTB_R2D_C_P

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_D2R_P<0>

USB_EXTB_N

USB3_EXTA_D2R_P

NC_USB_IRN

LPC_AD_R<1>LPC_AD_R<2>

NC_PCIE_FW_R2D_CN

USB_BT_P

TP_USB_5N

USB_TPAD_PUSB_TPAD_N

NC_USB_IRP

USB_BT_N

USB_EXTB_P

USB_EXTA_P

PCH_PCIE_RCOMPPP1V05_S0SW_PCH_VCCUSB3PLL

PCH_SML1ALERT_L

LPC_AD<2>

LPC_AD_R<0>

WOL_EN

XDP_USB_EXTA_OC_LXDP_USB_EXTB_OC_LXDP_USB_EXTC_OC_L

WOL_EN

SPI_IO<3>

PCH_SMBALERT_L

SPI_IO<2>

XDP_USB_EXTD_OC_L

PP3V3_SUSPP3V3_SUS

14 OF 76

15 OF 121

<E4LABEL>

<SCH_NUM>

<BRANCH>

68

64

64

64

64

64

64

64

64

64

64

14

64

8 11

14 16 35

14 16 61 65

14 16

14 64

14

14

14

14 16

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

www.vinafix.vn

IN

OUT

BI

BI

OUT

IN

IN

IN

IN

OUT

OUT

SERIRQ

THRMTRIP*

RCIN*/GPIO82

PCH_OPI_COMP

RSVD

RSVD

GSPI0_CS*/GPIO83

GSPI0_MISO/GPIO85

GSPI0_CLK/GPIO84

GSPI1_CLK/GPIO88

GSPI1_CS*/GPIO87

GSPI0_MOSI/GPIO86

GSPI_MOSI/GPIO90

GSPI1_MISO/GPIO89

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RXD/GPIO0

UART0_CTS*/GPIO94

UART0_RTS*/GPIO93

UART1_CTS*/GPIO3

UART1_RST*/GPIO2

UART1_TXD/GPIO1

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C0_SDA/GPIO4

I2C1_SCL/GPIO7

SDIO_CMD/GPIO65

SDIO_CLK/GPIO64

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D0/GPIO66

SDIO_D3/GPIO69

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

GPIO17

GPIO16

GPIO24

GPIO28

GPIO27

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO47

GPIO44

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO25

GPIO14

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0*/GPIO33

DEVSLP1*/GPIO38

SDIO_POWER_EN/GPIO70

DEVSLP2*/GPIO39

SPKR/GPIO81

SYM 10 OF 19

CPU/MISC

GPIO

LPIO

OUT

IN

IN

IN

IN

BI

BI

BI

OUT

NCOUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

OUT

BI

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

BI

BI

BI

IN

OUT

BI

OUT

OUT

OUT

IN

TABLE_BOMGROUP_ITEM

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

Pull-up on TBT page

TBTLC for CR, S0 for RR

(IPD)

(IPD)

(IPD-RSMRST#)

(IPD-DeepSx)

Requires connection to SMC via 1K series R(IPD-PLTRST#)

Pull-up/down on chipset support page (depends on TBT controller)Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

GPIO12:

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

(IPD-PLTRST#)

(IPD-PLTRST#)

R1616 should also be stuffed ifplatform does not use SD card

21R16521/20W5% 201MF

10K

21R1668MF 2015% 1/20W

100K21R1669

MF 2015% 1/20W100K

21R1672MF 2015%

100K1/20W

21R1674MF 2015% 1/20W

100K21R1673

MF 2015%100K

1/20W

21R1675MF 2015% 1/20W

100K

21R1676MF 2015% 1/20W

100K

21R1678 100K1/20W5% 201MF

21R1677MF 2015% 1/20W

100K

21R1679 100K1/20W5% 201MF

2

1R16395%

1/20WMF201

100K

21R16411/20W5% MF

1K201

NO STUFF

21R16295% 1/20W MF

100K201

2

1R1621

201MF

5%100K1/20W

13 15 16 18

18 27

18 25

15 37 46 64

29

15 29

2

1R1671

MF1/20W

100K5%

201

13 15 16 18

15 64

15 18 25

21R1670MF 2015% 1/20W

100K

2

1R1631RAMCFG3:H

1/20W5%

201MF

100K

2

1R1636

1/20W5%

201MF

100K

RAMCFG2:H

2

1R1635RAMCFG1:H

1/20W5%

MF201

100K

2

1R1611RAMCFG0:H

100K1/20WMF201

5%

27

15 64

G2

K4

J3

J4

K3

J1

J2

G1

D60

V2

T4

C4

E2

C3

E4

D3

F4

E3

AF20

AB21

V4

AW15

AM7

G4

F1

F2

F3

Y2

K2

N7

R7

L5

L8

N6

R6

L6

AM3

AU2

AT5

AL4

AP1

AG6

P3

Y3

U4

AB6

AG3

AG5

AK4

AD7

AN5

AN3

AM4

AD5

T3

Y1

AD6

AH4

AT3

AM2

N5

L2

P2

P1

U0500

2C+GT2HASWELL-ULT

BGA-TSP

CRITICALOMIT_TABLE

15 64

15 64

15 64

39

15 64

15 16

15 16 18

15 16 46 64

15 36

18

15 30 58 59 64

15 64

15 34

15 25

15 16 18 25

15 16 18 25

15 18 25

15 58

15 46 64

15 18

15 64

15 30 64

15 29

30

15 37

15 34

15 36

38 67

15 16

15 16 18

15 16 18

15 16 18

18 25

15 36

15 16 33

15 36

15 36 68

15 36 68

2

1R1650

201MF

1/20W

1K5%

15 36 68

21R1610 100K1/20W5% MF 201

21R1614 100K5% 2011/20W MF21R1615 100K

1/20W 201MF5%

21R1616SD_ON_MLB

1/20W MF 2015%100K

21R1617201MF5% 1/20W

100K21R1618

MF 2015% 1/20W100K

21R16195% MF1/20W

100K20121R1620

MF1/20W5%100K

20121R1622

MF 2011/20W5%100K

21R1623MF

100K1/20W5% 20121R1624 100K

5% 1/20W 201MF21R1625201

100K1/20W5% MF21R16261/20W5%

100K201MF21R1627

MF 201100K

1/20W5%21R1628 100K1/20W5% MF 201

21R1630 100K1/20W5% 201MF

21R1632 100K1/20W5% 201MF

NO STUFF

21R1633 100K1/20W5% 201MF21R1634 100K1/20W5% 201MF

21R1640MF 2015% 1/20W

100K

21R16371/20W MF 2015%

100K21R1638

MF 2015% 1/20W100K

21R1691 100KMF 2015% 1/20W

21R1694 100K1/20W5% 201MF

21R1693 100K1/20W5% 201MF

2

1R1655PLACE_NEAR=U0500.AW15:2.54mm

49.9

201

1%1/20WMF

21R1695 100K1/20W5% 201MF

21R1660MF 2015% 1/20W

100K21R1661 100K

MF 2015% 1/20W21R1662 100K1/20W5% 201MF21R1663

MF 2015% 1/20W100K

21R1664MF 2015% 1/20W

47K21R1665

MF 2015% 1/20W47K

21R16661/20W5% 201MF

47K21R1667

MF 2015% 1/20W47K

PCH GPIO/MISC/LPIOSYNC_MASTER=J41_MLB SYNC_DATE=04/02/2013

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAMCFG_SLOT

PP3V3_S0

PP3V3_S0

BT_PWRRST_L

PP3V3_S5

PP3V3_S0

SSD_RESET_L

FW_PME_L

PCH_TCO_TIMER_DISABLE

AP_S0IX_WAKE_SEL

JTAG_ISP_TDO

LPC_SERIRQ

FW_PWR_EN

FW_PME_L

SSD_DEVSLPAP_S0IX_WAKE_SEL

PCH_HSIO_PWR_ENTPAD_SPI_IF_EN

SPIROM_USE_MLBCAMERA_PWR_EN_PCH

PLT_RESET_L

TBT_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

HDD_PWR_EN

TPAD_SPI_INT_L

XDP_PCH_GPIO17

SSD_PWR_EN

PCH_TBT_PCIE_RESET_L

PCH_GSPI0_CLK

PCH_GSPI0_MOSI

PCH_UART1_TXD

BT_PWRRST_L

LCD_IRQ_LENET_MEDIA_SENSE

PCH_OPI_COMP

TPAD_SPI_CLK

PLT_RESET_L

PCH_I2C0_SCL

PCH_I2C1_SDA

PCH_I2C1_SCL

PCH_UART1_RXD

ENET_MEDIA_SENSE

TBT_POC_RESET_L

LCD_IRQ_L

LCD_PSR_EN

PCH_STRP_TOPBLK_SWP_L

CAMERA_PWR_EN_PCH

SPIROM_USE_MLB

XDP_MLB_RAMCFG3

TPAD_SPI_IF_EN

JTAG_TBT_TMS

XDP_LPCPLUS_GPIO

XDP_MLB_RAMCFG0

TP_MEM_VDD_SEL_1V5_L

XDP_PCH_GPIO76

XDP_MLB_RAMCFG2

SSD_DEVSLP

FW_PWR_EN

PCH_HSIO_PWR_EN

SMC_WAKE_SCI_L

PCH_I2C0_SDA

PCH_UART1_RTS_L

PCH_UART1_CTS_L

TPAD_SPI_MISO

PCH_GSPI0_MISO

PCH_GSPI0_CS_L

TBT_CIO_PLUG_EVENT

LPC_SERIRQ

PM_THRMTRIP_L

PP1V05_S0

XDP_MLB_RAMCFG2

XDP_MLB_RAMCFG0XDP_MLB_RAMCFG1

TPAD_USB_IF_EN

SD_RESET_L

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

TBT_GO2SX_BIDIR

PP3V3_S0

SD_PWR_EN

XDP_MLB_RAMCFG3

LCD_PSR_EN

XDP_MLB_RAMCFG1

XDP_JTAG_ISP_TDIXDP_JTAG_ISP_TCK

XDP_PCH_GPIO76

PP3V3_S0SW_SD

PP3V3_S3RS0_CAMERA

PP3V3_S3

PP3V3_S3

AP_RESET_L

JTAG_ISP_TDO

HDMITBTMUX_FLAG_L

AP_S0IX_WAKE_L

TPAD_SPI_MOSI

TPAD_SPI_CS_L

PCH_UART1_TXDPCH_UART1_RXD

PCH_UART1_RTS_L

PCH_I2C0_SDAPCH_I2C0_SCL

PCH_I2C1_SDA

PCH_UART1_CTS_L

PCH_I2C1_SCL

PCH_GSPI0_CS_LPCH_GSPI0_CLKPCH_GSPI0_MISOPCH_GSPI0_MOSI

TPAD_SPI_CS_LTPAD_SPI_CLK

AP_S0IX_WAKE_LHDMITBTMUX_FLAG_L

TPAD_SPI_MISOTPAD_SPI_MOSI

XDP_LPCPLUS_GPIO

SD_RESET_L

TPAD_SPI_INT_L

JTAG_TBT_TMS

TPAD_USB_IF_EN


PP3V3_TBTLC

TBT_PWR_ENSD_PWR_EN

SSD_PWR_EN

HDD_PWR_EN

SMC_WAKE_SCI_L

XDP_PCH_GPIO17

16 OF 121

<E4LABEL>

<SCH_NUM>

<BRANCH>

15 OF 76

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

15 64

8 11 13 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

15 18 25

15 37 46 64

15 64

15 64

15 30 64

15 29

15 58

15 36

15 46 64

15 18

15

15

15

15 64

15 64

15

15

15

15

15

15

15

15

15

6 8 11 16 17 27 38 42 51 55 58 59 62 64

15 16 18

15 16 18

15 16 18

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

15 16 18

15 64

15 16 18 25

15 16 18 25

15 16

34 37 39 65

31 41

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

15

15

15

15

15

15

15

15

15

15

15

15

15 36

15 36 68

15 29

15 64

15 36 68

15 36 68

15 16 46 64

15 34

15 36

15 18 25

15 36

15 16 33

17 25 26 27 62 64

15 25

15 34

15 30 58 59 64

15 64

15 37

15 16

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

NCNC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

TP

TP

TP

TP

TP

TP

OUT

OUT

OUT

G

D SG

D SG

D SG

D S

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

IN

TP

OUT IN

BI

OUT

TP

TPBI

TPBI

TPBI

OUT

BI

IN OUT

OUT

OUT

OUT

BI

IN

BI

IN

OUT

IN OUT

BI

TP

IN

OUT

GND

VCC

NCNC

YA

NC

IN

NC

IN

TP

IN

TP

IN

IN

BI

IN

OUT

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3


III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY ITLPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

OBSFN_A0OBSFN_A1

VCC_OBS_CD

Extra BPM Testpoints

support chipset debug.

OBSFN_C0

OBSDATA_C0

OBSFN_C1

OBSDATA_C1

OBSDATA_C3OBSDATA_C2

OBSDATA_D0

OBSFN_D1

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

ITPCLK/HOOK4

TMSTDI

OBSDATA_A0

OBSFN_B1

OBSDATA_A3OBSDATA_A2

OBSFN_B0

OBSDATA_B0OBSDATA_B1

HOOK3

HOOK1

SDA

TCK1

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to

OBSDATA_A1

OBSDATA_D2

SCL

OBSFN_D0

Merged (CPU/PCH) Micro2-XDP

TRSTnTDO

HOOK2

TDI and TMS are terminated in CPU.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

Unused & MLB_RAMCFGx GPIOs have TPs.

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

PCH/XDP Signals

RESET#/HOOK6

PCH XDP Signals

Non-XDP Signals

These signals do not connect to XDP connector in this architecture, only accessiblevia Top-Side Probe. Nets are listed here to show XDP associations and to make clearwhat restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

NOTE: Must not short XDP pins together!

OBSDATA_B3

OBSDATA_D1

TCK0

CPU JTAG Isolation

518S0847

OBSDATA_B2

PWRGD/HOOK0

VCC_OBS_AB

6

13 15 18

6 67

6 64 67

6 67

6 67

6 67

6 67

13 37

13 17 37

12 16 64 69

17 67

6

12 16 64 69

12 16 64 69

21R1805PLACE_NEAR=U0500.AG7:2.54mm

1KXDP

MF1/20W 2015%

12R1813PLACE_NEAR=U0500.E60:28mm

51XDP

MF1/20W 2015%

21R1804XDP

402MF-LF1/16W0

5%

21R1802PLACE_NEAR=U5000.J3:2.54mm

XDP

MF1/20W 02010

5%

21R1800PLACE_NEAR=U0500.C61:2.54mm

XDP1K

MF1/20W 2015%

6 67 9

8 7

64 63

62 61

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1800XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

M-ST-SM1

6 67

6 67

6 67

6 67

6 67

6 67

6 67

6 67

6 67

6 67

1 TP1806TP-P61 TP1807TP-P6

1 TP1805TP-P6

1 TP1804TP-P6

1 TP1803TP-P6

1 TP1802TP-P6

8

2

1R1830

1/16WMF-LF402

1505%

21R1810PLACE_NEAR=U0500.F62:28mm

XDP51

MF1/20W 2015%

12 16 64 69

2

1R1831XDP

MF-LF402

1/16W

1K5%

12R1896NO STUFF

PLACE_NEAR=U0500.AE62:28mm51

MF1/20W 2015%

12R1892PLACE_NEAR=U0500.AD62:28mm

XDP51

MF1/20W 2015%

12R1891PLACE_NEAR=U0500.AD61:28mm

XDP51

MF1/20W 2015%

12R1890PLACE_NEAR=U0500.AE61:28mm

51XDP

MF1/20W 2015%

12R1899NO STUFF

PLACE_NEAR=U0500.AE63:28mm1K

MF1/20W 2015%

21R1835PLACE_NEAR=J1800.58:28mm

XDP

MF1/20W 02010

5%12 16

12

6

Q1842

CRITICAL

DMN5L06VK-7SOT-563

XDP

PLACE_NEAR=J1800.57:28mm

45

3

Q1840


CRITICAL

DMN5L06VK-7SOT-563

XDP

45

3

Q1842SOT-563

DMN5L06VK-7

XDPCRITICAL


12

6

Q1840


SOT-563DMN5L06VK-7

XDPCRITICAL

6 12 16 64 67

6 64 67

6 64 67

6 16 64 67

2

1 C1801XDP

6.3VCERM-X5R0201

0.1UF10%

15 16 33

14

14 16 61 65

6 67

14 16 61 65

1 TP1870TP-P614 16 35 14 16 35

15 18

14

1 TP1874TP-P6

2

1C1800XDP

6.3VCERM-X5R

0201

0.1UF10%

1 TP1876TP-P615 18

1 TP1877TP-P615 18

1 TP1878TP-P615 18

12

15

15 16 18 25 15 16 18 25

12

12

12

21R1881 1KMF1/20W 2015%

21R1882 1KMF1/20W 2015%

6 64 67

21R1883 1KMF1/20W 2015%

21R1884 1KMF1/20W 2015%

30 64

15 16 46 64

6 64 67

15

15 16 18 25 15 16 18 25

15 16 46 64

1 TP1887TP-P6

2

1C1804XDP

6.3VCERM-X5R

0201

0.1UF10%

2

1 C1806XDP

6.3VCERM-X5R0201

0.1UF10%

6 67

6 12 16 64 67

12R1897 51NO STUFF

PLACE_NEAR=U0500.AU62:28mm MF1/20W 2015%

4

6

51

3

2

U1845SOT891

74LVC1G07GF2

1C1845

X5R-CERM0201

16V

0.1UF10%

6 67

2

1R1845330K

MF1/20W

201

5%

17 37 59

1 TP1873TP-P6

15 16 33

1 TP1886TP-P6

6 67

6 67

14 19 25 40 56 69

14 19 25 40 56 69

6 16 64 67

6

8 17

6

6 67

6 67

SYNC_DATE=02/06/2013

CPU/PCH Merged XDPSYNC_MASTER=J41_MLB

XDP_CPU_PRESENT_L


CPU_PWR_DEBUG

PP1V05_S0

XDP_CPU_PWRBTN_L

XDP_BPM_L<0>

CPU_CFG<3>

XDP_CPU_PRDY_L

XDP_CPU_VCCST_PWRGD

XDP_CPURST_LXDP_DBRESET_L

XDP_JTAG_ISP_TCK

XDP_USB_EXTA_OC_L


XDP_MLB_RAMCFG3

PCH_JTAGX

PP3V3_S5

XDP_SYS_PWROK

XDP_CPU_PREQ_L CPU_CFG<17>CPU_CFG<16>


CPU_CFG<13>

XDP_TRST_L

XDP_MLB_RAMCFG2

XDP_SSD_PCIE3_SEL_L

XDP_PCH_GPIO17

XDP_SSD_PCIE2_SEL_L

XDP_SSD_PCIE0_SEL_L

XDP_LPCPLUS_GPIOMAKE_BASE=TRUE

SMBUS_PCH_DATA

XDP_JTAG_ISP_TDIMAKE_BASE=TRUE

XDP_PCH_GPIO76

XDP_SSD_PCIE1_SEL_L

XDP_JTAG_ISP_TCKMAKE_BASE=TRUE

XDP_MLB_RAMCFG1

XDP_USB_EXTD_OC_L

XDP_SDCONN_STATE_CHANGE_LMAKE_BASE=TRUE

XDP_USB_EXTC_OC_LMAKE_BASE=TRUE

XDP_USB_EXTB_OC_LMAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

XDP_MLB_RAMCFG0

XDP_USB_EXTB_OC_L

XDP_CPU_TCK

XDP_JTAG_CPU_ISOL_L

XDP_PCH_TCK


XDP_CPU_TMS

XDP_CPU_TDI

XDP_CPUPCH_TRST_LXDP_CPUPCH_TRST_L

XDP_CPU_TDO

PLT_RESET_L


CPU_CFG<12>


PM_PCH_SYS_PWROK

PM_PWRBTN_L

CPU_VCCST_PWRGD

XDP_PCH_TCKSMBUS_PCH_CLK


XDP_BPM_L<1>

CPU_CFG<2>

CPU_CFG<0>

PP1V05_S0

XDP_PCH_TDO

XDP_CPU_TDO

XDP_PCH_TDI

PCH_JTAGX

PP1V05_SUS

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_CPU_TCK

XDP_CPUPCH_TRST_LMAKE_BASE=TRUE

XDP_PCH_TDI

XDP_PCH_TDO

CPU_CFG<1>

XDP_CPUPCH_TRST_L

XDP_PCH_TMS

XDP_PCH_TMS

PP5V_S0

ALL_SYS_PWRGD

SSD_PCIE_SEL_L

XDP_JTAG_ISP_TDI

XDP_LPCPLUS_GPIO

16 OF 76

<BRANCH>

<SCH_NUM>

<E4LABEL>

18 OF 121

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

64

67

8 11 13 15 17 18 28 29 34 42 57 58 59 60 62 64 74

64

12 16 64 69

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

12 16 64 69

6 16 64 67

12 16 64 69

12 16

57 62

6 16 64 67

6 12 16 64 67

6 12 16 64 67

12 16 64 69

17 32 45 46 51 52 56 58 59 61 62 64

www.vinafix.vn

OUT

OUT

NCNC

OUT

OUT

IN

IN

BIIN

OUT

IN

SD

G

S

D

G

OUT

NC

NCNC

OUT

IN

IN

NC

OUT

IN

NC

A Y

NC NC

VCC

GND

NC

IN

OUT

IN

IN

Y

A

B 08 Y

A

B 08

OUT

OUT

OUT

IN

OUT

IN

YA

B

NCGND

VCC

32.768K

GND THRM

VOUT

X2

X1

25M_A

25M_B

25M_C

VIOE_25M_A

VIOE_25M_B

VIOE_25M_C

VG3HOT

NC

VDD

PAD

NCNC

Apple Inc.


124578

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BRANCH

6 3



Must be powered if any VDDIO is powered.

available ~3.3V power

WF: Do we need this?

TPS51916 I(leak) = +/- 1uA, Vih(min) = 1.8V33uW when driven-low

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

Memory VTT Enable Level-Shifter

SMC controls strap enable to allow in-field control of strap setting.

VCCST (1.05V S0) PWRGD

IPD = 9-50k

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

PCH Reset Button

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

CAM XTAL Power

PCH PWROK Generation

PCH 24MHz Outputs

No bypass necessaryNo Coin-Cell: 3.3V S5Coin-Cell & No G3Hot: 3.3V S5

TBT XTAL Power

GreenCLK 25MHz Power

PCH 24MHz Crystal

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)Coin-Cell: VBAT (300-ohm & 10uF RC)

System RTC Power Source & 32kHz / 25MHz Clock GeneratorChipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

VBAT and +V3.3A areinternally ORed tocreate VDD_RTC_OUT.

+V3.3A should be first

to reduce VBAT draw.

For SB RTC Power

PCH ME Disable Strap

NOTE: 30 PPM or better required for RTC accuracy

pin 5 must receive S5 power (Stuff R2042)new and old parts. With GreenCLK Rev C This looks a little ugly to support

12

25 69

2

1 C1902

X5R

1UF

0201

20%6.3V

2

1 C1910

0201

6.3V20%1UF

X5R

31

42 Y1905

SM-3.2X2.5MM

CRITICAL

25.000MHZ-12PF-20PPM

2 1

C190512PF

25VNP0-C0G-CERM

0201

5%

21

C1906

25VNP0-C0G-CERM

0201

12PF

5%

17 37 69

46 64 69

21

R1927

PLACE_NEAR=U0500.AN15:5.1mm

22

MF1/20W

201

5%

21

R1926

PLACE_NEAR=U0500.AP15:5.1mm

22

MF1/20W

201

5%

12 69

12 69

13 37 64 16 67

2

1C1924

0201X5R-CERM

16V10%

0.1UF

21

R1905

MF1/20W

0201

0

5%

2

1R1906NO STUFF

1M

MF1/20W

201

5%

21

R1996XDP

MF

1/20W0201

0

5%

2

1R1997

402

1/16WMF-LF

SILK_PART=SYS RESET

NO STUFF

05%

2

1R199510K

MF1/20W

201

5%

2

1R1920100K

MF1/20W

201

5%

2

1R19211K

MF1/20W

201

5%

12 69

37

45

3

Q1920DMN5L06VK-7

SOT-563

12

6Q1920SOT-563

DMN5L06VK-7

2

1C19220.1UF

10%16V

0201X5R-CERM

32 69

2

1R19161M

MF1/20W

201

5%

21

R1915

MF1/20W

0201

0

5%

21

C1915

C0G

6.8PF

0201

+/-0.1PF25V

21

C19166.8PF

0201C0G25V

+/-0.1PF

12

12

12 17

8 16

2

1R193110K

MF1/20W

201

5%

2

1C1930

0201

16VX5R-CERM

10%0.1UF

13 18 37 59

2

1R1970330K

MF1/20W

201

5%

4

6

51

3

2

U1970SOT891

74AUP1G07GF2

1C19700.1UF

10%16V

0201X5R-CERM

6

17 53

27 37 38

16 17 37 59

7

8

4

2

1

U1950

74LVC2G08GTSOT833

2

1 C1950

X5R-CERM

10%

0201

16V

0.1UF

BYPASS=U1950:5MM

3

8

4

6

5

U1950

CKPLUS_WAIVE=UNCONNECTED_PINS

SOT83374LVC2G08GT


1

2R1963

MF1/20W

0201

05%

1

2R1960NO STUFF

MF1/20W

0201

05%

21

R19621K

MF1/20W

201

5%

13 16 37

13 17

13 17

21

R1951NO STUFF

MF1/20W

0201

0

5%

2

1R195010K

MF1/20W

201

5%

2

1R195510K

MF1/20W

201

5%

8 51

8 17 51

8 17 51

2

1R1961NO STUFF

100K

MF1/20W

201

5%

4

6

5

3

1

2

U193074AUP1G09SOT891

CRITICAL

3

4

1

14

6

11

13

5

17

2

16

10

7

12

15

8

9

U1900SLG3NB148CV

CRITICALTQFN

CKPLUS_WAIVE=PwrTerm2Gnd

31

42

Y1915CRITICAL

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

Chipset SupportSYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB

PP3V3_S5

PP3V3_S5RS3RS0_SYSCLKGEN

NC_RTC_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PP3V3_TBTLC

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

SYSCLK_CLK25M_X1

PCH_CLK24M_XTALOUT_R

PCH_CLK24M_XTALIN

PM_SLP_S3_L

ALL_SYS_PWRGD

PP3V3_S5

CPU_VCCST_PWRGD

PP1V05_S0

PM_PCH_PWROKMAKE_BASE=TRUE

SMC_DELAYED_PWRGD

ALL_SYS_PWRGD

MAKE_BASE=TRUECPU_VR_READY

CPU_VR_EN

CPU_VR_READY

PP3V42_G3H

XDP_DBRESET_L PM_SYSRST_L

PP3V3_S0


SPI_DESCRIPTOR_OVERRIDE_L

SPI_DESCRIPTOR_OVERRIDE

HDA_SDOUT_R

LPC_CLK24M_LPCPLUS

PCH_CLK24M_XTALOUT

LPC_CLK24M_SMC_R

LPC_CLK24M_LPCPLUS_R

SYS_PWROK_R

PP5V_S0

SPI_DESCRIPTOR_OVERRIDE_LS5V

CPU_MEMVTT_PWR_EN_LSVDDQ

PP1V2_S3

MEMVTT_PWR_ENMAKE_BASE=TRUE

PP3V3_S0

MEMVTT_PWR_EN

PM_PCH_SYS_PWROKPM_S0_PGOOD

PM_PCH_PWROK

CPUVR_PGOOD_R

PP3V3_S0

SYSCLK_CLK25M_X2

NO_TEST=TRUEMAKE_BASE=TRUENC_RTC_CLK32K_RTCX2

LPC_CLK24M_SMC

LPC_CLK24M_SMCMAKE_BASE=TRUE

PPVRTC_G3HSYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_CAMERASYSCLK_CLK25M_TBT

<BRANCH>

<SCH_NUM>

<E4LABEL>

19 OF 121

17 OF 76

8 11 13 15 16 17 18 28 29 34 42 57 58

59 60 62 64

74

18

15 25 26 27 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

31

69

16 17 37 59

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74 6 8 11 15 16 27 38 42 51 55 58

59 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8 11 58

16 32 45 46 51 52 56 58 59 61 62 64

19 20 21 22 23 42 53 62 70

17 53

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

69

12 17

17 37 69

8 12 13 62 64

69

www.vinafix.vn

S

D

G S

D

G

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

S

D

G S

D

G

IN

OUT

OUT

BI

BI

BI

OUT

BI

BI

BI

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT IN

OUT

OUTIN

IN

BI

BIBI

NC

08

NC

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUTIN

Apple Inc.


124578

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



MAKE_BASE

Single-port TBT implementation does not require DDC Crossbar

No MAKE_BASE on TCK/TDI as these are provided on XDP page.

RAM Configuration StrapsPull-downs for chip-down RAM systems

Platform Reset Connections

Scrub for Layout Optimization

MAKE_BASE

TBT Aliases

Cactus Ridge PLUG_EVENT is active-high, always driven (pull-down)

Buffered

(For development only)

GreekCLK A or B depending on S2 rail

R2042 should be stuffed for GreenCLK C

Required for unused second TBT port

Thunderbolt Pull-up/downs

2.2k pull-ups are required by PCH

DP port is used. No DDC on this port, AUX-only.TBTSNK1_DDC is pulled-up just to indicate that

DP++ spec violation, should remove!

R2041/2 should be stuffed for

GreenCLK 25MHz Power

Cactus Ridge GO2SX signal pulled-up to SUS rail

DDC Pull-Ups

MAKE_BASE

LPDDR3 Alias Support

DDC_CLK pull-ups are unstuffed.

Power State Debug LEDs

to indicate active display interface.Unbuffered

NOTE: Only DDC_DATA is sensed by PCH, so

MAKE_BASE MAKE_BASE

2

1R20225%

201

1/20WMF

NO STUFF

2.2K

2

1R20235%

201

1/20WMF

2.2K

2

1R20205%

201

1/20WMF

2.2K

NO STUFF

2

1R20215%

201

1/20WMF

2.2K

2

1R20505%

201

1/20WMF

RAMCFG3:L

10K

2

1R20515%

201

1/20WMF

RAMCFG2:L

10K

2

1R20525%

201

1/20WMF

RAMCFG1:L

10K

2

1R20535%

201

1/20WMF

RAMCFG0:L

10K

2

1R20165%

201

1/20WMF

10K

2

1R20175%

201

1/20WMF

10K

2

1R20185%

201

1/20WMF

10K

2

1R20195%

201

1/20WMF

10K

2

1R20145%

201

1/20WMF

10K

12

6Q2090DBGLED

DMN5L06VK-7SOT-563

45

3Q2090DMN5L06VK-7

DBGLED

SOT-563

K

AD2090GREEN-56MCD-2MA-2.65VLTQH9G-SMPLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S5_ONK

AD2091LTQH9G-SMGREEN-56MCD-2MA-2.65V

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=STBY_ON

2

1R20905%

201

1/20WMF

DBGLED

20K

2 1

R2094

5%

0

402MF-LF1/16W

PLACE_SIDE=BOTTOM

DBGLED

2

1R20915%

201

1/20WMF

DBGLED

20K

K

AD2092

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65VLTQH9G-SM

2

1R20925%

201

1/20WMF

DBGLED

20K

K

AD2093GREEN-56MCD-2MA-2.65VLTQH9G-SMPLACE_SIDE=BOTTOMSILK_PART=S0I3_ON

DBGLED

2

1R20935%

201

1/20WMF

DBGLED

20K

15 16

15 16

15 16

15 16

25

25

25

25

6 18

15 18

28 58 59

13 18 29 36 37 59

13 17 37 59

2

1R20955%

201

1/20WMF

20K

DBGLED

K

AD2095GREEN-56MCD-2MA-2.65VLTQH9G-SMPLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S0_ON

13 37

12

6Q2091DBGLED

SOT-563DMN5L06VK-7

45

3Q2091DBGLED

SOT-563DMN5L06VK-7

13 18 25

5 25 67

5 25 67

13 18 28

13 18 25 67

13 18 25 67

13 18 28

13 18

13 18 25 67

13 18 25 67

13 18 25

13 18

2

1 C207110%16V

0.1UF

X5R-CERM0201

5

4

1

2

3

U2071SC70-HF

CRITICALMC74VHC1G08

2

1R20705%

201

1/20WMF

100K21

R2088

5%

0

0201

1/20WMF

21

R2072

5%

0

0201

1/20WMF

13 15 16

21

R2071

5%

0

0201

1/20WMF

21

R2081

5%

201

1/20WMF

33

56

37

19

46 64 69

15 18 25

2

1R20155%

201

1/20WMF

100K

15 18 25

21

R2089

5%

0

0201

1/20WMF

31

15 18 27 15 18 27

21

R2040

5%

0

0201

1/20WMF

NO STUFF

21

R2041

5%

0

0201

1/20WMF

NO STUFF

13 18 28

13 18 28

15 18 25 15 18 25

2

1R20135%

201

1/20WMF

10K

4

6

5 3

1

2

U2030

NOSTUFFCRITICAL74LVC1G08SOT891

2

1C2030NOSTUFF

0.1UF

BYPASS=U2030:3mm

0201X5R-CERM

10%10V

21

R2030

5%

0

0201

1/20WMF

31

15

13 18 29 36 37 59

21

R2042

5%

0

0201

1/20WMF

15 18 25

15 16 18 25

15 16 18 25

15 18 25

15 16 18 25

15 16 18 25

15 18 25 15 18 25

SYNC_MASTER=J41_MLB

Project Chipset SupportSYNC_DATE=02/15/2013

DBGLED_S4

DBGLED_S4_D

DBGLED_S3

DBGLED_S3_D

PM_SLP_S3_LPM_SLP_S0_L

PP3V3_S5

TRUE JTAG_TBT_TMSXDP_JTAG_ISP_TDIXDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCKTRUEJTAG_ISP_TDO JTAG_ISP_TDO

XDP_JTAG_ISP_TCK

DP_TBTSNK1_DDC_CLK

DP_TBTSNK0_DDC_CLK TRUE

S4_PWR_EN

DBGLED_S5

DBGLED_S0I3_D DBGLED_S0_D

DBGLED_S0I3 DBGLED_S0

DP_TBTSNK1_DDC_CLK

PM_SLP_S4_LXDP_MLB_RAMCFG2XDP_MLB_RAMCFG3

MAKE_BASE=TRUETP_CPU_MEM_RESET_L

MAKE_BASE=TRUETP_MEM_VDD_SEL_1V5_L

VOLTAGE=0.6VMAKE_BASE=TRUEPP0V6_S3_MEM_VREFDQ_APP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_AVOLTAGE=0.6VMAKE_BASE=TRUE

PP0V6_S3_MEM_VREFCA_A

TP_CPU_MEM_RESET_L

TP_MEM_VDD_SEL_1V5_L

PP0V6_S3_MEM_VREFDQ_BVOLTAGE=0.6VMAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_BVOLTAGE=0.6VMAKE_BASE=TRUE

PP0V6_S3_MEM_VREFCA_B

TBT_B_CIO_SELDP_TBTPB_HPDTBT_B_CONFIG2_RCTBT_B_CONFIG1_BUF

DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_AUXCH_C_PTRUE

DP_TBTSNK1_DDC_CLKTRUEDP_TBTSNK1_DDC_DATATRUE

DP_TBTSNK0_DDC_DATA TRUE


TBT_CIO_PLUG_EVENT TBT_CIO_PLUG_EVENTTRUE

TRUE TBT_GO2SX_BIDIR

PP3V3_SUS

XDP_MLB_RAMCFG1XDP_MLB_RAMCFG0

TBT_GO2SX_BIDIR

PP3V3_S5RS3RS0_SYSCLKGENPP3V3_S0

DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_DDC_DATA

PP3V3_S3

DP_TBTSNK0_DDC_DATA

CAMERA_PWR_EN

PP3V3_S5

CAMERA_PWR_EN_PCH

PM_SLP_S4_L

PCA9557D_RESET_L

PLT_RESET_L

PP3V3_S0

PLT_RST_BUF_L

PCH_TBT_PCIE_RESET_LMAKE_BASE=TRUE

SMC_LRESET_L

CAM_PCIE_RESET_L


DP_TBTSNK1_AUXCH_C_NTRUE


TBT_B_LSRX

DP_TBTSNK1_HPD

TRUE DP_TBTSNK1_ML_C_N<3..0>

BKLT_PLT_RST_L

LPCPLUS_RESET_LMIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5RS3RS0_SYSCLKGEN

PP3V3_S0

PP3V3_S5_DBGLEDMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=3.3V

DP_TBTSNK0_DDC_DATA

JTAG_TBT_TMS

DP_TBTSNK1_DDC_DATA

=DP_TBTSNK1_ML_C_N<3..0>=DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_P<3..0>TRUE

TRUE DP_TBTSNK1_HPD

PP3V3_S5

<BRANCH>

<SCH_NUM>

<E4LABEL>

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13 18

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38 39 40 41 42

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61 62 64 65 74

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www.vinafix.vn

OUT

V-

V+

V-

V+

IN

IN

IN

G

DSG

DSG

DSG

DS

IN

G

DSG

DSG

DSG

DS

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GNDPAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



VRef Dividersof margining option.

+21uA - -21uA (- = sourced)

0.000V - 2.397V (0x00 - 0xBA)

0.800V - 1.600V (+/- 400mV)

NOTE: Margining will be disabled across all

Always used, regardless

Addr=0x98(WR)/0x99(RD)

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step

FETs for CPU isolation during DAC margining

R22x6 pin 2:

Q2265 pin 6:

to remove short due to CPU.

and disables margining after platform reset.DAC sets voltage level, PCA9557 & FETs enable outputs

Addr=0x30(WR)/0x31(RD)

soft-resets and sleep/wake cycles.

watchdog will disable margining.RST* on ’platform reset’ so that system

3.53mV / step @ output


1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

DDR3L (1.35V) DDR3L assumes TPS51916 supply with 19.6k/57.6k dividerNOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

1.200V (DAC: 0x5D)

5

D

MEM VREG

LPDDR3 (1.2V)

DAC Channel:

PCA9557D Pin:

MEM A VREF DQ

1

A B

2

MEM A VREF CA

C

3

MEM B VREF CA

DDR3L (1.35V)

C

4



DAC output, cannot enableNOTE: MEMVREG and SPARE share a

(All 4 R’s)


0.600V (DAC: 0x2E.5) 0.675V (DAC: 0x34)

Margined target: 0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

CPU-Based Margining

margining support. When

- =I2C_PCA9557D_SDA- =I2C_PCA9557D_SCL

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

Pins B1 & B4:

both at the same time!

(OD)

Q2225 pin 6:

DDR3L (1.35V) 6.99mV per step

VREFMRGN_CPU_EN is low

VREFCA. Split into two

- =I2C_VREFDACS_SCL

DAC range:

Nominal value

VRef current:

DAC step size:

- =PP3V3_S3_VREFMRGN- =PPDDR_S3_MEMVREF

- =I2C_VREFDACS_SDA

0.000V - 2.694V (0x00 - 0xD1)0.000V - 1.354V (0x00 - 0x69)

BOM options provided by this page:- DDRVREF_DAC - Stuffs DAC margining circuit.

EN RC’s to avoid drain glitchesMay not be necessary due to C22x0

LPDDR3 (1.2V) ?.??mV per step

DAC margining VREFCA ensure

LPDDR3 (1.2V)


DAC-Based Margining

signals for independent DAC

NOTE: CPU has single output for

MEM B VREF DQ

0.337V - 1.013V (+/- 337.5mV)


53 2

1C220210%

6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

21

R2214

201

PLACE_NEAR=R7415.2:1mm1%

DDRVREF_DAC

1/20WMF

38.3K

2

1R2213

201

5%100K1/20W

MF

DDRVREF_DAC

2

1R2212

201

5%100K1/20W

MF

DDRVREF_DAC

B4

B1

A4

A1

A2

A3

U2204

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

MAX4253UCSP

CRITICALDDRVREF_DAC

B4

B1

C4

C1

C2

C3

U2204UCSP

DDRVREF_DAC

MAX4253

CRITICAL

21

R2218SHORT

NONENONE

NONE

OMIT

402

18

7

7

12

6

Q2260DMN5L06VK-7

CRITICAL

SOT-563

2

1R2202

201

1/20W5%

MF

DDRVREF_DAC

100K

45

3

Q2220CRITICAL

DMN5L06VK-7SOT-563

45

3

Q2260CRITICAL

DMN5L06VK-7SOT-563

12

6

Q2220CRITICAL

DMN5L06VK-7SOT-563

7

12

6

Q2225DMN5L06VK-7

CRITICALDDRVREF_DAC

PLACE_NEAR=Q2220.6:2.54mm

SOT-563

2

1R2201

201

100K

DDRVREF_DAC

5%1/20W

MF

21

R2225

201

1/20W5%

MF

DDRVREF_DAC

100K

2

1C222510%

6.3V

DDRVREF_DAC

0.1UF

0201CERM-X5R

12

6

Q2265

CRITICALDDRVREF_DAC

DMN5L06VK-7SOT-563


2

1C224510%

6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC21

R2245

201MF

1/20W

DDRVREF_DAC

5%

100K

21

R2265

201MF

1/20W5%

DDRVREF_DAC

100K

45

3

Q2225DDRVREF_DACCRITICAL

DMN5L06VK-7SOT-563

2

1C226510%

6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

45

3

Q2265DDRVREF_DACCRITICAL

DMN5L06VK-7SOT-563

2

1C228510%

6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

2

1R2215

201

100K5%

1/20WMF

DDRVREF_DAC

21

R2285

201

DDRVREF_DAC

MF1/20W5%

100K

2

1R2207

201

DDRVREF_DAC

100K5%

1/20WMF

21R22262011% 1/20W MF

4.02KDDRVREF_DAC

PLACE_NEAR=Q2225.1:2.54mm21R22462011% 1/20W MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2265.1:2.54mm21R2266

2011% 1/20W MF4.02K

DDRVREF_DAC


21R22862011% 1/20W MF

4.02K

DDRVREF_DAC


2

1R2217

201MF1/20W5%

DDRVREF_DAC

1M

2

1R2200

201

100K5%

1/20WMF

2

1R2221

201PLACE_NEAR=Q2220.6:3mm

MF

1%8.2K1/20W

21

R2280

201MF

1/20W1%

24.9

2

1 C228010%0.022UF

0201X5R-CERM6.3V

PLACE_NEAR=Q2260.3:2mm

21

R2283

201MF

1/20W

10

1%

2

1R2281


1%8.2K1/20WMF

2

1R2282

201

1%8.2K1/20W

MF

PLACE_NEAR=R2281.2:1mm

2

1R2262

201


1%8.2K1/20W

MF

21

R2260

201MF

1/20W1%

24.9

21

R2263

201MF

1/20W

10

1%

2

1 C226010%0.022UF

0201X5R-CERM6.3V


2

1R2261


1%8.2K1/20WMF

2

1R2242

201


1%8.2K1/20W

MF

21

R2240

201MF

1/20W1%

24.9

21

R2243

201

10

MF1/20W1%

2

1 C2240

6.3VX5R-CERM0201

0.022UF10%


2

1R2241

201

8.2K


1%1/20WMF

21

R2223

201

1/20WMF

10

1%

2

1R2222

201


1%8.2K

MF1/20W

21

R2220

201MF

1/20W1%

24.9

2

1 C222010%0.022UF

0201X5R-CERM6.3V


16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2201

DDRVREF_DACCRITICAL

QFNPCA9557

14 16 19 25 40 56 69

14 16 19 25 40 56 69

5

4

2

1

8

7

6

3

10

9

U2200MSOP

DDRVREF_DACCRITICAL

DAC5574

14 16 19 25 40 56 69

14 16 19 25 40 56 69

2

1 C220110%6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC

2

1C2200

6.3V20%

CERM

2.2UF

DDRVREF_DAC

402-LF

2

1C220510%

6.3V

0.1UF

0201CERM-X5R

DDRVREF_DAC


DDR3 VREF MARGININGSYNC_MASTER=J41_MLB

VREFMRGN_DQ_A_EN_RC

CPU_MEM_VREFDQ_B_ISOL

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP0V6_S3_MEM_VREFDQ_A

VREFMRGN_CA_A_EN_RC

PP3V3_S3

PP3V3_S3

VREFMRGN_SPARE_BUF

VREFMRGN_MEMVREG_BUF

MEM_VREFCA_A_RC

MEM_VREFDQ_B_RC

SMBUS_PCH_CLK

SMBUS_PCH_DATA

VREFMRGN_CA_B_EN_RC

DDRREG_FB

MEM_VREFCA_B_RC

VREFMRGN_DQ_A

VREFMRGN_CA_A_RDIV

VREFMRGN_CA_B_RDIV

VREFMRGN_CA_AB

CPU_DIMM_VREFCA

PP0V6_S3_MEM_VREFCA_AMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

PP1V2_S3

PP0V6_S3_MEM_VREFCA_BMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

VREFMRGN_DQ_B

CPU_DIMMA_VREFDQ

CPU_MEM_VREFCA_A_ISOL

VREFMRGN_DQ_B_RDIV

VREFMRGN_DQ_A_RDIV

CPU_DIMMB_VREFDQ

VREFMRGN_MEMVREG

CPU_MEM_VREFCA_B_ISOL

VREFMRGN_DQ_B_EN_RC

PP0V6_S3_MEM_VREFDQ_BMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm

CPU_MEM_VREFDQ_A_ISOL

MEM_VREFDQ_A_RC

PCA9557D_RESET_L

SMBUS_PCH_CLKSMBUS_PCH_DATA

VREFMRGN_CPU_ENVREFMRGN_DQ_A_ENVREFMRGN_DQ_B_EN

VREFMRGN_MEMVREG_EN

PP3V3_S3_VREFMRGN_DACMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

VREFMRGN_CA_A_ENVREFMRGN_CA_B_EN

VREFMRGN_SPARE_EN

<SCH_NUM>

22 OF 121

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<E4LABEL>

<BRANCH>

18 20 21 70

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15 18 19 33 36 40 41 58 62 64

18 20 21 70

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18 22 23 70

18 22 23 70

www.vinafix.vn

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNCNC

NCNCNCNCNCNCNCNCNCNCNCNC

IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Distribute evenly.

LPDDR3 CHANNEL A (0-31)

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

63

63

2

1 C230610UF20%25VX5R-CERM0603

2

1 C2307

25V

0603

10UF20%

X5R-CERM2

1 C2302

402

10VX5R

1UF10%

63

2

1 C230010%0.1UF

X5R-CERM16V

02012

1 C2303

402

10VX5R

1UF10%

2

1 C2304

10VX5R402

1UF10%

2

1 C230110%0.1UF

0201X5R-CERM16V

2

1 C2305

10VX5R402

1UF10%

63

2

1 C2310

10VX5R402

1UF10%

2

1 C2311

10VX5R402

1UF10%

2

1 C2312

25V

0603

10UF20%

X5R-CERM

2

1 C232010%1UF

402X5R10V

2

1 C232110%1UF

402X5R10V

2

1 C232210%1UF

402X5R10V

63

2

1 C2324

X5R-CERM

20%10UF

0603

25V2

1 C2323

X5R-CERM

20%10UF

0603

25V

2

1 C233310UF20%

0603

25VX5R-CERM2

1 C2332

25V

0603

10UF20%

X5R-CERM2

1 C233110%1UF

402X5R10V

2

1 C233010%1UF

X5R10V

402

63

2

1 C23410.047UF

201

10%

X5R6.3V

2

1C2340

201

0.047UF

X5R6.3V10%

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

7 24 63 70

24 63 70

63

24 63 70

24 63 70

7 24 70

7 24 70

7 24 70

7 24 70

7 21 24 70

7 21 24 70

7 21 24 63 70

63

2

1R2300

201MF

1/20W1%

243

2

1R23011%

2431/20W

MF201

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2300FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2300

FBGALPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

63

LPDDR3 DRAM Channel A (0-31)SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013

PP1V2_S3

MEM_A_ZQ<0>

PP0V6_S3_MEM_VREFCA_APP0V6_S3_MEM_VREFDQ_A

MEM_A_ZQ<1>

MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_CAA<5>

MEM_A_CAA<7>

MEM_A_CLK_P<0>

MEM_A_CKE<1>

MEM_A_CAA<8>

MEM_A_CAA<4>

PP1V8_S3

MEM_A_CAA<9>

MEM_A_CAA<6>

=MEM_A_DQ<4>

PP1V2_S3

=MEM_A_DQ<13>=MEM_A_DQ<14>=MEM_A_DQ<15>=MEM_A_DQ<16>

=MEM_A_DQ<18>

=MEM_A_DQ<22>=MEM_A_DQ<23>

=MEM_A_DQ<20>

MEM_A_CAA<2>

MEM_A_CAA<0>

=MEM_A_DQ<24>

=MEM_A_DQ<17>

PP1V2_S3

=MEM_A_DQ<25>

=MEM_A_DQS_P<0>

PP1V2_S3

=MEM_A_DQ<3>

=MEM_A_DQS_N<1>

=MEM_A_DQ<19>

=MEM_A_DQS_P<3>

=MEM_A_DQS_P<1>=MEM_A_DQS_P<2>

=MEM_A_DQS_N<3>=MEM_A_DQS_N<2>

=MEM_A_DQS_N<0>

=MEM_A_DQ<31>=MEM_A_DQ<30>=MEM_A_DQ<29>


=MEM_A_DQ<26>

=MEM_A_DQ<21>

=MEM_A_DQ<12>


=MEM_A_DQ<9>=MEM_A_DQ<8>=MEM_A_DQ<7>=MEM_A_DQ<6>=MEM_A_DQ<5>


MEM_A_CS_L<1>

MEM_A_ODT<0>

PP1V8_S3

MEM_A_CKE<0>

MEM_A_CAA<3>

MEM_A_CAA<1>

PP1V2_S3

PP1V2_S3

23 OF 121

<SCH_NUM>

<E4LABEL>

<BRANCH>

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17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

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BI

BI

BI

BI

BI

BI

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BI

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BI

BI

BI

BI

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BI

BI

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BI

BI

BI

BI

BI

NCNCNC


IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

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REVISION

BRANCH

6 3



LPDDR3 CHANNEL A (32-63)

10uF caps are shared between DRAM.

PLACEMENT_NOTE:

Distribute evenly.

63

2

1 C2423

25V

0603

10UF20%

X5R-CERM

2

1 C240310%1UF

402X5R10V

2

1 C240410%1UF

402X5R10V

2

1 C240510%1UF

402X5R10V

2

1 C2406

0603X5R-CERM25V20%10UF

63

7 20 24 63 70

2

1R2400243

1%1/20W

MF201 2

1R2401

201MF

1/20W

2431%

2

1C2440

6.3VX5R

0.047UF

201

10%

63

2

1 C2441

6.3VX5R

10%0.047UF

201

63

63

63

63

7 63 70

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

7 63 70

7 63 70

63

63

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

7 24 63 70

24 63 70

63

24 63 70

24 63 70

7 24 70

7 24 70

7 24 70

7 24 70

7 20 24 70

7 20 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2400

OMIT_TABLE

FBGA

EDFA232A1MA-GD-F

CRITICAL

LPDDR3-16GB

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2400

FBGA

EDFA232A1MA-GD-F

LPDDR3-16GB

CRITICAL

OMIT_TABLE

2

1 C2430

10VX5R402

1UF10%

2

1 C2431

10VX5R402

1UF10%

2

1 C241010%1UF

402X5R10V

2

1 C241110%1UF

402X5R10V

63

2

1 C2432

X5R-CERM

20%10UF

0603

25V

2

1 C241210UF

X5R-CERM

20%

0603

25V

2

1 C2420

10VX5R402

1UF10%

2

1 C240010%0.1UF

X5R-CERM16V

0201

2

1 C2421

10VX5R402

1UF10%

2

1 C24010.1UF16VX5R-CERM

10%

0201

2

1 C2422

10VX5R402

1UF10%

2

1 C2402

10V10%1UF

402X5R


LPDDR3 DRAM Channel A (32-63)

MEM_A_CLK_P<1>

MEM_A_CAB<9>MEM_A_CAB<8>MEM_A_CAB<7>MEM_A_CAB<6>

MEM_A_DQ<32>

MEM_A_CLK_N<1>

=MEM_A_DQS_P<7>

=MEM_A_DQS_P<5>MEM_A_DQS_P<6>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<7>MEM_A_DQS_N<6>

=MEM_A_DQS_N<4>=MEM_A_DQS_N<5>



=MEM_A_DQ<58>=MEM_A_DQ<57>=MEM_A_DQ<56>=MEM_A_DQ<55>=MEM_A_DQ<54>=MEM_A_DQ<53>=MEM_A_DQ<52>=MEM_A_DQ<51>=MEM_A_DQ<50>=MEM_A_DQ<49>=MEM_A_DQ<48>=MEM_A_DQ<47>=MEM_A_DQ<46>=MEM_A_DQ<45>


=MEM_A_DQ<41>=MEM_A_DQ<40>=MEM_A_DQ<39>=MEM_A_DQ<38>=MEM_A_DQ<37>=MEM_A_DQ<36>



MEM_A_CS_L<1>

PP1V2_S3

PP1V2_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

PP1V2_S3

MEM_A_CAB<4>

MEM_A_CAB<0>MEM_A_CAB<1>MEM_A_CAB<2>MEM_A_CAB<3>

MEM_A_CAB<5>

MEM_A_CKE<2>MEM_A_CKE<3>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_ZQ<2>MEM_A_ZQ<3>

PP0V6_S3_MEM_VREFDQ_APP0V6_S3_MEM_VREFCA_A

<BRANCH>

<E4LABEL>

<SCH_NUM>

21 OF 76

24 OF 121

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

18 19 20 70

18 19 20 70

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IN

IN

IN

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IN

IN

IN

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(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

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REVISION

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6 3



LPDDR3 CHANNEL B (0-31)

Distribute evenly.10uF caps are shared between DRAM.

PLACEMENT_NOTE:

63

2

1 C2523

25V

0603

10UF20%

X5R-CERM

2

1 C250310%1UF

402X5R10V

2

1 C250410%1UF

402X5R10V

2

1 C250510%1UF

402X5R10V

2

1 C2506


63

7 23 24 63 70

2

1R2500

201MF

1/20W1%

243

2

1R25011%

2431/20W

MF201

2

1C2540

201

0.047UF

X5R6.3V10%

2

1 C2541

201

0.047UF10%

X5R6.3V

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

7 24 63 70

24 63 70

63

24 63 70

24 63 70

7 24 70

7 24 70

7 24 70

7 24 70

7 23 24 70

7 23 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2500FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2500

EDFA232A1MA-GD-F

LPDDR3-16GBFBGA

CRITICAL

OMIT_TABLE

2

1 C2530

10VX5R402

1UF10%

2

1 C2531

10VX5R402

1UF10%

2

1 C251010%1UF

402X5R10V

2

1 C251110%1UF

402X5R10V

63

2

1 C2532

X5R-CERM

20%10UF

0603

25V

2

1 C2512

X5R-CERM

20%10UF

0603

25V

2

1 C2520

10VX5R402

1UF10%

2

1 C250010%0.1UF

X5R-CERM16V

0201

2

1 C2521

10VX5R402

1UF10%

2

1 C2501

16VX5R-CERM

0.1UF10%

0201

2

1 C2522

10VX5R402

1UF10%

2

1 C250210%1UF

402X5R10V


LPDDR3 DRAM Channel B (0-31)

PP0V6_S3_MEM_VREFCA_BPP0V6_S3_MEM_VREFDQ_B

MEM_B_ZQ<1>MEM_B_ZQ<0>

MEM_B_ODT<0>

=MEM_B_DQS_P<3>

=MEM_B_DQS_P<1>=MEM_B_DQS_P<2>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<3>=MEM_B_DQS_N<2>


=MEM_B_DQ<31>=MEM_B_DQ<30>=MEM_B_DQ<29>

=MEM_B_DQ<27>=MEM_B_DQ<28>

=MEM_B_DQ<26>=MEM_B_DQ<25>=MEM_B_DQ<24>=MEM_B_DQ<23>=MEM_B_DQ<22>=MEM_B_DQ<21>=MEM_B_DQ<20>=MEM_B_DQ<19>=MEM_B_DQ<18>=MEM_B_DQ<17>=MEM_B_DQ<16>=MEM_B_DQ<15>=MEM_B_DQ<14>=MEM_B_DQ<13>=MEM_B_DQ<12>


=MEM_B_DQ<9>=MEM_B_DQ<8>=MEM_B_DQ<7>=MEM_B_DQ<6>=MEM_B_DQ<5>=MEM_B_DQ<4>



MEM_B_CS_L<1>

PP1V2_S3

PP1V2_S3

PP1V2_S3

PP1V8_S3

MEM_B_CS_L<0>

MEM_B_CLK_N<0>MEM_B_CLK_P<0>

MEM_B_CKE<1>MEM_B_CKE<0>

MEM_B_CAA<9>MEM_B_CAA<8>MEM_B_CAA<7>MEM_B_CAA<6>MEM_B_CAA<5>MEM_B_CAA<4>MEM_B_CAA<3>MEM_B_CAA<2>MEM_B_CAA<1>MEM_B_CAA<0>

PP1V2_S3

PP1V2_S3

PP1V2_S3

PP1V8_S3

22 OF 76

25 OF 121

<BRANCH>

<E4LABEL>

<SCH_NUM>

18 19 23 70

18 19 23 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

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IN

IN

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(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0

CA1

CA2

CA3

CA4

CA6

CA7

CA8

CA9

CKE0

DM0

DM2

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA

VREFDQ

ZQ0

ZQ1

CS0*

CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

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REVISION

BRANCH

6 3



LPDDR3 CHANNEL B (32-63)

PLACEMENT_NOTE:

Distribute evenly.10uF caps are shared between DRAM.

63

2

1 C2623

25V

0603

10UF20%

X5R-CERM

2

1 C260310%1UF

402X5R10V

2

1 C260410%1UF

402X5R10V

2

1 C260510%1UF

402X5R10V

2

1 C2606


7 22 24 63 70

63

2

1R2600243

1%1/20W

MF201 2

1R2601

201MF

1/20W

2431%

2

1C264010%

6.3VX5R

0.047UF

2012

1 C2641

6.3VX5R

10%0.047UF

201

63

63

63

7 63 70

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

63

7 63 70

63

63

63

7 63 70

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

24 63 70

7 24 63 70

24 63 70

63

24 63 70

24 63 70

7 24 70

7 24 70

7 24 70

7 24 70

7 22 24 70

7 22 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2600

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

LPDDR3-16GBFBGA

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2600

EDFA232A1MA-GD-F

LPDDR3-16GBFBGA

CRITICAL

OMIT_TABLE

2

1 C2630

10VX5R402

1UF10%

2

1 C2631

10VX5R402

1UF10%

2

1 C261010%1UF

402X5R10V

2

1 C261110%1UF

402

10VX5R

63

2

1 C2632

X5R-CERM

20%10UF

0603

25V

2

1 C2620

10VX5R402

1UF10%

2

1 C260010%0.1UF

X5R-CERM16V

0201

2

1 C2621

10VX5R402

1UF10%

2

1 C2601

16VX5R-CERM

0.1UF10%

0201

2

1 C2622

10VX5R402

1UF10%

2

1 C260210%1UF

402X5R10V

LPDDR3 DRAM Channel B (32-63)SYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB

PP0V6_S3_MEM_VREFDQ_BPP0V6_S3_MEM_VREFCA_B

MEM_B_ZQ<2>MEM_B_ZQ<3>

MEM_B_DQS_P<6>

=MEM_B_DQS_P<5>=MEM_B_DQS_P<6>

=MEM_B_DQS_P<4>

MEM_B_DQS_N<6>=MEM_B_DQS_N<6>




=MEM_B_DQ<58>=MEM_B_DQ<57>=MEM_B_DQ<56>=MEM_B_DQ<55>=MEM_B_DQ<54>=MEM_B_DQ<53>=MEM_B_DQ<52>=MEM_B_DQ<51>=MEM_B_DQ<50>=MEM_B_DQ<49>=MEM_B_DQ<48>=MEM_B_DQ<47>=MEM_B_DQ<46>=MEM_B_DQ<45>=MEM_B_DQ<44>


MEM_B_DQ<33>=MEM_B_DQ<40>=MEM_B_DQ<39>=MEM_B_DQ<38>=MEM_B_DQ<37>=MEM_B_DQ<36>



PP1V2_S3

PP1V2_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

MEM_B_CAB<0>MEM_B_CAB<1>MEM_B_CAB<2>MEM_B_CAB<3>MEM_B_CAB<4>MEM_B_CAB<5>MEM_B_CAB<6>MEM_B_CAB<7>MEM_B_CAB<8>MEM_B_CAB<9>


MEM_B_CLK_P<1>MEM_B_CLK_N<1>

MEM_B_CS_L<1>

PP1V2_S3

PP1V2_S3

PP1V8_S3

MEM_B_CS_L<0>

MEM_B_ODT<0>

26 OF 121

<SCH_NUM>

<E4LABEL>

<BRANCH>

23 OF 76

18 19 22 70

18 19 22 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

NC NC NCNC

Apple Inc.


124578

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Spare Spare

Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

2

1 C27020.47UF4V20%

CERM-X5R-1201

2

1 C2704

201

0.47UF

CERM-X5R-1

20%4V

2

1 C2700

201

4V20%0.47UF

CERM-X5R-1

2

1 C2701

CERM-X5R-1

0.47UF

201

4V20%

2

1 C2703

CERM-X5R-14V20%

201

0.47UF

2

1 C2706

201CERM-X5R-14V20%0.47UF

2

1 C2705

CERM-X5R-1

0.47UF4V20%

201

2

1 C2707

4V

201

0.47UF

CERM-X5R-1

20%

2

1 C270920%

CERM-X5R-1201

4V

0.47UF

20 63 70

7 20 63 70

20 63 70

7 20 70

7 20 70

7 20 70

7 21 70

21 63 70

21 63 70

21 63 70

20 63 70

7 20 70

20 63 70

20 63 70

21 63 70

20 63 70

7 21 63 70

21 63 70

21 63 70

21 63 70

63RP27014X0201-HF1/32W5%

5620 63 70

20 63 70

21 63 70

21 63 70

2

1 C2708

CERM-X5R-1201

20%4V

0.47UF

54RP27014X0201-HF5%

561/32W

72RP27014X0201-HF1/32W5%

5681RP2701

4X0201-HF1/32W5%56

22 63 70

2

1 C2712

201

20%4VCERM-X5R-1

0.47UF

2

1 C2714

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2716

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2718

4V

201

20%0.47UF

CERM-X5R-1

2

1 C2719

CERM-X5R-1201

4V20%0.47UF

2

1 C27170.47UF

201

20%4VCERM-X5R-1

2

1 C2715

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2713

4V20%

201

0.47UF

CERM-X5R-1

2

1 C2711

201

20%4V

0.47UF

CERM-X5R-1

2

1 C2710

201

4VCERM-X5R-1

20%0.47UF

54RP27124X0201-HF5%

561/32W

22 63 70

22 63 70

7 22 63 70

22 63 70

7 22 70

7 22 70

7 22 70

7 22 70

22 63 70

22 63 70

22 63 70

22 63 70

22 63 70

23 63 70

23 63 70

23 63 70

7 23 63 70

23 63 70

7 23 70

7 23 70

7 23 70

7 23 70

23 63 70

23 63 70

23 63 70

23 63 70

7 21 70

7 21 70

7 21 70

23 63 70

7 22 23 70

7 22 23 70

7 22 23 63 70

20 63 70

7 20 21 70

7 20 21 70

7 20 21 63 70

21R2700 562015% 1/20W MF

21R27011/20W5% 201 MF

3921R2702

5% 2011/20W MF39

21R2703 825% 2011/20W MF

21R27045% MF1/20W 201

8221R2705

5%56

MF1/20W 20121R2706

5%56

1/20W MF20154RP27034X0201-HF5%

561/32W63RP2703

4X0201-HF5%56

1/32W72RP27034X0201-HF

565% 1/32W

54RP27074X0201-HF5%

561/32W63RP2707

4X0201-HF5%56

1/32W72RP27074X0201-HF5%

561/32W81RP2707

4X0201-HF5%56

1/32W21R2707

5%39

MF1/20W 20121R2708

5%39

1/20W MF20121R2709

5%82

MF1/20W 20121R2720

5% 1/20W82

MF20121R2721

5%56

201 MF1/20W54RP27044X0201-HF5%

561/32W63RP2704

4X0201-HF5%56

1/32W72RP27044X0201-HF5%

561/32W81RP2704

4X0201-HF5%56

1/32W21R2722

5%82

MF1/20W 20121R2723

5%82

1/20W 201 MF21R2724

5%82

201 MF1/20W

63RP27124X0201-HF5%

561/32W72RP2712

4X0201-HF5%56

1/32W81RP27124X0201-HF5%

561/32W

21R27105%

56MF1/20W 201

21R27115%

39MF1/20W 201

21R27125% 1/20W MF

39201

21R27135%

82MF1/20W 201

21R27145%

82MF1/20W 201

21R27155%

56MF1/20W 201

21R27165%

561/20W MF20154RP2713

4X0201-HF5%56

1/32W63RP27134X0201-HF5%

561/32W72RP2713

4X0201-HF5%56

1/32W

54RP27174X0201-HF5%

561/32W63RP2717

4X0201-HF5%56

1/32W72RP27174X0201-HF5%

561/32W81RP2717

4X0201-HF5%56

1/32W21R2717

5%39

MF1/20W 20121R2718

5% 1/20W MF39

20121R2719

5%82

MF1/20W 20121R2730

5%82

MF1/20W 20121R2731

5%56

201 MF1/20W54RP27144X0201-HF5%

561/32W63RP2714

4X0201-HF5%56

1/32W72RP27144X0201-HF5%

561/32W81RP2714

4X0201-HF5%56

1/32W21R2732

5%82

MF1/20W 20121R2733

5%82

MF1/20W 20121R2734

5% 1/20W MF82

201

21R27255%

561/20W MF201

21R27355%

562011/20W MF

2

1 C2720CRITICAL

22UF

X5R-CERM-1603

20%6.3V

PLACE_NEAR=RP2701.5:4mm

2

1 C2740

6.3VX5R-CERM-1

22UF

603

20%

CRITICALPLACE_NEAR=RP2714.8:4mm

81

RP2703

1/32W4X0201-HF

56

5%

81

RP2713

1/32W4X0201-HF

56

5%


LPDDR3 DRAM Termination

MEM_B_ODT<0>MEM_B_CS_L<1>MEM_B_CS_L<0>MEM_B_CAB<0>

MEM_B_CAB<3>MEM_B_CAB<1>

MEM_B_CAB<2>MEM_B_CAB<4>MEM_B_CKE<3>MEM_B_CKE<2>MEM_B_CLK_P<1>MEM_B_CLK_N<1>MEM_B_CAB<5>MEM_B_CAB<6>MEM_B_CAB<7>MEM_B_CAB<8>MEM_B_CAB<9>MEM_B_CAA<0>MEM_B_CAA<1>MEM_B_CAA<3>MEM_B_CAA<2>MEM_B_CAA<4>

PP0V6_S0_DDRVTT


MEM_B_CLK_P<0>MEM_B_CLK_N<0>

MEM_B_CAA<5>MEM_B_CAA<6>MEM_B_CAA<7>MEM_B_CAA<8>MEM_B_CAA<9>

MEM_A_ODT<0>MEM_A_CS_L<1>MEM_A_CS_L<0>MEM_A_CAB<0>MEM_A_CAB<1>MEM_A_CAB<3>MEM_A_CAB<2>MEM_A_CAB<4>MEM_A_CKE<3>MEM_A_CKE<2>MEM_A_CLK_N<1>MEM_A_CLK_P<1>MEM_A_CAB<5>MEM_A_CAB<7>

MEM_A_CAB<8>MEM_A_CAB<6>

MEM_A_CAB<9>MEM_A_CAA<0>MEM_A_CAA<1>MEM_A_CAA<2>MEM_A_CAA<3>MEM_A_CAA<4>

PP0V6_S0_DDRVTT

MEM_A_CKE<0>MEM_A_CKE<1>MEM_A_CLK_N<0>MEM_A_CLK_P<0>MEM_A_CAA<5>MEM_A_CAA<7>MEM_A_CAA<6>

MEM_A_CAA<9>MEM_A_CAA<8>

<BRANCH>

<SCH_NUM>

<E4LABEL>

27 OF 121

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24 53 62 24 53 62

www.vinafix.vn

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

BI

BI

IN

IN

IN

IN

OUT

OUT

OUT

BI

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PETN_3

PETN_2

PETP_2

PETP_1

PETN_1

PETP_0

PETN_0

MONOBS_N

MONDC0

MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0

PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P

PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI

EE_DO

EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P

REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS

TCK

TEST_EN

TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N

PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0

SINK PORT 1

SOURCE PORT 0

PORT3

PORT2

PORT0

PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

IN

IN

OUT

IN

BI

IN

D

C

Q

S*

W*

HOLD*

PADVSS THM

VCC

IN

OUT

OUT

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.


124578

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SHEET


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



DEBUG: For monitoring current/voltage

SNK0 AC Couplingif necessary.of GPIO_2/GPIO_9allows separationR2881 for CYA,

Divides 3.3V to 1.8V

5 - PCIE_RST_1_N6 - PCIE_RST_2_N7 - PCIE_RST_3_N

4 - GPIO_5

0 - GPIO_131 - GPIO_12 - GPIO_23 - GPIO_3

15 - PB_LSRX14 - PB_LSTX13 - GPIO_1012 - GPIO_1211 - GPIO_010 - GPIO_149 - GPIO_11

Not used in host mode.

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

SNK1 AC Coupling

(FORCE_PWR)

(TBT_SPI_CS_L)

(TBT_SPI_MOSI) (TBT_SPI_MISO)

8 - GPIO_15NOTE: The following pins require testpoints:

(TBT_EN_CIO_PWR_L)

Stuff one of R2881/2.

(TBT_SPI_CLK)

2

1R28905%

201

1/20WMF

3.3K

13

13 18

2

1R28255%0

0201

1/20WMF

2

1R28325%

201

1/20WMF

100K

28

28 71

28 71

28 71

28 71

28 71

28 71

28 71

28 71

18

64

64

18

64

64

64

64

64

64

2

1R28305%

201

1/20WMF

100K

2

1R28315%

201

1/20WMF

100K

28 71

28 71

2

1R28295%0

0201

1/20WMF

2

1R28935%

201

1/20WMF

3.3K

21C282902010.1UF X5R-CERM

16V10%13 67

13 67

5 67

5 67

5 67

5 67

5 67

5 67

5 67

5 67

21C282802010.1UF X5R-CERM

10% 16V

21C282702010.1UF X5R-CERM

16V10%

21C282602010.1UF X5R-CERM

10% 16V

21C282502010.1UF X5R-CERM

16V10%

21C28240201

X5R-CERM0.1UF 10% 16V

21C282302010.1UF X5R-CERM

16V10%

21C282202010.1UF X5R-CERM

10% 16V

2

1R2855

201

1/20WMF

1%1K

21C282102010.1UF X5R-CERM

16V10%

21C282002010.1UF X5R-CERM

16V10%

21C283002010.1UF X5R-CERM

16V10%

21C283102010.1UF X5R-CERM

16V10%

21C283202010.1UF X5R-CERM

16V10%

21C283302010.1UF X5R-CERM

16V10%

21C28340201

X5R-CERM0.1UF 16V10%

21C283502010.1UF X5R-CERM

16V10%

21C283602010.1UF X5R-CERM

16V10%

21C283702010.1UF X5R-CERM

16V10%

21C283802010.1UF X5R-CERM

16V10%

21C28390201

X5R-CERM0.1UF 16V10%

5 18 67

5 18 67

5 18 67

5 18 67

5 18 67

5 18 67

5 18 67

5 18 67

2

1C28901UF10%

6.3VCERM402

BYPASS=U2890.8:2mm

13 18 67

13 18 67

28

28

64

18

27

64 71

64 71

18

15 16 18

15 18

15 16 18

15 18

28 71

28 71

28 71

28 71

28

25 27 28

28

25 28

25

18

25

13 25 27

33 37 38

AB23

AA24

AA4

Y3

AB3

Y7

AB5

N4

R2

V1

AA6

U20

AB21AD21

W20J2

AD17

AD13

AD9

AD5

AD19

AD15

AD11

AD7

R6

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

U2

Y5

T1

N6

W6

L6

G6

K3

A22

B23

A20

B21

H5

P1

W24

U24

W22

U22

R24

N24

R22

N22

D1

E2

N2

J6

H1

A18

B19

A16

B17

G4

K1

L24

J24

L22

J22

G24

E24

G22

E22

F3

F1

U4

W18

W16

AC24

AD23

M5

P3

AC2

AB1

AA2

J4

W2

Y1

M1

V5

T3

L4H3

L2M3

G2

K5

P5

R4

AD3

W4

V3

C2

D3

A14

B15

A12

B13

A10

B11

A8

B9

T5

A4

B3

E6

D5

E8

D7

E10

D9

E12

D11

U6

A6

B5

E14

D13

E16

D15

E18

D17

E20

D19

U2800CACTUSRIDGE4C

FCBGA

OMIT_TABLE

CRITICAL

27

17 69

2

1R28985%

201

1/20WMF

10K

21

R2895

201

1/20WMF

1%

806

2

1R28965%

201

1/20WMF

1K

2

1R28995%

201

1/20WMF

NO STUFF

10K

12 69

12 69

27

14 16 19 40 56 69

14 16 19 40 56 69

27

3

4

8

9

1

2

7

5

6

U2890MLP

CRITICAL

M95256-RMC6XG

OMIT_TABLE

2

1R28975%

201

1/20WMF

100K

2

1R2815NONE

NOSTUFFNONENONE

OMIT

0201

2

1R28885%

201

1/20WMF

10K

2

1R28875%

201

1/20WMF

10K

2

1R28865%

201

1/20WMF

10K

2

1R28855%

201

1/20WMF

10K

2

1R28805%

201

1/20WMF

10K

2

1R28825%

201

1/20WMF

NO STUFF

10K15

25

2

1C2810NO STUFF

16V

0.1UF10%

X5R-CERM0201

2

1R28105%

201

1/20WMF

47K

15 18

13 25 27

2

1R28835%

201

1/20WMF

10K

2

1R28815%0

0201

1/20WMF

15 18 25

28

21C2801020110%

16V

0.1UF X5R-CERM

21C2800020110%0.1UF

16VX5R-CERM

21C2802020110%0.1UF

16VX5R-CERM

21C2803020110%

16VX5R-CERM0.1UF

2

1R28925%

201

1/20WMF

3.3K

21C280402010.1UF 10%

16VX5R-CERM

21C280502010.1UF 10%

16VX5R-CERM

21C2806020110%0.1UF

16VX5R-CERM

21C2807020110%0.1UF

16VX5R-CERM

21C284016V10% X5R-CERM 02010.1UF

21C284116V10% X5R-CERM0.1UF 0201

21C284216V10% X5R-CERM 02010.1UF

2

1R28915%

201

1/20WMF

3.3K

21C284310% X5R-CERM 020116V0.1UF

21C284516V10% X5R-CERM0.1UF 0201

21C284416V10%0.1UF X5R-CERM 0201

21C284610% 16V X5R-CERM 02010.1UF21C284710% 16V X5R-CERM 02010.1UF

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

14 69

Thunderbolt Host (1 of 2)SYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB

NC_DP_TBTSRC_ML_CP<1>

DP_TBTSRC_HPD

TBT_GO2SX_BIDIRTBT_PWR_ENSMC_PME_S4_DARK_L

TBT_EN_CIO_PWR_LMAKE_BASE=TRUE

TBT_TMU_CLK_OUT

SYSCLK_CLK25M_TBT_R

NC_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_AUXCH_CP

PP3V3_TBTLC

SYSCLK_CLK25M_TBT

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<2>

TBT_SPI_CLK

TBT_SPI_MOSI

TBT_SPI_CS_L

TBTROM_WP_L

TBT_SPI_MISO

TBT_PWR_ON_POC_RST_L

PCIE_TBT_D2R_C_P<0>PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_R2D_N<0>PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<1>PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<2>

TBT_TMU_CLK_IN

TBT_RBIAS

PCIE_TBT_D2R_C_P<2>

PP3V3_TBTLC


DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_C_N<3> DP_TBTSNK0_ML_N<3>


PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_N<2>PCIE_TBT_R2D_C_N<2>

TBT_EN_CIO_PWR_L

TP_DP_TBTSRC_ML_CP<3>

TBT_CLKREQ_ISOL_L

PCIE_CLK100M_TBT_P

TBT_GPIO_14

TBT_B_HV_ENTBT_A_HV_EN

TBT_A_DP_PWRDNTBT_B_DP_PWRDN

SMBUS_PCH_DATA

TBT_GPIO_9

TBT_DDC_XBAR_EN_L

TP_DP_TBTSRC_ML_CP<0>

PCIE_CLK100M_TBT_N

PCIE_TBT_R2D_C_P<2>

TP_TBT_PCIE_RESET2_LTP_TBT_PCIE_RESET1_L

DP_TBTPA_AUXCH_C_N

DP_TBTPA_ML_C_N<3>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>












TBT_B_DP_PWRDNTBT_B_CIO_SELTBT_B_HV_EN

NC_DP_TBTPB_AUXCH_CN

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_N<1>DP_TBTPB_ML_C_P<1>

NC_TBT_B_D2RN<1>NC_TBT_B_D2RP<1>

NC_TBT_B_R2D_CN<1>NC_TBT_B_R2D_CP<1>

NC_TBT_B_D2RN<0>

NC_TBT_B_R2D_CN<0>

TP_DP_TBTSRC_ML_CP<2>TP_DP_TBTSRC_ML_CN<2>

NC_DP_TBTSRC_AUXCH_CN

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_C_N<2>

DP_TBTSNK1_HPD

DP_TBTPA_ML_C_P<3>

TBT_A_D2R_N<1>

TBT_A_R2D_C_N<0>TBT_A_R2D_C_P<0>

TP_TBT_THERM_DP

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_N<3>DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_N

TBT_RSENSE

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<1>

TBT_A_D2R_N<0>

NC_DP_TBTPB_AUXCH_CP

DP_TBTPB_ML_C_N<3>

NC_TBT_B_LSTXTBT_B_LSRX

TBT_A_D2R_P<0>


DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

TP_TBT_PCIE_RESET0_L

TP_TBT_XTAL25OUT

PCIE_TBT_R2D_P<3>

SMBUS_PCH_CLK

DP_TBTSNK1_ML_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_N<3>





DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK1_ML_P<2>DP_TBTSNK1_ML_N<2>

DP_TBTSNK0_HPD

PCIE_TBT_R2D_C_P<3>

TP_TBT_PCIE_RESET3_L

TBT_EN_LC_PWR

JTAG_ISP_TDO

XDP_JTAG_ISP_TDIJTAG_TBT_TMS

TP_TBT_MONDC1TP_TBT_MONDC0

PCIE_TBT_R2D_N<3>

TBT_TEST_PWR_GOOD

XDP_JTAG_ISP_TCKTBTROM_HOLD_L

TBT_A_DP_PWRDNTBT_A_CIO_SELTBT_A_HV_EN

NC_TBT_B_R2D_CP<0>

DP_TBTSNK1_ML_N<0>

PP3V3_S4_TBTAPWRTBT_GPIO_14

TBT_MONOBSPTBT_MONOBSN

PP3V3_S4_TBTAPWR

TBT_CIO_PLUG_EVENT

TBT_TEST_EN

DP_TBTSNK0_ML_P<3>

DP_TBTPB_HPD

NC_TBT_B_D2RP<0>

PCIE_TBT_D2R_N<3>

PP3V3_TBTLC

TBT_DDC_XBAR_EN_L

TBT_GPIO_9

TBT_GO2SX_BIDIR

TP_DP_TBTSRC_ML_CN<3>


TBT_PCIE_RESET_L

DP_TBTPA_ML_C_N<1>DP_TBTPA_ML_C_P<1>

TBT_A_LSRXTBT_A_LSTX

TBT_A_D2R_P<1>


TBT_A_CONFIG1_BUFTBT_A_CONFIG2_RC

TBT_B_CONFIG1_BUFTBT_B_CONFIG2_RC

25 OF 76

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<E4LABEL>

<SCH_NUM>

<BRANCH>

64

69

64

64

64

15 17 25 26 27 62 64

69

71

71

71

71

69

69

69

69

69

69

69

69 69

15 17 25 26 27 62 64

25 67

25 67

69

64

25

25

25 27 28

25 28

25

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25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

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64

64

69

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

25 67

69

25 67

69

69

25 67

25 67

25 67

25 67

69

25 67

25 26 27 28 62 25

25 26 27 28 62

25 67

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VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VCC1P0_DPAUX

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0

VCC1P0

VCC3P3_DP

VCC3P3_DP

VCC3P3_DP

VCC3P3_CIO

VCC3P3_CIO

VCC3P3_CIO

VCC3P3

VCC3P3

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC3P3

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCC

GND

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EDP: 1600 mA

EDP: 1100 mA

EDP: 50 mA

??? mW (Single Port)250 mW (Dual Port)

???? mW (Single-Port)2700 mW (Dual-Port)

250 mW (Dual-Port)??? mW (Single-Port)

EDP: 10 mA

Power consumption figures from CR DG v0.57, IBL doc #472455.EDP numbers are from 12/22/2011 email from Haim Lustig (Intel) to Paul Baker (Apple)

2

1C294520%

1.0UF

X5R6.3V

0201-1

2

1 C291620%1.0UF

X5R6.3V

0201-1

2

1 C290520%10UF

0402-1CERM-X5R6.3V

2

1C297320%

1.0UF

X5R6.3V

0201-12

1C297420%

1.0UF

X5R6.3V

0201-1

2

1 C291720%1.0UF

X5R6.3V

0201-1

2

1 C291320%1.0UF

X5R6.3V

0201-12

1C290010UF

20%

CERM-X5R6.3V

0402-1

2

1C290120%

10UF

CERM-X5R6.3V

0402-12

1 C2914

6.3VX5R

1.0UF20%

0201-12

1 C291520%1.0UF

X5R6.3V

0201-1

AC10

AB7

Y9

Y23

Y21

Y19

AB17

Y17

Y15

Y13

Y11

V23

V21

V17

V13

U18

T23

AB11

T21

R20

P23

P21

N20

M23

M21

L20

K23

K21

AA8

J20

J18

H23

H21

G20

F9

F7

F5

F23

F21

AA22

F19

F17

F15

F13

F11

E4

D23

D21

C8

C6

AA20

C4

C24

C22

C20

C18

C16

C14

C12

C10

B7

AA14

B1

AC8

AC6

AC4

AC22

AC20

AC18

AC16

AC14

AC12

A24

A2

N12

M9

M17

M13

L8

L16

L12

V9

U8

U16

U12

T9

K9

T17

T13

R8

R16

R12

P9

P17

P13

N8

N16

K13

AD1

K7

H7

H17

H15

H13

H11

R18

N18

L18

T7

P7

M7

T19

P19

M19

K19

H19

G18

G16

G14

W14

W12

V19

V15

G12

G10

W8

V7

U14

T15

K17

J8

J16

J14

J12

J10

H9

G8

P15

P11

N14

N10

M15

M11

L14

L10

W10

V11

U10

T11

R14

R10

K15

K11

U2800OMIT_TABLE

CACTUSRIDGE4CFCBGA

CRITICAL

2

1 C296020%10UF

0402-1CERM-X5R6.3V2

1C297220%

1.0UF

X5R6.3V

0201-12

1C297120%

1.0UF

X5R6.3V

0201-1

2

1 C291020%1.0UF

X5R6.3V

0201-1

2

1C297020%

1.0UF

X5R6.3V

0201-1

2

1C299020%

1.0UF

X5R6.3V

0201-1

2

1 C291120%1.0UF

X5R6.3V

0201-12

1 C291220%1.0UF

X5R6.3V

0201-12

1C294420%

1.0UF

X5R6.3V

0201-12

1C294320%

1.0UF

X5R6.3V

0201-12

1C294220%

1.0UF

X5R6.3V

0201-12

1C294120%

1.0UF

X5R6.3V

0201-12

1C294020%

1.0UF

X5R6.3V

0201-1

Thunderbolt Host (2 of 2)SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013

PP3V3_S4_TBTAPWR

PP1V05_TBTCIO

PP1V05_TBTLC

PP3V3_TBTLC

<BRANCH>

<SCH_NUM>

<E4LABEL>

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IN

IN

S

G

D

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND GND

NC

SNS1

SNS2

OUT

IN

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE+-

PAD

(OD)

0.7V

DLY

IN

OUT

IN

GND

VOUT

ON

VIN

OUTSENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

VOUT

GNDON

VIN

IN

IN

SYM_VER_2

G S

D

D

SYM_VER_3

SG

S

D

G

S

D

G

G

D S

S

D

G

VOUT

GNDON

VIN

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1.05V TBT "LC" Switch

3.3V TBT "LC" Switch

Load Switch

TPS22924C

U3010Max Current = 2A (85C)

Power aliases required by this page:

BOM options provided by this page:

for 2S.

UVLO(falling) = 1.22 * (R1 + R2) / R2

TBT 15V Boost Regulator

Platform (PCIe) Reset

Pull-up provided by SB page.

TPS3808G25Vt = 2.33V +/- 2%Delay = 27.3ms

Max Vgs: 10V

add property on another page.Voltage not specified here,

Rds(on): 46mOhm @ 4.5V Vgs

Vds(max): -30VSI8409DB:

Vgs(max): +/-12V

Id(max): 3.7A @ 70C

Vgs(th): -1.4V

<R1>

UVLO = 4.55V (falling), 4.95 (rising)UVLO(rising) = UVLO(falling) + (2uA * R1)

<R2>

- =PP3V3_TBT_FET (3.3V FET Output)- =PP3V3_S0_TBTPWRCTL- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

Signal aliases required by this page:

- =TBT_RESET_L- =TBT_CLKREQ_L

- =PPVIN_SW_TBTBST (8-13V Boost Input)- =PP15V_TBT_REG (15V Boost Output)

(NONE)

Load Switch

U3020TPS22920

Max Current = 4A (85C)

R(on)

Type

Part

1.05V TBT "CIO" Switch

Vout = 15.1VMax Current = 1.0AFreq = 300KHz

<Ra>

<Rb>

Vout = 1.6V * (1 + Ra / Rb)

GND inside package,

no XW necessary.

SGND shorted to

Load Switch

@ 1.05VR(on)

Type

Part


18.5 mOhm Typ

Type

Part

DLY = 60 ms +/- 20%

Supervisor & CLKREQ# Isolation

8-13V InputChanges required

- =PP1V05_TBT_FET (1.05V FET Output)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

Page Notes

Pull-up: R2810

TBT "POC" Power-up Reset

(IPU)

@ 2.5VR(on)

TPS22920

U3015

25.8 mOhm Max

@ 1.05V6.1 mOhm Typ10.4 mOhm Max

6.1 mOhm Typ10.4 mOhm Max

25 28

2

1R30805%

201

1/20WMF

470K

2

1 C30800.1UF

402X5R25V10%

2

1R3092

201

1/20WMF

73.2K1%

2

1R30875%

201

1/20WMF

330K

2

1R3094

201

1/20WMF

41.2K1%

2

1 C30940.33UF

402CERM-X5R6.3V10%

2

1R30885%

201

1/20WMF

330K

17 37 38

2

1 C30895%

NO STUFF

100PF

402CERM50V

2

1R309615.8K

1%1/16WMF-LF

402

2

1 C309510UF25V20%

0603X5R-CERM

2

1 C30875%47PF25VNP0-C0G-CERM0201

2

1C30922.2UF

402

10V20%

X5R-CERM

4

1

32

Q3080CRITICAL

BGASI8409DB

2

1R3091

201

1/20WMF

200K1%

2

1C309010UF

0603

25V20%

X5R-CERM 2

1C309110UF

0603

25V20%

X5R-CERM

2

1 C30885%50VCERM0402

22PF

27

30

34

38

21

2098

32

37

24

23

4

3

6

33

36

35

10

2

1

28

17

16

15

14

13

12

31

25

U3090CRITICAL

LT3957QFN

2 1

XW3095SM

PLACE_NEAR=C3095.1:2 mm

21

R3089

5%

0

0201

1/20WMF

KA

D3095POWERDI-123

DFLS230L

CRITICAL

2

1 C30990.001UF

0402X7R-CERM50V10%

2

1 C3093

X7R-CERM10V

3300PF

0201

10%

2

1R30815%

201

1/20WMF

150K

2

1R3093

201

1/20WMF

10K1%

2

1R3095133K

1%1/16WMF-LF

402

21

L3095

PIMB062D-SM

6.8UH-4.0A

CRITICAL

25

25 27

2

1R30075%

201

1/20WMF

100K

1

9

2

4

8

3

7

5

6

U3000

CRITICAL

SLG4AP016VTDFN

2

1C3000

16V

0.1UF

X5R-CERM0201

10%

15 18

12

25

B1

A1

B2

A2

C2

C1

U3010CSP

TPS22924

CRITICAL

2

1C301020%

1.0UF

0201-1X5R

6.3V

2

1C3015

6.3VX5R

0201-1

20%1.0UF

2

1C3016

6.3VX5R

0201-1

1.0UF20%

NO STUFF

2

1R30305%

201

1/20WMF

100K

25

1

7

2 6

4

5

3

U3030QFN

CRITICAL

TPS3808

2

1C30300.1UF

16VX5R-CERM

0201

10%

C1

B1

A1

C2

B2

A2

D2

D1

U3020CSP

TPS22920

CRITICAL

2

1C3020

6.3VX5R

0201-1

1.0UF20%

2

1 C30310.0047UF

0402CERM25V10%

2

1R30205%

201

1/20WMF

100K

13 25

15

1

2R3090

MF-LF1/16W

1%49.9K

402

21

R3016

5%

0

0201

1/20WMF

2

1R30405%

201

1/20WMF

10K

2

1C3025

16VX7R-CERM

330PF

0201

10%

2

1 C30822.2UF

402

10V20%

X5R-CERM

2

1C308120%10V

402

2.2UF

X5R-CERM2

1C309610UF

0603

25V20%

X5R-CERM

2

1 C309710UF

0603

25V20%

X5R-CERM

2

1C309810UF

0603

25V20%

X5R-CERM

2

1 C308410UF

0603

25V20%

X5R-CERM

2

1C308520%25V

0603

10UF

X5R-CERM 2

1C309B10UF

0603

25V20%

X5R-CERM

2

1 C309A20%25V

0603

10UF

X5R-CERM

2 1

R3011

201

1/20WMF

36.5K

1%

2

1C3011

6.3VX5R

0201-1

1.0UF20%

21

3Q3005DFN1006H4-3

DMN32D2LFB4

21

3

Q3040DMN32D2LFB4

DFN1006H4-3

12

6 Q3088SOT-563DMN5L06VK-7

45


45

3

Q3025SOT-563

DMN5L06VK-7

12

6Q3025SOT-563

DMN5L06VK-7

C1

B1

A1

C2

B2

A2

D2

D1

U3015

CRITICAL

CSPTPS22920


TBT Power Support

TBT_POC_RESET_L

SMC_DELAYED_PWRGD

TBTPOCRST_MR_L

PP3V3_S0TBT_PWR_ON_POC_RST_L

PP3V3_S0

TBT_EN_LC_PWR


TBT_CLKREQ_L

TBT_PCIE_RESET_L

TBT_CLKREQ_ISOL_L

TBT_EN_LC_ISOL

MAKE_BASE=TRUETBT_CLKREQ_ISOL_L

TBT_EN_LC_RC3V3

PP3V3_S0 PP3V3_TBTLC

TBT_EN_LC_RC1V05

PP1V05_S0 PP1V05_TBTLC

PP1V05_TBTLC

PP3V3_TBTLC

TBTBST_VSNS_RC

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmTBTBST_FBX

PP15V_TBT

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmTBTBST_INTVCC

PP1V05_S0

TBTBST_SNS2MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm

TBTBST_VC_RC

TBTBST_VCMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

TBTBST_SS

PP3V3_S4_TBTAPWR

TBTPOCRST_CT

SWITCH_NODE=TRUEDIDT=TRUE

TBTBST_BOOSTMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmTBTBST_VSNS

TBTBST_SNS1MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR

PP1V05_TBTCIO

PP3V3_TBTLC

TBTBST_SHDN_DIV

PPVIN_S4SW_TBTBST_FETMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

TBTBST_EN_UVLO

TBTBST_RT

TBT_A_HV_EN

TBTBST_PWREN_DIV_L

PPBUS_G3H

TBTBST_PWREN_L

GND_TBTBST_SGND

VOLTAGE=0V


<BRANCH>

<SCH_NUM>

<E4LABEL>

30 OF 121

27 OF 76

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45

56 59 61 62 64 65 74

25 27

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43

44 45 56 59 61 62 64 65

74

15 17 25 26 27 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

26 27 62 64

26 27 62 64

15 17 25 26 27 62 64

28 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

25 26 28 62

26 62 64

15 17 25 26 27 62 64

62 64

41 42 49 50 56 62 64

www.vinafix.vn

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

BI

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

BI

IN

IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+

DPMLO-

HPD

THMPADGND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENATB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN

IN

IN

DP_PWR

AUX_CHP

ML_LANE3P

ML_LANE3N

CONFIG1

AUX_CHN

RETURN

GND GND

ML_LANE0N

ML_LANE0P

CONFIG2

HOT_PLUG_DETECT

GND

GND

GND

ML_LANE1P

ML_LANE1N

ML_LANE2P

ML_LANE2N

SHIELD PINS

V3P3

ISET_V3P3

OUT

THRMGND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD


Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



from Thunderbolt device attach.

514-0818

TBT Dir

down HPD input with

ILIM = 40000 / RISET

TBT: Unused

Sink HPD range:

(Both C’s)

DP Dir(Both C’s)

on AC-coupled signals.470k R’s for ESD protection

(Both C’s)

TBT Dir

(0-18.9V)

TBT: TX_0

(0-18.9V)

DP Dir

(Both C’s)

to 100K (DPv1.1a).

Low: 0 - 0.8VHigh: 2.0 - 5.0V

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(IPU)

(IPD)

(IPD)

(IPU)

Nominal Min Max

18.9V Max

Single-fault protection

below

ISET_Sx with CD3210.requires two R’s per HV

Single R on ISET_V3P3 OK.

12V: See

<RHVS0><RHVS3>

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) Nominal Min Max

For 12V systems:

TBT: TX_1

TBT: RX_0

TBT: LSX_R2P/P2R (P/N)

Thunderbolt Connector A

greater than or equal

DP Source must pull

TBT: RX_1

<RV3P3>

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

V3P3 must be S4 to support wake

IV3P3 1100mA 1030mA 1200mAIHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

3.3V/HV Power MUX

2

1C3200

50V10%

0402X7R-CERM

0.01UF

25 71

25 71

2

1 C3202

X5R-CERM0201

16V10%0.01UF

21

R3201

MF

5%1/20W

12

201

2

1 C3201

50V10%

0402X7R-CERM

0.01UF

2

1R3294GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

1/20W5%

201MF

1K

2

1R3295


GND_VOID=TRUE

1/20W5%

201MF

1K

2

1R3241

1/20W5%

201MF

100K

2

1 C328610UF

CERM-X5R

20%6.3V

0402-12

1C3285

16V10%

0201X5R-CERM

0.1UF

2

1 C3281

0201

0.1UF

X5R-CERM16V10%

2

1C328022UF

20%6.3V

603X5R-CERM-12

1C3287

6.3V20%

CASE-B2-SMPOLY-TANT

100UF

CRITICAL

2

1R3252

1/20W5%

201MF

1M

2

1R3251

1/20W5%

201MF

1M

2

1C3294

16V10%

0201X7R-CERM

330PF

2

1 C3295

16V10%

0201X7R-CERM

330PF

21

L3200

0603

CRITICAL

FERR-120-OHM-3A

25

2

1 C3210

25V10%

402X5R

0.1UF

2

1R3270470K

MF201

5%1/20W

GND_VOID=TRUE

2

1R3271470K

MF201

5%1/20W

GND_VOID=TRUE

21C32710.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

21C32700.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

25 71

25 71

21C32720.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

21C32730.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

2

1R3273470K

MF201

5%1/20W

GND_VOID=TRUE

2

1R3272470K

MF201

5%1/20W

GND_VOID=TRUE

25 27

18 58 59

57 59

2

1R32121%1/20W

201MF

36.5K

2

1 C3211

25V10%

402X5R

0.1UF

2

1C32200.1UF

0201

10%16V

X5R-CERM

25

13 18

13 18

25

25

25 71

25 71

25 71

25 71

21C32320.22UF 6.3V20%

0201X5R21C3233

0.22UF 6.3V20%0201X5R

25 71

25 71

21C32300.1UF 10% 16V

X5R-CERM020121C32310201

0.1UF X5R-CERM10% 16V

25 71

25 71

21C32780.22UF 6.3V20%

0201X5R21C3279

0.22UF 6.3V20%0201X5R

25 71

25 71

2

1R3211

201

TBTHV:P15V

1/20W1%

MF

22.6K

2

1R3210

1/20W1%

201MF

22.6K

TBTHV:P15V

2

1R3214TBTHV:P15V

22.6K

MF201

1%1/20W

2

1R3213TBTHV:P15V

22.6K

MF201

1%1/20W

2

1C3215

25V10%

0603X5R-CERM

4.7UF

2

1C32050.01UF

X5R-CERM0201

10%25V

GND_VOID=TRUE

2

1C3206GND_VOID=TRUE

25V10%

0201X5R-CERM

0.01UF

25

21C32744V

GND_VOID=TRUE

201CERM-X5R-10.47UF 20%

21C32752014V

GND_VOID=TRUE

CERM-X5R-10.47UF 20%

3

25

8

7 15

14

13

12 17

219

19

20

6

11

10

4

5

16 18

22

23

24

2

1

U3220

SIGNAL_MODEL=TBT_MUX

CBTL05024

CRITICAL

HVQFN24-COMBO

13

25

25

2

1R3279

1/20W5%

201MF

470K

2

1R3278

1/20W5%

201MF

470K

21C32772014V0.47UF 20%

GND_VOID=TRUE

CERM-X5R-121C3276

2014V0.47UF 20%

GND_VOID=TRUE

CERM-X5R-1

19

10

12

15

17

9

11

3

5

28

27

26

25

24

23

22

21

2

14 8

13 7

1

20

6

4

16

18

J3200

CRITICAL

MDP-J11F-RT-TH

7

6

18

20

19

21

17

14

12

8

9

1011

15

13321

416

5

U3210QFN

CRITICAL

CD3211A0RGPR

Thunderbolt Connector ASYNC_DATE=02/07/2013SYNC_MASTER=J41_MLB

TBTHV:P12VR3210,R32132118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

TBTHV:P12V118S0145 R3211,R32142 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

PP3V3_S4_TBTAPWRMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM

VOLTAGE=3.3V

TBTAPWRSW_ISET_S3_RTBTAPWRSW_ISET_S0_R

PP3V3RHV_S4_TBTAPWR_F

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM

TBT_A_D2R1_AUXDDC_P

DP_TBTPA_ML_P<3>DP_TBTPA_ML_N<3>

TBT_A_D2R1_AUXDDC_N

TBTACONN_7_CMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

TBT_A_R2D_N<0>TBT_A_R2D_P<0>

TBT_A_HPD

TBTACONN_1_CMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

DP_A_LSX_ML_P<1>DP_A_LSX_ML_N<1>

TBT_A_D2R_P<1>TBT_A_D2R_C_P<1>

TBT_A_D2R_N<1>TBT_A_D2R_C_N<1>

DP_TBTPA_AUXCH_C_NDP_TBTPA_AUXCH_P

DP_TBTPA_HPD

TBT_A_LSRXTBT_A_LSTX

DP_TBTSNK0_DDC_DATADP_TBTSNK0_DDC_CLK

TBT_A_CONFIG1_BUF

TBT_A_D2R1_AUXDDC_NTBT_A_D2R1_AUXDDC_P

TBT_A_CIO_SELDP_AUXCH_ISOL_LTBT_A_DP_PWRDN

DP_TBTPA_AUXCH_N

DP_TBTPA_ML_N<1>DP_TBTPA_ML_P<1>

TBT_A_HPD

DP_A_LSX_ML_N<1>DP_A_LSX_ML_P<1>

TBT_A_CONFIG1_RC

PP3V3_S4_TBTAPWR

TBT_A_CONFIG1_RC

TBT_A_CONFIG2_RC

TBT_A_R2D_C_N<0>


TBT_A_R2D_C_P<0>


TBT_A_D2R_N<0>TBT_A_D2R_P<0>

DP_TBTPA_AUXCH_C_P


MIN_NECK_WIDTH=0.20 MMVOLTAGE=18V

TBTACONN_20_RCMIN_LINE_WIDTH=0.38 MM

TBT_A_D2R_C_N<0>TBT_A_D2R_C_P<0>

TBT_A_R2D_P<1>TBT_A_R2D_N<1>

PP15V_TBT

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_S0

S4_PWR_EN

PM_SLP_S3_BUF_L

TBT_A_HV_EN

VOLTAGE=15V

PP3V3RHV_S4_TBTAPWRMIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM

TBTAPWRSW_ISET_V3P3

PP3V3_S5

<BRANCH>

<SCH_NUM>

<E4LABEL>

32 OF 121

28 OF 76

25 26 27 28 62

28 71

71

71

28 71

71

71

28

28 71

28 71

71

71

71 28 71

28 71

71

71

71

28

28 71

28 71

28

25 26 27 28 62

28

71

71

71

71

27 62 64

8 11 13 15 16 17 18 29 34 42 57 58 59 60 62 64 74

www.vinafix.vn

IN

IN

IN

IN

OUT

OUT

OUT

NC

BI

BI

BI

IN

GND

VOUT

ON

VIN

IN

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE

RESET*

+-

PAD

(OD)

DLY

VREF

IN

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

OUT

SYM_VER_2

G S

D

IN

GND

VCC

A

B0

B1

S

VER-3 OUT

OUT

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PCIe Wake Muxing

SEL OUTPUT

L PCIE_WAKE_L (B0)H AP_S0IX_WAKE_L (B1)

BLUETOOTH

L BT_WAKE (1)H USB_BT (2)

SEL OUTPUT


514S0335

3.3V WLAN SwitchTPS22924C

25.8 mOhm Max

Load Switch

18.5 mOhm Typ

Part

@ 2.5VR(on)

Type

sensor pageSense resistor on

AIRPORT

Delay = 130 ms +/- 20%


14 69

14 69

12 64 69

12 64 69

2

1 C352110%0.1UF

0201CERM-X5R6.3V

BYPASS=J3501:5mm

14 64 69

14 64 69

2

1 C353210%0.1UF

0201CERM-X5R6.3V

BYPASS=J3501:1.5mm

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

21

20

19

J3501SSD-K99F-RT-SM1

CRITICAL

37 38 64

2

1 C351010%0.1UF

0201CERM-X5R6.3V

14 68

14 68

12

29 37 39

2

1R35535%

201

1/20WMF

100K

APCLKRQ:ISOL

2

1R3554

201

1/20WMF

1%232K

2

1R3555

201

1/20WMF

1%100K

2

1 C354010%0.1UF

0201CERM-X5R6.3V

21C353110%0.1UF X5R-CERM

16V0201

21C353010%0.1UF X5R-CERM 0201

16V

B1

A1

B2

A2

C2

C1

U3550

CRITICAL

CSPTPS22924

29 37 39

2

1 C3550

X5R6.3V

1.0UF20%

0201-1

2

1R35565%0

0201

1/20WMF

APCLKRQ:ISOL

2 1

R3557

5%

0

0201

1/20WMF

APCLKRQ:BIDIR

1

9

2

4

8

3

7

5

6

U3540SLG4AP041V

TDFNCRITICAL

21

R3558

5%

0

0201

1/20WMF

2 1

R3559

5%

0

0201

1/20WMF

NOSTUFF

15

5

4

3

8

6

2

107

1

9

U3510

SIGNAL_MODEL=BT_MUX

DFNUSB3740

CRITICAL

36 37 39

2

1R3512

201

1/20WMF

1%15K

21

3Q3510DMN32D2LFB4


DFN1006H4-3

13 18 36 37 59

5

6

2

1

3

4

U3560CRITICAL

SC70NC7SB3157P6XG

13 31 64

2

1C356010%

0.1UF

0201CERM-X5R

6.3V

15

15

21

R3560

5%

0

0201

1/20WMF

NOSTUFF

2

1R35615%

201

1/20WMF

100K


Wireless ConnectorSYNC_MASTER=J41_MLB

USB_BT_CONN_P

USB_BT_CONN_N

AP_PCIE_WAKE_L

PP3V3_S5

AP_CLKREQ_Q_L

AP_RESET_CONN_L

PCIE_AP_D2R_PPCIE_AP_D2R_N

PP3V3_S4

PCIE_CLK100M_AP_PPCIE_CLK100M_AP_N

PP3V3_S4

BT_WAKE

SMC_PME_S4_WAKE_L

USB_BT_P

USB_BT_N

PM_SLP_S4_L

AP_RESET_CONN_R_L

P3V3WLAN_VMON

PCIE_AP_R2D_C_N

SMC_WIFI_PWR_EN

PP3V3_S5

SMC_WIFI_PWR_EN

PP3V3_WLAN_R


PCIE_AP_R2D_P

PCIE_AP_R2D_N

AP_CLKREQ_R_L

WIFI_EVENT_L

PCIE_AP_R2D_C_P

AP_CLKREQ_L

AP_RESET_L


PP3V3_WLANMIN_LINE_WIDTH=0.5 mm

PP3V3_S5

PCIE_WAKE_LAP_S0IX_WAKE_L

AP_S0IX_WAKE_SEL

<BRANCH>

<SCH_NUM>

<E4LABEL>

35 OF 121

29 OF 76

64 68

64 68

8 11 13 15 16 17

18 28 29

34 42 57

58 59 60

62 64 74

64

64

29 33 36 38 39 58 62 64

29 33 36 38 39 58 62 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

41

64 69

64 69

37 38 39 41 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

www.vinafix.vn

OUT

OUT

IN

IN

NC

08

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

NC

08

IN

NC

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLY

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




SMC_PWRFAIL_WARN_L Signal has PU on SSD module

are only permitted on the device side,provided the device PHY supports it.

PCIe polarity inversion and lane reversal

Gumstick3 Connector

GND_VOID

OOB Isolation

514S0449

GND_VOID

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

Delay = ~55ms

37

2

1 C3702

PLACE_NEAR=L3700.1:1mm0201X5R-CERM10V

0.1UF10%

21

L3700CRITICAL

FERR-26-OHM-6A


0603

2

1 C3701

0201X5R-CERM10V

PLACE_NEAR=L3700.1:1mm

0.1UF10%

2

1R3742

1/20W

100K1%

MF201

2

1R37405%

MF1/20W

100K

201 2

1R3741232K1/20WMF

1%

201

12

2

1 C37400.1UF

CERM-X5R6.3V

0201

10%

15

15 30 58 59 64

4

6

5 3

1

2

U3711

SOT891

BYPASS=U3711:5 mm

CRITICAL74LVC1G08

2

1C3719

10VX5R-CERM

0201

0.1UF10%

12 67

12 67

12 67

12 67

12 67

12 67

12 67

12 67

21C3716X5R-CERM 020116V

GND_VOID=TRUE

0.1UF 10%

21C3717 GND_VOID=TRUEX5R-CERM 020116V0.1UF 10%

21C3713020116V X5R-CERM

GND_VOID=TRUE

0.1UF 10%

21C3712020116V X5R-CERM

GND_VOID=TRUE

0.1UF 10%

21C3715X5R-CERM 020116V

GND_VOID=TRUE

0.1UF 10%

21C3714020116V X5R-CERM

GND_VOID=TRUE

0.1UF 10%

21C3711 GND_VOID=TRUE020116V X5R-CERM0.1UF 10%

21C3710 GND_VOID=TRUEX5R-CERM16V 02010.1UF 10%

12 64 67

12 64 67

12 64 67

12 64 67

12 64 67

12 64 67

12 64 67

12 64 67

12 64 67

12 64 67

15 30 58 59 64

37

15 64

16 64

9

8

7

63

62

61

60

6

59

58

57

56

55

54

53

52

51

505

49

48

47

46

45

44

43

42

41

40

4

39

38

37

36

35

34

33

32

31

30

3

2928

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3700

TRUE

F-RT-SM

TRUE

CRITICAL

TRUE

TRUETRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

SSD-GS3 2

1R37001%

MF1/20W

100K

201

4

6

53

1

2

U3710

SOT891

CRITICAL74LVC1G08

37

2

1 C3718BYPASS=U3710:5 mm

X5R-CERM0201

10V

0.1UF10%

2

1R37105%

MF1/20W

100K

201

1

9

2

4

8

3

7

5

6

U3740

CRITICAL

TDFNSLG4AP016V

SSD ConnectorSYNC_MASTER=J41_MLB SYNC_DATE=04/09/2013

PP3V3_S0SW_SSD

VOLTAGE=3.3V

PP3V3_S0SW_SSD_FLTMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.15mm

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_N<0>

SSD_PCIE_SEL_L

SMC_OOB1_D2R_CONN_L

PP3V3_S0

PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_P<3>PCIE_SSD_R2D_N<3>

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_P<0>

NC_SSD_MFG_RSVD

PP3V3_S0SMC_OOB1_D2R_L

PP3V3_S0

PP3V3_S0SW_SSD

SMC_OOB1_R2D_L

SMC_OOB1_R2D_CONN_L

SSD_PWR_EN

SSD_DEVSLPSMC_PWRFAIL_WARN_L

PCIE_SSD_D2R_N<3>PCIE_SSD_D2R_P<3>

PCIE_CLK100M_SSD_NPCIE_CLK100M_SSD_P



PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_P<0>

P3V3SSD_VMON

PP3V42_G3H

SSD_CLKREQ_CONN_L

SSD_RESET_L

SSD_PWR_ENSSD_CLKREQ_L

SSD_RESET_CONN_L

PP3V3_S0SW_SSD

PCIE_SSD_R2D_C_P<1>

<BRANCH>

<SCH_NUM>

<E4LABEL>

37 OF 121

30 OF 76

30 41 62 64 64

64 67

64 67

64

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

64 67

64 67

64 67

64 67

64 67

64 67

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41

42 43 44 45 56 59 61

62 64 65 74

30 41 62 64

64

17 35 36 37 38 40 46 49 50 59 61 62 64 65

64

64

30 41 62 64

www.vinafix.vn

NCNC

NCNC

OUT

IN

OUT

BI

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

SYM 1 OF 3

DEBUG_15

DEBUG_14

DDR_PWR_SEL

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03

DEBUG_04

DEBUG_05

DEBUG_09PCIE_RDP0

DEBUG_06

DEBUG_00

DEBUG_01

DEBUG_02

DEBUG_07

DEBUG_08

DEBUG_10

DEBUG_11

DEBUG_12

DEBUG_13

DEBUG_16

GPIO_00

GPIO_01

GPIO_02

GPIO_03

GPIO_04

GPIO_05

GPIO_06

GPIO_07

I2C_CLK_DBG

I2C_CLK_SENSOR

I2C_DATA_DBG

I2C_DATA_SENSOR

JTAG_TCK

JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS

UARTRTS

UARTRXD

UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1

MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00

DDR_AD01

DDR_AD02

DDR_AD03

DDR_AD04

DDR_AD05

DDR_AD06

DDR_AD07

DDR_AD08

DDR_AD09

DDR_AD10

DDR_AD11

DDR_AD12

DDR_AD13

DDR_AD14

DDR_BA0

DDR_BA1

DDR_BA2

DDR_CS*

DDR_DM0

DDR_DM1

DDR_DQ00

DDR_DQ01

DDR_DQ02

DDR_DQ03

DDR_DQ04

DDR_DQ05

DDR_DQ06

DDR_DQ07

DDR_DQ08

DDR_DQ09

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF_O

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

SYM 3 OF 3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

NC

OUT

NCNCNC

NCNC

NCNCNC

NCNCNC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PU on PCH page

PD = 1.35V

PU = 25MHz

A1 SILICON BUG

L3902:1L3901:1

(=PP3V3_S3RS0_CAMERA)

(=PP3V3_S3RS0_CAMERA)

12

32

32 64

32 64

2

1R3930

MF1/20W5%

NOSTUFF

100K

201 2

1R3932NOSTUFF

1/20W5%

201MF

100K

18

18

2

1 C390010%0.1UF

0201CERM-X5R6.3V

2

1 C392410%0.1UF

0201CERM-X5R6.3V2

1 C3923

X5R6.3V20%

0201-1

1.0UF

2

1 C392210%0.1UF

0201CERM-X5R6.3V2

1 C3921

X5R6.3V

1.0UF

0201-1

20%

2

1 C391010%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.D6:2.54MM

2

1 C395110%0.1UF

0201CERM-X5R6.3V


2

1R39015%

201

1/20WMF

100K

32 69

32 69

32 69

32 69

32 69

32 69

32 69

32 69

2

1R39065%

201

1/20WMF

CAM_XTAL:YES

100K

2

1R39075%

201

1/20WMF

CAM_XTAL:NO

100K

2

1R39045%

201

1/20WMF

100K

21

L3901

1008

PLACE_NEAR=U3900.M13:4MM

1.0UH-1.6A-55MOHM

21

L3902

PLACE_NEAR=U3900.K13:4MM1008

1.0UH-1.6A-55MOHM

21

L390622NH

0402

2

1 C391610%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.L7:2.54MM

2

1 C391910%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.J1:2.54MM

2

1 C393710%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900:5mm

2

1 C393510%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900:5mm

2

1 C394010%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900:5mm

2

1 C3941

6.3V

BYPASS=U3900.F15:2.54MM

2.2UF20%

402-LFCERM

2

1 C393910%

X5R

BYPASS=U3900.G15:2.54MM

1UF10V

402

2

1 C396010%0.1UF

0201CERM-X5R6.3V

A13

A12

E14

E13

D14

D13

J12

M10

C12

C13

H12

R13

E15

N12

B9

C9

A8

B8

R14

B10

A10

B7

A7

P13

P6

P8

R6

R8

P7

R7

D11

D12

F12

E12

F13

C11

R9

C15

R10

D15

N9

N10

N11

P9

P10

P11

P12

R12

L10

L11

K10

K11

J10

H10

H11

G10

G11

F10

F11

E10

E11

A15

B14

C14

B11

G12

U3900

CRITICAL

BCM15700FBGA

OMIT_TABLE

G3

J2

R3

H3

A2

E2

A3

D2

B3

B2

C5

A5

B4

B1

C3

B5

F2

F4

F1

F3

D3

E4

E3

C2

C4

C1

L4

J3

H2

G2

H4

K2

L2

K3

R4

P1

L1

R2

J4

P2

P3

N2

P4

M2

M1

M3

N3

M4

L3

U3900BCM15700

CRITICAL

FBGA

OMIT_TABLE

B12

B13

G8

G7

G6

G1

E5

D5

E9R5

R1

P5

D1

N1

M9

A14

K9

K8

K7

K6

K5

K1

J9

B6

J8

J7

J6

J5

H9

H8

H7

H6

H5

G9

A6

A1

K12

M11

R11

B15

L9

L8

L5

L6

F9

F8

F7

F6

J11

F14

G15

F15

K14

K13

N14

M13

J15

J14

J13

H15

H14

N15

M15

M14

L15

L14

L13

L12

K15

R15

P15

P14

N13

M12

G14

D6

C8

D9

C7

C10

D7

L7

N6

N8

N7

N5

G5

N4

K4

G4

D4

A4

J1

U3900

CRITICAL

BCM15700FBGA

OMIT_TABLE

2

1 C391810%

BYPASS=U3900.J1:2.54MM

16VX7R-CERM0201

1000PF

2

1 C393410%1000PF

X7R-CERM0201

16V

BYPASS=U3900:3mm

2

1 C391710%


1000PF16VX7R-CERM0201

2

1 C393610%

BYPASS=U3900:3mm

0201X7R-CERM

1000PF16V

2

1 C393810%16V

1000PF


0201X7R-CERM

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32 72

32

2

1R39105%

201

1/20WMF

NO STUFF

100K

2

1R39115%

201

1/20WMF

100K

21

R3912

201

1/20WMF

1%

240

2

1R39135%

201

1/20WMF

1K

2

1R39145%

201

1/20WMF

1K

32 72

21

XW3900SM

21

XW3901SM

2

1R39905%

201

1/20WMF

100K

2

1 C399010%0.1UF

0201CERM-X5R6.3V

NOSTUFF

2

1 C392710%0.1UF

0201CERM-X5R6.3V

2

1 C3930

X5R6.3V

1.0UF20%

0201-1

32 72

2

1 C3932

X5R6.3V

0201-1

1.0UF20%

2

1 C393120%10UF6.3VCERM-X5R0402-1

2

1 C393320%10UF6.3VCERM-X5R0402-1

2

1R39155%

201

1/20WMF

CAM_A1

100K

21

L3903

0603

220-OHM-1.4A

21

L3904220-OHM-1.4A

0603

21

R3991NOSTUFF

5%

0

0201

1/20WMF

13 29 64

2

1 C3975

6.3V10%0.1UF

0201CERM-X5R


2

1 C397410%0.1UF

0201CERM-X5R6.3V


2

1 C397310%1000PF


16VX7R-CERM0201

2

1 C397210%0.1UF

0201CERM-X5R6.3V


2

1 C3971


10%

0201

16V

1000PF

X7R-CERM2

1 C397010%0.1UF

0201CERM-X5R6.3V


2

1R39755%

201

1/20WMF

51K

2

1R39765%

201

1/20WMF

51K

2

1R39205%

201

1/20WMF

100K

2

1R39215%

201

1/20WMF

100K

2

1R3934NOSTUFF

1/20W5%

201MF

100K

2

1R3931

MF1/20W5%330K

201 2

1R3933

MF1/20W5%330K

201 2

1R3935

MF

5%330K

201

1/20W

2

1R39365%

201

1/20WMF

100K

NOSTUFF

2

1R39375%

201

1/20WMF

100K

NOSTUFF

2

1 C3912

X5R6.3V

BYPASS=U3900.K13:2.54MM

402

20%4.7UF

2

1 C3913

X5R6.3V

402

20%4.7UF

2

1 C3914

X5R6.3V20%4.7UF

4022

1 C3915

X5R6.3V

4.7UF

402

20%

PLACE_NEAR=U3900.M13:2.54MM

2

1 C3926

X5R6.3V

PLACE_NEAR=U3900.M14:2.54MM

402

20%4.7UF

2

1 C3928

X5R6.3V

402

20%4.7UF

2

1 C3942

X5R6.3V

402

BYPASS=U3900:7mm

20%4.7UF

32 72

SYNC_MASTER=J41_MLB

Camera 1 of 2SYNC_DATE=04/02/2013

PP1V8_CAM

CAM_RAMCFG0CAM_RAMCFG1CAM_RAMCFG2

PP1V2_CAM

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP1V2_CAM_PCIE_VDD_FLT

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

PP1V8_CAM

GND_CAM_PVSSD

MEM_CAM_A<14>MEM_CAM_A<13>

PP1V8_CAM

MEM_CAM_A<3>MEM_CAM_A<4>MEM_CAM_A<5>

MEM_CAM_A<7>

MEM_CAM_A<10>

MIN_LINE_WIDTH=0.6MMP1V2_CAM_SRVLXC_PHASE

MIN_NECK_WIDTH=0.2MMDIDT=TRUE

PP3V3_S3RS0_CAMERA

PCIE_CAMERA_D2R_C_P

TP_CAM_PLL_BYPASSCAM_GPIO3

CAM_UARTCTS

CAM_UARTRXDTP_CAM_UARTTXD

CAM_RAMCFG1CAM_RAMCFG2

CAM_RAMCFG0

TP_CAM_UARTRTS

CAM_XTAL_FREQ

CAM_TEST_MODECAM_TEST_OUT

CAM_XTAL_SEL

TP_CAM_LV_JTAG_TRSTN

TP_CAM_TEST_MODE0TP_CAM_TEST_MODE1TP_CAM_TEST_MODE2TP_CAM_LV_JTAG_TCKTP_CAM_LV_JTAG_TDITP_CAM_LV_JTAG_TDOTP_CAM_LV_JTAG_TMS


GND_CAM_PVSSDMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

P1V35_CAM_SRVLXD_PHASE

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

GND_CAM_PVSSCMIN_NECK_WIDTH=0.2MM

GND_CAM_PVSSC

PCIE_CLK100M_CAMERA_C_P

VOLTAGE=1.2V


PP1V2_CAM_PCIE_PVDD_FLT

I2C_CAM_SDA

I2C_CAM_SCK

CAM_PCIE_WAKE_LCAM_PCIE_RESET_L

CAM_TEST_OUT

PCIE_WAKE_L

PP1V8_CAMCAM_TEST_MODE

MEM_CAM_RESET_LMEM_CAM_CAS_LMEM_CAM_WE_LMEM_CAM_RAS_L

MEM_CAM_DQS_N<1>MEM_CAM_DQS_P<1>

MEM_CAM_DQS_N<0>MEM_CAM_DQS_P<0>


CAMERA_CLKREQ_L

P1V35_CAM_SRVLXD_PHASE

CLK25M_CAM_CLKP

CAM_UARTRXD

CAM_UARTCTS

CAM_XTAL_FREQ

PP1V8_CAM

CAM_XTAL_SEL

CAM_PWR_SELCAM_DEBUG_RESET_L

PP1V8_CAM

PP1V8_CAM

PCIE_CAMERA_R2D_P

MIPI_DATA_P

I2C_CAM_SMBDBG_CLK

I2C_CAM_SMBDBG_DAT

TP_CAM_JTAG_TCK

CAM_JTAG_SRST_LTP_CAM_JTAG_TRST_L

TP_CAM_JTAG_TDOTP_CAM_JTAG_TDI

TP_CAM_JTAG_TMS

CAM_SENSOR_WAKE_LCAMERA_PWR_EN

CAM_JTAG_SRST_L

MEM_CAM_DQ<0>MEM_CAM_DQ<1>MEM_CAM_DQ<2>MEM_CAM_DQ<3>MEM_CAM_DQ<4>MEM_CAM_DQ<5>

MEM_CAM_DQ<7>MEM_CAM_DQ<8>MEM_CAM_DQ<9>MEM_CAM_DQ<10>MEM_CAM_DQ<11>MEM_CAM_DQ<12>MEM_CAM_DQ<13>MEM_CAM_DQ<14>MEM_CAM_DQ<15>

MEM_CAM_CS_LMEM_CAM_CKE

MEM_CAM_DM<1>MEM_CAM_DM<0>

MEM_CAM_CLK_NMEM_CAM_CLK_P

MEM_CAM_BA<2>MEM_CAM_BA<1>MEM_CAM_BA<0>



MEM_CAM_A<6>

MEM_CAM_A<2>MEM_CAM_A<1>MEM_CAM_A<0>

MEM_CAM_ZQ_S2

PP1V35_DDR_CLK

VOLTAGE=1.35V


VOLTAGE=0.675VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP0V675_CAM_VREF

PP1V2_CAMPP1V35_CAM

PP1V35_CAM

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

PP1V2_CAM_XTALPCIEVDDMIN_NECK_WIDTH=0.2MM

PP1V2_CAM

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

GND_CAM_PVSSC

I2C_CAM_SMBDBG_CLKI2C_CAM_SMBDBG_DAT

PP1V8_CAM

P1V2_CAM_SRVLXC_PHASE

PP1V8_CAM

MEM_CAM_DQ<6>

PCIE_CAMERA_R2D_N


GND_CAM_PVSSD

VOLTAGE=1.35V

PP1V35_CAMMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

MIPI_CLK_PMIPI_CLK_N

MIPI_DATA_N

PCIE_CAMERA_D2R_C_N

CLK25M_CAM_CLKN

PCIE_CLK100M_CAMERA_C_N

<BRANCH>

<SCH_NUM>

<E4LABEL>

39 OF 121

31 OF 76

31 32

31

31

31

31

31

31

15 41

31

31

31

31

31

31

31

31

31

31

31

31

31 32

31 17 31

31

31

31

31

31 32

31

31 32

31 32

31

31

31

31

32 72

31

31 32 72

31 32 72

17 31

31

31

31

31

31 32

31

31 32

17 31

31

31 32 72

www.vinafix.vn

OUT

OUT

OUT

OUT

IN

IN

IN

IN

BI

IN

IN

IN

BI

BI

SYM_VER-1

SYM_VER-1

BI

IN

A4

A14

DQSL*

DQL1

VDD

A2

A3

A1

A0

NC

A6

ODT

RESET*

VSSQ VSS

CAS*

RAS*

BA2

BA0

BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML

DMU

DQL5

DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NCNCNCNCNC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

NCNC

OUT

IN

OUT

OUT

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

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A


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12

D

A

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



96.2 mA peak77.2 mA nominal max

ALS

NOTE: TBD PPM crystal required

518S0892

CAMERA SENSOR

31 69

31 69

14 69

14 69

21C403310%0.1UF 16V 0201X5R-CERM

21C403210%0.1UF 16V 0201X5R-CERM

21C403110%0.1UF X5R-CERM 020116V

21C403010%0.1UF X5R-CERM 020116V

14 69

14 69

31 69

31 69

21

R4009

5%

0

0201

1/20WMF

CAM_XTAL:YES

21

R4010

5%

0

0201

1/20WMF

CAM_XTAL:YES

21

R4008

5%

0

02011/20W

MF

CAM_XTAL:NO

21

R4007

5%

0

02011/20WMF

CAM_XTAL:YES

21

R4000

5%

0

02011/20W

MF

2

1 C4004

201

BYPASS=U4000.H9:4mm

0.47UF

CERM-X5R-14V20%

2

1 C4008

402

10V

2.2UF20%

X5R-CERM

BYPASS=U4000.K2:4mm

2

1 C4006

402

20%10VX5R-CERM

2.2UF

BYPASS=U4000.D2:4mm

2

1R4012

201

1/20WMF

1%1M

NOSTUFF

21

C4015

5%25V

0201

12PFCAM_XTAL:YES

NP0-C0G-CERM

21

C4014

5%25V

CAM_XTAL:YES

12PF

NP0-C0G-CERM0201

2

1 C400910%0.1UF

0201CERM-X5R6.3V2

1 C400710%0.1UF

0201CERM-X5R6.3V

BYPASS=U4000.R9:4mm

2

1C4013

402

0.1uF10V

CERM

20%

31 64

31 64

2

1 C400510%0.1UF

0201CERM-X5R6.3V

31 72

31 72

31 72

31 72

2 1

L4010

0402-LF

FERR-120-OHM-1.5A

2

1 C4003BYPASS=U4000.B2:4mm

20%10UF6.3VCERM-X5R0402-1

2

1 C4002BYPASS=U4000.A1:4mm

20%10UF6.3VCERM-X5R0402-1

4

32

1

L4009

PLACE_NEAR=J4002.2:2.54MM

TCM0605-190-OHM-50MA

CRITICAL

4

32

1

L4007

CRITICAL

TCM0605-190-OHM-50MA

PLACE_NEAR=J4002.5:2.54MM14 37 40 43 44 64 69 73

14 37 40 43 44 64 69 73

2

1R4022

201

1/20WMF

1%1K

2

1R4023

201

1/20WMF

1%1K

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

P9

P1

M9

M1

J8

J2

G8

E1

T9

T1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

M7

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

T7

T3

N7

R7

L7

P7

N3 U40004GB-DDR3-256MX16

CRITICAL

FBGAH5TC4G63AFR

31 72

31 72

2

1 C401110%0.1UF

0201CERM-X5R6.3V

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

2

1C401010%

0.1UF

0201CERM-X5R

6.3V

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31

31 72

31 72

31 72

31 72

2

1R4020

201

1/20WMF

84.51%

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

31 72

2

1R4021

201

1/20WMF

821%

NO STUFF

31 72

2

1R40025%

201

1/20WMF

1K

2

1R40035%

201

1/20WMF

1K

NOSTUFF

2

1R4004

201

1/20WMF

2401%

21

R4030

5%

0

02011/20WMF

CAM_WAKE:YES

2

1 C40165%25V

0201NP0-CERM

CAM_XTAL:NO

100PF

2

1R40315%0

0201

1/20WMF

CAM_WAKE:NO

9

8

7

6

5

4

3

2

12

11

10

1

13

14

J4002CCR20-AK7100-1

CRITICAL

F-RT-SM

21C406110%0.1UF 16V 0201X5R-CERM

21C406210%0.1UF 16V 0201X5R-CERM

2 1

L4011FERR-120-OHM-1.5A

0402-LF

NOSTUFF

2

1 R40065%25V

NO STUFF

100PF

0201NP0-CERM

31 72

31

42

Y4000CRITICAL

25.000MHZ-12PF-20PPMSM-3.2X2.5MM

CAM_XTAL:YES31 69

31 69

31 69

31 69

12 69

12 69

2

1R40055%

201

1/20WMF

100K

17 69

Camera 2 of 2SYNC_MASTER=J41_MLB SYNC_DATE=03/20/2013

PP1V35_CAM

MEM_CAM_A<11>

MEM_CAM_BA<1>MEM_CAM_BA<2>

MEM_CAM_CAS_LMEM_CAM_WE_L

MEM_CAM_CLK_N

MEM_CAM_CKE

MEM_CAM_CLK_PCAM_SENSOR_WAKE_L_CONN

PP0V675_MEM_CAM_VREFDQ


MEM_CAM_DM<1>

MEM_CAM_A<14>

MEM_CAM_A<4>

I2C_CAM_SCK

MIPI_DATA_CONN_N

PP5V_S4RS3

CAM_SENSOR_WAKE_L_CONN

MEM_CAM_A<13>

MEM_CAM_BA<0>

MEM_CAM_A<12>

MEM_CAM_DM<0>

MEM_CAM_CKE_R

PCIE_CLK100M_CAMERA_C_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_N

PCIE_CAMERA_D2R_C_N

MEM_CAM_CS_L

MEM_CAM_RAS_L




MEM_CAM_DQ<13>

MEM_CAM_DQ<9>

MEM_CAM_DQS_P<1>

MEM_CAM_DQ<6>MEM_CAM_DQ<5>

MEM_CAM_DQS_P<0>

MEM_CAM_DQS_N<1>


MEM_CAM_DQ<12>


MEM_CAM_DQ<0>

MEM_CAM_DQ<2>MEM_CAM_DQ<3>MEM_CAM_DQ<4>

MEM_CAM_DQ<7>

MEM_CAM_DQ<1>

MEM_CAM_DQS_N<0>

CLK25M_CAM_CLKP

CLK25M_CAM_XTALP

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_N

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_P

SYSCLK_CLK25M_CAMERA

PCIE_CAMERA_R2D_C_P

CLK25M_CAM_XTALP_R

MEM_CAM_A<6>

MEM_CAM_A<0>

PP1V8_CAM

MEM_CAM_A<3>

MEM_CAM_RESET_L

MEM_CAM_ZQ_DDR

PCIE_CLK100M_CAMERA_P

CLK25M_CAM_XTALN CLK25M_CAM_CLKN

VOLTAGE=0.675VMIN_NECK_WIDTH=0.2 mm

PP0V675_MEM_CAM_VREFCAMIN_LINE_WIDTH=0.5 mm

CAM_SENSOR_WAKE_L

MEM_CAM_DQ<8>

MEM_CAM_ODT

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=5V

PP5V_S3RS0_ALSCAM_F PP5V_S0

SMBUS_SMC_1_S0_SDASMBUS_SMC_1_S0_SCL

I2C_CAM_SDA

MIPI_CLK_CONN_PMIPI_CLK_CONN_N

MIPI_DATA_CONN_PMIPI_DATA_N

MIPI_DATA_P

MIPI_CLK_N

MIPI_CLK_P

MEM_CAM_A<5>

PP0V675_CAM_VREF

<BRANCH>

<SCH_NUM>

<E4LABEL>

40 OF 121

32 OF 76

31 72

32 64

72

64 72

35 47 49 54 55 58 62 64

32 64

69 69

31

69

72

31

72

64 16 17 45 46 51 52 56 58 59 61 62 64

64 72

64 72

64 72

31 72

www.vinafix.vn

OUT

BI

OUT

BI

BI

IN

BI

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW

CARD_DETECT_GND

DAT6

DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

VSS

CLK

CMD

DAT0

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

NCNCNCNC

NC

DET_OUT

DET_IN

RST_IN*

DET_CHNGD*

LOW_PWRRST_OUT*

VDD

THRMGND PAD

(IPU) (OD)

(OD)

DLY

XOR

LOGICRST

OUT

G

D S

G

D S

OUT Y A

B

NCGND

VCC

NC

Apple Inc.


124578

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SD CARD CONNECTOR

516-0253

(CARD INSERTED = GROUND)

SDCONN_STATE_CHANGE Isolation

(IPU) FROM SD CONN ->

DLY block is 20ms nominal

To PCH

To SMC

34 75

34 75

34 75

34 75

34 75

34 75

34 75

21R4479 33 MF1/20W 2015% 21

L4400CRITICAL

47NH-1.3OHM0402

2

1 C4470NOSTUFF

CERM402

50V

15PF5%

2

1 C4471

402

50V

NOSTUFF

22PF

CERM

5%

21R4471 MF1/20W 02010 5%

21R4472 MF1/20W 02010 5%

21R4473 MF1/20W 02010 5%

21R4474 MF1/20W 02010 5%

21R4461 MF1/20W 02010 5%

2

1C4430

X5R-CERM

0.1UF16V10%

0201

BYPASS=U4430.1:5mm

16

6

3

4

20

19

18

17

13

12

11

10

9

8

7

2

5

1

14

15

J4400

CRITICAL

SD-CARD-K16F-RT-TH-1

1

9

4

3

2

5

7

68

U4430

CRITICAL

SLG4AP014VTDFN

34 75

2

1R4410470K

MF1/20W

201

5%

2

1R4411470K

MF1/20W

201

5%

12

6

Q4410DMN5L06VK-7

SOT-563

45

3

Q4410SOT-563

DMN5L06VK-7

2

1C4410

0201

10%0.1UF

CERM-X5R6.3V

BYPASS=U4410.5:5mm

15 16

2

1 C4472

CERM50V

10PF

402

NOSTUFF

5%

2

1 C4473

CERM402

NOSTUFF

50V

10PF5%

2

1 C4474

CERM50V

10PF

402

NOSTUFF

5%

2

1 C4475

50V

10PF

CERM402

NOSTUFF

5%

2

1 C4476

402

50V

10PF

CERM

NOSTUFF

5%

21

R4480

MF-LF 1/16W

40205%

21

R4481

MF-LF

402

1/16W

05%

2

1R4482

1/16WMF-LF

NOSTUFF

402

05%

4

6

5

3

1

2

U4410CRITICAL

SOT89174AUP1G09


SD READER CONNECTORSYNC_MASTER=MASTER

SD CARD

PP3V3_S3

PP3V3_S4


SMC_PME_S4_DARK_L

SMC_PME_S4_DARK_L

SDCONN_STATE_CHANGE_SAK_L

SDCONN_R_DATA<0>

SDCONN_WP

SDCONN_R_DATA<1>

SDCONN_CMD_RSDCONN_CLK_R2

SDCONN_R_DATA<2>

SDCONN_DATA<0>

SD_CONN_CLK

PP3V3_S0_SD_CONN

SDCONN_CLK

SMC_PME_SDCONN

PP3V3_S4

SDCONN_DETECT_L

SDCONN_CLK_R1

SDCONN_DATA<2>SDCONN_DATA<1>

SDCONN_DATA<3>

SDCONN_CMD

SDCONN_R_DATA<3>

SDCONN_CLK_L

SD_CD_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

44 OF 121

33 OF 76

15 18 19 36 40 41 58 62 64

29 33 36 38 39 58 62 64

25 33 37 38

25 33 37 38

34

29 33 36 38 39 58 62 64

www.vinafix.vn

VCC

GNDTHRM

CS*

HOLD*

DIO(IO0)

DO(IO1)

CLK

WP*

PAD

NCNC

GND

VDD

D

SON

CAP

IN

IN

OUT

IN

BI

IN

BI

BI

BI

BI

NC

PAD

PMOS33

AVDD12

AVDD12

AVDD33

AVDD33

DVDD12

DVDD12

DVDD33

V33IN

DVDD33

DVDD33

VUHSI

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

RTERM

RSTZ*

RXP

X1

X2

RXN

DP

DM

THRM

GND

LED

SD_WP

TXP

TXN

SD_D3

SD_D2

SD_D1

SD_D0

SPI_CS

SD_CLK

SD_CMD

SD_CDZ

SPI_SO

SPI_SI

SPI_CKNCNCNCNCNCNCNCNCNC

OUT

NC

IN

OUT

IN

Apple Inc.


124578

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D

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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



900mA max

USING ON CHIP CLOCK SOURCE MODE (CRYSTAL AS BACK-UP)

15 mOhm Typ

(IPU)(IPU)

(IPU)

U4550

Load Switch

EDP: 1.05A

SLG5AP1438V

17 mOhm Max

2.5A

R(on)

Type

Part

NO USB 2.0 INTERFACE

Current

3.3V S3 SD Card Switch

21C4513PLACE_NEAR=U4500.2:5mm0.1UFGND_VOID=TRUE

X5R-CERM 020116V10%

2

1R45805%0

0201

1/20WMF

3

8

9

7

4

2

5

1

6

U4590

NOSTUFF

W25X05CLUSON512KB

CRITICAL

2

1R45825%

201

1/20WMF

1M

21

R4581

5%

0

0201

1/20WMF

31

42 Y4580

CRITICAL

25.000MHZ-12PF-20PPMSM-3.2X2.5MM

2 1

C4580

5%25V

12PF

NP0-C0G-CERM0201

21C4512PLACE_NEAR=U4500.1:5mm

02010.1UFGND_VOID=TRUE16V10% X5R-CERM

21

C4581

5%

NP0-C0G-CERM25V

0201

12PF

1

52

8

37

U4550TDFN

SLG5AP1443V

CRITICAL

2

1C4561

201

4700PF10V10%

X7R

2

1C4570

201

6.3V

0.047UF

X5R

10%

2

1C4521BYPASS=U4500.38:5mm

402

6.3V20%

X5R

4.7UF

2


4.7UF20%

6.3V

402X5R

21

R4570

5%

201

1/20WMF

3.3K

14 65 68

14 65 68

21C4511X5R-CERM10% 020116V

GND_VOID=TRUE0.1UFPLACE_NEAR=U4500.5:5mm

21C4510PLACE_NEAR=U4500.4:5mm

0.1UF 16V10% 0201X5R-CERMGND_VOID=TRUE

33 75

33 75

33 75

33 75

33 75

33 75

33 75

33 75

2

1R4500

201

1/20WMF

1%680

2


X5R-CERM4V

0201

20%2.2UF

2

1C4522

0201-1X5R-CERM

10%6.3V

BYPASS=U4500.22:5mm

1.0UF

2

1C4526

X5R-CERMBYPASS=U4500.9:5mm 10%

0.1UF

0201

16V2

1C4528

402-LFCERM

2.2UF6.3V20% BYPASS=U4500.43:5mm

2

1C4527

0201

16V10%

BYPASS=U4500.43:5mm

X5R-CERM

0.1UF

2

1C4524

X5R-CERM0201

BYPASS=U4500.3:5mm

10%16V

0.1UF

2


X5R-CERM0201

0.1UF10%16V

2


0201-1

1.0UF10%

6.3VX5R-CERM

2

1C4531

0201-1

BYPASS=U4500.30:5mm

10%1.0UF

6.3VX5R-CERM2

1C45305%

BYPASS=U4500.30:5mm

100PF

NP0-CERM25V

02012

1C45295%

0201NP0-C0G-CERM

47PF25VBYPASS=U4500.30:5mm

21

L4500FERR-1000-OHM-450MA

CRITICAL

0402

21

L4501FERR-1000-OHM-450MA

0402

CRITICAL

8

7

30

22

2

1

47

37

36

34

35

23

28

29

24

25

27

26

20

5

4

10

41

39

32

19

18

17

16

15

14

13

12

11

33

6

40

38

31

42

21

44

45

43

946

3

U4500

OMIT_TABLE

GL3219LQFN

CRITICAL14 65 68

2

1C4590NOSTUFF

0201-1

BYPASS=U4590.8:5mm

X5R-CERM6.3V10%

1.0UF

2

1R45905%

201

1/20WMF

NOSTUFF

3.3K

2

1R45915%

201

1/20WMF

NOSTUFF

3.3K

15

14 65 68

2

1C4560

0201-1

1.0UF

X5R6.3V20%

BYPASS=U4550.A2:5mm

2

1R45955%

201

1/20WMF

10K

NOSTUFF

15

2

1C4519

X5R-CERM

BYPASS=U4500.42:5mm

0201

16V10%

0.1UF

2

1C4518

X5R-CERM0201

10%0.1UF

BYPASS=U4500.31:5mm

16V

SD CONTROLLER (GL3219)SYNC_MASTER=MASTER SYNC_DATE=10/11/2010

PP3V3_S5

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MMPP1V2_S3_SD_DVDD12

VOLTAGE=1.2V

PP3V3_S0SW_SD

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MMPP1V2_S0_SD_VUHS1

VOLTAGE=3.3V

PP3V3_S0_SD_AVDD33MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM

SDCONN_CLK

SDCONN_CMD

SDCLK_CLK25M_X2_R

SD_RTERM

PP1V2_S0_SD_AVDD12MIN_LINE_WIDTH=0.5 MM


SD_SPI_MOSI

SD_PWR_EN

USB3_SD_D2R_N

USB3_SD_D2R_P

PP3V3_S0_SD_CONN

USB_SD_DM

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.20MM

PP3V3_S0_SD_CONN

USB_SD_DP

SD_RESET_L

SDCONN_DATA<3>

SDCONN_DATA<0>

P3V3_SD_FET_RAMP

PP3V3_S0SW_SD

SDCLK_CLK25M_X2

USB3_SD_D2R_C_N

SDCONN_DATA<1>

SDCONN_DATA<2>

SDCONN_WP

SD_SPI_MISO

SD_SPI_CS_L

USB3_SD_D2R_C_P

SDCONN_DETECT_L

USB3_SD_R2D_NUSB3_SD_R2D_P

SDSCLK_CLK25M_X1

SD_RESET_R_L

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

SD_SPI_CLK

SD_SPI_HOLD_LSD_SPI_WP_L

<SCH_NUM>

<E4LABEL>

34 OF 76

45 OF 121

<BRANCH>

8 11 13 15 16 17 18 28 29 42 57 58 59 60 62 64 74

15 34 37 39 65

69 75

75

33 34

33 34

15 34 37 39 65

69

68

75

75

68

68

68

69

75

www.vinafix.vn

SYM_VER-1

OUT

OUT

IN

IN

GND

SSRX-

SXRX+

GND

D+

GND

SSTX+

SSTX-

D-

VBUS

FAULT*

IN_1

IN_0

ILIM

OUT1

OUT2

EN

GNDTHRMPAD

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

BI

BI

IN

OUT

IN

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

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A


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A

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Current limit per port (R4600+R4601): 2.19A min / 2.76A max

H USB (D)

Mojo SMC Debug Mux

SEL OUTPUT

APN: 514-0819

USB Port Power Switch

Right USB Port A

L SMC (M)

2

1C46050.01UF

16V

0201X5R-CERM

10%

4 3

21

L4600DLP0NS90-OHM

CRITICAL

14 68

14 68

14 68

14 68

21

C4620GND_VOID=TRUE

6.3VCERM-X5R0201

0.1UF

10%

21

C4621

GND_VOID=TRUE

6.3VCERM-X5R0201

0.1UF

10%

1

8

2

3

9

18

17

16

15

14

13

12

11

10

7

4

6

5

J4600CRITICAL

F-RT-THUSB3.0-J11-J13

2

1

D4610

GND_VOID=TRUE

ESD0P2RF-02LSTSSLP-2-1

CRITICAL

2

1

D4620ESD0P2RF-02LS

CRITICAL

GND_VOID=TRUE

TSSLP-2-1

2

1

D4611

GND_VOID=TRUE

CRITICAL

TSSLP-2-1ESD0P2RF-02LS

2

1

D4621CRITICAL


GND_VOID=TRUE

2

1R46011%22.1K1/20WMF201

9

7

6

3

2

5

1

8

4

U4600TPS2557DRB

CRITICAL

SON

1

2

9

108

5

4

3

7

6

U4650

CRITICALTQFN

PI3USB102EZLE

SIGNAL_MODEL=MOJO_MUX_SMSC

2

1C4650BYPASS=U4650.9:3:5mm

0201X5R-CERM

10V

0.1UF10%

2

1R4650

201

100K

MF1/20W5%

14 68

14 68

37 38 68

37 38 68

37

2

1

D4600CRITICAL


2

1

D4601ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

2

1C4695

0402-1

6.3V

10UF

CERM-X5R

20%

2

1 C4691

16VX5R-CERM0201

0.1UF10%

14 16

2

1C4690

0402-1

6.3VCERM-X5R

20%10UF 2

1R4600

MF1/20W

22.1K1%

201

2

1 C4696

CRITICAL

POLY-TANT

20%

CASE-B2-SM1

220UF-35MOHM

6.3V

21

L4605CRITICAL

FERR-120-OHM-3A

0603


External A USB3 Connector

XDP_USB_EXTA_OC_L

USB_PWR_EN

USB_ILIM_R

USB3_EXTA_R2D_C_N

USB3_EXTA_R2D_C_P

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5VMIN_NECK_WIDTH=0.15 mmMIN_LINE_WIDTH=0.5 mm

USB_ILIM

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_P

SMC_DEBUGPRT_RX_LSMC_DEBUGPRT_TX_L

USB_EXTA_P

MIN_NECK_WIDTH=0.375 mmMIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_S3_RTUSB_A_F

USB2_EXTA_MUXED_F_PUSB2_EXTA_MUXED_F_N

USB2_EXTA_MUXED_P

USB3_EXTA_R2D_N

PP5V_S4RS3

USB_EXTA_N

PP3V42_G3H

USB2_EXTA_MUXED_N

SMC_DEBUGPRT_EN_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

46 OF 121

35 OF 76

59 61 65

68

68

68

68

68

32 47 49 54 55 58 62 64

17 30 36 37 38 40 46 49 50 59 61 62 64 65

68

www.vinafix.vn

IN

IN

OUT

D

SYM_VER_3

SG

OUT

IN

OUT

OUT

BI

BI

BI

BI

OUT

IN

IN

Y

A

B 08

Y

A

B 08IN

IND

SYM_VER_3

SG

IN

Apple Inc.


124578

B

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8 7 6 5 4 3

C

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A


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12

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



518S0884

(TPAD_SPI_INT_S4_WAKE_L_CONN)

(TPAD_WAKE_L)

(TPAD_USB_IF_EN_CONN)

(=PP3V42_G3H_IPD)

IPD Flex Connector

From PCH

From PCH

(TPAD_SPI_IF_EN_CONN)

To SMC

To PCH

2

1C4810

0201X5R-CERM

16V


0.1UF10%

13 18 29 36 37 59

15

15

21

3

Q4800TPAD_INTWAKE:SHARED

DMN32D2LFB4DFN1006H4-3

PLACE_NEAR=R4842.2:5MM

2

1C4841BYPASS=U4810:3mm 6.3V

CERM-X5R0201

0.1UF10%

29 37 39

21

R4842

5%

0

0201

1/20WMF

TPAD_INTWAKE:SPLIT

PLACE_NEAR=R4843.2:1.5MM

21

R4843

5%

0

0201

1/20WMF

TPAD_INTWAKE:SHARED

PLACE_NEAR=R4841.1:1.5MM

21

R4841

5%

0

0201

1/20WMF

TPAD_INTWAKE:SPLITPLACE_NEAR=R4844.1:1.5MM

2

1R48445%0

0201

1/20WMF


TPAD_INTWAKE:SHARED

36 37 38 61 64 65

36 38 64

36 37 38 64

36 37 40 44 64 73

36 37 40 44 64 73

14 64 68

14 64 68

9

8

7

6

5

4

3

20

2

19

18

17

16

15

14

13

12

11

10

1

21

22

J4800F-RT-SM-1

CRITICAL

TF13BS-20S-0.4SH

2

1R48105%

201

1/20WMF

100K

NOSTUFF

21

R4850

5% 2011/20W MFPLACE_NEAR=J4800.2:2.54mm

3315 68

21 R48525% 2011/20W MFPLACE_NEAR=J4800.9:2.54mm

3315 68

21 R48515% 2011/20W MFPLACE_NEAR=J4800.7:2.54mm

3315 68

21 R48535% 2011/20W MF

33

PLACE_NEAR=J4800.12:2.54mm

7

8

4

2

1

U4810

74LVC2G08GTSOT833

CRITICAL

3

8

4

6

5

U4810



SOT83374LVC2G08GT

15

13 18 29 36 37 59

21

3

Q4860DFN1006H4-3DMN32D2LFB4

15

2

1R48605%

201

1/20WMF

100K

2

1C4820BYPASS=J4800.19:1.5MM

6.3VCERM-X5R

0201

0.1UF10%

2

1C4800

BYPASS=J4800.10:1.5MM6.3V

CERM-X5R0201

0.1UF10%

2

1 C48325%

BYPASS=J4800.6:1.5MM

NP0-CERM0201

100PF

NOSTUFF

25V 2

1 C48335%

NOSTUFF

100PF

BYPASS=J4800.5:1.5mm

0201NP0-CERM25V 2

1 C48345%

NP0-CERM


0201

100PF25V 2

1 C48355%100PF


0201NP0-CERM25V 2

1 C48365%


100PF

0201NP0-CERM25V

21



0402-LF

21

R4830

5%

0

0201

1/20WMF


IPD ConnectorSYNC_MASTER=J41_MLB SYNC_DATE=02/12/2013SMC_ONOFF_L

SMBUS_SMC_3_SDA

TPAD_SPI_IF_EN_CONN

TPAD_SPI_MISO

PP3V3_S4_IPD


MIN_LINE_WIDTH=0.5 mm

PP3V3_S4

TPAD_SPI_INT_L

PP5V_S5

SMC_PME_S4_WAKE_L

TPAD_SPI_MOSI

TPAD_SPI_CLK

TPAD_USB_IF_EN

TPAD_SPI_IF_EN

PM_SLP_S4_L

PM_SLP_S4_L

SMC_LID

SMBUS_SMC_3_SCL

PP3V3_S4

SMC_ONOFF_L

TPAD_SPI_INT_S4_WAKE_L_CONN

TPAD_SPI_MOSI_RTPAD_WAKE_LTPAD_SPI_CLK_R

USB_TPAD_NUSB_TPAD_P

SMC_LIDTPAD_SPI_MISO_R

TPAD_SPI_CS_R_L

SMC_LSOC_RST_L

PP3V3_S3

TPAD_SPI_CS_CONN_L

PP3V3_S3

PP3V3_S0

TPAD_SPI_CS_L

PP3V42_G3H

SMC_LSOC_RST_L

SMBUS_SMC_3_SDASMBUS_SMC_3_SCL

TPAD_USB_IF_EN_CONNPP5V_S4_IPD

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=5V

48 OF 121

<BRANCH>

<SCH_NUM>

<E4LABEL>

36 OF 76

36 37 38 64

36 37 40 44 64 73

64

64

29 33 36 38 39 58 62 64

53 54 62

36 37 38 61 64 65

36 37 40 44 64 73

29 33 36 38 39 58 62 64

64

64

64

64

64

64

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

8 11 12 13 15 17 18 27 30 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

17 30 35 37 38 40 46 49 50 59 61 62 64 65

36 38 64

64

64

www.vinafix.vn

LPC0AD3

LPC0CLK

LPC0FRAME*

LPC0AD1

LPC0AD2

AIN08

AIN07

LPC0CLKRUN*

LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX

PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119

PP4/IRQ120

C0-

WT2CCP0/PH0

WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2

SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127

PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4

PF5

T1CCP0/PJ0

T2CCP0/PJ2

T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK

SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

IN

BI

BI

BI

BI

IN

IN

IN

BI

OUT

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

NC

OUT

NC

BI

OUT

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT

BI

OUT

OUT

BI

IN

OUT

IN

IN

OUT

OUT

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(PL6)

(PL7)(OD)

(OD)

Unused pins have "SMC_Pxx" names. Unused

NOTE:

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

If SMS interrupt is not used, pull up to SMC rail.

NOTE:

(OD)

(OD)

pins designed as outputs can be left floating,those designated as inputs require pull-ups.

(OD)

SMS Interrupt can be active high or low, rename net accordingly.

H10

G4

H3

H4

J3

K4

K3

L7

K7

E12

E13

E11

F11

M1

L3

C5

D5

C8

A9

B9

C9

F3

F4

N9

M9

K10

L10

N1

L4

M3

M2

L6

M6

K5

N6N5

F5

E4

D4

K6

D8

L5

J13

J12

M5

L12M13

M11

N11

N12L11

D10

G3

L13

H11

A12C11

B12

J2

J4

K9

L9

C6

C4

L1

H13

F12

C13

F13

D12

G11

H12

D11

C12

A13

B13

N3

N4

M7

N7

K8

L8

M8

N8

N2

M4

D13

E10

L2

K1

K2

A8

B8

A7

B7

H2

H1

G1

G2

B2

B1

C2

C1

A6

B6

A5

B5

A4

B4

A3

B3

F1

F2

E1

E2

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

N10

M10

N13

D2

D1

D6

K13

J6

J1

D3

J10

J9

J7

F10

E9

E8

E6

D7

K12

B10

A11

A10

C10G10

B11

G13G12

A2

M12

E3C3

J11

J8

J5

H9

H5

F9

E5

D9

K11

C7

A1

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

2 1

XW5000SM

PLACE_NEAR=U5000.A1:4MM

38 46 50 64

38 69

2

1R50021M

MF

5%1/20W

2012

1 C50060.1UF

X5R-CERM0201

10V10%

2

1 C50050.1UF

0201X5R-CERM10V10%

2

1 C5009

0201

10V

0.1UF

X5R-CERM

10%2

1 C50080.1UF

0201X5R-CERM10V10%

2

1 C50040.1UF

0201X5R-CERM10V10%

2

1 C50030.1UF

X5R-CERM0201

10V10%

2

1 C50070.1UF

0201X5R-CERM10V10%

14 46 64 69

14 46 64 69

14 46 64 69

14 46 64 69

17 69

14 46 64 69

18

15 46 64

13 46 64

13 46 64

13

40 60 73

40 60 73

14 32 40 43 44 64 69 73

14 32 40 43 44 64 69 73

40 61 65 73

40 61 65 73

36 40 44 64 73

36 40 44 64 73

64

64

40 48 50 64 73

40 48 50 64 73

39 41

39 42

39 41

39 42

39 41

39 43

39 41

39 42

39 43

39 41

39 41

39 42

39 41

39 41

39 41

15 34 39 65

39 41

39 42

39 42

39 42

39 42

39 43

39 43

29 38 39 41 64

38 54 59

13

17 27 38

38

35 38 68

35 38 68

64

46 69

46 69

46 69

46 69

35

64

16 17 59

38

13 16

13 17 64

13 38

15

38

38

38 46 64

38 46 64

64

64

39

56

45

45

64

29 36 39

36 38 61 64 65

38

38 50 61 65

13 18

13 17 18 59

13 18 29 36 59

13 59

36 38 64

25 33 38

38 59

13

29 38 64

64

39

38

39

54 59

17

21

L5001

0402

30-OHM-1.7A

6 38 51 67

30

64

30

61 65

13 16 17

6 67

38

39 42 58

2

1 C5016

PLACE_NEAR=U5000.K13:5MM

10V

0201X5R-CERM

0.1UF10%

2

1 C5015

PLACE_NEAR=U5000.K13:5MM

10V10%0.1UF

0201X5R-CERM 2

1 C5013

PLACE_NEAR=U5000.J1:5MM

10%0.1UF

0201

10VX5R-CERM2

1 C5010

0201-1X5R6.3V20%1.0UF

PLACE_NEAR=U5000.D6:5MM

2

1 C5001

X5R-CERM

0.1UF

0201

10V10%

2

1 C5002

0201

6.3V

1UF20%

X5R

38

43

64

2

1 C502120%1UF

0201X5R6.3V

BYPASS=U5000.D2:D1:1MM

2

1 C5020

10VX5R-CERM0201

0.01UF10%

BYPASS=U5000.D2:D1:1MM

64

2

1 C5011


0.1UF10%

0201

10VX5R-CERM2

1 C5012

X5R-CERM10V

0201

0.1UF10%


2

1 C5014

0201-1X5R6.3V20%1.0UF


2

1 C5017

0201-1X5R6.3V

1.0UF20%

PLACE_NEAR=U5000.D6:5MM

38 39

29 39

38

38

30

39

SMCSYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013

SMC_PCH_SUSWARN_L

PM_PCH_SYS_PWROK

SMC_WIFI_PWR_EN

SMC_RX_L

SMC_ONOFF_L

PM_SLP_S0_L

NC_SMC_DP_HPD_L

TP_SMC_5VSW_PWR_EN

SMC_PWRFAIL_WARN_L

SMC_TX_L

SMS_INT_L

SMC_PME_S4_WAKE_L

SMC_PECI_LCPU_PECI_R

SMC_LID

SMC_BC_ACOK

NC_SMBUS_SMC_4_ASF_SCLSMBUS_SMC_3_SDA

SMC_TOPBLK_SWP_LNC_SMC_FAN_1_TACH

PP3V3_S0SW_SDSMC_CAMERA_ISENSE


PP3V3_S5_SMC_VDDAMIN_LINE_WIDTH=0.25MM

VOLTAGE=3.3VMIN_NECK_WIDTH=0.1MM

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

SMC_LRESET_L

SMC_EXTAL

SMC_P1V05S0_ISENSE

SMC_CLK32K

SMC_WAKE_SCI_L

SMC_HS_COMPUTING_ISENSE

LPC_SERIRQ

LPC_AD<0>

CPU_PROCHOT_L

SPI_SMC_CS_L

SMC_TDOSMC_TDI

SMC_RESET_L

NC_SMC_HIB_L

SMC_BMON_DISCRETE_ISENSE

LPC_AD<2>

SMC_WAKE_LWIFI_EVENT_L

SMC_XTAL

SMC_P3V3S5_ISENSE

SMC_CPU_IMON_ISENSE

SMC_PBUS_VSENSE

SMC_CPUDDR_ISENSE

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_3_SCL

NC_SMC_XOSC1

SMC_RUNTIME_SCI_L

SMC_DEBUGPRT_EN_L

SMC_TCKSMC_TMS

SMC_BMON_ISENSESMC_DCIN_ISENSE

SMC_PANEL_ISENSESMC_1V2S3_ISENSE

SMC_WLAN_ISENSESMC_SSD_ISENSESMC_P3V3S0_ISENSE

SMC_P1V05S0_VSENSE

SMC_LCDBKLT_ISENSE

PP1V2_S5_SMC_VDDCMIN_LINE_WIDTH=0.25MMMIN_NECK_WIDTH=0.1MMVOLTAGE=1.2V

PP3V42_G3HSMC_CPU_ISENSE

SMBUS_SMC_0_S0_SDA

LPC_FRAME_LLPC_CLK24M_SMC

LPC_AD<1>

PM_CLKRUN_L

SMBUS_SMC_1_S0_SCL

PM_SLP_S5_L

SPI_DESCRIPTOR_OVERRIDE_L

SPI_SMC_CLK

SPI_SMC_MISO

NC_SMC_SYS_LED

CPU_CATERR_L

NC_SMC_GFX_THROTTLE_L

CPU_THRMTRIP_3V3

PM_BATLOW_L

NC_BDV_BKL_PWM

PM_SYSRST_LMEM_EVENT_L

NC_SMC_GFX_OVERTEMP

LPC_AD<3>SMC_DCIN_VSENSE

SMC_OTHER_HI_ISENSE

SMC_THRMTRIPALL_SYS_PWRGD

SMC_SENSOR_PWR_EN

PP3V3_WLAN

SMC_CPUVR_ADJUST_ISENSE

SPI_SMC_MOSI

SMC_PCH_SUSACK_L

SMC_OOB1_R2D_L

SMC_PME_S4_DARK_LSMC_S4_WAKESRC_EN

NC_SMC_FAN_5_CTL

SMC_CPU_VSENSE

PM_SLP_S3_LPM_SLP_S4_L

NC_SMBUS_SMC_4_ASF_SDASMBUS_SMC_5_G3_SCLSMBUS_SMC_5_G3_SDA

SMC_FAN_0_CTLSMC_FAN_0_TACHNC_SMC_FAN_1_CTL

SMC_SYS_KBDLEDNC_SMC_T25_EN_L

SMC_ADAPTER_EN

SMC_OOB1_D2R_L

SMC_CPU_DBGPWR_RD_L

SMC_PM_G2_EN

SMC_DELAYED_PWRGDSMC_PROCHOT

SMC_DEBUGPRT_RX_LSMC_DEBUGPRT_TX_L

SMC_VCCIO_CPU_DIV2SMC_S5_PWRGD_VIN

SYS_ONEWIRE

PM_DSW_PWRGD

PM_PWRBTN_L

S5_PWRGD

SMC_SENSOR_ALERT_L

SMBUS_SMC_0_S0_SCL

LPC_PWRDWN_L

SMC_BIL_BUTTON_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

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IN

OUT

BI

IN

IN

IN OUT

IN OUT

OUT

IN

BIOUT

IN

OUT

SYM_VER_2

G S

D

S

D

G

S

D

G

NCNC IN

SN0903049

PAD

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

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SMC Reset "Button", Supervisor & AVREF Supply

Mobiles: 3.42VDesktops: 5V

Module has 3.3K PU

(IPU)

(IPU)

SMC Crystal Circuit

Debug Power "Buttons"

Used on mobiles to support SMC reset via keyboard.MR1* and MR2* must both be low to cause manual reset.

values:5,6,8,10,12,16,18,20,24,25 MHz

To SMC

SMC12 PECI Support

From SMC

From/To CPU/PCH

SMC USB Clock require these crystal

NOTE: Internal pull-ups are to VIN, not V+.

21R5170 10KMF1/20W 2015%

21R5171 100KMF1/20W 2015%21R5173 10KMF1/20W 2015%21R5174 100KMF1/20W 2015%

21R5177 10KMF1/20W 2015%21R5178 10KMF1/20W 2015%21R5179 10KMF1/20W 2015%

21R5180 10KMF1/20W 2015%

21R5185 10KMF1/20W 2015%

37 38

15 38 67

2

1R5115

SILK_PART=PWR_BTN

OMIT

603

PLACE_SIDE=TOP

1/10WMF-LF

05%

6 37 51 67

37

21R5189 10KNO STUFF

MF1/20W 2015%

21R5181 10KMF1/20W 2015%

21

R5110

1%

2.49K

MF1/20W

201

2

1 C5111

0201NP0-C0G-CERM25V

12PF5%

21R5187 100KMF1/20W 2015%21R5192 100KMF1/20W 2015%

2

1R5116PLACE_SIDE=BOTTOM

OMIT

MF-LF603

1/10W

SILK_PART=PWR_BTN

05%

2

1R5101

SILK_PART=SMC_RST

1/10W

PLACE_SIDE=BOTTOM

603MF-LF

OMIT

05%

36 37 38 64

36 64

2

1C5101

0201

10%10V

0.01UF

X5R-CERM

2

1C5120

CERM-X5R6.3V10%

402

0.47UF

2

1 C5126

0201

10VX5R-CERM

0.01UF10%

2

1R5100100K

MF1/20W

201

5%

37 46 50 64

13 69 21

R5112

PLACE_NEAR=U0500.AE6:5.1mm

22

MF1/20W 2015%37 69

21R5190100KMF1/20W 2015%

21R5175 20KMF1/20W 2015%21R5176 20KMF1/20W 2015%

21R5186 10KMF1/20W 2015%

2

1R51881K

MF1/20W

201

5%

2

1 C511012PF25VNP0-C0G-CERM0201

5%

2

1R5197100K1%

MF1/20W

201

2

1R51961%100K

MF1/20W

201

21R5193 10KMF1/20W 2015%

36 37 38 64

37

2

1R5153NOSTUFF

1.6K

MF1/20W

201

5%

21

R5152

MF1/20W

0201

0

5%

2

1R5151330

MF1/20W

201

5%

21R5114 10KNO STUFFMF1/20W 2015%21R5117 100KMF1/20W 2015%

21R5167 100KMF1/20W 2015%

6 67

37 21

R513443

MF1/20W

201

5%

15 38 67

2

3

1Q5158

DFN1006-3

CRITICAL

MMBT3904LP-7

37 38

2

1C512510UF

X5R-CERM

20%10V

0402-1

21

R51583.3K

MF1/20W

201

5%

21R5191100KMF1/20W 2015%

31

42

Y5110CRITICAL

12.000MHZ-30PPM-10PF-85C3.2X2.5MM-SM

21

3Q5150DMN32D2LFB4

DFN1006H4-3

CRITICAL1

2


45


2

1 C5127NOSTUFF

4.7UF6.3V

402

20%

X5R

21

R5127

MF-LF1/16W

402

0

5%

21R5172 10KMF1/20W 2015%

25 33 37 38

2

1 C5134

PLACE_NEAR=Q5150.2:5MM

NOSTUFF

47PF

0201NP0-C0G-CERM25V5%

2

1C5131

0201NP0-C0G-CERM

PLACE_NEAR=Q5159.6:5MM

25V

47PF5%

31

9

5

8

7

6

2

4

U5110VREF-3.3V-VDET-3.0V

DFN

CRITICAL

21R5198100KMF1/20W 2015%


SMC Shared SupportSYNC_MASTER=J41_MLB

SMC_BC_ACOK

PM_THRMTRIP_L

CPU_PROCHOT_L

SMC_PECI_L

CPU_PECI_R

PP1V05_S0

PM_THRMTRIP_L

SMC_PME_S4_DARK_L

SMC_ONOFF_L

SMC_THRMTRIP

SMC_PROCHOT

PP1V05_S0

SMC_PECI_L_R

SMC_CLK32K

CPU_THRMTRIP_3V3

CPU_PECI

PM_THRMTRIP_R_L

SMC_XTAL

MAKE_BASE=TRUESMC_PME_S4_DARK_L

PM_CLK32K_SUSCLK_R

MAKE_BASE=TRUESMC_BC_ACOK

SMC_EXTAL

GND_SMC_AVSS

PP3V42_G3H

VOLTAGE=3.42V

PP3V42_G3H_SMC_SPVSRMIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.4 mm

SMC_ONOFF_L

SMC_MANUAL_RST_L

SMC_RESET_L

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSSMIN_NECK_WIDTH=0.1 mmVOLTAGE=0V

SMC_LSOC_RST_L

PP3V3_S5_AVREF_SMCMIN_LINE_WIDTH=0.4 mm


WIFI_EVENT_L

SMC_ROMBOOT

PP3V42_G3H

SMC_PME_S4_DARK_L

SMC_ONOFF_LSMC_SENSOR_ALERT_LSMC_LIDSMC_TX_LSMC_RX_LSMC_DEBUGPRT_TX_L

CPU_THRMTRIP_3V3MEM_EVENT_L

PP3V3_S4

PP3V3_WLAN

SMC_BC_ACOK

SMS_INT_L

SMC_TCK

SMC_S5_PWRGD_VIN

SMC_BIL_BUTTON_L

SMC_TDO

SMC_VCCIO_CPU_DIV2

SMC_TMS

SMC_S4_WAKESRC_EN

SMC_DELAYED_PWRGD

SMC_THRMTRIPSMC_ADAPTER_ENSMC_PM_G2_EN

SMC_TDI

SMC_DEBUGPRT_RX_L

SMC_XTAL_R

PP3V42_G3H

PP3V3_S0

<BRANCH>

<SCH_NUM>

<E4LABEL>

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6 8 11 15 16 17 27 38 42 51

55 58 59 62 64

37

25 33 37 38

37 38 50 61 65

37

37 38 41 42 43

17 30 35 36 37 38

40 46 49

50 59 61

62 64 65

37 38 41 42 43

37

29 37 64

46 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

25 33 37 38

36 37 38 64

37 39

36 37 61 64 65

37 46 64

37 46 64

35 37 68

37 38

37

29 33 36 39 58 62 64

29 37 39 41 64

37 38 50 61 65

37

37 46 64

37

37

37 46 64

37

37 46 64

37 59

17 27 37

37 38

13 37

37 54 59

37 46 64

35 37 68

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8 11 12 13 15 17 18 27 30 36 39 40 41 42 43 44 45 56 59 61

62 64 65 74

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IN

IN

OUT

OUT

IN

IN

IN

OUTIN

IN

IN

IN

IN

OUT

IN OUT

INOUT

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Top-Block Swap

SD alias on page 103

29 36 37 39

29 36 37 39

2

1R52825%

201

1/20WMF

100K

29 36 37 39

37 38

44

44 21

R5212

5%

201

1/20WMF

100

21

R5211

5%

201

1/20WMF

100

NOSTUFF

21

R5210

5%

201

1/20WMF

10061 65

21

R5283

5%

201

1/20WMF

1K15 37

21R52945% 2011/20W MFNOSTUFF10K

21

R5213

5%

201

1/20WMF

10043

21

R5214

5%

201

1/20WMF

10044

21

R5215

5%

201

1/20WMF

100

NOSTUFF

14

2

1R52965%

201

1/20WMF

1K

21R52955% 2011/20W MF

10K NOSTUFF

21

R5216

5%

201

1/20WMF

10043

15 34 37 65

37 13

13 37

21

R5230

5%

0

0201

1/20WMF

21

R5231

5%

0

0201

1/20WMF

SMC Project SupportSYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013

PCH_SUSACK_L

PCH_SUSWARN_L

SMC_PCH_SUSACK_LMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_PCH_SUSWARN_L

SMC_SENSOR_PWR_EN

SMC_CPU_VSENSE

SMC_LCDBKLT_ISENSE

SMC_P3V3S5_ISENSE

SMC_SSD_ISENSE

SMC_CPUDDR_ISENSE

SMC_WIFI_PWR_ENMAKE_BASE=TRUESMC_WIFI_PWR_EN

PP3V3_S0SW_SD

SMC_CAMERA_ISENSEMAKE_BASE=TRUESMC_P3V3S0_ISENSE

SMC_BMON_COMP_ALERT_L

MAKE_BASE=TRUESMC_SENSOR_PWR_EN

FINSTACKSNS_ALERT_L

SMC_WLAN_ISENSE

SMC_PANEL_ISENSE

SMC_DCIN_VSENSEMAKE_BASE=TRUE

SMC_SENSOR_PWR_EN

PCH_STRP_TOPBLK_SWP_L

SMC_PME_S4_WAKE_LSMC_PME_S4_WAKE_L

PP3V3_S4

SMC_HS_COMPUTING_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_PBUS_VSENSE

SMC_BMON_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_CPU_ISENSE

MAKE_BASE=TRUESMC_DCIN_ISENSE

SMC_CPU_IMON_ISENSE


SMC_HS_COMPUTING_ISENSE

MAKE_BASE=TRUESMC_PME_S4_WAKE_L

PP3V3_WLAN

CPUBMONSNS_ALERT_L

SMC_DCIN_ISENSE

SMC_OTHER_HI_ISENSEMAKE_BASE=TRUE

SMC_P1V05S0_ISENSEMAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUESMC_BMON_DISCRETE_ISENSE

MAKE_BASE=TRUESMC_CPUDDR_ISENSE

SMC_1V2S3_ISENSE

SMC_P3V3S0_ISENSE

SMC_CPU_ISENSE

SMC_BMON_ISENSE

SMC_PBUS_VSENSE

SMC_TOPBLK_SWP_L

PP3V3_S0

SMC_P1V05S0_VSENSE

SMC_P1V05S0_ISENSE

TP_SMC_5VSW_PWR_ENTP_SMC_5VSW_PWR_ENMAKE_BASE=TRUE

SMC_SENSOR_PWR_EN

PP3V3_S4

SMC_WIFI_PWR_EN


SMC_DCIN_VSENSE

SMC_SSD_ISENSEMAKE_BASE=TRUE

SMC_WLAN_ISENSEMAKE_BASE=TRUE

SMC_LCDBKLT_ISENSEMAKE_BASE=TRUE

SMC_PANEL_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_1V2S3_ISENSE

MAKE_BASE=TRUESMC_CAMERA_ISENSE

MAKE_BASE=TRUESMC_P1V05S0_VSENSE

SMC_CPU_VSENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_P3V3S5_ISENSE

MAKE_BASE=TRUEPP3V3_WLAN

SMC_CPU_IMON_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_CPUVR_ADJUST_ISENSE

PCH_SML1ALERT_L

SMC_HS_COMP_ALERT_L

CPUTHMSNS_ALERT_L

SMC_SENSOR_ALERT_LTBTMLBSNS_ALERT_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

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37 39 42

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29 37 39 29 37 39

37 39 41

37 39 41

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37 39 41

37 39 43

37 39 42

37 39 42 58

29 33 36 38 39 58 62 64

37 39 41

37 39 42

37 39 41

37 39 42

37 39 41

37 39 43

37 39 43

37 39 41

29 37 38 39 41 64

37 39 41

37 39 41

37 39 42

37 39 41

37 39 43

37 39 42

37 39 41

37 39 41

37 39 42

37 39 41

37 39 42

8 11 12 13 15 17 18 27 30 36 38 40 41 42 43 44 45 56 59 61 62

64 65 74

37 39 42

37 39 42

37 39 37 39

37 39 42 58

29 33 36 38 39 58 62 64

29 37 39

37 39 43

37 39 42

37 39 41

37 39 41

37 39 41

37 39 43

37 39 41

37 39 41

37 39 42

37 39 42

37 39 42

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(Write: 0x30 Read: 0x31)

ISL6259 - U7100

SMC "5" SMBus G3H Connections

SMC "3" SMBus S0 Connections

Battery Charger


SMC

XDP Connectors

(Write: 0x72 Read 0x73)

J4002

ALS

U5000

(MASTER)

SMC


PAC1921: U5620

EMC1704-02: U5800

CPU Temp, Inlet, DDR, BMON THR

J4800



VRef DACs

connector page andgated by EDP_PANEL_PWR

J43 J41

(See Table)

Pullups are on eDP

J6950

(See Table)

TBT & MLBBOT, TBD Temp

EMC1414: U5810

LYNX POINT LP S0 "SMLink 0" Connections

LYNX POINT LP S0 "SMLink 1" Connections

U0500

U0500

LYNX POINT LP

LYNX POINT LP

J1800

U0500

LYNX POINT LP

(MASTER)


Battery Manager - (Write: 0x16 Read: 0x17)


U5000


Battery

J9500

U2800

U5000

(MASTER)

U5000

(MASTER)

(MASTER)

U5000

SMC

U2201

U2200

Trackpad

J8300

TBT

SMC

(MASTER)

Margin Control

(MASTER)

(Write: 0xFE Read: 0XFF)

LIO Finstack Temp


SMC

(MASTER)


access PCH

SMLink 1 is slave port to

U7701

(Write: 0x92 Read 0x93)

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

(Write: 0x58 Read: 0X59)

LCD BACKLIGHT

LYNX POINT LP S0 SMBus "0" Connections

Battery

Internal DP

Samsung LGD Samsung LGD AUO

(* = Multiple options)

Chipset current

Internal DP

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

SMC S0 "1" SMBus Connections

2

1R5361

1/20WMF

5%2.0K

2012

1R5360

1/20W5%

MF

2.0K

201

2

1R53802.0K1/20W

MF201

5%

2

1R5381

201

2.0K5%1/20WMF

2

1R53705%

201MF

1/20W

1K

2

1R5371

MF1/20W

201

5%1K

2

1R5310

201MF

1/20W5%

8.2K

2

1R5311

201MF

8.2K1/20W5%

2

1R53011K

MF201

1/20W5%

2

1R5300

201

1/20WMF

1K5%

2

1R5391

201MF

5%2.0K

1/20W

2

1R53905%

MF201

1/20W

2.0K


SMBus ConnectionsSYNC_MASTER=J41_MLB

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_DATA

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_3_SDAMAKE_BASE=TRUE

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

SMBUS_PCH_CLK

SMBUS_PCH_DATA

PP3V3_S0

SMBUS_PCH_CLK

SMBUS_PCH_CLK

SMBUS_PCH_DATA

PP3V3_S0

SML_PCH_0_CLKMAKE_BASE=TRUE

SML_PCH_0_DATAMAKE_BASE=TRUE

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_3_SCL

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

PP3V3_S3

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE

SMBUS_PCH_CLK

PP3V3_S0

SMBUS_SMC_3_SCLMAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_S0

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

PP3V42_G3H

SMBUS_SMC_5_G3_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_1_S0_SDAMAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

40 OF 76

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<E4LABEL>

<SCH_NUM>

<BRANCH>

37 40 61 65 73

37 40 61 65 73

14 32 37 40 43 44

64 69 73

14 32 37 40 43 44

64 69 73

37 40 60 73

37 40 60 73

14 16 19 25 40 56 69

14 16 19 25 40 56 69

14 16 19 25 40 56

69

14 16 19 25 40 56

69

36 37 40 44 64 73

36 37 40 44 64 73

36 37 40 44 64 73

36 37 40 44 64 73

14 16 19 25 40 56

69

14 16 19 25 40 56

69

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

14 16 19 25 40 56

69

14 16 19 25 40 56 69

14 16 19 25 40 56

69

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

14 69

14 69

37 40 48 50 64 73

37 40 48 50 64 73

37 40 61 65 73

36 37 40 44 64 73

14 16 19 25 40 56

69

14 16 19 25 40 56

69

37 40 61 65 73

37 40 48 50 64 73

37 40 48 50 64 73

15 18 19 33 36 41 58 62 64

37 40 60 73

37 40 60 73

14 16 19 25 40 56 69

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

36 37 40 44 64 73

14 32 37 40 43 44 64 69 73

14 32 37 40 43 44 64 69 73

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

14 32 37 40 43 44

64 69 73

14 32 37 40 43 44 64 69

73

14 32 37 40 43 44 64

69 73

17 30 35 36 37 38 46 49 50 59 61 62 64 65

37 40 48 50 64 73

37 40 48 50 64 73

14 32 37 40 43 44 64 69

73

14 32 37 40 43 44

64 69 73

14 32 37 40 43 44 64 69

73

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OUT OUTIN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

V+

REFIN+

IN- OUT

GNDIN

OUT

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

OUT

V+

REFIN+

IN- OUT

GND

OUT

V+

REFIN+

IN- OUT

GND

OUTIN-

IN+ REF

V+

GND

OUTIN-

IN+ REF

V+

GND

V+

REFIN+

IN- OUT

GND

Apple Inc.


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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3





EDP Current :12A

GAIN : 100X

IC0R : COMPUTING High Side Current Sense

MAX Vdiff : 0.06 mV

IBLC : LCD Backlight Driver Input Current Sense

(For R and C)

MAX Vdiff : 16.36 mV

GAIN : 200X

IS2C : 3.3V Camera Current Sense

IR0C : 3.3V S0 FET Current Sense

DC-IN (AMON) Current Sense

Max VOut: 1.4V at 8.25A

GAIN : 1000X

EDP Current :1.02A

MAX Vdiff : 3.06 mV

EDP Current : 0.82A

IO0R : OTHER High Side Current Sense

GAIN : 50X


(500V/V)

(200V/V)

(100V/V)

APN: 107S0137

(50V/V)

(1000V/V)

PLACEMENT_NOTEs:

(200V/V)

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

(For R and C)

Scale: 2.5A / V

CHARGER BMON High Side Current SenseReplacing caps with 100K PD on ISENSE SMC inputs

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

(For R and C)

PLACEMENT_NOTEs:

(200V/V)

PLACEMENT_NOTEs:

(For R and C)

(100V/V)

APN: 104S0024

IAPC :AirPort Current Sense

MAX Vdiff : 24 mV

EDP Current :10.75A

IM3C :DDR 1V2 Current Sense (LPDDR + CPUDDR)EDP Current : 7.57A


ISDC : SSD Current Sense

EDP Current : 1.00A

MAX Vdiff : 25 mV

GAIN : 100X

EDP Current : 3.00A

GAIN : 200X

MAX Vdiff : 15 mV

EDP Current : 0.67A

GAIN : 500X

GAIN : 200X

EDP Current: 3.5A

Sense R is R7120, 20mOhm

ISL6259 Gain: 20x

ISL6259 Gain: 36x

Scale: 2.78A / V


EDP Current: 310A

SENSE R : R7450 0.002R

37 39 37 39

2

1 C5431

10%

PLACE_NEAR=U5000.B3:11MM

2.2NF

10V

0201

X5R-CERM

21

R5431

201


45.3K

1%

MF1/20W

50

37 39

37 39

37 39

37 39

2

1 C5465

Place close to SMC

X5R6.3V

PLACE_NEAR=U5000.A5:11mm

DRAM_ISNS:YES

20%0.22UF

0201

21

R5465

DRAM_ISNS:YESPLACE_NEAR=U5000.A5:11mm

Place close to SMC

201

4.53K

1%

MF1/20W

2

1 C5460DRAM_ISNS:YES

10%0.1UF

0201CERM-X5R6.3V

53 74

53 74

2

1 C5475PLACE_NEAR=U5000.C1:11mm

AIRPORT_ISNS:YES

Place close to SMC

X5R6.3V

0.22UF20%

0201

21

R5475

PLACE_NEAR=U5000.C1:11mm

AIRPORT_ISNS:YES

Place close to SMC

201

4.53K

1%1/20WMF

2

1 C5485SSD_ISNS:YES

Place close to SMC 0201

0.22UF20%


6.3VX5R

21

R5485


SSD_ISNS:YES

Place close to SMC

201

1/20W1%

4.53K

MF

2

1 C5470

10%0.1UF

0201CERM-X5R6.3V

AIRPORT_ISNS:YES

2

1 C5495PLACE_NEAR=U5000.B6:11mm

LCDBKLT_ISNS:YES

Place close to SMC

0.22UF20%

0201

6.3VX5R

21

R5495

PLACE_NEAR=U5000.B6:11mm

LCDBKLT_ISNS:YES

Place close to SMC

1%

4.53K

1/20WMF201

2

1 C5490LCDBKLT_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

21

R5422

201


1/20W

MF

1%

300K

2

1 C5422

10%

0201

10V

X7R-CERM

3300PF


37 39

2

1 C5455

Place close to SMC

X5R6.3V

PLACE_NEAR=U5000.E2:11mm

0201

CPU_HS_ISNS:YES0.22UF20%

21

R5455

201


1%

MF

4.53K

CPU_HS_ISNS:YES

1/20W

2

1 C5450

10%0.1UF

0201CERM-X5R6.3V

CPU_HS_ISNS:YES

2

1 C5480SSD_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

37 39

2

1 C5433

OTHER_HS_ISNS:YES0201

20%0.22UF


6.3VX5R

Place close to SMC

21

R5433

201


4.53K

MF

1%1/20W

Place close to SMC

OTHER_HS_ISNS:YES2

1 C5430

CERM-X5R

10%0.1UF

0201

6.3V

OTHER_HS_ISNS:YES

3

1

6

4

5

2

U5430

OTHER_HS_ISNS:YESPLACE_NEAR=R5430:5mm

INA213

CRITICALSC70

27 41 42 49

50 56

62 64

54 62 64

50

3

1

6

4

5

2

U5460

PLACE_NEAR=R7450:5mm

DRAM_ISNS:YES

CRITICALSC70

INA210

4

3

2

1R5450

0612

1%0.002

MF1W

CRITICAL

4

3

2

1R5480

0612MF1W1%

0.003

CRITICAL

OMIT_TABLE

3

1

6

4

5

2

U5480

SSD_ISNS:YESPLACE_NEAR=R5480:5mm

SC70INA210

CRITICAL

37 39

2

1 C5445

Place close to SMC

X5R6.3V

PLACE_NEAR=U5000.B1:11mm

0.22UF20%

0201

3V3S0_ISNS:YES

21

R5445

Place close to SMC

201

1/20WMF

1%

4.53K

3V3S0_ISNS:YESPLACE_NEAR=U5000.B1:11mm

2

1 C544010%

0201CERM-X5R6.3V

0.1UF

3V3S0_ISNS:YES

3

1

6

4

5

2

U5440

SC70INA212

CRITICAL


3V3S0_ISNS:YES

37 39 21

R5425

Place close to SMC

201

CAM_ISNS:YESPLACE_NEAR=U5000.B2:11mm

1/20W

4.53K

MF

1%

2

1 C5425

Place close to SMC

CAM_ISNS:YES

20%

0201

0.22UF PLACE_NEAR=U5000.B2:11mm

6.3VX5R

2

1 C5420

6.3VCERM-X5R0201

10%

CAM_ISNS:YES

0.1UF

3

1

6

4

5

2

U5490


LCDBKLT_ISNS:YES

SC70INA211

CRITICAL

21

R5421

402

5%

MF-LF

0

1/16W

21

R5423NOSTUFF

402

5%

MF-LF1/16W

0

4

3

2

1

R5470CRITICAL

0612

0.0251WMTL

1%

3

1

6

4

5

2

U5450SC70

INA214

CPU_HS_ISNS:YES

CRITICAL

3

1

6

4

5

2

U5470


AIRPORT_ISNS:YES

CRITICALSC70

INA214

3

1

6

4

5

2

U5420

CRITICALSC70

INA210

PLACE_NEAR=R8061:5mmCAM_ISNS:YES

2

1R545120K

201MF

1/20W5%

2

1R5432

201

5%1/20W

MF

20K

2

1R5461

201

5%1/20W

MF

20K

2

1R5471

201

5%1/20W

MF

20K

2

1R548120K

MF1/20W

5%

201

2

1R549120K

5%1/20W

MF201

2

1R5441

201

5%1/20W

MF

20K

2

1R542420K

5%1/20W

MF201

4

3

2

1R5430

0612-SHORT

0.0031%1wCYN

OMIT

4

3

2

1R5440

0612-SHORTCYN1w1%

0.003

OMIT

4

3

2

1R5420

0612-SHORT

0.0200.5%

1wMF

OMIT

4

3

2

1R5490

0612-SHORT

OMIT

MF1w

0.5%0.020

1 C5475 AIRPORT_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD117S0008

117S0008 1 C5485 SSD_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD

1117S0008 C5495 LCDBKLT_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD

3V3S0_ISNS:NO117S0008 1 C5445RES,MF,1/20W,100K OHM,5,0201,SMD

C54251117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD CAM_ISNS:NO

C54331117S0008 OTHER_HS_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD

107S0248 CRITICALRES,SENSE,0.003OHM,1W,4-TERM,1%,0612,TFT R54801

117S0008 DRAM_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD1 C5465

CPU_HS_ISNS:NORES,MF,1/20W,100K OHM,5,0201,SMD117S0008 1 C5455SYNC_MASTER=J41_MLB SYNC_DATE=03/28/2013

High Side Current Sensing

ISNS_AIRPORT_N

ISNS_AIRPORT_P

ISNS_P5VWLAN_IOUT SMC_WLAN_ISENSE

PP3V3_S4SW_SNS

PP3V3_WLAN

PP3V3_WLAN_RGND_SMC_AVSS

ISNS_1V2_S3_P

ISNS_1V2_S3_N ISNS_1V2_IOUT SMC_1V2S3_ISENSE

PP3V3_S4SW_SNS

GND_SMC_AVSS

PP3V3_S4SW_SNS

ISNS_LCDBKLT_IOUT

SMC_SSD_ISENSEISNS_P5VSSD_IOUT

PP3V3_S0SW_SSD

PP3V3_S0SW_SSD_FET_R

CHGR_BMON SMC_BMON_ISENSE CHGR_AMON SMC_DCIN_ISENSE

GND_SMC_AVSS

SMC_CAMERA_ISENSEISNS_CAMERA_IOUT

GND_SMC_AVSS

SMC_OTHER_HI_ISENSE

PP3V3_S3

PP3V3_S0

PP3V3_S3RS0_CAMERA

GND_SMC_AVSS

GND_SMC_AVSS

SMC_P3V3S0_ISENSE

PP3V3_S0

ISNS_HS_COMPUTING_N

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_IOUT SMC_HS_COMPUTING_ISENSE

PPBUS_S5_HS_COMPUTING_ISNS

GND_SMC_AVSS

ISNS_SSD_P

GND_SMC_AVSS

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUEVOLTAGE=8.6V


PPVIN_S0SW_LCDBKLT_FET

ISNS_SSD_N

MIN_LINE_WIDTH=0.4 MMPPVIN_S0SW_LCDBKLT



ISNS_HS_OTHER_N

ISNS_HS_OTHER_P

PPBUS_G3H

PP3V3_S4SW_SNS

HS_OTHER_IOUT

ISNS_P3V3_S0_IOUT

PP3V3_S4SW_SNS

PPBUS_G3H

GND_SMC_AVSS

PPBUS_S5_HS_OTHER_ISNS

ISNS_P3V3_S0_N

PP3V3_S0

ISNS_P3V3_S0_P

PP3V3_S4SW_SNS



PP3V3_S3RS0_CAMERAMIN_NECK_WIDTH=0.2 MM

ISNS_CAMERA_N

ISNS_CAMERA_P

PP3V3_S3RS0_CAMERA


VOLTAGE=3.3VPP3V3_S3RS0_CAMERA_R

PP3V3_S0_FET_R

PP3V3_S4SW_SNS


PPVIN_S0SW_LCDBKLT

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

<BRANCH>

<SCH_NUM>

<E4LABEL>

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www.vinafix.vn

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUTIN

IN

V+

REFIN+

IN- OUT

GND

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

IN

V-

V++

-

OUT

IN

IN

OUT

V+

REFIN+

IN- OUT

GND

OUT

IN

OUTIN-

IN+ REF

V+

GND

OUT

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL Apple Inc.


124578

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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



IR5C :3.3 S5 REG Current Sense

Replacing caps with 100K PD on ISENSE SMC inputs

(100V/V)


EDP Current : 3.00A

GAIN : 100X

1.05V Voltage Sense / Filter

CPU Vcore Voltage Sense / Filter

RTHEVENIN = 4573 Ohms

Max VOut: 3.3V at 19.77V Input

Enables DC-In VSense

divider when SUS present.

VD0R: DC-In Voltage Sense Enable & Filter

Max VOut: 3.3V at 19.77V Input

IC1C: 1.05V S0 CURRENT SENSE / FILTER

RTHEVENIN = 4573 Ohms

(200V/V)

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

Sense R is 0.75mOhm each, combined 0.375mOhm

EDP: 32A TDP :28.05A

Sense R is R7310, R7320

Gain:274.72x

EDP Current : 1A

MAX Vdiff : 5.65 mV

GAIN : 500X

(500V/V)

ICS0 : CPU VCore Load Side Current Sense

GAIN : 200X

VP0R: PBUS Voltage Sense Enable & Filter

IM0C : CPU DDR Current SenseEDP Current : 3.00A


37 39

58

2

1R5502

MF

1%100K1/20W

201

2

1R5501

1/20W

100K1%

MF201

37 39

2

1 C550420%0.22UF

0201

6.3VX5R

PLACE_NEAR=U5000.E1:11MM

2

1R55031%

MF1/20W

27.4K

201PLACE_NEAR=U5000.E1:11MM

2

1R55045.49K1/20W

1%

MF201


4

1

5

2

3

6

Q5500SOT-963

NTUD3169CZ

37 39 21

R5561

PLACE_NEAR=U5000.H2:11MM

P1V05_ISNS:YES

201

1/20WMF

1%

4.53K

2

1 C5561P1V05_ISNS:YES

X5R6.3V20%0.22UF

0201

PLACE_NEAR=U5000.H2:11MM

2

1 C5560P1V05_ISNS:YES

10%0.1UF

0201CERM-X5R6.3V

55 74

55 74

3

1

6

4

5

2

U5560SC70


P1V05_ISNS:YES



CRITICAL

INA211

21

R5548

201

1/20W

4.53K

MF

1%

CPUVR_ISNS:YESPLACE_NEAR=U5000.B4:11MM

37 39

2

1 C5541

X5R6.3V

CPUVR_ISNS:YES

0.22UF20%

0201


2

1 C554010%0.1UF

0201CERM-X5R6.3V

CPUVR_ISNS:YESPLACE_NEAR=U5540.5:3MM

52 74

37 39

2

1R551327.4K

1/20WMF

1%

PLACE_NEAR=U5000.B3:11MM201

2

1 C55140.22UF

0201


6.3VX5R

20%

2

1R5514

1/20W

5.49K

MF

1%

201

PLACE_NEAR=U5000.F1:11MM

2

1R5512

MF

100K1%

201

1/20W

4

1

5

2

3

6

Q5510NTUD3169CZ

SOT-963

2

1R5511100K

1/20W1%

MF201

13 59

5

2

4

3

1

U5540SC70-5OPA333DCKG4

CRITICALCPUVR_ISNS:YES

37 39

2

1 C5595

0201

0.22UF20%

Place close to SMC

6.3VX5R


P3V3S5_ISNS:YES

21

R5595

Place close to SMC

1/20WMF

1%

4.53K

201

P3V3S5_ISNS:YESPLACE_NEAR=U5000.A6:11mm

2

1 C5590P3V3S5_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

52 74

52 74

21

R5540

402

1%

4.42K

MF-LF

CPUVR_ISNS:YES

1/16W


21

R5541

402

1%

4.42K

MF-LF

CPUVR_ISNS:YES

1/16W


21

R5542

CPUVR_ISNS:YES

402MF-LF1/16W

4.42K

1%


21

R5543

CPUVR_ISNS:YES

402

1/16W

4.42K

1%

MF-LF


21

R5545

MF-LF402

1.43K

1%

CPUVR_ISNS:YES

1/16W

21

R5544

402

1.43K

MF-LF

1%1/16W

CPUVR_ISNS:YES

21

R5547

402

1M

CPUVR_ISNS:YES

MF-LF1/16W1%


2

1R5546CPUVR_ISNS:YES

MF-LF

1%1/16W

1M

402

37 39

2

1 C5575

Place close to SMC

CPUDDR_ISNS:YES

0.22UF20%

0201

6.3VX5R

PLACE_NEAR=U5000.H1:11mm

21

R5575

1/20W

Place close to SMC

MF

1%

4.53K

201

CPUDDR_ISNS:YESPLACE_NEAR=U5000.H1:11mm

2

1 C5570CPUDDR_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

3

1

6

4

5

2

U5570INA210

CPUDDR_ISNS:YES

SC70


37 39

2

1 C55300.22UF20%

0201

6.3VX5R

PLACE_NEAR=U5000.G1:11MM

21

R5530

1%

4.53K

MF1/20W

201

PLACE_NEAR=U5000.G1:11MM

21

XW5530SM

PLACE_NEAR=R7640.2:5 MM

52 74

3

1

6

4

5

2

U5590INA214

SC70

CRITICAL


P3V3S5_ISNS:YES

2

1R5571

MF1/20W

5%20K

201

2

1R5591

MF

5%20K

201

1/20W

2

1R5562

201

20K

MF1/20W

5%

4

3

2

1R5570

OMIT

0612-SHORTCYN1w1%

0.003

4

3

2

1R5590

0612-SHORT

OMIT

CYN1w1%

0.003

37 39 21

R5520

1/20W1%

MF

4.53K

201


2

1 C5520

0201

0.22UF20%6.3VX5R


21

XW5520

PLACE_NEAR=R7310.2:5 MM

SM

RES,MF,1/20W,100K OHM,5,0201,SMD CPUVR_ISNS:NO117S0008 1 C5541

1117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD C5595 P3V3S5_ISNS:NO


Voltage & Load Side Current Sensing

RES,MF,1/20W,100K OHM,5,0201,SMD P1V05_ISNS:NO117S0008 1 C5561

C5575RES,MF,1/20W,100K OHM,5,0201,SMD CPUDDR_ISNS:NO1117S0008

PPVMEMIO_S0_CPU

ISNS_P3V3S5_N

ISNS_P3V3S5_P

PBUS_S0_VSENSE

PBUSVSENS_EN_L


MAKE_BASE=TRUE


PPVMEMIO_S0_CPU

VOLTAGE=1.2V

PP3V3_S4SW_SNS

ISNS_1V05_S0_N

ISNS_1V05_S0_P

P1V05S0_IOUT SMC_P1V05S0_ISENSE

GND_SMC_AVSS

PP3V3_S4SW_SNS

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.20MM

PP3V3_S5_REG_RMIN_LINE_WIDTH=0.5 MM

ISNS_P3V3S5_IOUT

ISNS_CPUDDR_IOUT

SMC_P3V3S5_ISENSE

SMC_CPUDDR_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

CPUVR_ISUM_R_NCPUVR_ISNS1_N_R

CPUVR_ISUM_R_P

CPUVR_ISNS1_P_R

CPUVR_ISNS2_N

CPUVR_ISNS1_N

CPUVR_ISNS2_P

CPUVR_ISNS1_P

PPDCIN_G3H_ISOL

SMC_SENSOR_PWR_EN

GND_SMC_AVSSPBUSVSENS_EN_L_DIV

PPBUS_G3H

SMC_PBUS_VSENSE

PM_SLP_SUS_L

DCIN_S5_VSENSE

PDCINVSENS_EN_L_DIV

SMC_DCIN_VSENSE

P1V05VSENSE_INPP1V05_S0

CPUVSENSE_INPPVCC_S0_CPU

SMC_P1V05S0_VSENSE

SMC_CPU_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

PP3V3_S0

SMC_CPU_ISENSE

GND_SMC_AVSS

CPUVR_ISUM_IOUT

GND_SMC_AVSS

DCINVSENS_EN_L

PP3V3_S4SW_SNS

ISNS_CPUDDR_N

ISNS_CPUDDR_P

PP1V2_S3

PP3V3_S5

PP3V3_S5_REG_R

<BRANCH>

<SCH_NUM>

<E4LABEL>

55 OF 121

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74

74

8 10 42

41 42 43 58 62

37 38 41 42 43

41 42 43 58 62

42 54 37 38 41 42 43

37 38 41 42 43

74 43 74

74

43 74

49 50

62

64

37 38 41 42 43

27 41 49 50 56 62 64

6 8 11 15 16 17

27 38 51

55 58 59

62 64

8 10 52 62

64

37 38 41 42 43

37 38 41 42 43

8 11 12 13 15 17 18 27 30 36 38 39 40 41 43 44 45 56 59 61

62 64 65 74

37 38 41 42 43

37 38 41 42 43

41 42 43 58 62

74

74

17 19 20 21 22 23 53 62 70

8 11 13 15 16 17 18 28 29 34 57 58 59 60 62 64 74

42 54

www.vinafix.vn

SYM_VER_2

G S

D

IN

OUT

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

IN

IN

OUT

V+

REFIN+

IN- OUT

GND

OUT

SYM_VER_2

G S

D

IN

BI

IN

IN

BI

IN

IN

IN

OUT

OUT

OUT

VDD

SENSE-

ADDR_SEL/GAIN_SEL

SENSE+

EPADGND

SM_DATA/OUT_SEL

SM_CLK/INT_SEL

COMM_SEL

OUT

READ*/INT

OUT

OUTIN


Apple Inc.


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REVISION

BRANCH

6 3



ICS3 : Adjustable Gain CPU VR Current

PU: SMBus mode

(500V/V)

GAIN: 500X

In battery discharge scenario negative voltage will be

Sense Pins gain stage for U5800 (EMC1704)

With 100mA battery current, Will have 10.2mV differencegoing into sense pins of U5800.This will set the minumum current threshold at 0.100mAfrom 3.3V with increasing discharge current.

Replacing caps with 100K PD on ISENSE SMC inputs

CHGR_CSO_R_P/N are swapped on purpose


Gain: 50x

Scale: 0.25A / V

Vref = 0.406mV Vth = 0.442 = 1A from Battery

Vtl = 0.290mv = 0.687A from battery

(50V/V)

VR IMON Current Sense Filter

to measure power into the system

PLACEMENT_NOTEs:

(For R and C)

Hysteresis TBD based on RC value changes

R5821: ADDR - 0x56/0x57 (r/w)

present on IN+/- pins with INA output voltage decreasing

BMON : Discrete BMON Current Sense / Filter

Scale: 2A / V

MAX VOUT: 3V AT 0.825AEDP Current: 0.750 A

Max Vdiff: 15 mV

Gain: 200x(200V/V)

ILDC :LCD Panel Current Sense / Filter

Discrete High side Current threshold

2

5

1

4

3U5601

SC70-5MCP6541T

21

3U5602DFN1006H4-3

DMN32D2LFB4

42 74

39

21

R5609200K

MF-LF1/16W1%

40221

R560610.2K

1%1/16WMF-LF402

2

1R5604

MF-LF1/16W1%100K

402

2

1R5605

MF-LF1/16W1%100K

402

21

C5601

20%

0201

0.22UF

NO STUFF

6.3VX5R

42 74

2

1 C5603BYPASS=U5601:3MM

0.1UF10%

0201CERM-X5R6.3V

2

1R56214.3K

MF1/20W

201

5%

3

1

6

4

5

2

U5600CKPLUS_WAIVE=NdifPr_badTerm

SC70INA213

CKPLUS_WAIVE=NdifPr_badTerm

CRITICAL

2

1R5600

MF1/20W

0201

05%

2

1 C5600NOSTUFF

X5R

0.1UF10%25V

402

K

AD5607

SM-201

NOSTUFF

RB521ZS-30

2

1R5607NOSTUFF

MF1/20W

0201

05%

3

1

6

4

5

2

U5660

PLACE_NEAR=R7150:5MM



INA211SC70

CRITICAL

50 73

50 73

2

1 C5670PANEL_ISNS:YES

6.3VCERM-X5R0201

0.1UF10%

21

R5675

201

1/20W

Place close to SMC

4.53K

PANEL_ISNS:YES

1%


MF

2

1 C5675

X5R


0201

Place close to SMC

20%0.22UF

PANEL_ISNS:YES

6.3V

37 39

3

1

6

4

5

2

U5670

CRITICAL

PLACE_NEAR=R5470:5mmPANEL_ISNS:YES

INA210SC70

39

21

3U5612DMN32D2LFB4

DFN1006H4-3

21

C5611

20%

0201

0.22UF

NO STUFF

6.3VX5R

21

R5619

MF-LF1/16W1%

255K

402

2

5

1

4

3U5611MCP6541TSC70-5

21

R5616

MF-LF1/16W1%

10.2K

402

2

1 C5610

X5R

0.1UF10%25V

402

NOSTUFF

2

1 C5613BYPASS=U5601:3MM

6.3VCERM-X5R0201

0.1UF10%

2

1R5610

MF1/20W

0201

05%

2

1R5617NOSTUFF

MF1/20W

0201

05%

2

1R5614

MF-LF

1%1/16W

294K

402

2

1R56151%

MF-LF

49.9K1/16W

402

K

AD5617

SM-201

RB521ZS-30

NOSTUFF

41

21

R5668

MF1/20W

0201

0

5%

21

R5669NO STUFF

MF1/20W

0201

0

5%

21

R5667NO STUFF

MF1/20W

0201

0

5%

21

R5666

MF1/20W

0201

0

5%

14 32 37 40 44 64 69 73

41 43

74

41 43

74

2

1R5671

201

20K

MF1/20W

5%

2

1R560120K

MF1/20W

201

5%

2

1R566320K

MF1/20W

201

5%

4

3

2

1R5670OMIT

MF1w

0.5%0.020

0612-SHORT

14 32 37 40 44 64 69 73

2

1 C5665

20%

0201

6.3VX5R

NO STUFF

0.22UF

2

1 C5660PLACE_NEAR=U5660.3:5MM

6.3V

0.1UF10%

CERM-X5R0201

37

41 43 74

41 43 74

21

R5665

MF1/20W

0201

0

5%

2

1R56621%1K

MF1/20W

201

2

1R56611%

27K

MF1/20W

201

44 74

44 74 21

R5660

MF1/20W

0201

0

5%

37 39

2

1C5606BYPASS=U5600:3MM

6.3V

0.1UF10%

CERM-X5R0201

2

1 C5602

0201

0.22UF


20%6.3VX5R

21

R56084.53K

1%


MF1/20W

201

1

11

9

10

2

3

8

4

5

7

6

U5620

DFN

PAC1921-1-AIA

PLACE_NEAR=U5540.1:5MM

37 39 21

R5625PLACE_NEAR=U5000.A7:5MM

MF1/20W

0201

0

5%

2

1 C5625

NO STUFF0201

20%0.22UF


6.3VX5R

2

1 C5620

BYPASS=U5620.1:5:3MM

1.0UF20%6.3VX5R0201-1

21

R5620

MF-LF1/16W

100

1%

402

37 39

2

1 C56412.2NF

0201

X5R-CERM10V

PLACE_NEAR=U5000.B8:5MMNO STUFF

10%

51 21

R5641PLACE_NEAR=U5000.B8:5MM

MF1/20W

0201

0

5%

Debug Sensors 1SYNC_MASTER=J41_MLB SYNC_DATE=03/28/2013

C5675 PANEL_ISNS:NO1117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD

PP3V3_S0SW_LCD_RPP3V3_S0SW_LCD_R



ISNS_PANEL_P

PP3V3_S0

PP3V3_S4SW_SNS

PP3V3_S0SW_LCD



PP3V3_S0SW_LCD

ISNS_PANEL_N

BMON_COMP_OUT

ISNS_HS_COMPUTING_IOUT

HS_IOUT_R

CPUVRSNS_ADDR_SEL

PP3V3_SNS_CPUVR_ADJUST_ISNS


PP3V3_S4SW_SNS

SMC_CPUVR_ADJUST_ISENSE_R

PP3V3_S0 ISNS_HS_GAIN_P

ISNS_HS_COMPUTING_P

GND_SMC_AVSS

SMBUS_SMC_1_S0_SCL

CPUVR_IMON

HS_COMP_OUT

HS_COMP_FB

HS_IOUT_D

HS_COMP_VREF

SMC_BMON_COMP_ALERT_L


GND_SMC_AVSS

SMC_PANEL_ISENSE

GND_SMC_AVSS

CHGR_CSO_R_N

CHGR_CSO_R_P

SMC_CPU_IMON_ISENSE

GND_SMC_AVSS

SMC_CPU_DBGPWR_RD_L

SMBUS_SMC_1_S0_SDA


CPUVR_ISNS1_P_R

ISNS_HS_GAIN_N_R

ISNS_PANEL_IOUT

ISNS_HS_GAIN_OUT

BMON_COMP_VREF

BMON_IOUT_R

BMON_IOUT

BMON_IOUT_D

BMON_COMP_FB

PP3V3_S0

CPUVR_ISNS1_N_R

ISNS_HS_GAIN_N

SMC_HS_COMP_ALERT_L

ISNS_HS_COMPUTING_N

ISNS_HS_GAIN_OUT_R

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

ISNS_HS_GAIN_P_R

<BRANCH>

<SCH_NUM>

<E4LABEL>

56 OF 121

43 OF 76

43 60

43 60

74

8 11 12 13

15 17

18 27

30 36

38 39

40 41

42 43

44 45

56 59

61 62

64 65

74

41 42 43 58 62

43 60

43 60

74

41 42 43 58 62

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

37 38 41 42 43

37 38

41

42

43

37 38 41 42 43

37 38 41 42 43

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

www.vinafix.vn

DUR_SEL

DP1

VDD

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

GPIO

THRM_PADGND

TH_SEL

SENSE-

SENSE+

DN2/DP3

DP2/DN3

DN1

BI

BI

OUT

OUT

OUT

BI

BI

ALERT*

THERM*/ADDRDP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3GND

BI

BI

OUT

BI

BI

NC

OUT

Apple Inc.


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6 3



Detect DDR/5V/3.3V Proximity Temperature

Placement note:Place Q5830 between near rear vent on bottom side

Place Q5810 next to DDR/5V/3.3V supply on TOP side

Read Address: 0x99

Placement note:

Place Q5840 on MLB bottom side opposite U5810

Place Q5820 close to TBT on TOP side

Placement note:

Placement note:

TBD

Write Address: 0x39Read Address: 0x38

TBT,MLB Bottom Proximity Sensors

Placement note:

TBT, MLBBOT and TBD Temp Sensor

Write Address: 0x98

Place U5800 under CPU

Placement note:

CPU Proximity, Inlet ,DDR and BMON THR Sensor

21

R5840

MF1/20W

0201

0

5%

21

R5841

MF1/20W

0201

0

5%

2

3

1Q5810BC846BLPDFN1006H4-3

2

3

1Q5820DFN1006H4-3BC846BLP

2

3


2

3

1Q5840DFN1006H4-3BC846BLP

1

17

9

14

11

12

16

157

8

13

4

2

5

3 10

6

U5800EMC1704-2

QFN

CRITICAL

2

1 C58000.1UF10%6.3VCERM-X5R0201

21

R580047

MF1/20W

201

5%

14 32 37 40 43 64 69 73

14 32 37 40 43 64 69 73

2

1C5801

10%

PLACE_NEAR=U5800.2:5mm

PLACE_NEAR=U5800.3:5mm10V

X7R-CERM0201

2200PFNO_XNET_CONNECTION=TRUE

2

1C5802

10%

X7R-CERMPLACE_NEAR=U5800.5:5mm0201

10V

NO_XNET_CONNECTION=TRUEPLACE_NEAR=U5800.4:5mm

2200PF

2

1R5805

MF1/20W

0201

05%

39

43 74

43 74

36 37 40 64 73

36 37 40 64 73

2

1 C5810

10%0.1UF

0201CERM-X5R6.3V

1

7

9

10

6

4

2

5

3 8

U5810

CRITICAL

EMC1414-1-AIZLMSOP

21

R581047

MF1/20W

201

5%

2

1C5812

10%PLACE_NEAR=U5810.4:5mm

PLACE_NEAR=U5810.5:5mm 0201X7R-CERM

10V


2200PF

44 74

44 74

39

2

1R5803NOSTUFF

10K

MF1/20W

201

5%

2

1R5804NOSTUFF

10K

MF1/20W

201

5%

2

3


2

1C5813

10%10V

2200PF


X7R-CERM0201

44 74

44 74

2

1R5802100K

NOSTUFF

MF1/20W

201

5%

2

1R581122K

MF1/20W

201

5%

2

3

1Q5860

BC846BLPDFN1006H4-3

2

1R5806100K

MF1/20W

201

5%

39

2

1 C5830

25V

PLACE_NEAR=Q5830:3MM

NP0-C0G-CERM

47PF

0201

5%

2

1 C5811

25V


NP0-C0G-CERM

47PF

0201

5%2

1C5860

25V


NP0-C0G-CERM

47PF

0201

5%

2

1 C5820

25V


NP0-C0G-CERM

47PF

0201

5%

2

1 C5840

25V


NP0-C0G-CERM

47PF

0201

5%

2

1 C5850

25V


NP0-C0G-CERM

47PF

0201

5% SYNC_DATE=02/06/2013

Thermal SensorsSYNC_MASTER=J41_MLB

CPUBMONSNS_ALERT_L

CPUTHMSNS_ALERT_L

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_S0_CPUTHMSNS_R

VOLTAGE=3.3V


CPUTHMSNS_ADDR_SEL

INLET_THMSNS_D1_P

CPUTHMSNS_DUR_SEL

ISNS_HS_GAIN_N

TBDTHMSNS_D2_N

CPUTHMSNS_D2_N

CPUTHMSNS_TH_SEL

PP3V3_S0

PP3V3_S0

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

TBTMLBSNS_ALERT_L

TBT_INLET_THM_L

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

PP3V3_S0_TBTMLB_ISNS_R



TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_NMAKE_BASE=TRUE

MAKE_BASE=TRUETBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

ISNS_HS_GAIN_P

TBTTHMSNS_D2_R_P

TBTTHMSNS_D2_R_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBDTHMSNS_D2_N

TBDTHMSNS_D2_P

INLET_THMSNS_D1_N

CPUTHMSNS_D2_P

TBDTHMSNS_D2_P

<BRANCH>

<SCH_NUM>

<E4LABEL>

58 OF 121

44 OF 76

74

74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

44 74

44 74

44 74

44 74

44 74

44 74

44 74

44 74

74

74

44 74

44 74

44 74

44 74

74

74

www.vinafix.vn

D

SYM_VER_3

SG

NC

NC

OUT

IN

NC

08

NC

Apple Inc.


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6 3



MOTOR CONTROL

FAN CONNECTOR

TACH5V DC

GND

518S0793

21

R606547K

MF1/20W

201

5%

2

1R606047K

MF1/20W

201

5%

2

1R6061100K

MF1/20W

201

5%

4

3

2

1

6

5

J6000F-RT-SM

FF14A-4C-R11DL-B-3H

CRITICAL

21

3

Q6060DMN32D2LFB4DFN1006H4-3

37

37

4

6

53

1

2

U6010

74LVC1G08SOT891

CRITICALNOSTUFF

2

1 C6010BYPASS=U6010:3mm

NOSTUFF

6.3VCERM-X5R0201

0.1UF10%

21

R6010

MF1/20W

0201

0

5%

FanSYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB

PP3V3_S0

PP5V_S0

FAN_RT_PWM

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

MIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.1 MMVOLTAGE=3.3V

PP3V3_S0_FAN

<BRANCH>

<SCH_NUM>

<E4LABEL>

60 OF 121

45 OF 76

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 56 59 61 62

64 65 74

16 17 32 46 51 52 56 58 59 61 62 64

64

64

www.vinafix.vn

BIBI

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

IN

BI

BI

IN

BI

IN

BI

OUT

IN

BI

IN

IN

OUT

BI

IN

OUT

IN RST*/HOLD*

CE*

WP*

SCK

VSS THRM_PAD

SI/SIO0

SO/SOI1

VDD

IN

IN

IN

OUT

OUTIN

OUTIN

BIBI

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6 3



High Speed CLK Frequency - 50MHz for fast read dual I/O

DUAL I/O MODE (MODE 0 & 3) SUPPORTED

ROM will ignore SPI cycles.

NOTE: If HOLD* is asserted

516S1039

LPC+SPI Connector

SMC12 Master

CPU Master

Matt Card ROM Slave

MLB ROM Slave

SPI Bus Series Termination

2

1R6126


1/20W5%

201MF

LPCPLUS

43

46 69 21

R6122

MF

43

201

PLACE_NEAR=R6127.2:5mm5%

1/20W

21

R6112

PLACE_NEAR=U0500.AA2:5mm1/20W5%

201MF

1514 69

2

1R6127


201

LPCPLUS

MF1/20W5%43

2

1R6128


24.91%1/20WMF201

LPCPLUS

37 38 64

37 38 64

37 38 64

37 38 64

38 64

37 38 50 64

37 38 64

15 16 64

18 64 69

14 37 64 69

14 37 64 69

46 64

14 37 64 69

17 64 69

14 37 64 69

37 38 64

13 37 64

15 37 64

46 64

46 64

13 37 64

15 46 64

14 37 64 69

46 64

9

87

65

4

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J6100

LPCPLUSCRITICAL

M-ST-SMDF40C-30DP-0.4V

15 46 64

2

1R6101

1/20W5%

201MF

3.3K

2

1C6100BYPASS=U6100:3mm

16V10%

0.1UF

0201X5R-CERM

3

48

9

2

56

7

1

U6100

WSON

SST25VF064C

64MBIT

CRITICAL

OMIT_TABLE

37 69

37 69

37 69

37 69

21

R6117

201MF

5%

15

1/20WPLACE_NEAR=U6100.1:1mm

21

R6115


201

5%

MF

15

1/20W

21

R6116


201

15

MF

5%1/20W

21

R6114


MF

1%

24.9

201

1/20W

21

R6113

201


MF

15

2

1R6102

1/20W5%

MF201

100K

46 69 21

R6110

PLACE_NEAR=U0500.Y7:5mm1/20W

201MF

15

5%14 69

46 69 21

R6111


MF

15

201

14 69

46 69 21

R6123

1/20W

201MF

PLACE_NEAR=U6100.2:5mm1%

24.914 69

21

R6120

PLACE_NEAR=R6125.2:5mm1/20W

201MF

43

5%

2

1R6125


201MF

43

LPCPLUS

1/20W5%

21

R6121

PLACE_NEAR=R6126.2:5mm1/20W5%

MF

43

201


LPC+SPI Debug Connector

SPI_MLB_MISO

SPI_MLB_MOSI

SPI_MISO

SPI_MOSI_R

SPI_MISO_R

SPI_MOSI

SPI_CLK SPI_MLB_CLK

SPI_ALT_MISO

SPI_CS0_L

SPI_ALT_CLK

SPI_MLB_CS_L

SMC_ROMBOOTSMC_RX_LSMC_TMS

SMC_TX_L

SPI_MLB_MISO

SPI_MLB_MOSI

SPI_WP_LSPI_MLB_CS_L

SPI_SMC_CS_L

SPI_SMC_CLK

SPI_SMC_MISO

SPI_CLK_R

SPI_CS0_R_L

SPI_ALT_MOSI

SPI_ALT_CS_L

LPC_SERIRQSPI_ALT_CS_LSPI_ALT_CLKPM_CLKRUN_L

SPIROM_USE_MLB

SMC_RESET_LSMC_TCK

TP_SMC_MD1

LPC_AD<0>

PP5V_S0PP3V42_G3H

LPC_PWRDWN_LSMC_TDI

SMC_TDOLPCPLUS_RESET_LXDP_LPCPLUS_GPIOSPI_ALT_MOSILPC_AD<3>LPC_AD<1>LPC_AD<2>

LPC_CLK24M_LPCPLUSSPI_ALT_MISOLPC_FRAME_L

TP_SMC_TRST_L

SPI_SMC_MOSI

SPI_MLB_CLK

SPIROM_USE_MLB

PP3V3_SUS

<BRANCH>

<SCH_NUM>

<E4LABEL>

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69

69

69

46 64

69

46 64

46 69

46 69

46 69

46 64

46 64

64

16 17 32 45 51 52 56 58 59 61 62 64

17 30 35 36 37 38 40 49 50 59 61 62 64 65

64

46 69

8 11 14 18 57 58 59 62 64

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IN

IN

IN

IN-

IN+ OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

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6 3



518S0519

SPEAKER AMPLIFIERS

80 HZ < FC < 132 HZ

APN:353S2888

GAIN 6DB

ALIAS OF PP5VRT_S0, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.20MM

Right Speaker Connector

SPEAKER LOWPASS

21

C6410

0201

10%16V

CRITICAL

0.1UF

X5R-CERM

61 65 74

61 65

61 65 74

C2

A1

A2

B1

C1

B2

A3

B3

C3

U6410

WLPMAX98300

CRITICAL

2

1R6412

MF

5%1/20W

100K

201

21

C6411CRITICAL

16V10%

0.1UF

X5R-CERM0201

2

1R6411

MF

5%

201

1/20W

100K

2

1R6413

1/20W

201MF

NOSTUFF

100K5%

21

R6414

5%

MF-LF

0

1/10W

603

2

1 C64070.1UF10%

0201

16VX5R-CERM

2

1 C6401

0805-LLP

6.3V

47UF20%

POLY-TANT

CRITICAL

2

1

4

3

J640478171-0002

M-RT-SM

CRITICAL


Audio: Speaker Amp

PP5V_S3_U6210VOLTAGE=5VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

PP5V_S4RS3

SPKRAMP_INR_P

SPKRAMP_INR_N

SPKRAMP_SHDN_L

R_AMP_GAIN

MAX98300_R_N

MAX98300_R_P SPKRAMP_ROUT_PMIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 mm


SPKRAMP_ROUT_N

<BRANCH>

<SCH_NUM>

<E4LABEL>

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74

74 64 74

64 74

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IN

BI

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6 3



13" SPECIFIC

Battery Connector

518S0540

37 40 50 64 73

37 40 50 64 73

21

3

D6950RCLAMP2402B

NO STUFF

SC-75

CRITICAL

2

1R695010K

5%1/20W

MF201

2

1 C695010%

402

25VX5R

0.1UF

2

1C6951

X5R

1UF16V

402

10%

9

8

7

6

5

4

3

2

1

J6950WTB-PWR-M82

CRITICAL

M-RT-SM

Battery Connector

SYNC_DATE=MASTERSYNC_MASTER=MASTER

SYS_DETECT_LSMBUS_SMC_5_G3_SDASMBUS_SMC_5_G3_SCL

PPVBAT_G3H_CONN

<BRANCH>

<SCH_NUM>

<E4LABEL>

69 OF 121

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64

50 64

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NC

G

D

S

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

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6 3



MLB to LIO Power Cable Connector

3.425V "G3Hot" SupplySupply needs to guarantee 3.31V delivered to SMC VRef generator

6.8V Zener

300mA Max Output

for detection of B121 (16.5V)

Input impedance of 68K meetssparkitecture requirements

(Switcher limit)

518S0508

Vout = 1.25V * (1 + Ra / Rb)

<Rb>

<Ra>

Vout = 3.425V

6

5

4

3

2

1

J7000CRITICAL

M-RT-SMWTB-PWR-M82

21

L7095

2520

10UH-20%-0.85A-0.46OHM

CRITICAL2

1C709410%

CERM

0.22UF10V

402

3

2

1

D7005CRITICAL

BAT30CWFILMSOT-32321

R70064.7

805MF-LF1/8W5%

21

R7005

1/8W

805

10

MF-LF

5%

2

1R70951%

348K

MF1/20W

201

2

1R7096200K

1%

MF1/20W

201

2

1R7010100K

MF1/20W

201

5%

5A

5

4

1

Q7010SI5419DUPOWERPAK

CRITICAL

K

A

D7012GDZT2R6.8

CRITICAL

GDZ-0201

2

1C7005NO STUFF

0.1UF

603-1X7R50V10%2

1 C70060.1UF

0201X5R-CERM16V10%

2

1C7091

X5R

1UF

CRITICAL

10%25V

4022

1C7090CRITICAL

X5R

1UF10%25V

4022

1C7092CRITICAL

20%5.6UF

POLY-TANTCASE-B2-SM

25V

2

1C709910V

0402-1X5R-CERM

20%10UF

CRITICAL

2

1C7098

10V

0402-1X5R-CERM

20%10UF

CRITICAL

2

1 C7008NO STUFFCRITICAL

1UF

603X5R35V10%

2

1C7007CRITICAL

NO STUFF

1UF

603X5R35V10%

2

1 C7095

50V

22PF

NP0-C0G-CERM0201

5%

2

1C7012

X5R

0.047UF

CRITICAL

0402

10%25V

21

R7011

1%

10K

MF1/20W201

6

9

48

7

5

1

3

2

U7090

CRITICAL

DFNLT3470AED

2

1R701268K1%

MF1/20W

201

2

1R7080

MF1/20W0201

05%

2

1R70811%

NO STUFF

49.9KMF1/20W201

2

1C7080NO STUFF

1000PF

0402CERM25V5%

DC-In & G3H Supply



PPVIN_G3H_P3V42G3H

VOLTAGE=18.5VP3V42G3H_BOOSTDIDT=TRUEMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm


P3V42G3H_SW


PP5V_S4RS3

PPDCIN_G3H_ISOL

PPBUS_G3H


PPBUS_G3H_RMIN_LINE_WIDTH=0.4 mm

DCIN_ISOL_GATE_R

DCIN_ISOL_GATE

VOLTAGE=18.5V

PP18V5_DCIN_ISOL_RMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM


P3V42G3H_FB

P3V42G3H_SHDN_LPP3V42_G3H

PPDCIN_G3H

<BRANCH>

<SCH_NUM>

<E4LABEL>

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62 64

42 50 62 64

27 41 42 50 56 62 64

17 30 35 36 37 38 40 46 50 59 61 62 64 65

50 62 64

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OUT

OUT

IN

BI

OUT

IN

S

G

D

IN

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N

GG

SDS D

NCNCNCNC

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f = 400 kHz

(CHGR_CSO_P)

(GND)

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

Max Current = 8A

ACIN pin threshold is 3.2V, +/- 50mV

DIVIDER SETS ACIN THRESHOLD AT 13.55V

Float CELL for 1S

Reverse-Current Protection

(CHGR_AGATE)

Inrush Limiter

FROM ADAPTER

(AGND) (OD)

36V/V

20V/V

Vout = 1.25V * (1 + Ra / Rb)

30mA max load

(Switcher limit)

.

(PPVBAT_G3H_CHGR_R)

<Ra>

<Rb>

Vout = 5.50V200MA MAX OUTPUT

For Erp Lot6 spec

5.5v "G3Hot" Supply

(CHGR_DCIN)

TO/FROM BATTERY

Need to stuff R7192 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!

TO SYSTEM

(CHGR_BGATE)

(CHGR_SGATE)

* R7151 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

2

1R711146.4K1%

MF1/20W

201

2

1 C7142

6.3VCERM-X5R0201

0.1UF10%

2

1 C7116470PF

16V

0201X5R-X7R-CERM

10%

2

1C7115470PF

X5R-X7R-CERM16V

0201

10%

2

1 C71021UF

10VX5R

10%

402

2

1 C71001UF

402-1

10VX5R

10%

21

R7101

MF-LF

4.7

1/16W

402

5%

2

1R7110130K1%

MF1/20W

201

21

XW7100


SM

2

1C71011UF

10VX5R

10%

402

2

1 C7121

X5R

0.1UF10%25V

402

2

1C7122

X5R

0.1UF10%25V

402

2

1 C71200.047UF

16VX7R-CERM0402

10%

2

1 C7125PLACE_NEAR=U7100.25:2mm

CERM10V

0.22UF10%

402

21

R712210

MF1/20W

201

5%

21

R712110

MF1/20W

201

5%

2

1C7130

CASE-D3LPOLY-TANT

33UF-0.06OHM

CRITICAL

25V20%

2

1C713133UF-0.06OHM

POLY-TANT

CRITICAL

CASE-D3L

25V20%

21

F71408AMP-24V

1206

CRITICAL

2

1R7186332K

1%

MF1/20W

201

2

1R718162K

MF1/20W

201

5%

2

1C71050.22UF

X5R-CERM50V10%

0603-1

41

41

37 40 48 64 73

37 40 48 64 73

2

1C7111

10VX5R-CERM

0201

0.01UF10%

2

1 C71500.47UF

10V

0402X5R

10%

2

1C7126

X7R-CERM0201

16V10%

1000PF

37 38 61 65

2

1 C7137BYPASS=Q7130:1.5mm

0.001UF

X7R-CERM0402

50V10%

2

1 C7145BYPASS=L7130:Q7130:1.5mm

X7R-CERM0201

16V10%1000PF

2

1R7102100K

NO STUFF

MF1/20W

201

5%

59

32

1

4

5

Q7155CRITICAL

SO-8SI7137DP

2

1R7113100

MF1/20W

201

5%

3

2

1

D7105BAT30CWFILM

CRITICAL

SOT-323

2

1C7185

X5R

0.1UF10%25V

402

2

1R7180100K

MF1/20W

201

5%

2

1R7185470K1%

MF1/20W

201

2

1 C71351UF

603-1X5R

10%25V

2

1 C71361UF

603-1X5R

10%25V

21

R7100

MF1/20W

0201

0

5%

37 38 46 64

2

1 C7114

603-1

1UF

X5R

10%25V

2

1 C7113

X5R

0.1UF10%25V

402

2

1 C71120.01UF

X7R

10%25V

402

2

1C7117

805

10UF

X5R

10%25V

21R7151 2.2MF1/20W201 5%

21R7152MF1/20W 0201

05%

2

1R71151%255K

MF1/20W

201

2

1R71161%

10K

MF1/20W

201

2

1C7140

11VTANT-POLYCASE-B2S-1

20%62UF-0.023OHM

2

1C7143


20%62UF-0.023OHM

2

1C7141

11V20%

TANT-POLYCASE-B2S-1

62UF-0.023OHM

543

7

6

1

2

Q7130

WPAK

CRITICAL

RJK03P0DPA

21

L7130

PIMC104T4R7MN-SM

CRITICAL

4.7UH-17A

21

R7105PP5V5_DCIN:NO

1/10WMF-LF603

20

5%

2

1 C7199

603

10UF

CRITICAL

10V

NO STUFF

X5R

20%

2

1 C7198

NO STUFF

603X5R10V

10UF

CRITICAL

20%

2

1

R7195

1%

681K

NO STUFF

MF

1/20W

201

2

1

R7196

1%

200K

NO STUFF

MF

1/20W

201

2

1C7194

NO STUFF

0.22UF

CERM

10V

10%

402

2

1 C719522PF

0201

50V

NP0-C0G-CERM

NO STUFF

5%

6

9

48

7

5

1

3

2

U7190NO STUFF

DFN

LT3470A

CRITICAL

21

R7190

PP5V5_DCIN:YES

MF-LF1/16W

402

0

5%

21

R7191PP5V5_VDDP

1/16W402MF-LF

0

5%

21

R7192

1/16W

MF-LF

NO STUFF

402

0

5%

2

1C7190

X5R-CERM

4.7UF

0603

NO STUFF

10%25V

21

L7195NO STUFF

CRITICAL

10UH-20%-0.85A-0.46OHM

2520

2

1C7184

X5R-CERM

4.7UF

0603

10%25V

8

12

4

20

19

7

24

29

1326

10

11

23

22

21

5

2

18

17

28

276

25

15

16

9

1

14

3

U7100TQFN

CRITICAL

ISL6259

2 51 4

3 6

10

97 8

Q7180CRITICAL

DIRECTFET-MCIRF9395TRPBF

4

3

2

1

R7120

0612

CRITICAL

MF-LF1W0.5%0.020

2

1R71421K

MF1/20W

201

5%

43

21

R7150

0612-4

0.5%

0.01

1W

MF

SYNC_MASTER=J41_MLB

PBus Supply & Battery ChargerSYNC_DATE=02/09/2013

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

GND_CHGR_AGNDMIN_LINE_WIDTH=0.2 mm

CHGR_CELL

CHGR_ICOMP_R


CHGR_ICOMPMIN_LINE_WIDTH=0.2 mm


VOLTAGE=8.6VSWITCH_NODE=TRUE

DIDT=TRUE

CHGR_PHASE

CHGR_BGATE


PP3V42_G3H

CHGR_ACIN

CHGR_DCIN


CHGR_CSI_P


CHGR_AGATE



PPDCIN_G3H

SMBUS_SMC_5_G3_SCL

CHGR_CSI_N

SMBUS_SMC_5_G3_SDA

CHGR_VFRQ

CHGR_VCOMP_R


VOLTAGE=5.1V

PP5V1_CHGR_VDDP

DIDT=TRUE

GATE_NODE=TRUE


MIN_NECK_WIDTH=0.2 mmCHGR_LGATE



CHGR_CSI_R_P

CHGR_CSO_R_N

CHGR_CSO_R_P


PPCHGR_DCIN_D_RMIN_NECK_WIDTH=0.2 mm

CHGR_DCIN

PPBUS_G3H

PP5V1_CHGR_VDDP

SMC_BC_ACOK

CHGR_BMON

CHGR_AMON


CHGR_DCIN_D

VOLTAGE=8.6V


PPVBAT_G3H_CONNMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P5V1_BOOST


SWITCH_NODE=TRUE


P5V1_SW

DIDT=TRUE

GATE_NODE=TRUEDIDT=TRUE

CHGR_UGATEMIN_LINE_WIDTH=0.5 mm



CHGR_VNEG MIN_LINE_WIDTH=0.2 mm


CHGR_SGATE_DIV

CHGR_CSI_R_N

PPDCIN_G3H_INRUSHMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=18.5V

CHGR_AGATE_DIV

CHGR_RST_L


CHGR_VCOMPMIN_LINE_WIDTH=0.2 mm

SMC_RESET_L

PPDCIN_G3H_ISOL


VOLTAGE=18.5V

PPCHGR_DCIN_D_RMIN_LINE_WIDTH=0.5 mm

CHGR_VNEG_R



CHGR_CSO_N

PP5V1_CHGR_VDD



VOLTAGE=5.1VMIN_NECK_WIDTH=0.15 mmVOLTAGE=18.5V

PPDCIN_G3H_CHGRMIN_LINE_WIDTH=0.6 mm

P5V1_FB


VOLTAGE=5.5V

PP5V5_CHGR_VDDP

CHGR_SGATE



CHGR_BOOTDIDT=TRUEMIN_LINE_WIDTH=0.5 mm




CHGR_CSO_P

PPVBAT_G3H_CHGR_REG



PPVBAT_G3H_CHGR_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 MM

VOLTAGE=8.6V

<BRANCH>

<SCH_NUM>

<E4LABEL>

71 OF 121

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73

49 62 64

73

50

73

43 73

43 73

50 50

27 41 42 49 56 62 64

50

48 64

73

42 49 62 64

50

73

73

www.vinafix.vn

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC

NC

NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

OUT

NCNC

OUT

OUT

IN

IN

IN

OUT

IN

IN

IN

NC

NCNC

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6 3



FCCM = 1: Forced CCM

(GND)

FCCM = FLOATING: PS4FCCM = 0: DCM

(CPUVR_ISUMP)

8 67

8 67

8 67

8 17

6 37 38 67

2

1R72791%

54.9


MF1/20W

201 2

1R7280


1%130

MF1/20W

201

1

4

17

16

33

29

30

32

13

23

22

2026

27

28

2

5

24

21

19

9

15

14

10

11

12

3

18

8

7

25

6

31

U7200

LLP

CRITICAL

ISL95826HRZ-_R6200

8 17

52

52

52

21

R7224

MF1/20W

0201

0

5%

21

R7202

402

1/16WMF-LF

10

5%

2

1C7202

25V10%

0402

PLACE_NEAR=U7200.17:2mm0.22UF

X7R

21

R7201

402

1/16WMF-LF

1

5%

2

1 C720110%

X5R402-1

1UF10V


52

52

2

1 C721010%0.01UF10V

0201X7R-CERM 2

1 C721110%10V

0201

0.01UF

X7R-CERM

52

2

1C721310%

0.1UF

0201CERM-X5R

6.3V

2

1R72206.04K1%

MF1/20W

2012

1R722121K1%

MF1/20W

201

43

2

1R723095.3K1%

MF1/20W

2012

1C723010%10V

1800PF

X5R-CERM201

52

2

1C7214

25V10%

X7R-CERM


220PF

201

21

R7215

1%

845

MF1/20W201

21

C7215

25V10%

X7R-CERM

820PF

020121

C7216

25V0201

47PF

NP0-C0G-CERM5%

8 67

9 67

2

1 C726010%

0201X7R-CERM

330PF16V

2

1 C726110%

X7R-CERM

330PF16V

0201

2

1C7240

0201-1

+/-10%1.2NF

CERM10V

2 1

C7242

25V


NP0-CERM0201

100PF

5%

2

1C7241

25VNP0-C0G-CERM

0201

56PF


5%

2

1R724075K


1%

MF1/20W

201

2 1

R7242

1%

1K

MF1/20W

201

21

R7243NO_XNET_CONNECTION=TRUE

MF1/20W

0201

0

5%

21

R72359.31K

1%

MF1/20W

201

2

1R723695.3K

1%

MF1/20W

2012

1

R7237

0201

100KOHM

21

R7250

NOSTUFFNO_XNET_CONNECTION=TRUE

2K

1%

MF1/20W

201

2

1 C725010%330PF16VX7R-CERM0201

NOSTUFF

21

R72411.37K

1%

MF1/20W

201

21

R7210

1%

255

MF1/20W

201

2

1R72231%16.9K

MF1/20W

201 2

1R72229.31K1%

MF1/20W

201

21

XW7261


SM

2

1R7225NOSTUFF

MF1/20W

0201

05%

2

1C727810%

0.1UF

0201CERM-X5R

6.3VPLACE_NEAR=R7279.32:2mm


CPU VR12.6 VCC Regulator IC

CPUVR_ISUMN_R

CPUVR_PROG3

CPUVR_FB2

PP5V_S0_CPUVR_VDDMIN_LINE_WIDTH=0.3 mm

VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm

CPUVR_PWM1

CPUVR_IMON

CPU_VCCSENSE_P_RC

CPU_VCCSENSE_N

CPU_VCCSENSE_P

VOLTAGE=12.9VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPPVIN_S0_CPUVR_VIN

CPUVR_PWM2

PPBUS_S5_HS_COMPUTING_ISNSPP5V_S0

CPUVR_COMP_RC

CPUVR_ISUMN_RC

CPU_VCCSENSE_P_R

CPUVR_NTC_R

PP1V05_S0CPUVR_NTC

CPUVR_FCCM

CPUVR_FB_RC

CPU_PROCHOT_L

CPU_VIDSCLK

CPUVR_ISUMPCPUVR_COMP

CPUVR_ISEN2CPUVR_ISEN1

CPU_VIDSOUT

CPUVR_FB

CPUVR_ISUMN

CPUVR_DRSEL

CPUVR_SLOPE

CPU_VR_EN

CPU_VR_READY

CPUVR_PROG1

CPU_VIDALERT_L

CPU_RTN

CPUVR_PROG2

51 OF 76

72 OF 121

<E4LABEL>

<SCH_NUM>

<BRANCH>

41 52 53 55 62 64 16 17 32 45 46 52 56 58 59 61 62 64

6 8 11 15 16 17 27 38 42 55 58 59 62 64

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IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

G

D

S

G

D

S

G

D

S

G

D

S

OUTOUT

OUTOUT

THRMPAD

PHASE

VCC

LGATE

BOOT

UGATEFCCM

GND

PWM

THRMPAD

PHASE

VCC

LGATE

BOOT

UGATEFCCM

GND

PWM

Apple Inc.


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R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PHASE 1

PHASE 2

353S3942

353S3942

152S1757

152S1757

.

THESE TWO CAPS ARE FOR EMC

THESE TWO CAPS ARE FOR EMC

Additonal Input Bulk Caps

Vout = 1.85V max32A max outputf = 700kHz

2

1 C737262UF-0.023OHM

20%

CASE-B2S-1TANT-POLY11V

CRITICAL

2

1 C737162UF-0.023OHM

20%


CRITICAL

2

1 C737062UF-0.023OHM

20%


CRITICAL

2

1 C7319

X7R-CERM0402

0.001UF10%50V

2

1 C7318

50VX7R-CERM0402

0.001UF10%

2

1 C7317

16V

0402

1UF10%

X6S-CERM2

1 C7316

20%16V

NOSTUFF

10UF

CRITICAL

0603X6S-CERM2

1 C7315

20%16V

CRITICAL

10UF

0603X6S-CERM

NOSTUFF

2

1R7314

0201MF-LF1/20W1%1.00

2

1 C731462UF-0.023OHM

20%


CRITICAL

2

1 C731362UF-0.023OHM

20%


CRITICAL

21

L73100.40UH-20%-16A

MPCG0730-SM

CRITICAL

2

1R7312

2.2

603

5%1/10WMF-LF

NOSTUFF

2

1 C73120.001UF10%

X7R-CERM0402

50V

NOSTUFF

51

51 52

2

1 C737362UF-0.023OHM

20%


CRITICAL

2

1R7316

201

200K1%

MF


1/20W

2

1R7315

201MF

1%1K

1/20W

51

51 52

51 52

21

R7317

NONE0201

NO_XNET_CONNECTION=TRUENONENONE

OMIT

NOSTUFF

2

1 C73290.001UF

0402

50V10%

X7R-CERM

51 52

2

1 C7328

0402X7R-CERM50V10%0.001UF

2

1 C7327

X6S-CERM16V

0402

10%1UF

2

1R7324

0201

1/20WMF-LF

1.001%

2

1 C7326

20%16VX6S-CERM0603

10UF

CRITICALNOSTUFF

2

1 C7325

20%16V

10UF

X6S-CERM0603

NOSTUFFCRITICAL

2

1 C732462UF-0.023OHM

20%


CRITICAL

2

1 C732362UF-0.023OHM

20%


CRITICAL

21

L7320

MPCG0730-SM

CRITICAL

0.40UH-20%-16A

2

1 C7322

50V

0.001UF

NOSTUFF

0402X7R-CERM

10%

2

1R7326NO_XNET_CONNECTION=TRUE

1%

201

200K

MF1/20W

2

1R73251%

MF1/20W

1K

201

2

1R7322

NOSTUFF

603

2.25%

1/10WMF-LF

51

21

R7327

NO_XNET_CONNECTION=TRUENONE

OMIT

NOSTUFF

NONENONE

0201

51

51 52

1 2

R7311

402

5%1/16WMF-LF

2.2

21

C7311

402CERM

10%16V

0.22UF

2

1C7310

16V

1UF

X6S-CERM

10%

0402

2

1C7320

0402X6S-CERM

10%1UF

16V

51 52

2

1 C737662UF-0.023OHM

20%


CRITICAL

2

1 C737562UF-0.023OHM

20%


CRITICAL

2

1 C737762UF-0.023OHM

20%


CRITICAL

2

1 C737462UF-0.023OHM

20%


CRITICAL

2 1

R7321

402

2.2

5%1/16WMF-LF

21

C73210.22UF

CERM

10%16V

402

321

4

5

Q7310SISA18DNPWRPAK-SM

CRITICALOMIT_TABLE

321

4

5

Q7320CRITICALOMIT_TABLE

SISA18DNPWRPAK-SM

4 3

2 1

R7310CRITICAL

1%0.00075

1WMF0612

43

21

R7320CRITICAL

0.00075

1W1%

MF0612

321

4

5


CRITICALOMIT_TABLE

321

4

5


CRITICALOMIT_TABLE

42 52 74 42 74

42 52 74 42 74

6

1

9

3

8

5

4

7

2

U7310

CRITICAL

DFNISL6208D

6

1

9

3

8

5

4

7

2

U7320

CRITICAL

DFNISL6208D


CPU VR12.5 VCC Power StageSYNC_MASTER=J41_MLB

PP5V_S0

DIDT=TRUE

CPUVR_PH1_SNUB

CPUVR_BOOT2_RCMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MMDIDT=TRUE

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMCPUVR_LGATE2


DIDT=TRUESWITCH_NODE=TRUE


CPUVR_PHASE2


DIDT=TRUE


CPUVR_BOOT1_RC


MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

CPUVR_LGATE1


CPUVR_BOOT1

DIDT=TRUE

CPUVR_ISEN2



CPUVR_BOOT2

DIDT=TRUE

SWITCH_NODE=TRUE


DIDT=TRUEMIN_NECK_WIDTH=0.2 MM

CPUVR_PHASE1

CPUVR_ISUMP

PPVCC_S0_CPU

CPUVR_ISNS2_N

CPUVR_ISUMN

CPUVR_ISNS2_P

CPUVR_ISUMN

CPUVR_ISNS1_N

CPUVR_ISNS2_N

CPUVR_ISUMP


PPVCC_S0_CPU_PH2


PPVCC_S0_CPU_PH1


CPUVR_ISNS1_N

DIDT=TRUE

CPUVR_PH2_SNUB

CPUVR_PWM1

CPUVR_FCCM


CPUVR_UGATE1

DIDT=TRUE

CPUVR_FCCM


DIDT=TRUE

CPUVR_UGATE2


CPUVR_PWM2

PP5V_S0

CPUVR_ISNS1_P

CPUVR_ISEN1

<BRANCH>

<SCH_NUM>

<E4LABEL>

73 OF 121

52 OF 76

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61 62 64

41 51 53 55 62 64

8 10 42 62 64

42 52 74

42 52 74

16 17 32 45 46 51 52 56 58 59 61 62 64

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BG

TGR

TG

PGND

VIN

VSWIN

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

IN

OUT

OUT

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BRANCH

6 3



(DDRREG_VDDQSNS)

(DDRREG_DRVL)

(DDRREG_LL)

(DDRREG_DRVH)

(VTT Enable)(VDDQ/VTTREF Enable)

10mA max load

f = 400 kHz

(Q7435 limit)

14.1A max output

Vout = 1.35V

2

1 C746220%

603X5R6.3V

10UF

CRITICAL

BYPASS=U7400.3:3mm

8

7

6

1

4

3

9

5

Q7430CRITICAL

Q3DCSD58873Q3D

2

1R74352.25%

NOSTUFF

1/10WMF-LF603

2

1C7435NOSTUFF

X7R-CERM0402

50V

0.001UF10%

21

R7460

201

5%

10

1/20WMF

2

1C740020%

603

BYPASS=U7400.12:1mm

10UF

X5R10V

2

1 C743210%

X5R603-1

1UF25V

21

C74250.1UF

402X5R

10%25V

2

1 C74330.001UF10%

X7R-CERM0402

50V

2

1 C744520%

6.3V

10UF

603X5R

2

1C7446

X7R-CERM0402

50V10%

0.001UF

2

1

XW7401

PLACE_NEAR=C7440.1:1mm

SM

59

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14U7400TPS51916

CRITICAL

QFN

59

21XW7460


SM

2

1

XW7400


SM 2

1C74500.22UF

10%

CERM402

10V

17

2

1C74150.1UF

0402X7R-CERM

10%16V

BYPASS=U7400.6:1mm

2

1R7417PLACE_NEAR=U7400.19:3mm

1%1/20W

201

200K

MF

2

1R7415

201MF

1%1/20W


28.7K

2

1R7416

1/20W

57.6K

MF201

1%


2

1 C7416

16V10%

0402X7R-CERM

0.01UF

BYPASS=U7400.8:1mm

2

1C740120%

BYPASS=U7400.2:1mm

603

10UF

X5R10V

21

R74254021/16W

MF-LF05%

21

L74301.0UH-20%-11A-0.011OHM

FDSD0630-SM

CRITICAL

43

21

R7450

1206

0.0021/4WMF-LF1%

CRITICAL

41 74

41 74

2

1R7418

1/20W1%

MF


49.9K

201

2

1C744020%

CRITICAL

2.0V

CASE-B2-SM1

330UF

POLY-TANT

2

1C744120%

CRITICAL

2.0V

CASE-B2-SM1POLY-TANT

330UF

2

1C743020%62UF-0.023OHM

CASE-B2S-1TANT-POLY11V 2

1C743120%62UF-0.023OHM

CASE-B2S-1TANT-POLY11V 2

1C7434


62UF-0.023OHM20%


LPDDR3 SupplySYNC_MASTER=J41_MLB


GND_DDRREG_SGND

VOLTAGE=0V


MEMVTT_PWR_ENDDRREG_EN

DDRREG_1V8_VREFMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

PP1V2_S3

MIN_LINE_WIDTH=0.2 mmDDRREG_VDDQSNS_RMIN_NECK_WIDTH=0.17 mm


PPDDR_S3_REG_RVOLTAGE=1.2V


DDRREG_VTTSNSMIN_LINE_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mmDDRREG_FB


DDRREG_TRIPDDRREG_MODE

ISNS_1V2_S3_P

PP5V_S5

DIDT=TRUESWITCH_NODE=TRUEDDRREG_LL



DDRREG_VBST_RCMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.1 MMDIDT=TRUE

PDDR_S3_REG_LMIN_LINE_WIDTH=0.6 MM

DIDT=TRUEPDDR_S3_REG_SNUB


DDRREG_DRVHGATE_NODE=TRUE DIDT=TRUE


DIDT=TRUEDDRREG_VBST

PP1V2_S3

PP0V6_S0_DDRVTTDDRREG_VDDQSNS


DDRREG_PGOODDDRREG_DRVL DIDT=TRUE GATE_NODE=TRUE


MIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mmPPVTT_S3_DDR_BUF

VOLTAGE=0.6V

ISNS_1V2_S3_N

<BRANCH>

<SCH_NUM>

<E4LABEL>

74 OF 121

53 OF 76

41 51 52 55 62 64

17 19 20 21 22 23 42 53

62 70

19

36 54 62

17 19 20 21 22 23 42 53 62 70

24 62

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OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1

SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2

CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

BG

TGR

TG

PGND

VIN

VSW

BG

TGR

TG

PGND

VIN

VSW

Apple Inc.


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REVISION

BRANCH

6 3



OOA Auto Skip (Lower Efficiency)

6.5A MAX OUTPUT

Auto Skip (Higher Efficiency)

7.2A MAX OUTPUT

F=400KHZ

VREF2VREG3

SKIPSEL Strap

152S1798152S1798

F=400KHZ

Vout = 3.3VVout = 5.0V

353S3905

2

1C7500

10%16V

X5R402

1UF

21

L7560

PIME063T2R2MS-SM

2.2UH-20%-13A-0.012OHM

CRITICAL

2

1 C75411UF10%

402

16VX5R

2

1C7564

25V

10%

402

0.1UF

X5R2

1 C7524

402

10%

0.1UF

X5R

25V

2

1C7552

6.3VPOLY-TANTCASE-B2-SM

20%

150UF-0.035OHM

CRITICAL

2

1 C7581

402X5R16V10%1UF

2

1

R7506

201

1/20W

MF

249K1%

59

2

1

XW7561SM


2

1C7501

10%

10V

CERM

402

0.22UF

2

1R7560

201

1/20WMF

1%

23.2K

2

1R7561

201

1/20WMF

10K1%

2

1R7520

201

1/20WMF

41.2K1%

2

1R7521

201

1/20WMF

1%

10K

21

XW7500


SM

2

1R7516

201

1/20WMF

1%6.65K

21

R7546

201

1/20WMF

1%

1.54K

2

1

XW7560SM

PLACE_NEAR=L7560.1:3mm21

C75180.1UF

X7R-CERM

10%16V

0402

21

R7547

201

1/20WMF

1%

1.33K

2

1R7556

201

1/20WMF

1%4.22K

2

1

XW7520

PLACE_NEAR=L7520.1:3mmSM

2

1

XW7521


SM

2

1

R7536

201

1/20W

MF

1%

7.5K

2

1

R7537

201

1/20W

MF

NO STUFF

1%

20K

2

1

XW7562PLACE_NEAR=L7560.2:3mm

SM

2

1

XW7522


SM

2

1

C7592

6.3VTANT

CRITICAL

CASE-B2-SM

20%

150UF-0.018OHM-1.8A

2

1

R7539

201

1/20W

MF

20K1%

2

1C7539

5%

0201

22PF

NP0-C0G25V

2

1

R7538

201

1/20W

MF

7.5K1%

2

1C7538

201

4700PF10%

X7R10V

59 59

21R7548

5%

0

02011/20W

MF

NO STUFF

2

1

R7549

5%

0

0201

1/20W

MF

2

1 C7572

PLACE_NEAR=L7560.2:1.5mm

16V10%1000PF

X7R-CERM0201

2

1 C7583

16V10%

X7R-CERM0201

BYPASS=Q7560.1:1.5mm

1000PF

2

1 C7570

X7R-CERM

10%16V

0201

1000PF

BYPASS=Q7520.1:1.5mm

2

1 C7571

X7R-CERM

1000PF10%16V

0201

PLACE_NEAR=L7520.1:1.5mm

29

22

13

23

169

2631

2

33

2532

19

6

3

205

14

11

28

214

12

2730

241

187

178

1510

U7501CRITICAL

QFN

TPS51980A

2

1R7545

5%0

402

1/16WMF-LF

2

1R75515%0

0201

1/20WMF


2

1R75525%0

0201

1/20WMF


37 59

37 38 59

2

1C7536

201

4700PF10%

X7R10V

2

1C7537

16VX7R-CERM

270PF10%

0201-1

21

C7588

X7R-CERM16V10%

0402

0.1UF

1

2R7564

5%0

MF-LF402

1/16W

2

1C7554

20%

62UF

CASE-B2S

6.3VELEC

CRITICAL

2

1 C7590

20%

603X5R

10UF

10V

2

1C7550

20%

603

10UF

X5R10V

21

L7520

PIME063T2R2MS-SM

2.2UH-20%-13A-0.012OHM

CRITICAL

2

1 C7505

20%

X5R

603

10V

10UF

2

1C7542

11VTANT-POLY

20%

62UF-0.023OHM

CASE-B2S-1

2

1C7540

11V

20%

TANT-POLY

62UF-0.023OHM

CASE-B2S-1

2

1C7584

20%

62UF-0.023OHM

TANT-POLY11V

CASE-B2S-1

2

1C7582

11VTANT-POLY

20%

62UF-0.023OHM

CASE-B2S-1

2

1R7500

5%

0

0201

1/20WMF

2

1R7501

5%

0

0201

1/20WMF

NOSTUFF

2

1C7503

20%

402

10V

2.2UF

X5R-CERM

8

7

6

1

4

3

9

5

Q7560

Q3D

CRITICAL

CSD58873Q3D

8

7

6

1

4

3

9

5

Q7520

Q3D

CRITICAL

CSD58873Q3D

2

1 C7562NOSTUFF

0402

50VX7R-CERM

0.001UF10%

2

1R75625%

NOSTUFF

603MF-LF1/10W

2.2

2

1R75225%

603MF-LF

2.2

NOSTUFF

1/10W

2

1C75220.001UF

NOSTUFF

10%

X7R-CERM50V

0402

2

1R75235%

201

1/20WMF

10

2

1R75635%

201

1/20WMF

10

2

1

C7553

POLY-TANT6.3V20%

CASE-B2-SM

CRITICAL150UF-0.035OHM

2

1

C7593

6.3VTANT

CRITICAL

20%

CASE-B2-SM

150UF-0.018OHM-1.8A

Power


5V S4RS3 / 3.3V S5 Power Supply


PP3V3_S5_REG_R

P5VS4RS3_EN_R

MIN_LINE_WIDTH=0.6 mmGND_P5VP3V3_SGND


P3V3_S5_REG_LDIDT=TRUE

P3V3_S5_CSP2_R

MIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mm DIDT=TRUE

DIDT=TRUEP3V3_S5_REG_SNUB

P3V3S5_EN_R

S5_PWRGD


P3V3_S5_COMP2

SMC_PM_G2_EN

DIDT=TRUEGATE_NODE=TRUEP3V3_S5_DRVH



DIDT=TRUE

P5V_S4RS3_VBST_R

P5VP3V3_VREF2

P3V3_S5_VFB2


P5V_S4RS3_CSP1

P5V_S4RS3_CSN1


P5VS4RS3_PGOOD

MIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mmP5V_S4RS3_CSP1_R

DIDT=TRUE

P5VP3V3_VREF2


P5V_S4RS3_VFB1

P3V3_S5_RF

P5VP3V3_SKIPSEL

P5VP3V3_VREF2


P5VP3V3_VREG3

GATE_NODE=TRUEMIN_LINE_WIDTH=0.6 mm DIDT=TRUEMIN_NECK_WIDTH=0.2 mm

P5V_S4RS3_DRVH

P3V3_S5_CSP2

PP5V_S4RS3

PP5V_S4RS3

S5_PWR_EN

P5V_S4RS3_REG_LDIDT=TRUE

GATE_NODE=TRUEP3V3_S5_DRVL


DIDT=TRUE

MIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mmP3V3_S5_VFB2_R


P3V3_S5_VFB2_XWMIN_LINE_WIDTH=0.2 mm

P5V_S4RS3_VFB1_XW


P5V_S4RS3_VFB1_R


MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm DIDT=TRUE GATE_NODE=TRUE

P5V_S4RS3_DRVL

P5V_S4RS3_LL

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm DIDT=TRUE SWITCH_NODE=TRUE

P5V_S4RS3_FUNC

DIDT=TRUEP5V_S4RS3_REG_SNUB


P5V_S4RS3_VBSTDIDT=TRUE

DIDT=TRUE


P3V3_S5_VBST_R

P5V_S4RS3_COMP1MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

P5VP3V3_VREG3

P5V_S4RS3_COMP1_RP3V3_S5_COMP2_R

P5VS4RS3_EN

MIN_LINE_WIDTH=0.6 mmSWITCH_NODE=TRUEP3V3_S5_LL

MIN_NECK_WIDTH=0.2 mmDIDT=TRUE

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmDIDT=TRUE

P3V3_S5_VBST

PP5V_S5

P3V3_S5_CSN2


75 OF 121

<BRANCH>

<E4LABEL>

<SCH_NUM>

54 OF 76

41 62 64

42

54 54

54

54

32 35 47 49 54 55 58 62 64

32 35 47 49 54 55 58 62 64

54

36 53 62

www.vinafix.vn

GND

GND

GND

HSG

V+

V+

LSG

SW

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

OUTOUT

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REVISION

BRANCH

6 3



Scrub S3 & S5 pins connections!

1.05V S0 Regulator

f = 300 kHz

21A Max Output

Vout = 1.05V

2

1 C7630

0402

10%16VX7R-CERM

0.1UF

2

1C7623PLACE_NEAR=L7630.2:1.5mm

5%1000PF

0402CERM25V

2

1C7622

0402

5%1000PF

CERM25V


2

1R7630

5%

603

2.2

MF-LF

1/10W

21

R7631

5%1/16WMF-LF402

0

2

1C7648

CASE-B2-SM1POLY-TANT

CRITICAL

330UF

2.0V

20%

2

1C7649

POLY-TANTCASE-B2-SM1

CRITICAL

330UF

2.0V20%

21

L7630

CRITICAL

1.0UH-20%-11A-0.011OHM

FDSD0630-SM

2

1 C7619

20%

62UF-0.023OHM

CASE-B2S-1

TANT-POLY11V2

1C7620

20%

CASE-B2S-1

TANT-POLY11V

62UF-0.023OHM

2

1C762162UF-0.023OHM

11VTANT-POLY

CASE-B2S-1

20%

9

8

4

3

2

7

1

10 6 5

Q7630FDPC1012S

LLP

CRITICAL

2

1 C76241UF16VX5R

10%

402

2

1C7632NOSTUFF

0.001UF

X7R-CERM0402

10%50V

2

1R7632

603

5%2.21/10WMF-LF

NOSTUFF

2

1C7650

402CERM

0.22UF10V10%

2

1

XW7600SM


2

1C7601

BYPASS=U7600.2:1mm603

10VX5R

10UF20%

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14U7600TPS51916

QFN

CRITICAL

2

1R7614

201

17.4K1/20WMF

1%


2

1C760010UF

BYPASS=U7600.12:1mm

X5R603

10V20%

2

1R7613


1/20W

201

47.5K1%

MF

2

1 C7616

BYPASS=U7600.8:1mm0402

0.01UF

X7R-CERM

10%16V

2

1R7611


35.7K1/20W1%

201MF

2

1R7612


1/20W

201

49.9K1%

MF

2

1C7615

BYPASS=U7600.6:1mm

10%0.1UF

X7R-CERM16V

0402

2

1R7610

MF

1%1/20W

1K

201

2

1

XW7610SM


21

R7641

5%

MF1/20W

10

201

42 74

42 74 59

43

21

R7640

CYN0612-SHORT

0.0031%1w

OMIT

1.05V S0 Power Supply


P1V05S0_TRIP

MIN_LINE_WIDTH=0.5 mmP1V05S0_VBST

MIN_NECK_WIDTH=0.2 mmDIDT=TRUE

ISNS_1V05_S0_N

ISNS_1V05_S0_P

PP1V05_S0

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mmPP1V05_S0_REG_R




P1V05S0_VDDQSNS_R

GATE_NODE=TRUE


DIDT=TRUE

P1V05S0_DRVH_R


P1V05S0_LL


P1V05S0_VTTREF

VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_AGND

PP5V_S4RS3

P1V05S3_EN


P1V05S0_FB

P1V05_S0_VREFMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

P1V05S0_PGOOD

GATE_NODE=TRUE


P1V05S0_DRVH

DIDT=TRUE

P1V05S0_LL_SNUBDIDT=TRUE

P1V05S0_EN

P1V05S0_MODE


P1V05S0_VDDQSNS

P1V05S0_VTT

PP1V05_S0


P1V05S0_DRVL

GATE_NODE=TRUEDIDT=TRUE

P1V05S0_BOOT_RC

DIDT=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

<BRANCH>

<SCH_NUM>

<E4LABEL>

76 OF 121

55 OF 76

6 8 11 15 16 17 27

38 42 51

55 58 59

62 64

41 51 52 53 62 64

32 35 47 49 54 58 62 64

59

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

www.vinafix.vn

VDDIO VINVLDO

SW_0

SW_1

FB

OUT3

OUT2

OUT1

OUT4

OUT5

OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

TP

S

D

G

S

D

G

BI

NC

VIN

SW

OUTFB

EN

NC

THRMGNDPAD

NC

NC

IN

IN

BI


Apple Inc.


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6 3



Keyboard Backlight Driver & Detection

10.2 ohm resistors for currentmeasurement on LED strings.

Fpwm=9.62kHzsee spec for others

PPBUS_SW_LCDBKLT_PWR

AND PPBUS_SW_BKL

LOADING

RDS(ON)

I_LED=369/Riset

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

THERE IS A SENSE RESISTOR BETWEEN

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

ON THE SENSOR PAGE

FDC638APZ

P-TYPE

0.65 A (EDP)

43 mOhm @4.5V

518S0793

Keyboard Backlight Connector

Addr: 0x58(Wr)/0x59(Rd)

(GND_BKL_SGND)

I_LED=17.1mA

(EEPROM should set EN_I_RES=1)

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*C7797 AND C7799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

2

1 C7799

PLACE_NEAR=D7701.2:5mm

CRITICAL

10UF50V

1210-1X5R

10%2

1 C7797

PLACE_NEAR=D7701.2:3mm

CRITICAL

10UF50V

1210-1X5R

10%

21

L7701CRITICAL

15UH-2.8A

PIMB053T-SM

D2

D1

C1

C4

B2

B1

D4

D3

A4

E1

E2

E3

C5

D5

E5

B3

A2

A1

B5

E4

B4

C2

A5

C3

A3

U770125-BUMP-MICRO

LP8550

CRITICAL

18

13

2

1R7789

201

1/20WMF

147K1%

21

F7700

PLACE_SIDE=BOTTOM

603-HF

3AMP-32V-467

2

1R7788

201

1/20WMF

301K1%

2

1C7782

X7R-CERM0402

16V

0.1UF10%

4

3

65

21

Q7706

SSOT6-HF

CRITICAL

FDC638APZ_SBMS001

21

XW7720


SM

2

1R7714

201

1/20WMF

1%21.5K

21

R7731

201

1/20WMF

200K1%

2

1R7715

201

1/20WMF

100K1%

21

R7741

5%

201

1/20WMF

10K

21

R7753

5%

0

0201

1/20WMF

21

R7757

5%

0

0201

1/20WMF

21

R7704

5%

201

1/20WMF

33

2

1 C77045%33PF

NPO-C0G0201

25V

2

1R7716

201

1/20WMF

90.9K1%

2

1R77555%

201

1/20WMF

10K

2

1C7711BYPASS=U7701.C4:4mm

6.3VCERM-X5R

0201

0.1UF10%

2

1 C7714

10V

0201X5R-CERM

0.01UF

BYPASS=U7701.D1:3mm

10%

21R77175%

0


BKLT:PROD

MF-LF1/16W 40260 64

60 64 21R77185%

0

PLACE_NEAR=U7701.D5:10mm

1/16W MF-LF

BKLT:PROD

402

60 64

60 64

21R77195%

0


BKLT:PROD

MF-LF1/16W 402

21R77205%

0


1/16W MF-LF

BKLT:PROD

402

60 64

60 64

21R77215%

0


BKLT:PROD

MF-LF1/16W 402

21R77225%

0


1/16W MF-LF

BKLT:PROD

402

1TP7701TP-P6PLACE_SIDE=BOTTOM

45

3Q7707SOT-563

DMN5L06VK-7

12

6Q7707DMN5L06VK-7

SOT-563

37

2

1R77005%

MF-LF1/16W

4.7

402

2

1C7750BYPASS=U7750.1:2:2 MM

1UF

402-1

10VX5R

10%

21

L775010UH-0.58A-0.35OHM

1098AS-SM

CRITICAL

2

1 C77550.22UF

0603-1X5R-CERM50V10%

2

1 C7756

50VX5R-CERM0603-1

0.22UF10%

2

9

7

1

5

84

6

3

U7750

CRITICAL

MLFSPN035007G

4

3

2

1

6

5

J7715FF14A-4C-R11DL-B-3H

F-RT-SM

CRITICAL

2

1C7712


CRITICAL

805

10UF

X5R

10%25V 2

1 C7713


X5R

0.1UF10%25V

4022

1 C7796


220PF

0402

50VX7R-CERM

10%

KA

D7701


CRITICAL

RB160M-60G

SOD-123

2

1C7710

603-1

1UF

BYPASS=U7701.D1:5mm

X5R

10%25V

21

XW7710

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

SM

13

14 16 19 25 40 69

14 16 19 25 40 69


LCD/KBD Backlight Driver

3103S0198 R7717,R7718,R7719RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM BKLT:ENG

103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM BKLT:ENG3 R7720,R7721,R7722

LCDBKLT_EN_DIV_L

GND_BKL_SGNDMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=0V

BKL_FLTR

BKL_FSET

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmBKL_ISEN3


BKL_ISEN4


BKL_ISEN5


BKL_ISEN6BKL_FAULT

PPBUS_G3H


EDP_BKLT_EN

BKLT_PLT_RST_L

LCDBKLT_DISABLE

LCDBKLT_EN_L


LED_RETURN_1


LED_RETURN_2


LED_RETURN_3

LED_RETURN_4



LED_RETURN_5

SMBUS_PCH_CLK

SMBUS_PCH_DATA

EDP_BKLT_PWM

PP5V_S0

PP3V3_S0


BKL_ISEN1


BKL_ISEN2

PPVIN_S0SW_LCDBKLT

SMC_SYS_KBDLED

PPHV_S0SW_LCDBKLT

PPVIN_S0SW_LCDBKLT

BKL_ISET



PPVIN_S0SW_LCDBKLTFET

PPVOUT_SW_LCDBKLT_FBVOLTAGE=50V


PP5V_S0


LED_RETURN_6

LCDBKLT_BOOSTMIN_NECK_WIDTH=0.150 MM

DIDT=TRUESWITCH_NODE=TRUEVOLTAGE=50V


BKL_SCL

BKL_VSYNC_R

BKL_PWM

BKL_SDA

BKL_EN

KBDLED_ANODE

VOLTAGE=40V


MIN_NECK_WIDTH=0.225 MMSWITCH_NODE=TRUE

KBDLED_SW

DIDT=TRUE


VOLTAGE=40V

KBDLED_FBMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MM

<BRANCH>

<SCH_NUM>

<E4LABEL>

77 OF 121

56 OF 76

27 41 42 49 50 62 64

41

16 17 32 45 46 51 52 56 58 59 61 62 64

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 59 61

62 64 65 74

41 56

60 62 64

41 56

16 17 32 45 46 51 52 56 58 59 61 62 64

64 64

www.vinafix.vn

IN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND THRM_PAD

NC NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

Apple Inc.


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BRANCH

6 3



Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

Max Current = 0.35A

Vout = 1.05V

1.05V SUS LDOPull-ups (3) must be 51 ohms to support XDP (not required in production).

70mA is required to support pull-ups. Alternative is strong voltage

Vout = 1.5V

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

Max Current = 0.02A

1.5V S0 LDO

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

<Rb>

Vout = 1.794VMax Current = 1.8AFreq = 1 MHz

1.8V S3 REGULATOR

152S1870

2

1 C7821

603X5R-CERM-16.3V20%

CRITICAL

22UF

2

1C7822

603X5R-CERM-1

20%6.3V

22UF

CRITICAL

2

1 C7823

NP0-C0G-CERM0201

47PF

25V5%

2

1R7820

MF1/20W

201

1%113K

21

L7820

2520-SM

2.2UH-20%-2.0A-0.108OHM

CRITICAL

2

1C7820

6.3VX5R-CERM-1

603

20%22UF

CRITICAL

2

1C7824

X7R-CERM

10%16V

0201

1000PF

59

59

2

1R7821

1%

MF1/20W

201

90.9K

2

1 C7872

402X5R6.3V

2.2UF10%

7

1

2

6

5

3

4

U7870

CRITICAL

TPS72015

SON

2

1C7871

402

6.3VCERM

1UF10%

BYPASS=U7870.6:1mm

2

1C7870

402

1UF

CERM6.3V10%

BYPASS=U7870.4:1mm

20 21 22 23 57 62

28 59

1

6

9

4 5

3

8

7

2

U7820ISL8009B

DFN

CRITICAL43

21

R7829

0612-SHORT

OMIT

MF1W

0.0021%

2

1C7840

6.3VCERM402

1UF10%

XDP

7

1

2

6

5

3

4

U7840TPS720105

CRITICAL

SON

XDP

2

1 C7841

6.3V

2.2UF

402X5R

10%

XDP

2

1C7825

603X5R-CERM-1

20%6.3V

22UF

CRITICAL

Misc Power SuppliesSYNC_DATE=02/06/2013SYNC_MASTER=J41_MLB


P1V8S3_SW

P1V8S3_FB

PP3V3_S5

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP1V8_S3_REG_R PP1V8_S3

PP1V5_S0

PP1V8_S3

PP3V3_S5

P1V8S3_EN

P1V8S3_PGOOD

PM_SLP_S3_BUF_L

PP3V3_SUSPP1V05_SUS

<BRANCH>

<SCH_NUM>

<E4LABEL>

78 OF 121

57 OF 76

8 11 13 15 16 17 18 28 29 34

42 57 58 59

60 62 64 74

20 21 22 23 57 62

8 58 59 62 64 8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 14 18 46 58 59 62 64 16 62

www.vinafix.vn

INGND

VOUT

ON

VIN

NC NC

GND

VOUT

ON

VIN

IN

NCNC

GND

VOUT

ON

VIN

IN

NC NC

IN

INGND

VOUT

ON

VIN

IN

IN

INGND

VOUT

ON

VININ

GND

VDD

D

SON

CAP

NC NC

GND

VOUT

ON

VIN

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

S

D

G

S

D

G

G

D S

IN

GND

VDD

D

SON

CAP

S

D

ON S

D

VDD

GND

IN

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REVISION

BRANCH

6 3



@ 2.5VR(on)

1.5V S0 Audio Switch

5V S0 Switch

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e

EDP: 35mA

R(on)

3.3V SUS Switch

Current

25.8 mOhm Max

18.5 mOhm Typ

TPS22924C

Type

Load Switch

18.5 mOhm Typ

U8040

TPS22924C


2A Max

@ 2.5V

Current

@ 1.8VR(on)

Part

Current

3.3V Sensor Switch

Sense R on sensor page

2A Max

25.8 mOhm Max

Type

Current

2A MaxCurrent

Type

R(on)@ 2.5V

EDP: 1A

2.5A

17 mOhm Max15 mOhm Typ

25.8 mOhm Max

Load Switch

@ 2.5VR(on)

Type

Part

Load Switch

Current

R(on)

Part

@ 2.5V

2A Max

EDP: 1.02A

U8010TPS22924C

Current

EDP: 50mA

18.5 mOhm Typ

Part

Current 2A Max

EDP: 112mA

8.5 mOhm Max

Type Load Switch

Type

Part

U8050

Part

R(on)

Load Switch

U8020

TPS22924C

U8030Part

3.3V S0 Switch

Type

SLG5AP1438V

Load Switch

18.5 mOhm Typ

TPS22924C

Load Switch

Load Switch

3.3V S3 Switch

EDP: 300mA?

U8080

Part

U8005

Load Switch

Current

Type

R(on)

(HSIOFET_EN_L)

U807025.8 mOhm Max

3.3V SSD Switch

Type


EDP: 5A Sense R on sensor page

6A Max

@ 4V Vgs9.8 mOhm Typ

EDP: 1.84A

1.05V PCH HSIO Switch

3.3V S4 Switch

R(on)@ 25C

5.3A Max

SLG5AP1453VPart

7.8 mOhm Typ

2A Max

EDP: 1.84A

U8000

TPS22924C

SLG5AP1417V

TBD mOhm Max

EDP: 119mA

HSIO has turn-on requirement of

<65uS from EN to 95% (1.05V)<0.1V/uS ramp rate and

58 59

2

1C803020%

0201-1

1.0UF6.3VX5R

B1

A1

B2

A2

C2

C1

U8030

CRITICAL

CSPTPS22924

B1

A1

B2

A2

C2

C1

U8000TPS22924

CSP

CRITICAL18 28 59

2

1C8000

0201-1

20%1.0UF

6.3VX5R

B1

A1

B2

A2

C2

C1

U8020CSP

TPS22924

CRITICAL

2

1C8020

0201-1

20%1.0UF

6.3VX5R

59

2

1C80714700PF

10VX7R

10%

201

2

1 C8070

6.3VCERM-X5R0201

0.1UF10%

15 30 59 64

59

2

1C8010

0201-1

20%1.0UF

6.3VX5R

B1

A1

B2

A2

C2

C1

U8010CSP

TPS22924

CRITICAL

43

21

R8011

0612-SHORT

0.002

OMIT

1W1%

MF

43

21

R8000

0612-SHORT

OMIT

1W1%

0.002

MF

43

21

R8020

0612-SHORT

OMIT

1W1%

0.002

MF

2

1C8040

0201-1

20%1.0UF

6.3VX5R

59

2

1R8040NOSTUFF

10K

MF1/20W

201

5%

21

R8070NOSTUFF

MF1/20W

0201

0

5%58 59

21

R8041

MF1/20W

0201

0

5%

21

R8042NOSTUFF

MF1/20W

0201

0

5%

37 39 42

B1

A1

B2

A2

C2

C1

U8050CSP

TPS22924

CRITICAL

2

1C8050

0201-1

20%1.0UF

6.3VX5R

21

R8050

MF-LF402

1/16W

0

5%

2

1 C8080

16VX5R-CERM0201

0.1UF10%

59

1

52

8

37

U8080

CRITICAL

TDFNSLG5AP1443V

43

21

R8081

0612-SHORT

OMIT

1W1%

0.002

MF

2

1C80814700PF

10VX7R

10%

201

B1

A1

B2

A2

C2

C1

U8040TPS22924

CRITICAL

CSP

4

1

5

2

3

6

Q8061NTUD3169CZ

SOT-963

NOSTUFF

12

6Q8062SOT-563

NOSTUFF

DMN5L06VK-745

3Q8062SOT-563

NOSTUFF

DMN5L06VK-72

1R8061330

NOSTUFF

MF1/20W

201

5%

2

1R8062330

NOSTUFF

MF1/20W

201

5%2

1C8060

0201

0.01UF

X5R-CERM10V

NOSTUFF

10%

32

1

4

5

Q8060IRFHM830DPBFPQFN3.3X3.3

NOSTUFFCRITICAL

2

1R8060300

402

1/16WMF-LF

NOSTUFF

5%

2

1R806310K

NOSTUFF

MF1/20W

201

5%

15 58 1

52

8

37

U8070SLG5AP1453V

TDFN

CRITICAL

1

7

59

8

3

2

U8005

TDFNSLG5AP1471V

CRITICAL15 58

2

1C8005

10V

1UF

402X5R

10%

SYNC_MASTER=J41_MLB

Power FETsSYNC_DATE=02/06/2013

SSD_PWR_EN


PP1V05_S0


P3V3S0SW_SSD_FET_RAMP

HSIOFET_EN_L

PCH_HSIO_PWR_EN

PP5V_S0

PP3V3_S5


PP3V3_S0SW_SSD_FET_RVOLTAGE=3.3VMIN_LINE_WIDTH=0.50MM

HSIOFET_DISCHARGE

HSIOFET_DRV_HPCH_HSIO_PWR_EN

HSIOFET_DRV_L

PP1V05_S0

HSIOFET_EN

PP5V_S0

PP5V_S0

P1V5S0SW_AUDIO_EN

PP1V5_S0

S4_PWR_EN

SMC_SENSOR_PWR_EN

PP3V3_S4SW_SNSPP3V3_S4SW_SNS_FET_RVOLTAGE=3.3VMIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm

P3V3SUS_EN

PP3V3_SUSPP3V3_S5


PP3V3_SUS_FET_RVOLTAGE=3.3V

P3V3S3_EN

PP3V3_S3

PP3V3_S5

P3V3S0_EN

PP3V3_S5

PP3V3_S4_FET_RVOLTAGE=3.3VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

PP3V3_S0_FET_R

P5VS0_FET_RAMP

PP3V3_S4

PP1V5_S0SW_AUDIO

PP5V_S4RS3


MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMVOLTAGE=3.3VPP3V3_S3_FET_R

P5VS0_EN PP5V_S0_FET_RVOLTAGE=5VMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

PP3V3_S5

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.3 mmPP1V5_S0SW_AUDIO_HDA

VOLTAGE=1.5V


PP1V5_S0SW_AUDIO

MAKE_BASE=TRUE


VOLTAGE=1.5V

PP3V3_S5

P3V3S0_EN

<BRANCH>

<SCH_NUM>

<E4LABEL>

80 OF 121

58 OF 76

8 11 58 62

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 58 62

16 17 32 45 46 51 52 56 58 59 61 62 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

41

6 8 11 15 16 17 27 38 42 51 55 58 59

62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

8 57 59 62 64

41 42 43 62

8 11 14 18 46 57 59 62 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

15 18 19 33 36 40 41 62 64

8 11 13 15

16

17 18

28

29 34

42

57 58

59

60 62

64

74

8 11 13 15 16 17

18 28 29

34 42 57

58 59 60

62 64 74

41

29 33 36 38 39 62 64

58 61 65

32 35 47 49 54 55 62 64

8 11 17 58

8 11 13 15 16 17 18 28

29 34 42 57

58 59 60 62

64 74

8 11 17 58

58 61 65

8 11 13 15 16 17 18 28

29 34 42 57

58 59 60 62

64 74

www.vinafix.vn

OUT

OUT

IN

NC

NC

NC

Q3

Q2

Q4

Q1

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND THRM_PAD

IN

OUT

NC

NC

IN

IN

OUT

OUT

IN

SYM_VER_2

G S

D

OUT

IN OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUTIN

OUTIN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

IN

OUT

OUT

OUT

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



1.5V Codec Enable

so 1.05V can fall after 1.5V

Vce(sat) 0.1V max @ 1mA

V4MON: 0.572V-0.630V

Vbe 0.7V max @ 2mA

(IPU)

V3MON: 0.572V-0.630V

Thresholds:

S5_PWRGD-->SMC

5V needs to be held up

U8130 Sense input

SSD Enable

VFRQ High: Variable Frequency

5V Divider:

1.5V Divider:

1.05V Divider:

3.19V @ 4.5Vmin

0.718V @ 1.45Vmin

0.723V @ 1.02Vmin

353S2310

S3 Enables

S5 Power Good

SMC-->PM_DSW_PWRGD

S5 Enables

Min delay timeNo stuff C8131, 12ms

threhold is 3.07V

Standby Enables

VFRQ Low: Fix Frequency

SUS Enables

3.3V Divider: 1.07V

VDD: 2.734V-3.010V

5.0V Divider: 1.07V

V2MON: 2.815V-3.099V

Q1 Vth 0.7~1V @Id 250uA

CHGR VFRQ Generation

(ISL version used for development)S0 Rail PGOOD Circuitry

9ms RC delay

3.3V SUS Detect

S0 Rail PGOOD (BJT Version)

376S0854

PM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_LPM_SUS_EN

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

0

0

0

0

1

0

0

1

11

0

1

0

0

0

0

0

1

Mobile System Power State Table

SMC_S4_WAKESRC_ENSMC_PM_G2_ENABLESMC_ADAPTER_ENState

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

1

1

1

0

1

1

0

1

0

toggle 3Hz

1

X

Battery Off (G3HotAC)

Battery Off (G3Hot)

Sleep (S3AC)

Deep Sleep (S4)

Run (S0)

Deep Sleep (S5AC)

Deep Sleep (S4AC)

Sleep (S3)

Deep Sleep (S5)

S0 Enables

2

1R8131330K

MF1/20W

201

5%

50 2

1R816710K

MF1/20W

201

5%

16 17 37 59

2

1R8157100

MF1/20W

201

5%

21

R8166100

MF1/20W

201

5%

21

R8164100

MF1/20W

201

5%

21

R8162S0PGOOD_ISL

330

MF1/20W

201

5%

55

2

1R81561%

150K

MF1/20W

201

2

1C8160S0PGOOD_ISL

6.3VCERM-X5R

0201

0.1UF10%

2

1R815154.9K1%

MF1/20W

201

2

1R815215K1%

MF1/20W

201

3

2

8

46

1

7

5

Q8150

DFN2015H4-8

CRITICAL

ASMCC0179

21

R81541K

MF1/20W

201

5%

21

R81551K

MF1/20W

201

5%

2

1 C8131NO STUFF

16VX7R-CERM0201

10%1000PF

2

1R8133100K

MF1/20W

201

5%2

1C8130BYPASS=U8130.6:2.3mm

6.3VCERM-X5R

0201

0.1UF10%

13 64

72

6

5

3

9

8

1

4

U8160ISL88042IRTEZ

TDFN

CRITICAL

S0PGOOD_ISL

2

1R817315K1%

S0PGOOD_ISL

MF1/20W

2012

1R817115K1%

S0PGOOD_ISL

MF1/20W

2012

1R81611%15K

S0PGOOD_ISL

MF1/20W

201

2

1R817015K1%

S0PGOOD_ISL

MF1/20W

201 2

1R81726.04K1%

S0PGOOD_ISL

MF1/20W

2012

1R81606.04K1%

S0PGOOD_ISL

MF1/20W

201

13 42 59

58 59

21

R81531K

MF1/20W

201

5%

21

R8115

MF1/20W

0201

0

5%

4

6

5 3

1

2

U8170SOT89174LVC1G32

NOSTUFF

13 37

2

1C8170

BYPASS=U8170.6:2.3mm

NOSTUFF

6.3VCERM-X5R

0201

0.1UF10%

37 38

18 28 58 59

18 28 58 59

53

21

3Q8131DFN1006H4-3

DMN32D2LFB4

21

R8168100

MF1/20W

201

5%

37 54 59

2

1R8141PLACE_NEAR=U7501.20:7mm

100K

MF1/20W

201

5%

37 38 54 59

21

R8140100


MF1/20W

201

5%54 59

13 18 29 36 37 59

2

1 C8111

10VCERM

20%


0.1UF

4022

1 C8112

CERM-X5R

0.47UF


NO STUFF

6.3V10%

402

2

1R811120K


MF1/20W

201

5%

2

1R8112


MF1/20W

0201

05%

2

1 C8114NO STUFF

0.47UF


CERM-X5R6.3V10%

402

2

1R8114100


USB_PWR:STBY

MF1/20W

201

5%

53 59

58 59

35 59 61 65

13 42 59

2

1R815815K1%

MF1/20W

201

2

1R81597.15K1%

MF1/20W

201

13 17 18 37 21

R8178100

MF1/20W

201

5% 28 57 59

5

4

1

2

3

U8180SC70-HF

MC74VHC1G08

2

1R8180330K

NOSTUFF

MF1/20W

201

5%

2

1 C8185


NO STUFF

10V

0.22UF

CERM

10%

402

21

R8138820

NO STUFF


MF1/20W

201

5%

2

1R8185


MF1/20W

0201

05%

2

1 C8186

CERM10V20%


0.1UF

402

2

1R818620K


MF1/20W

201

5%

2

1 C81870.68UF

CERM


NO STUFF

6.3V10%

402

2

1R8187


MF1/20W

0201

05%

55 59

28 57 59

58 59

57 59

2

1R8116


MF1/20W

0201

05%

2

1 C8116NO STUFF


0.47UF

CERM-X5R6.3V10%

402

15 30 58 59 64 15 30 58 59 64

58

2

1 C8146


X5R

0.1UF10%25V

402

21

R81461K

MF1/20W

201

5%

21

R8145100K

PLACE_NEAR=U8040.2:C7mm

MF1/20W

201

5%13 61 65

2

1 C8180BYPASS=U8180.6:3mm

6.3VCERM-X5R0201

0.1UF10%

1

7

2 6

4

5

3

U8130

CRITICAL

TPS3808G33QFN

K

AD8175


NO STUFF

RB521ZS-30SM-201

21

R8176


NO STUFF

240

MF1/20W

201

5%

2

1R8175


MF1/20W

0201

05%

2

1 C8175


NO STUFF

2.2UF6.3VX5R

10%

402

2

1 C81420.47UF

CERM-X5R


NOSTUFF

6.3V10%

402

K

AD8185SM-201


NO STUFF

RB521ZS-30

K A

D8146SM-201

RB521ZS-30PLACE_NEAR=U8040.2:C7mm

58 59

2

1R8190

MF1/20W

0201

05%

2

1 C8190NO STUFF

X5R

0.1UF10%25V

402

2

1R8117100


USB_PWR:S3

MF1/20W

201

5%

37 38 54 59

54

21

R8179USB_PWR:S3

MF1/20W

0201

0

5%

21

R8177USB_PWR:STBY

MF1/20W

0201

0

5%

21

R8165100

MF1/20W

201

5%54

2

1C8159

10V

1UF

X5R

10%

402

K A

D8184


SM-201

RB521ZS-30

2

1R8184330


MF1/20W

201

5%


Power Control

P3V3S0_EN_D

MAKE_BASE=TRUEPM_SLP_S3_BUF_L

P1V05S0_ENMAKE_BASE=TRUE

P1V05S0_EN

P3V3S0_EN

P5VS0_ENMAKE_BASE=TRUE

P5VS0_EN

PM_SLP_S3_BUF_LPM_SLP_S3_BUF_L

P3V3S0_ENMAKE_BASE=TRUE

PM_SLP_S3_L PM_SLP_S3_R_L

PP3V3_S5

P1V05_EN_D

PM_SLP_S5_L

VMON_Q4_BASE

P1V5CODEC_EN_D

AUD_PWR_EN

USB_PWR_EN

PP1V5_S0PM_SLP_S3_BUF_L

ALL_SYS_PWRGD

VMON_Q2_BASE

S0PGD_BJT_GND_R

P1V8S3_PGOOD

PP3V3_S5

VMON_5V_DIV

VMON_3V3_DIV

VMON_Q3_BASE

PP3V3_S0

TP_SUS_PGOOD_MR_L

MAKE_BASE=TRUEPM_SLP_SUS_L

PP5V_S0

PP3V3_S5

PM_SLP_S3_R_L

PP3V3_SUS

PM_SLP_SUS_L

PM_RSMRST_L

S4_PWR_EN

S4_PWR_ENMAKE_BASE=TRUE

SMC_PM_G2_EN

SMC_PM_G2_ENMAKE_BASE=TRUE

S5_PWR_ENMAKE_BASE=TRUE

S5_PWR_EN

DDRREG_PGOOD

ALL_SYS_PWRGDS0PGD_C

P1V05_DIV_VMON

P5V_DIV_VMONP1V5_DIV_VMON

PP5V_S0

CHGR_VFRQ

PP3V42_G3H

ALL_SYS_PWRGD_R

PP1V05_S0

PP1V5_S0

PP3V42_G3H

S5_PWRGDMAKE_BASE=TRUES5_PWRGD

MAKE_BASE=TRUESSD_PWR_EN

PP3V3_SUS

SUS_PGOOD_CT

S4_PWR_EN

S4_PWR_EN

PM_SLP_S4_L

P5VS4RS3_PGOOD

SMC_S4_WAKESRC_EN

P3V3SUS_ENMAKE_BASE=TRUE

P3V3SUS_EN

P5VS4RS3_EN

MAKE_BASE=TRUEP3V3S3_EN P3V3S3_EN

P1V8S3_EN

SSD_PWR_EN

MAKE_BASE=TRUEDDRREG_EN

PP3V3_S0

P1V05S0_PGOOD

PP3V3_S5

P5VS4RS3_EN_RC

DDRREG_ENMAKE_BASE=TRUEP1V8S3_EN

PM_SLP_S4_L

P5VS4RS3_EN_D

USB_PWR_ENMAKE_BASE=TRUE

P1V5S0SW_AUDIO_EN

<BRANCH>

<E4LABEL>

81 OF 121

<SCH_NUM>

59 OF 76

28 57 59

55 59

58 59

58 59

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 57 58 59 62 64 28 57 59

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 12 13 15 17 18 27

30 36 38 39

40 41 42 43 44 45 56

59 61 62 64 65 74

16 17 32 45 46 51 52 56 58 59 61 62 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

59

8 11 14 18 46 57 58 59 62 64

18 28 58 59

54 59

16 17 37 59

16 17 32 45

46 51

52 56

58 59

61 62

64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

6 8 11 15 16 17 27 38 42 51 55 58 62 64

8 57 58 59 62 64

17 30 35 36 37 38 40 46

49 50 59 61

62 64 65

37 54 59

8 11 14 18 46 57 58 59 62 64

13 18 29 36 37 59

58 59

58 59

53 59

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56

59 61 62 64 65 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

57 59

35 59 61 65

www.vinafix.vn

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

BI

BI

BI

IN

NC

NCNC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



sensor pageSense resistor on

(DP_INT_AUX_CH_C_P)

(DP_INT_AUX_CH_C_N)

Pull-ups on panel side,

DisplayPort I/F

LED Backlight I/F

LCD ConnectorInternal DP Connector: 518S0829

4.7 kOhm to 3.3V

2

1 C831220%

603

10UF6.3VX5R2

1C8311

6.3VCERM-X5R

0201

0.1UF10%

2

1 C8309

6.3VCERM-X5R0201

0.1UF10%

5

4

3

2

7

1

6

U8300FPF1009

CRITICAL

MFET-2X2-8IN

2

1C83175%


1000PF

603C0G-CERM

50V

2

1C8315

0201

16V

1000PF

X7R-CERM

10%

21

C8324

16VX5R-CERM

0201

0.1UF

10%

21

C8325

16V

0201X5R-CERM

0.1UF

10%

21

C8320

16V

0201X5R-CERM

0.1UF

10%

21

C8321

16V

0201X5R-CERM

0.1UF

10%

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J8300F-RT-SM

20525-130E-01

CRITICAL

2

1R83505%

201

1/20WMF


100K

21

R8360

5%

0

0201

1/20WMF

2

1R83805%

201

1/20WMF

1M

2

1R83705%

201

1/20WMF

1M

13

56 64

56 64

56 64

56 64

56 64

56 64

5 67

5 67

13

5 67

5 67

37 40 73

37 40 73

21

R8361

5%

0

0201

1/20WMF

21

R8362

5%

0

0201

1/20WMF

2

1R83185%

201

1/20WMF


1M

2

1R83175%

201

1/20WMF


1M

2

1R83635%

201

1/20WMF

4.7K

2

1R83645%

201

1/20WMF

4.7K

21


0402-LF


Internal DisplayPort Connector

PP3V3_S0SW_LCDPP3V3_S0SW_LCD_R

I2C_TCON_SCL_R

PPHV_S0SW_LCDBKLT

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MMPP3V3_S0SW_LCD_UF

EDP_PANEL_PWR

PP3V3_S5

I2C_TCON_SDA_R

LED_RETURN_2LED_RETURN_1

LED_RETURN_3LED_RETURN_4LED_RETURN_5LED_RETURN_6

DP_INT_ML_C_N<0>

DP_INT_HPD_CONN

DP_INT_ML_C_P<0>

DP_INT_AUXCH_C_N

DP_INT_AUXCH_C_P

SMBUS_SMC_0_S0_SDA

DP_INT_ML_N<0>DP_INT_ML_P<0>

DP_INT_AUX_CH_C_PDP_INT_AUX_CH_C_N

DP_INT_HPD

SMBUS_SMC_0_S0_SCL

<BRANCH>

<SCH_NUM>

<E4LABEL>

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64

56 62 64

64

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64

64

64 67

64 67

64 67

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IN

IN

BI

BI

IN

OUT

IN

IN

OUT

BI

BI

BI

OUT

IN

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

Apple Inc.


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6 3



(Right Speaker Enable)

516S1036

ON MLB SIDE AS LIO CAN’T FIT CAPS

2

1C95100.1UF

10%

X5R-CERM0201

16V


36 37 38 64 65

12 65 69

2

1C9520

X5R-CERM020116V10%

0.1UF


14 65 68

14 65 68

47 65 74

47 65 74

37 38 50 65

35 59 65

39 65

37 65

37 40 65 73

37 40 65 73

14 16 65

12 65 69

47 65

12 65 69

12 65 69

12 65 69

21

C9522

0.1UF020116V

10%X5R-CERM

GND_VOID=TRUE

21

C9521

020110%16V 0.1UF

X5R-CERM

GND_VOID=TRUE

14 65 68

14 65 68

14 65 68

14 65 68

2

1

D9511ESD0P2RF-02LSTSSLP-2-1

GND_VOID=TRUE

CRITICAL2

1

D9510CRITICAL


GND_VOID=TRUE

2

1

D9520CRITICAL

GND_VOID=TRUE


2

1

D9521CRITICAL


GND_VOID=TRUE

21

R9510GND_VOID=TRUE

MF1/20W 0201

05%

21

C9532NOSTUFF

25V

15PF

0201NP0-CERM

GND_VOID=TRUE

5%

21

R9520GND_VOID=TRUE

MF1/20W 0201

05%

21

C9531

NOSTUFF

15PF

GND_VOID=TRUE

0201NP0-CERM

25V5%

9876

5251

50

5

49

484746454443424140

4

3938373635

323130

3

29282726252423222120

2

19

16151413121110

1

J9500DF40CG3.0-48DS-0.4V

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

F-ST-SM

GND_VOID=TRUE

GND_VOID=TRUE

13 59 65

2 1

R9501NOSTUFF

MF1/20W

0201

0

5%

2

1C955010PF

C0G-CERM50V

0402

NOSTUFF

5%

2

1 C9500

0201

10%0.1UF

X5R-CERM16V


IO Ports

Left I/O (LIO) ConnectorSYNC_MASTER=CLEAN_J43 SYNC_DATE=11/13/2012

USB3_EXTB_D2R_NUSB3_EXTB_D2R_RC_N

AUD_PWR_EN

USB3_EXTB_R2D_C_N

USB3_EXTB_R2D_C_P

USB3_EXTB_D2R_P

USB_EXTB_NPP5V_S0

USB3_EXTB_R2D_P

USB_EXTB_P

FINSTACKSNS_ALERT_LUSB_PWR_ENSMC_BC_ACOK

SYS_ONEWIRE

XDP_USB_EXTB_OC_L

USB3_EXTB_R2D_N

HDA_RST_L

PP1V5_S0SW_AUDIO

SPKRAMP_SHDN_L

HDA_SDIN0

HDA_SYNC

SMC_LID

HDA_SDOUTHDA_BIT_CLK

VOLTAGE=5V

PP5V_S0_ALT_AUD_LDO_ENMIN_LINE_WIDTH=0.1 mmMIN_NECK_WIDTH=0.1 mm

SPKRAMP_INR_PSPKRAMP_INR_N

PP3V3_S0

PP3V42_G3H


USB3_EXTB_D2R_RC_P

<BRANCH>

<SCH_NUM>

<E4LABEL>

95 OF 121

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17 30 35 36 37 38 40 46 49 50 59 62 64 65

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Apple Inc.


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LCDBKLT Rail

1.84A

Digital Ground

CPU "VCORE" RAILS

1.8V/1.5V/1.2V/1.05V Rails TBT Rails (off when no cable)

"G3Hot" (Always-Present) Rails

2A max supply

3.3V Rails

5V Rails

? mA


Power AliasesSYNC_MASTER=J41_MLB

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP3V3_SUSMIN_LINE_WIDTH=0.50MM



MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3VPP3V3_S5

MAKE_BASE=TRUE

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5


PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP5V_S4RS3MIN_NECK_WIDTH=0.175 MM

PP1V05_S0

VOLTAGE=1.05V


MAKE_BASE=TRUEPP5V_S4RS3

VOLTAGE=5V


MAKE_BASE=TRUE

PP5V_S4RS3


PP5V_S5

MAKE_BASE=TRUEVOLTAGE=5V


PP5V_S5

PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PPVRTC_G3H

MIN_LINE_WIDTH=0.6 MMPP3V42_G3H

MAKE_BASE=TRUEVOLTAGE=3.42VMIN_NECK_WIDTH=0.2 MM

PP3V42_G3H




PP1V05_SUSMIN_LINE_WIDTH=0.4 MM


PP1V2_S3

PP1V2_S3

PP1V2_S3


PP1V5_S0


PP1V5_S0

PP1V05_SUS

PP0V6_S0_DDRVTT

PP1V05_SUS

PP0V6_S0_DDRVTT

PP0V6_S0_DDRVTT

PP1V5_S0

PP5V_S5

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S4RS3

PP5V_S4RS3

PP5V_S4RS3

PP3V3_S4_TBTAPWR

PP3V3_S5

PP1V2_S3



PP3V3_SUS

PP3V3_S3

PP3V3_S3

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS


MIN_LINE_WIDTH=0.6MMPP1V8_S3

MIN_NECK_WIDTH=0.2MMVOLTAGE=1.2VMAKE_BASE=TRUE

PP5V_S0

PP5V_S0

PP5V_S5

PP3V42_G3H

PP1V05_S0


MAKE_BASE=TRUEVOLTAGE=8.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

PPBUS_G3H

PP1V2_S3

MAKE_BASE=TRUE



PPBUS_G3H

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP1V05_S0


PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

VOLTAGE=8.6V



MAKE_BASE=TRUE

PP1V05_S0

PP1V05_S0


PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PP1V8_S3

PP3V3_S4_TBTAPWR

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=0.38 MM


PPBUS_G3H

PPBUS_G3H

PP3V42_G3H

PPDCIN_G3H



PP3V42_G3H

PPDCIN_G3H

MAKE_BASE=TRUE



PP3V3_S0SW_SSD

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S0SW_SSD

PP1V2_S3

PPHV_S0SW_LCDBKLT

MAKE_BASE=TRUE

PPHV_S0SW_LCDBKLTMIN_LINE_WIDTH=0.5 MM

VOLTAGE=50VMIN_NECK_WIDTH=0.375 MM

PPVCC_S0_CPU

PPVCC_S0_CPU

PPVCC_S0_CPU



MIN_LINE_WIDTH=0.6 MMPPVCC_S0_CPU

PP1V05_S0

PP1V05_S0

PP1V2_S3

PP1V2_S3 PP1V05_TBTLCMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMAKE_BASE=TRUE

MAKE_BASE=TRUE


PP1V05_TBTCIO

PP3V3_TBTLC

PP1V05_TBTLC

PP1V05_TBTLC

PP1V05_TBTCIO

PP15V_TBT


MAKE_BASE=TRUE


PP3V3_TBTLC

PP1V5_S0

PP1V2_S3

PP3V3_TBTLC

PP3V3_TBTLC

PP3V3_TBTLC

PP3V3_S4_TBTAPWR

PP1V8_S3

VOLTAGE=8.6VPPVIN_S4SW_TBTBST_FET

PPHV_S0SW_LCDBKLT

PP1V05_TBTCIO

PP3V3_S0SW_SSD

PPDCIN_G3H_ISOL


PP5V_S4RS3

PPVRTC_G3H

PP5V_S0

PP5V_S0

PP5V_S0

PP5V_S0


MAKE_BASE=TRUE


PP5V_S0

PP5V_S0

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP5V_S0

PP5V_S4RS3

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS

PP3V42_G3H

PP3V42_G3H


VOLTAGE=3VMAKE_BASE=TRUE


PPVRTC_G3H

PP1V5_S0

PP3V3_S4SW_SNS

PP3V3_S4SW_SNS



PP1V05_S0SW_PCH_HSIOMIN_LINE_WIDTH=0.6 MM

PP5V_S0

PP1V05_S0

PP1V05_S0

PP0V6_S0_DDRVTT

MIN_NECK_WIDTH=0.17 mmVOLTAGE=0.75VMAKE_BASE=TRUE


PP3V3_S5

PP3V3_S4

PP3V3_S4

PP3V3_S4

PP3V3_S4MIN_LINE_WIDTH=0.60MM VOLTAGE=3.3V

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM

PP3V3_S4SW_SNS

PP3V3_S5

PP3V3_S5

PP3V3_S5 PP15V_TBT

PP15V_TBT



PP1V8_S3

PPDCIN_G3HPP3V3_S4

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S5

PP3V3_S5

PP3V3_S4

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

PP3V3_S3

PP3V3_S3

PP3V42_G3H

PP3V42_G3H

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PPDCIN_G3H_ISOLMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MMPPDCIN_G3H_ISOL


PP3V42_G3H

PP3V42_G3H

PP3V42_G3H

PPDCIN_G3H_ISOL

PP3V3_S3

PP3V3_SUS

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

MAKE_BASE=TRUE

PP3V3_S4SW_SNSMIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

PP3V3_S0

PP3V3_S0

PP3V3_S0

MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUEMIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

GNDVOLTAGE=0V


<BRANCH>

<SCH_NUM>

<E4LABEL>

100 OF 121

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6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 14 18 46 57 58 59 62 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 58 62

41 42 43 58 62

41 42 43 58 62

32 35 47 49 54 55 58 62 64 6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

32 35 47 49 54 55 58 62 64

32 35 47 49 54 55 58 62 64

36 53 54 62

36 53 54 62

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8 12 13 17 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

17 30 35 36 37 38

40 46 49

50 59 61

62 64 65

41 51 52 53 55 62

64

41 54 62 64

16 57 62

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70

8 57 58 59 62 64

8 57 58 59 62 64

16 57 62

24 53 62

16 57 62

24 53 62

24 53 62

8 57 58 59 62 64

36 53 54 62

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

32 35 47 49 54 55 58 62 64

32 35 47 49 54 55 58 62 64

32 35 47 49 54 55 58 62 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

17 19 20 21 22 23 42 53 62 70

8 11 14 18 46 57 58 59 62 64

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

41 51 52 53 55 62 64

20 21 22 23 57 62

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

36 53 54 62

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

41 54 62 64

27 41 42 49 50 56 62 64

17 19 20 21 22 23 42 53 62 70

27 41 42 49 50 56 62 64

41 42 43 58 62

41 42 43 58 62

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

41 54 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

41 51 52 53 55 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

8 11 58 62

27 41 42 49 50 56 62 64

27 41 42 49 50 56 62 64

27 41 42 49 50 56 62 64

20 21 22 23 57 62

25 26 27 28 62

27 41 42 49 50 56 62 64

27 41 42 49 50 56

62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

49 50 62 64

41 51 52 53 55 62 64

41 51 52 53 55 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

49 50 62 64

30 41 62 64

30 41 62 64

17 19 20 21 22 23 42 53 62 70

56 60 62 64 56 60 62 64

8 10 42 52 62 64

8 10 42 52 62 64

8 10 42 52 62 64

8 10 42 52 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

17 19 20 21 22 23 42 53 62 70

17 19 20 21 22 23 42 53 62 70 26 27 62 64

26 27 62 64

15 17 25 26 27 62 64

26 27 62 64

26 27 62 64

26 27 62 64

27 28 62 64

15 17 25 26 27 62 64

8 57 58 59 62 64

17 19 20 21 22 23 42 53 62 70

15 17 25 26 27 62 64

15 17 25 26 27 62 64

15 17 25 26 27 62 64

25 26 27 28 62

20 21 22 23 57 62

27 64

56 60 62 64

26 27 62 64

30 41 62 64

42 49 50 62 64

8 11 58 62

32 35 47 49 54 55 58 62 64

8 12 13 17 62 64

16 17 32 45 46 51 52 56 58 59 61 62

64

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

16 17 32 45 46 51 52 56 58 59 61 62 64

41 42 43 58 62

41 42 43 58 62

41 42 43 58 62

16 17 32 45 46 51 52 56 58 59 61 62 64

32 35 47 49 54 55 58 62 64

41 42 43 58 62

41 42 43 58 62

41 42 43 58 62

41 42 43 58 62

41 42 43 58 62

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8 12 13 17 62 64

8 57 58 59 62 64

41 42 43 58 62

41 42 43 58 62

8 11 58 62

16 17 32 45 46 51 52 56 58 59 61 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

6 8 11 15 16 17 27 38 42 51 55 58 59 62 64

24 53 62

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

29 33 36 38 39 58 62 64

29 33 36 38 39 58 62 64

29 33 36 38 39 58 62 64

29 33 36 38 39 58 62 64

41 42 43 58 62

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74 27 28 62 64

27 28 62 64

20 21 22 23 57 62

49 50 62 64 29 33 36 38 39 58 62 64

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

29 33 36 38 39 58 62 64

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

8 11 14 18 46 57 58 59 62 64

15 18 19 33 36 40 41 58 62 64

15 18 19 33 36 40 41 58 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62

64 65 74 8 11 12 13 15 17 18 27 30 36

38 39 40 41 42 43 44 45

56 59 61 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38

39

40 41 42 43 44 45 56 59 61 62

64

65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62

64 65 74 8 11 12 13 15 17 18 27 30 36

38 39 40 41 42 43 44 45

56 59 61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62

64 65 74 8 11 12 13 15 17 18 27 30 36

38 39 40 41 42 43 44 45

56 59 61 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38

39

40 41 42 43 44 45 56 59 61 62

64

65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62

64 65 74 8 11 12 13 15 17 18 27 30 36

38 39 40 41 42 43 44 45

56 59 61 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38

39

40 41 42 43 44 45 56 59 61 62

64

65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

42 49 50 62 64

42 49 50 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

42 49 50 62 64

8 11 14 18 46 57 58 59 62 64

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44

45 56 59 61 62 64 65 74

41 42 43 58 62

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62

64 65 74 8 11 12 13 15 17 18 27 30 36

38 39 40 41 42 43 44 45

56 59 61 62 64 65 74

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

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Apple Inc.


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MAKE_BASE

Memory Bit/Byte Swizzle

MAKE_BASEMAKE_BASE

LPDDR3 Command/Address

Signal AliasesSYNC_MASTER=J41_MLB SYNC_DATE=08/30/2012

TRUE MEM_B_DQ<32>

TRUE MEM_B_DQ<44>=MEM_B_DQ<32>

=MEM_A_DQ<29>

TP_LPDDR3_RSVD1

TRUE MEM_B_CAB<4>

=MEM_B_A<15>=MEM_B_A<11>

=MEM_A_A<2>

MEM_A_CAB<2>TRUE

MEM_A_CAB<5>TRUE

MEM_A_ODT<0>TRUE

TRUE TP_LPDDR3_RSVD1

TP_LPDDR3_RSVD3TRUETP_LPDDR3_RSVD4TRUE

MEM_B_ODT<0>TRUE

TRUE MEM_B_CAA<0>TRUE MEM_B_CAA<1>TRUE MEM_B_CAA<2>

MEM_B_CAA<3>TRUE

TRUE MEM_B_CAA<5>TRUE MEM_B_CAA<4>

TRUE MEM_B_CAA<6>TRUE MEM_B_CAA<7>TRUE MEM_B_CAA<8>TRUE MEM_B_CAA<9>

TRUE MEM_B_CAB<0>TRUE MEM_B_CAB<1>TRUE MEM_B_CAB<2>TRUE MEM_B_CAB<3>

TRUE MEM_B_CAB<6>

TRUE MEM_B_CAB<8>TRUE MEM_B_CAB<9>

TP_LPDDR3_RSVD2TRUE

MEM_A_CAB<1>TRUE

MEM_A_CAB<3>TRUE

MEM_A_CAB<8>TRUEMEM_A_CAB<9>TRUE

MEM_A_CAB<7>TRUE

TRUE MEM_A_CAA<7>

TRUE MEM_A_CAA<9>TRUE MEM_A_CAA<8>

TRUE MEM_A_CAB<0>

MEM_A_CAB<4>TRUE

TRUE MEM_A_CAA<1>TRUE MEM_A_CAA<0>

MEM_A_CAA<3>TRUE

TRUE MEM_A_CAA<4>

MEM_A_CAA<6>TRUE

MEM_A_CAB<6>TRUE

TRUE MEM_B_CAB<7>

MEM_B_CAB<5>TRUE

TP_LPDDR3_RSVD3TP_LPDDR3_RSVD4

MEM_A_ODT<0>

=MEM_B_A<5>=MEM_B_A<9>=MEM_B_A<6>=MEM_B_A<8>

=MEM_B_BA<2>=MEM_B_A<7>

=MEM_B_A<14>

=MEM_B_A<13>=MEM_B_CAS_L=MEM_B_WE_L=MEM_B_RAS_L=MEM_B_BA<0>=MEM_B_A<2>MEM_B_CAB<6>=MEM_B_A<10>=MEM_B_A<1>=MEM_B_A<0>

TP_LPDDR3_RSVD2

=MEM_A_A<15>


=MEM_A_A<11>

=MEM_A_A<13>=MEM_A_CAS_L

=MEM_A_RAS_L=MEM_A_BA<0>


=MEM_A_A<5>


MEM_A_CAA<6>

=MEM_A_A<10>

=MEM_A_BA<2>

=MEM_A_A<14>

=MEM_A_WE_L

MEM_B_CAA<6>

MEM_A_CAB<6>

MEM_B_ODT<0>

TRUE MEM_B_DQ<12>=MEM_B_DQ<0>TRUE MEM_B_DQ<9>=MEM_B_DQ<1>


TRUE MEM_B_DQ<14>TRUE MEM_B_DQ<8>=MEM_B_DQ<5>


TRUE MEM_B_DQ<15>=MEM_B_DQ<7>TRUE MEM_B_DQ<0>=MEM_B_DQ<8>TRUE MEM_B_DQ<1>=MEM_B_DQ<9>TRUE MEM_B_DQ<2>=MEM_B_DQ<10>

MEM_B_DQ<7>TRUE=MEM_B_DQ<11>

TRUE MEM_A_DQ<12>=MEM_A_DQ<1>TRUE MEM_A_DQ<9>=MEM_A_DQ<0>

MEM_A_DQ<13>TRUE=MEM_A_DQ<5>TRUE MEM_A_DQ<8>=MEM_A_DQ<4>

TRUE MEM_A_DQ<14>

TRUE MEM_A_DQ<10>TRUE MEM_A_DQ<11>=MEM_A_DQ<3>

TRUE MEM_A_DQ<1>TRUE MEM_A_DQ<2>=MEM_A_DQ<10>

TRUE MEM_A_DQ<15>=MEM_A_DQ<7>

=MEM_A_DQ<11>

TRUE MEM_A_DQ<0>

TRUE MEM_B_DQ<4>TRUE MEM_B_DQ<5>=MEM_B_DQ<13>

TRUE MEM_B_DQ<28>=MEM_B_DQ<16>TRUE MEM_B_DQ<3>=MEM_B_DQ<15>TRUE MEM_B_DQ<6>=MEM_B_DQ<14>

TRUE MEM_B_DQ<29>=MEM_B_DQ<17>TRUE MEM_B_DQ<30>=MEM_B_DQ<18>TRUE MEM_B_DQ<27>=MEM_B_DQ<19>







TRUE MEM_B_DQ<18>=MEM_B_DQ<30>=MEM_B_DQ<31>


TRUE MEM_B_DQ<47>

TRUE MEM_B_DQ<34>=MEM_B_DQ<42>TRUE MEM_B_DQ<33>MEM_B_DQ<33>

TRUE MEM_B_DQ<46>








TRUE MEM_A_DQ<4>=MEM_A_DQ<12>MEM_A_DQ<5>TRUE=MEM_A_DQ<13>

=MEM_A_DQ<16>MEM_A_DQ<6>TRUE=MEM_A_DQ<15>MEM_A_DQ<3>TRUE=MEM_A_DQ<14>


MEM_A_DQ<27>TRUE=MEM_A_DQ<18>



=MEM_A_DQ<22>TRUE MEM_A_DQ<30>=MEM_A_DQ<23>


TRUE MEM_A_DQ<16>=MEM_A_DQ<26>TRUE MEM_A_DQ<21>

MEM_A_DQ<19>TRUE



TRUE MEM_A_DQ<17>


TRUE MEM_A_DQ<41>=MEM_A_DQ<32>=MEM_A_DQ<33>=MEM_A_DQ<34>

TRUE MEM_A_DQ<40>=MEM_A_DQ<36>=MEM_A_DQ<35>







TRUE MEM_A_DQ<39>TRUE MEM_A_DQ<32>MEM_A_DQ<32>














TRUE MEM_B_DQS_P<1>=MEM_B_DQS_P<0>

TRUE MEM_B_DQS_N<0>=MEM_B_DQS_N<1>TRUE MEM_B_DQS_P<0>=MEM_B_DQS_P<1>TRUE MEM_B_DQS_N<1>=MEM_B_DQS_N<0>

TRUE MEM_B_DQS_P<3>=MEM_B_DQS_P<2>TRUE MEM_B_DQS_N<3>=MEM_B_DQS_N<2>TRUE MEM_B_DQS_P<2>=MEM_B_DQS_P<3>TRUE MEM_B_DQS_N<2>=MEM_B_DQS_N<3>TRUE MEM_B_DQS_P<5>=MEM_B_DQS_P<4>TRUE MEM_B_DQS_N<5>=MEM_B_DQS_N<4>TRUE MEM_B_DQS_P<4>=MEM_B_DQS_P<5>

MEM_B_DQS_N<7>TRUE=MEM_B_DQS_N<6>TRUE MEM_B_DQS_P<7>=MEM_B_DQS_P<6>TRUE MEM_B_DQS_N<4>=MEM_B_DQS_N<5>

TRUE MEM_B_DQS_P<6>MEM_B_DQS_P<6>TRUE MEM_B_DQS_N<6>MEM_B_DQS_N<6>









TRUE MEM_A_DQS_P<0>=MEM_A_DQS_P<1>TRUE MEM_A_DQS_N<0>=MEM_A_DQS_N<1>

TRUE MEM_A_DQS_N<1>=MEM_A_DQS_N<0>TRUE MEM_A_DQS_P<1>=MEM_A_DQS_P<0>


TRUE MEM_A_DQS_P<5>=MEM_A_DQS_P<4>



TRUE MEM_A_DQS_N<6>MEM_A_DQS_N<6>TRUE MEM_A_DQS_P<6>MEM_A_DQS_P<6>TRUE MEM_A_DQS_N<4>=MEM_A_DQS_N<5>

TRUE MEM_A_DQS_P<7>=MEM_A_DQS_P<7>TRUE MEM_A_DQS_N<7>=MEM_A_DQS_N<7>

TRUE MEM_A_DQ<26>

TRUE MEM_A_DQ<7>


=MEM_A_DQ<6>

=MEM_A_DQ<2>

MEM_A_DQ<44>TRUE


=MEM_A_DQ<25>

TRUE MEM_A_CAA<5>

TRUE MEM_A_CAA<2>

=MEM_A_DQ<31>

=MEM_A_DQ<43>

TRUE MEM_A_DQ<47>TRUE MEM_A_DQ<46>

=MEM_B_DQ<33>

TRUE MEM_B_DQ<19>

TRUE MEM_B_DQ<21>

=MEM_B_DQ<12>

=MEM_B_DQ<6>

TRUE MEM_A_DQ<29>

=MEM_B_DQ<37>



TRUE MEM_B_DQ<40>TRUE MEM_B_DQ<45>TRUE MEM_B_DQ<43>

TRUE MEM_B_DQ<41>

=MEM_B_DQ<28>

<BRANCH>

<SCH_NUM>

<E4LABEL>

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www.vinafix.vn

Apple Inc.


124578

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(Need to add 8 GND TPs)

J3501: AirPort / BT Connector

J4800: IPD Flex ConnectorFUNC_TEST

FUNC_TEST

(Need to add 1 GND TP)

(Need 5 TPs)

(Need 4 TPs)

(Need 3 TPs)

Misc Voltages & Control SignalsFUNC_TESTFUNC_TEST

Functional Test PointsJ6000: Fan Connector

FUNC_TEST

FUNC_TEST


(Need to add 4 GND TPs near

J8300: Internal DP Connector


J6950: Battery Connector

CPU/PCH

NO_TESTMAKE_BASE

NO_TEST Nets

SMC

J6100: LPC+SPI ConnectorFUNC_TEST


FUNC_TEST

J3700: SSD Connector

FUNC_TEST

J4002: Camera Connector

(Need to add TBD GND TPs)

(Need 2 TPs)

(Need 6 TPs)

(Need TBD TPs)

FUNC_TEST


TBT

FUNC_TEST


J7715: KB BKLT Connector

FUNC_TEST

J1800: XDP Connectorfor FCT HVM test fixture)

(Only a subset are needed



J7050 and 1 for shield)

FUNC_TEST

(Need 2 TPs)

(Nets with offpages not used on this project)

Unused nets with offpage

J6404: Speaker Connector


J7000: DC-In Connector


(Need 4 TPs)

I776

I777

I778

I779

I780

I781

I782

I783

I784

I785

I786

I787

I788

I789

I790

I791

I792

I793

Func Test / No TestSYNC_MASTER=J41_MLB SYNC_DATE=02/01/2013

TRUE PCIE_CLK100M_AP_P

TRUE SMBUS_SMC_3_SDA

TRUE AP_RESET_CONN_L

SMBUS_SMC_3_SCLTRUE

TRUE SSD_PWR_ENTRUE PCIE_SSD_D2R_N<3..0>

TRUE SPI_ALT_MOSILPC_AD<3..0>TRUE

TRUE PP5V_S0

TRUE LED_RETURN_4

LED_RETURN_1TRUE

TRUE SYS_DETECT_L

TRUE I2C_TCON_SDA_R

TRUE DP_INT_AUX_CH_C_PTRUE XDP_LPCPLUS_GPIO

TP_SMC_TRST_LTRUE

SMC_TDOTRUE

TRUE LPCPLUS_RESET_L

TRUE GND

TRUE SMC_TMS

TRUE PP1V05_S0

TRUE XDP_PCH_TCKTRUE XDP_CPU_TCK

TRUE PM_SYSRST_LTRUE CPU_CFG<3>

TRUE PM_RSMRST_LTRUE XDP_SYS_PWROK

TRUE XDP_CPU_PRDY_LTRUE XDP_CPU_VCCST_PWRGD

TRUE XDP_PCH_TDOTRUE XDP_CPU_PREQ_L

TRUE XDP_PCH_TMSTRUE XDP_PCH_TDI

TRUE XDP_CPUPCH_TRST_LTRUE XDP_CPU_TMS

TRUE XDP_CPU_TDITRUE XDP_CPU_TDO

TRUE KBDLED_FBKBDLED_ANODETRUE

NC_DP_TBTSRC_ML_CP<3>TRUE TRUENC_DP_TBTSRC_ML_CN<3>TRUE TRUENC_DP_TBTSRC_ML_CP<2>TRUE TRUENC_DP_TBTSRC_ML_CN<2>TRUE TRUE

TRUE NC_DP_TBTSRC_ML_CP<0>TRUE

TRUE NC_DP_TBTSRC_ML_CN<0>TRUE

NC_DP_TBTSRC_ML_CP<1>TRUE TRUENC_DP_TBTSRC_ML_CN<1>TRUE TRUE

NC_DP_TBTSRC_AUXCH_CPTRUE TRUENC_DP_TBTSRC_AUXCH_CNTRUE TRUENC_DP_TBTSRC_AUXCH_CN

NC_DP_TBTSRC_AUXCH_CP

NC_DP_TBTSRC_ML_CN<1>NC_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<0>TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CN<2>TP_DP_TBTSRC_ML_CP<2>TP_DP_TBTSRC_ML_CN<3>TP_DP_TBTSRC_ML_CP<3>

TRUE PP3V3_S4TRUE PPDCIN_G3H_ISOL

TRUE PPVCC_S0_CPU

PP1V05_S0TRUE

ODD_PWR_EN_L

SMBUS_SMC_5_G3_SDATRUE

ENET_LOW_PWRAUD_IP_PERIPHERAL_DETAUD_I2C_INT_L

PPVRTC_G3HTRUE

TRUE PPDCIN_G3H

TRUE PPBUS_S5_HS_OTHER_ISNSTRUE PP1V05_TBTCIO

TRUE LED_RETURN_6TRUE LED_RETURN_5

TRUE LED_RETURN_3

TRUE PP1V05_TBTLCTRUE PP3V3_TBTLCTRUE PP15V_TBT

TRUE PP3V3_S3

TRUE PP3V3_S5

SMC_RX_LTRUE

TRUE SMC_ROMBOOTTRUE SMC_RESET_LTRUE SMC_TCKTRUE SMC_TDITRUE LPC_PWRDWN_L

TRUE SPI_ALT_CS_LTRUE LPC_SERIRQ

TRUE SPI_ALT_CLK

TRUE SPIROM_USE_MLBTRUE PM_CLKRUN_L

SPI_ALT_MISOTRUE

TRUE LPC_FRAME_L

TRUE SMC_TX_LTP_SMC_MD1TRUE

LPC_CLK24M_LPCPLUSTRUE

TRUE PP3V42_G3H

TRUE PP5V_S3RS0_ALSCAM_FTRUE I2C_CAM_SDATRUE I2C_CAM_SCK

TRUE SMBUS_SMC_1_S0_SDATRUE SMBUS_SMC_1_S0_SCL

TRUE MIPI_DATA_CONN_PMIPI_DATA_CONN_NTRUE

TRUE PCIE_CLK100M_SSD_PTRUE PCIE_CLK100M_SSD_N

SSD_CLKREQ_CONN_LTRUE

TRUE SSD_RESET_CONN_L

TRUE SMC_OOB1_D2R_CONN_LTRUE SSD_PCIE_SEL_L

SSD_DEVSLPTRUESSD_PWRFAIL_WARN_LTRUE

TRUE PCIE_SSD_D2R_P<3..0>

TRUE CAM_SENSOR_WAKE_L_CONN

TRUE MIPI_CLK_CONN_NTRUE MIPI_CLK_CONN_P

TRUE WIFI_EVENT_L

TRUE PCIE_AP_R2D_PTRUE PCIE_CLK100M_AP_N

TRUE PP3V3_WLAN

TRUE PP3V3_S0SW_SSD_FLT

TRUE PCIE_AP_D2R_PPCIE_AP_D2R_NTRUE

TRUE PCIE_SSD_R2D_N<3..0>

I2C_TCON_SCL_RTRUE

TRUE DP_INT_AUX_CH_C_N

NC_BDV_BKL_PWM TRUETRUE NC_BDV_BKL_PWMNC_SMBUS_SMC_4_ASF_SDANC_SMBUS_SMC_4_ASF_SCL TRUETRUE NC_SMBUS_SMC_4_ASF_SCL

TRUETRUE NC_SMC_T25_EN_LNC_SMC_DP_HPD_L TRUE NC_SMC_DP_HPD_LTRUE

NC_SMC_MPM5_LED_CHG TRUETRUE NC_SMC_MPM5_LED_CHGNC_SMC_MPM5_LED_PWR TRUE NC_SMC_MPM5_LED_PWRTRUE

TRUETRUE NC_ENET_ASF_GPIO

NC_SMC_FAN_1_TACH NC_SMC_FAN_1_TACHTRUETRUENC_SMC_FAN_5_CTL NC_SMC_FAN_5_CTLTRUETRUE

NC_SMC_FAN_1_CTLTRUE TRUE

NC_SMC_GFX_THROTTLE_L NC_SMC_GFX_THROTTLE_LTRUETRUE

NC_SMC_GFX_OVERTEMP NC_SMC_GFX_OVERTEMPTRUE TRUE

NC_USB_SMCN NC_USB_SMCNTRUE TRUE

NC_USB_SMCP NC_USB_SMCPTRUE TRUE

NC_IR_RX_OUT_RC TRUE TRUE NC_IR_RX_OUT_RCNC_SMC_SYS_LED TRUE TRUE NC_SMC_SYS_LED

TRUE TRUE NC_CLINK_RESET_LNC_CLINK_DATATRUE TRUE

NC_CLINK_CLK TRUE TRUE NC_CLINK_CLKTRUE TRUE NC_PCI_PME_L

NC_HDA_SDIN1 TRUE TRUE NC_HDA_SDIN1DP_INT_ML_C_N<3..1> NC_INT_ML_CN<3..1>TRUE TRUE

NC_USB_SDN TRUE TRUE NC_USB_SDNDP_INT_ML_C_P<3..1> NC_INT_ML_CP<3..1>TRUETRUE

NC_USB_SDP TRUE TRUE NC_USB_SDPNC_USB_CAMERAN TRUE TRUE NC_USB_CAMERANNC_USB_CAMERAP TRUE NC_USB_CAMERAPTRUE

NC_USB_IRP TRUE TRUE NC_USB_IRPNC_USB_IRN TRUE TRUE NC_USB_IRN

NC_PCIE_FW_R2D_CN NC_PCIE_FW_R2D_CNTRUE TRUE

NC_PCIE_FW_R2D_CP TRUE TRUE NC_PCIE_FW_R2D_CP

NC_PCIE_FW_D2RP NC_PCIE_FW_D2RPTRUE TRUENC_PCIE_FW_D2RN NC_PCIE_FW_D2RNTRUETRUE

NC_PCIE_CLK100M_FWN TRUE TRUE NC_PCIE_CLK100M_FWNNC_PCIE_CLK100M_FWP TRUE TRUE NC_PCIE_CLK100M_FWPNC_PCIE_CLK100M_SDN TRUE TRUE NC_PCIE_CLK100M_SDNNC_PCIE_CLK100M_SDP TRUE TRUE NC_PCIE_CLK100M_SDP

TRUE DP_INT_ML_P<0>TRUE DP_INT_ML_N<0>

TRUE PPHV_S0SW_LCDBKLT

LED_RETURN_2TRUE

DP_INT_HPD_CONNTRUE

TRUE PP3V3_S0SW_LCD_UF

SMC_ONOFF_LTRUE

TRUE PP3V42_G3H

TRUE SPKRAMP_ROUT_NSPKRAMP_ROUT_PTRUE

TRUE PP5V_S4RS3

SMBUS_SMC_5_G3_SCLTRUE

FAN_RT_PWMTRUE

FAN_RT_TACHTRUE

TRUE TPAD_USB_IF_EN_CONN

TRUE TPAD_SPI_INT_S4_WAKE_L_CONNTRUE PP5V_S4_IPD

PP3V42_G3HTRUE

TRUE PPBUS_S5_HS_COMPUTING_ISNS

TRUE PPBUS_G3H

TRUE PP3V3_S0

TRUE PP1V5_S0

TRUE PP3V3_SUS

TRUE PP3V3_S0SW_SSD

TRUETRUE NC_SMBUS_SMC_4_ASF_SDA

NC_ENET_ASF_GPIO

NC_SMC_FAN_1_CTL

NC_CLINK_RESET_LNC_CLINK_DATA

NC_PCI_PME_L

NC_SMC_T25_EN_L

TRUE TRUE NC_TBT_B_R2D_CN<1..0>TBT_B_R2D_C_N<1..0>TRUE TRUE NC_TBT_B_D2RP<1..0>TBT_B_D2R_P<1..0>

TRUE TRUE NC_TBT_B_R2D_CP<1..0>TBT_B_R2D_C_P<1..0>

TRUE TRUE NC_TBT_B_D2RN<1..0>TBT_B_D2R_N<1..0>TRUE TRUE NC_TBT_B_LSTXNC_TBT_B_LSTXTRUE TRUE NC_DP_TBTPB_ML_CP<3..1:2>NC_DP_TBTPB_ML_CP<3..1:2>

TRUE TRUE NC_DP_TBTPB_AUXCH_CPNC_DP_TBTPB_AUXCH_CPTRUE TRUE NC_DP_TBTPB_ML_CN<3..1:2>NC_DP_TBTPB_ML_CN<3..1:2>

NC_DP_TBTPB_AUXCH_CNTRUE TRUENC_DP_TBTPB_AUXCH_CN

TRUE PPVIN_S4SW_TBTBST_FET

HDD_PWR_EN

AUD_IPHS_SWITCH_EN

FW_PME_L

BT_PWRRST_LWOL_EN

ENET_MEDIA_SENSELCD_PSR_ENLCD_IRQ_L

FW_PWR_ENHDMITBTMUX_FLAG_L

TRUE PPVBAT_G3H_CONN

SMC_OOB1_R2D_CONN_LTRUE

TRUE PP3V3_S0TRUE PCIE_SSD_R2D_P<3..0>

PP5V_S0TRUE

SMC_LSOC_RST_LTRUE

AP_CLKREQ_Q_LTRUE

TRUE PCIE_WAKE_L

TRUE TPAD_SPI_IF_EN_CONN

SMC_LIDTRUE

TRUE TPAD_SPI_MISO_RTRUE USB_TPAD_P

TRUE TPAD_SPI_CLK_RTRUE TPAD_WAKE_LTRUE TPAD_SPI_MOSI_RTRUE PP3V3_S4_IPDTRUE TPAD_SPI_CS_R_L

TRUE USB_TPAD_N

TRUE PCIE_AP_R2D_N

TRUE PP3V3_S4TRUE USB_BT_CONN_NTRUE USB_BT_CONN_P

TRUE PPDCIN_G3H

<BRANCH>

<SCH_NUM>

<E4LABEL>

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31 32

14 32 37 40 43 44 69 73

14 32 37 40 43 44 69 73

32 72

32 72

12 30 67

12 30 67

30

30

30

16 30

15 30

12 30 67

32

32 72

32 72

29 37 38

29 69

12 29 69

29 37 38 39 41

30

14 29 69

14 29 69

30 67

60

60 67

37 64 37 64

37 64

37 64 37 64

37 64

37 64 37 64

64 64

64 64

64

37 64 37 64

37 64 37 64

37 64

37 64 37 64

37 64 37 64

64 64

64 64

64 64

37 64 37 64

14 64

14 64

14 64 14 64

13 64

12 64 12 64

67 5

14 64 14 64

67 5

14 64 14 64

14 64 14 64

14 64 14 64

14 64 14 64

14 64 14 64

14 64 14 64

14 64 14 64

14 64 14 64

14 64 14 64

12 64 12 64

12 64 12 64

64 64

64 64

60 67

60 67

56 60 62

56 60

60

60

36 37 38

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

47 74

47 74

32 35 47 49 54 55 58 62

37 40 48 50 73

45

45

36

36

36

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

41 51 52 53 55 62

27 41 42 49 50 56 62

8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65 74

8 57 58 59 62

8 11 14 18 46 57 58 59 62

30 41 62

37 64

64

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14 64

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25 71

25 71

25 71

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25 64 25 64

64 71 64 71

25 64 71 25 64 71

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25 64 71

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13

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15

14

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42 43 44 45 56 59 61

62 64 65 74

30 67

16 17 32 45 46 51 52 56 58 59 61 62 64

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29

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36 37 38 61 65

36

14 36 68

36

36

36

36

36

14 36 68

29 69

29 33 36 38 39 58 62 64

29 68

29 68

49 50 62 64

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FUNC_TEST

Bead Probes

J9500: LIO Connector MAKE_BASE

SD Card Aliases

(MAKE_BASE=TRUE on page 45)

Functional Test Points

1 BPA522BEAD-PROBE

1 BPA523BEAD-PROBE

1 BPA512BEAD-PROBE

1 BPA521BEAD-PROBE1 BPA513BEAD-PROBE

1 BPA520BEAD-PROBE

1 BPA510BEAD-PROBE

1 BPA511BEAD-PROBE

Project FCT/NC/AliasesSYNC_DATE=09/13/2012SYNC_MASTER=J41_MLB

SYS_ONEWIRETRUE

TRUE SMC_lID

TRUE USB_EXTB_N

PP3V3_S0SW_SD

USB3_SD_R2D_C_NTRUE

USB3_SD_R2D_C_PTRUE

TRUE USB3_SD_D2R_NTRUE USB3_SD_D2R_P

PP3V3_S0SW_SD

USB3_SD_R2D_C_N

USB3_SD_D2R_PUSB3_SD_D2R_NUSB3_SD_R2D_C_P

TRUE USB3_EXTB_R2D_N

PP3V42_G3HTRUE

USB3_EXTB_D2R_NUSB3_EXTB_D2R_PUSB3_EXTB_D2R_RC_NUSB3_EXTB_D2R_RC_PUSB3_EXTB_R2D_C_N

USB3_EXTB_R2D_P

USB3_EXTB_R2D_C_PUSB3_EXTB_R2D_N

TRUE PP1V5_S0SW_AUDIOPP3V3_S0TRUE

TRUE SPKRAMP_SHDN_LSMBUS_SMC_2_S3_SCLTRUE

SMBUS_SMC_2_S3_SDATRUE

USB_PWR_ENTRUE

SMC_BC_ACOKTRUE

TRUE SPKRAMP_INR_NFINSTACKSNS_ALERT_LTRUE

SPKRAMP_INR_PTRUE

USB_EXTB_PTRUE

TRUE PP5V_S0_ALT_AUD_LDO_EN

HDA_SDOUTTRUE

HDA_SDIN0TRUE

TRUE HDA_BIT_CLK

TRUE HDA_RST_LTRUE XDP_USB_EXTB_OC_L

TRUE HDA_SYNC

USB3_EXTB_D2R_RC_NTRUE

USB3_EXTB_D2R_RC_PTRUE

TRUE USB3_EXTB_R2D_P

TRUE AUD_PWR_EN

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35 59 61

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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

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TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD

AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM















TABLE_SPACING_ASSIGNMENT_ITEM



TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS

































Spacing ConstraintsSingle-ended Physical Constraints

Differential Pair Physical Constraints

J41/J43 Board-Specific Spacing & Physical Constraints

100 MM100 MMN* =STANDARD =STANDARD=STANDARD50_OHM_SE

=STANDARD55_OHM_SE =STANDARD* N 100 MM 100 MM =STANDARD

70_OHM_DIFF ISL3,ISL10 Y 0.105 MM 0.100 MM 0.100 MM0.105 MM

Y70_OHM_DIFF ISL2,ISL11 0.105 MM 0.105 MM 0.100 MM 0.100 MM

ISL4,ISL9 Y70_OHM_DIFF 0.110MM 0.095 MM 0.095 MM0.110 MM

=STANDARD=STANDARD* N70_OHM_DIFF =STANDARD100 MM100 MM

80_OHM_DIFF Y 0.132 MM 0.130 MM 0.130 MMTOP,BOTTOM 0.132 MM

YISL3,ISL1090_OHM_DIFF 0.070 MM 0.070 MM 0.180 MM 0.180 MM

N =STANDARD =STANDARD =STANDARD100 MM*90_OHM_DIFF 100 MM

YISL4,ISL990_OHM_DIFF 0.180 MM0.180 MM0.076 MM 0.076 MM

Y70_OHM_DIFF TOP,BOTTOM 0.165 MM 0.165 MM 0.110 MM 0.110 MM

0.110 MM50_OHM_SE YTOP,BOTTOM 0.110 MM

YISL3,ISL1045_OHM_SE 0.075 MM0.075 MM

0.125 MM35_OHM_SE Y 0.125 MMISL2,ISL11

0.182 MM 0.182 MMISL4,ISL9 Y27P4_OHM_SE

35_OHM_SE TOP,BOTTOM Y 0.195 MM0.195 MM

N27P4_OHM_SE * 100 MM 100 MM =STANDARD=STANDARD=STANDARD

0.182 MM0.182 MMYISL3,ISL1027P4_OHM_SE

0.182 MM 0.182 MMY27P4_OHM_SE ISL2,ISL11

DEFAULT ISL3,ISL10 Y =45_OHM_SE =45_OHM_SE

ISL2,ISL11DEFAULT Y =45_OHM_SE =45_OHM_SE

TOP,BOTTOM =50_OHM_SEDEFAULT =50_OHM_SEY

16.2MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA,MEM_TERM

0.135 MMTOP,BOTTOM Y45_OHM_SE 0.135 MM

0 MM10 MM100 MM 100 MMN*DEFAULT 0 MM

BGA BGA_P075MM**

0.075 MMBGA_P075MM * ?

Y27P4_OHM_SE 0.310 MM0.310 MMTOP,BOTTOM

STANDARD * =DEFAULT ?

0.099 MM40_OHM_SE YISL4,ISL9 0.099 MM

=DEFAULT =DEFAULTSTANDARD * =DEFAULT =DEFAULT =DEFAULT=DEFAULT

0.100 MM1:1_SPACING * ?

* 0.090 MM ?1x_DIELECTRIC

DEFAULT * 0.1 MM ?

1x_DIELECTRIC ISL4,ISL9 0.050 MM ?

0.053 MMISL3,ISL10 ?1x_DIELECTRIC

0.071 MM1x_DIELECTRIC TOP,BOTTOM ?

P070MM_BGABGA*

ISL4,ISL9 Y =45_OHM_SE =45_OHM_SEDEFAULT

ISL2,ISL11 Y45_OHM_SE 0.075 MM0.075 MM

0.106 MM0.106 MM73_OHM_DIFF 0.150 MM0.150 MMISL2,ISL11 Y


73_OHM_DIFF =STANDARD=STANDARD=STANDARD* N 100 MM100 MM

0.165 MM0.165 MM73_OHM_DIFF YTOP,BOTTOM 0.150 MM 0.150 MM

0.150 MM0.150 MMYTOP,BOTTOM85_OHM_DIFF 0.120 MM 0.120 MM


ISL3,ISL10 Y85_OHM_DIFF 0.078 MM 0.078 MM 0.160 MM 0.160 MM


N* =STANDARD =STANDARD =STANDARD85_OHM_DIFF 100 MM 100 MM

0.096 MMISL2,ISL11 Y40_OHM_SE 0.096 MM

YISL2,ISL1190_OHM_DIFF 0.070 MM0.070 MM 0.180 MM 0.180 MM

TOP,BOTTOM Y90_OHM_DIFF 0.200 MM 0.200 MM0.115 MM 0.115 MM


0.090 MMTOP,BOTTOM Y 0.090 MM55_OHM_SE

0.170 MMTOP,BOTTOM Y40_OHM_SE 0.170 MM

100 MMN* =STANDARD =STANDARD40_OHM_SE =STANDARD100 MM

P070MM_BGA 5 MM 0.075 MM0.070 MM*

YISL3,ISL10 0.125 MM 0.125 MM35_OHM_SE

YISL4,ISL935_OHM_SE 0.125 MM0.125 MM

100 MMN*35_OHM_SE 100 MM =STANDARD =STANDARD=STANDARD

0.096 MM 0.096 MMY40_OHM_SE ISL3,ISL10

0.080 MMYISL4,ISL945_OHM_SE 0.080 MM

100 MM100 MMN* =STANDARD45_OHM_SE =STANDARD=STANDARD

PCB Rule DefinitionsSYNC_DATE=10/24/2012SYNC_MASTER=CONSTRAINTS

=STANDARD100 MM80_OHM_DIFF =STANDARD=STANDARD* N 100 MM

80_OHM_DIFF ISL4,ISL9 Y 0.088 MM 0.088 MM 0.110 MM 0.110 MM

80_OHM_DIFF ISL3,ISL10 Y 0.081 MM 0.081 MM 0.115 MM 0.115 MM

ISL2,ISL1180_OHM_DIFF 0.081 MM 0.081 MM 0.115 MM 0.115 MMY

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PCI-Express Interface Constraints

PCIe SSD

SPACING

NET_TYPE

PHYSICALELECTRICAL_CONSTRAINT_SET

CPU Net Properties

DPNote: DisplayPort tables are on Page 113

once rdar://10308147 is resolved

back to TABLE_SPACING_RULE

Note: CPU_8MIL and CPU_ITP can be converted

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

PCH PCIE Spacing

PCIE Clock Spacing

CPU Signal Constraints

CPU PCIE Spacing

(FSB_CPURST_L)

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I214

I215

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF*PCIE_80D =80_OHM_DIFF=80_OHM_DIFF

* * CPU_COMP_2OTHERCPU_COMP

CPU_COMP_2SELF*CPU_COMPCPU_COMP

* * CPU_ITP_2ANYCPU_ITP

CPU_VCCSENSE_2OTHER ?TOP,BOTTOM =10x_DIELECTRIC

PCIE_RX2RX =5x_DIELECTRIC ?TOP,BOTTOM

TOP,BOTTOMCPU_COMP_2OTHER ?=10x_DIELECTRIC

CPU_COMP_2SELF ?TOP,BOTTOM =6x_DIELECTRIC

CPU_VCCSENSE_2SELF =4x_DIELECTRIC* ?

CPU_VCCSENSE_2OTHER =6x_DIELECTRIC* ?

CLK_PCIE_2SELF =6x_DIELECTRIC ?TOP,BOTTOM

?*CPU_AGTL =STANDARD

=4x_DIELECTRIC* ?CPU_COMP_2SELF

=6x_DIELECTRIC* ?CPU_COMP_2OTHER

?TOP,BOTTOM =6x_DIELECTRICCPU_VCCSENSE_2SELF

=6x_DIELECTRIC* ?CLK_PCIE_2OTHER

CPU_VCCSENSE_2OTHER* *CPU_VCCSENSE

PCIE_TX2RX**_CPU_RXPCIE_CPU_TX

* PCIE_RX2TXPCIE_CPU_RX *_CPU_TX

PCIE_CPU_TX *_TX * PCIE_2OTHERHS

CPU_VCCSENSE CPU_VCCSENSE_2SELF*CPU_VCCSENSE

=27P4_OHM_SE 0.100 MM*CPU_27P4S =27P4_OHM_SE =27P4_OHM_SE 0.100 MM=27P4_OHM_SE

*CLK_PCIE * CLK_PCIE_2OTHER

*PCIE_RX2TX ?=6x_DIELECTRIC

=3x_DIELECTRIC* ?PCIE_2OTHER

PCIE_CPU_TX * PCIE_TX2TXPCIE_CPU_TX

PCIE_CPU_RX * PCIE_RX2RXPCIE_CPU_RX

*_CPU_RX PCIE_RX2OTHERRX*PCIE_CPU_RX

*_CPU_TXPCIE_CPU_TX * PCIE_TX2OTHERTX

PCIE_2OTHERHSPCIE_CPU_RX *_TX *

PCIE_CPU_RX * PCIE_2OTHERHS*_RX

PCIE_CPU_RX * PCIE_2OTHER*

PCIE_PCH_RX * * PCIE_2OTHER

PCIE_PCH_TX * PCIE_2OTHER*

*_RX * PCIE_2OTHERHSPCIE_PCH_RX

*_PCH_TX * PCIE_RX2TXPCIE_PCH_RX

*_PCH_RX * PCIE_TX2RXPCIE_PCH_TX

PCIE_PCH_TX PCIE_2OTHERHS**_TX

PCIE_PCH_RX * PCIE_2OTHERHS*_TX

PCIE_2OTHERHS*_RX *PCIE_PCH_TX

PCIE_PCH_RX * PCIE_RX2OTHERRX*_PCH_RX

*PCIE_PCH_TX *_PCH_TX PCIE_TX2OTHERTX

PCIE_RX2RX*PCIE_PCH_RX PCIE_PCH_RX

PCIE_PCH_TXPCIE_PCH_TX * PCIE_TX2TX

PCIE_TX2TX TOP,BOTTOM =5x_DIELECTRIC ?

PCIE_TX2OTHERTX ?TOP,BOTTOM =5x_DIELECTRIC

PCIE_RX2TX TOP,BOTTOM ?=7x_DIELECTRIC

PCIE_2OTHERHS TOP,BOTTOM ?=6x_DIELECTRIC

TOP,BOTTOMPCIE_2OTHER =5x_DIELECTRIC ?

?PCIE_TX2TX =2.5x_DIELECTRIC*

=2.5x_DIELECTRICPCIE_RX2RX ?*

=4x_DIELECTRICPCIE_TX2OTHERTX * ?

?*PCIE_TX2RX =6x_DIELECTRIC

CLK_PCIE_2OTHER =10x_DIELECTRIC ?TOP,BOTTOM

*CLK_PCIE CLK_PCIE CLK_PCIE_2SELF

PCIE_TX2RX ?=7x_DIELECTRICTOP,BOTTOM

PCIE_RX2OTHERRX =4x_DIELECTRIC* ?

?* =4x_DIELECTRICPCIE_2OTHERHS

=4x_DIELECTRIC* ?CPU_ITP_2ANY

CPU_8MIL_2ANY ?8 MIL*

CLK_PCIE_2SELF * ?=4x_DIELECTRIC

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFFCLK_PCIE_80D * =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

=45_OHM_SE* =STANDARDCPU_45S =45_OHM_SE=45_OHM_SE =45_OHM_SE =STANDARD

?=2x_DIELECTRICCPU_AGTL TOP,BOTTOM

CPU_8MIL CPU_8MIL_2ANY**

*PCIE_CPU_TX *_RX PCIE_2OTHERHS

PCIE_CPU_TX ** PCIE_2OTHER

PCIE_RX2OTHERRX ?TOP,BOTTOM =5x_DIELECTRIC

SYNC_MASTER=CONSTRAINTS

CPU ConstraintsSYNC_DATE=09/25/2012

DMI_CLK100M_CPU_NCLK_PCIECLK_PCIE_80DDMI_CLK100M

DPLL_REF_CLKNCLK_PCIEDPLL_REF_CLK120M CLK_PCIE_80DITPCPU_CLK100M_PITPCPU_CLK100M CLK_PCIE_80D CLK_PCIE

CLK_PCIEITPCPU_CLK100M CLK_PCIE_80D ITPXDP_CLK100M_P

CPU_CFG<15..12>CPU_ITPCPU_45S

XDP_CPU_CLK100M_NCLK_PCIEITPCPU_CLK100M CLK_PCIE_80DXDP_CPU_TDICPU_45S CPU_ITPXDP_TDI

CPU_VCCSENSE_NSENSE_1TO1_P2MMCPU_VCCSENSE CPU_VCCSENSE

CPU_AXG_SENSE_PCPU_VCCSENSECPU_AXG_SENSE SENSE_1TO1_P2MMCPU_AXG_SENSE_NCPU_AXG_SENSE CPU_VCCSENSESENSE_1TO1_P2MM

CPU_27P4SCPU_VALSENSE CPU_VCCSENSE CPU_AXG_VALSENSE_N

PCIE_CPU_SSD_R2D PCIE_80D PCIE_CPU_TX PCIE_SSD_R2D_C_P<3..0>

CPU_COMPCPU_45SCPU_SVIDSOUT CPU_VIDSOUT

CPU_27P4SCPU_VALSENSE CPU_VCCSENSE CPU_VCC_VALSENSE_NCPU_VALSENSE CPU_VCCSENSECPU_27P4S CPU_VCC_VALSENSE_P

XDP_CPURST_LCPU_ITPCPU_45S

CPU_27P4S CPU_VCCSENSECPU_VALSENSE CPU_VDDQ_SENSE_N

CPU_ITPCPU_45S XDP_BPM_L<7..2>CPU_ITPXDP_BPM_L XDP_BPM_L<1..0>CPU_45S

XDP_OBSDATA_B<3..0>CPU_ITPCPU_45S

CPU_VCCIOSENSE_NCPU_VCCSENSECPU_VCCIOSENSE SENSE_1TO1_P2MM

CPU_VDDQ_SENSE_PCPU_27P4SCPU_VALSENSE CPU_VCCSENSE

PCIE_CPU_SSD_R2D PCIE_CPU_TXPCIE_80D PCIE_SSD_R2D_C_N<3..0>

CPU_COMPCPU_45SCPU_SVIDSCLK CPU_VIDSCLK

CPU_VCCIOSENSE_PCPU_VCCIOSENSE CPU_VCCSENSESENSE_1TO1_P2MM

XDP_CPUPCH_TRST_LXDP_TRST_L CPU_45S CPU_ITP

CLK_PCIEITPCPU_CLK100M CLK_PCIE_80D ITPCPU_CLK100M_N

CPU_VCCSENSE_PSENSE_1TO1_P2MM CPU_VCCSENSECPU_VCCSENSE

CLK_PCIE ITPXDP_CLK100M_NITPCPU_CLK100M CLK_PCIE_80D

CLK_PCIE_80D DMI_CLK100M_CPU_PCLK_PCIEDMI_CLK100M

PM_THRMTRIP_LCPU_8MILPM_THRMTRIP_L CPU_45S

CPU_PWRGDCPU_AGTLCPU_PWRGD CPU_45S

CPU_PROCHOT_LCPU_AGTLCPU_PROCHOT_L CPU_45S

CPU_VCCIO_SELCPU_AGTLCPU_45S

CPU_CATERR_LCPU_AGTLCPU_CATERR_L CPU_45S

CPU_CFG<11..0>CPU_ITPCPU_45S

CPU_SM_RCOMP<2>CPU_COMPCPU_SM_RCOMP CPU_27P4S

CPU_COMP CPU_SM_RCOMP<1>CPU_27P4SCPU_SM_RCOMP

CPU_SM_RCOMP<0>CPU_COMPCPU_SM_RCOMP CPU_27P4S

CPU_PEG_COMPCPU_27P4S CPU_COMP

EDP_COMPCPU_27P4S CPU_COMP

XDP_CPU_PREQ_LCPU_45S CPU_ITP

XDP_CPU_PRDY_LCPU_45S CPU_ITP

XDP_DBRESET_LCPU_ITPCPU_45S

PM_SYNCCPU_AGTLPM_SYNC CPU_45SPM_MEM_PWRGDCPU_AGTLPM_MEM_PWRGD CPU_45S

CPU_PECICPU_45S CPU_COMPCPU_PECI

PCIE_SSD_R2D_N<3..0>PCIE_80D PCIE_CPU_TX

PCIE_CPU_TXPCIE_80D PCIE_SSD_R2D_P<3..0>

XDP_CPU_TMSCPU_45S CPU_ITPXDP_TMSXDP_CPU_TCKXDP_TCK CPU_45S CPU_ITP

XDP_CPU_TDOCPU_ITPXDP_TDO CPU_45S

XDP_CPU_CLK100M_PCLK_PCIEITPCPU_CLK100M CLK_PCIE_80D

DPLL_REF_CLKPCLK_PCIEDPLL_REF_CLK120M CLK_PCIE_80D

PCIE_CLK100M_SSD_NPCIE_CLK100M_SSD CLK_PCIE_80D CLK_PCIE

PCIE_CLK100M_SSD PCIE_CLK100M_SSD_PCLK_PCIE_80D CLK_PCIE

PCIE_SSD_D2R_N<3..0>PCIE_CPU_SSD_D2R PCIE_CPU_RXPCIE_80D

PCIE_SSD_D2R_P<3..0>PCIE_CPU_SSD_D2R PCIE_CPU_RXPCIE_80D

PCIE_SSD_D2R_C_N<3..0>PCIE_80D PCIE_CPU_RX

PCIE_SSD_D2R_C_P<3..0>PCIE_80D PCIE_CPU_RX

DP_80D DP_AUX DP_INT_AUXCH_N

CPU_COMPCPU_SVIDALERT_L CPU_45S CPU_VIDALERT_L

CPU_AXG_VALSENSE_PCPU_VCCSENSECPU_VALSENSE CPU_27P4S

DP_80DDP_TBT_ML DP_TBTSNK0_ML_P<3..0>DP_TX

DP_80D DP_TBTSNK0_ML_C_N<3..0>DP_TX

DP_80DDP_TBT_ML DP_TBTSNK0_ML_N<3..0>DP_TX

DP_80D DP_TBTSNK0_ML_C_P<3..0>DP_TX

DP_80D DP_TBTSNK0_AUXCH_NDP_TBT_AUXCH DP_AUX

DP_80D DP_TBTSNK0_AUXCH_PDP_TBT_AUXCH DP_AUX

DP_80D DP_TBTSNK0_AUXCH_C_PDP_AUX

DP_80D DP_TBTSNK0_AUXCH_C_NDP_AUX

DP_TBTSNK1_ML_N<3..0>DP_80DDP_TBT_ML DP_TX

DP_TBTSNK1_ML_P<3..0>DP_80DDP_TBT_ML DP_TX

DP_80D DP_TBTSNK1_AUXCH_PDP_TBT_AUXCH DP_AUX

DP_TBTSNK1_ML_C_P<3..0>DP_80D DP_TXDP_TBTSNK1_ML_C_N<3..0>DP_80D DP_TX

DP_80D DP_TBTSNK1_AUXCH_C_PDP_AUX

DP_TBT_AUXCH DP_80D DP_TBTSNK1_AUXCH_NDP_AUX

DP_80D DP_TBTSNK1_AUXCH_C_NDP_AUX

DP_INT_ML_P<3..0>DP_TXDP_80DDP_INT_MLDP_INT_ML_N<3..0>DP_TXDP_80DDP_INT_MLDP_INT_ML_C_P<3..0>DP_TXDP_80DDP_INT_ML_C_N<3..0>DP_TXDP_80D

DP_INT_AUX_CH_C_NDP_AUXDP_80DDP_INT_AUXCH

DP_INT_AUXCH DP_INT_AUXCH_C_PDP_AUXDP_80D

DP_80D DP_AUX DP_INT_AUXCH_PDP_INT_AUXCH DP_80D DP_AUX DP_INT_AUXCH_C_N

DP_INT_AUX_CH_C_PDP_AUXDP_80DDP_INT_AUXCH

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8 51

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6

6 37 38 51

6 37

6 16 64

6

6

6

6 16 64

6 16 64

16 17

6 38

30 64

30 64

6 16 64

6 16 64

6 16 64

12 30 64

12 30 64

12 30 64

12 30 64

8 51

25

5 25

25

5 25

25

25

13 25

13 25

25

25

25

5 18 25

5 18 25

13 18 25

25

13 18 25

60 64

60 64

5 60 64

5 60 64

60 64

5 60

5 60

60 64

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TP SPI nets

UART Interface Constraints

USB Hucopyb nets

USB EXTA nets (Right USB port)

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB 2.0 Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 3.0 Interface Constraints

PCH Net Properties

PHYSICAL

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

SATA Interface Constraints

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB EXTB nets (Left USB port)

=45_OHM_SE=45_OHM_SE=45_OHM_SEUART_45S * =45_OHM_SE =45_OHM_SE=45_OHM_SE

SYNC_DATE=11/13/2012SYNC_MASTER=CLEAN_J43

PCH Constraints 1

* ?USB3_TX2TX =2.5x_DIELECTRICUSB3_2OTHERUSB3_PCH_TX **

USB3_PCH_RX **_RX USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_RX **

USB3_PCH_TX **_RX USB3_2OTHERHS

USB3_PCH_TX **_TX USB3_2OTHERHS

USB3_PCH_RX **_TX USB3_2OTHERHS

USB3_TX2RXUSB3_PCH_TX **_PCH_RX

USB3_RX2OTHERRXUSB3_PCH_RX **_PCH_RX

USB3_PCH_TX USB3_TX2OTHERTX**_PCH_TX

USB3_RX2TXUSB3_PCH_RX **_PCH_TX

USB3_TX2TXUSB3_PCH_TXUSB3_PCH_TX *

* ?USB3_2OTHERHS =4x_DIELECTRIC

* =3x_DIELECTRICUSB3_2OTHER ?

* =6x_DIELECTRIC ?USB3_RX2TX

* =4x_DIELECTRIC ?USB3_RX2OTHERRX

* =4x_DIELECTRIC ?USB3_TX2OTHERTX

* =6x_DIELECTRIC ?USB3_TX2RX

* =2.5x_DIELECTRIC ?USB3_RX2RX

TOP,BOTTOMUSB3_2OTHER ?=5x_DIELECTRIC

USB3_2OTHERHS =6x_DIELECTRIC ?TOP,BOTTOM

=7x_DIELECTRICUSB3_RX2TX ?TOP,BOTTOM

USB3_TX2RX TOP,BOTTOM ?=7x_DIELECTRIC

USB3_RX2OTHERRX ?=5x_DIELECTRICTOP,BOTTOM

TOP,BOTTOMUSB3_TX2OTHERTX ?=5x_DIELECTRIC

=5x_DIELECTRICUSB3_RX2RX ?TOP,BOTTOM

USB3_TX2TX ?=5x_DIELECTRICTOP,BOTTOM

?USB =4x_DIELECTRICTOP,BOTTOM

=4x_DIELECTRICSATA_ICOMP * ?

=80_OHM_DIFFSATA_80D =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFF

USB3_RX2RXUSB3_PCH_RXUSB3_PCH_RX *

?USB * =2x_DIELECTRIC

UART ?* =2x_DIELECTRIC

=80_OHM_DIFF =80_OHM_DIFF* =80_OHM_DIFFUSB_80D =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

=STANDARD* =STANDARD 8 MIL =STANDARD8 MILPCH_USB_RBIAS =STANDARD

USB USB_TPAD_M_PUSB_80DUSB_TPAD_M

USB USB_TPAD_M_NUSB_80DUSB_TPAD_M

USB_80D USB USB_SDCARD_PUSB_SDCARD

SPISPI_45S TPAD_SPI_CLK

USBUSB_EXTA USB_80D USB_EXTA_PUSB_EXTA USB_80D USB USB_EXTA_N

UART_45S SMC_DEBUGPRT_TX_LUART

USB2_EXTA USBUSB_80D USB2_EXTA_MUXED_NUSB2_EXTA USB_80D USB USB2_EXTA_MUXED_F_PUSB2_EXTA USBUSB_80D USB2_EXTA_MUXED_F_NUSB3_EXTA_RX USB_80D USB3_PCH_RX USB3_EXTA_D2R_PUSB3_EXTA_RX USB_80D USB3_EXTA_D2R_NUSB3_PCH_RX

USBUSB_80D TPAD_SPI_MOSI_USB_PUSBUSB_80D TPAD_SPI_MISO_USB_N

PCH_USB_RBIASPCH_USB_RBIAS PCH_USB_RBIAS

USB_80D USB USB_TPAD_CONN_P

USB2_EXTA USBUSB_80D USB2_EXTA_MUXED_P

SATA_ICOMPPCH_SATA_ICOMP PCH_SATAICOMP

USB_80DUSB_BT USB USB_BT_N

USB3_EXTA_TX USB_80D USB3_PCH_TX USB3_EXTA_R2D_P

USB3_PCH_RXUSB_80D USB3_EXTA_D2R_F_PUSB3_EXTA_D2R_F_NUSB_80D USB3_PCH_RX

PCIE_CLK100M_PCH_NPCH_DIFFCLK_UNUSED_ CLK_PCIECLK_PCIE_80D

USB USB_HUB_UP_PUSB_80DUSB_HUB1_UP

USBUSB_80D USB_BT_CONN_P

USBUSB_TPAD USB_80D USB_TPAD_N

USB USB_BT_PUSB_80DUSB_BT

USB3_EXTA_R2D_F_NUSB_80D USB3_PCH_TX

USB3_EXTB_R2D_PUSB3_EXTB_TX USB_80D USB3_PCH_TX

USB_80D USB3_PCH_TX USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_F_PUSB_80D USB3_PCH_TX

USB3_EXTA_TX USB3_PCH_TXUSB_80D USB3_EXTA_R2D_N

USB3_EXTA_R2D_C_NUSB_80D USB3_PCH_TX

USB3_EXTB_D2R_RC_NUSB3_PCH_RXUSB_80D

USB3_EXTB_D2R_PUSB_80D USB3_PCH_RXUSB3_EXTB_RX

USB_EXTB_PUSBUSB_80DUSB_EXTBUSB_EXTB_NUSB_80DUSB_EXTB USB

PCH_CLK14P3M_REFCLKCPU_45S CLK_PCIE

PCH_CLK100M_SATA_NPCH_DIFFCLK_UNUSED_ CLK_PCIECLK_PCIE_80D

PCH_CLK100M_SATA_PCLK_PCIE_80DPCH_DIFFCLK_UNUSED_ CLK_PCIE

PCH_CLK96M_DOT_NPCH_DIFFCLK_UNUSED_ CLK_PCIE_80D CLK_PCIE

PCH_CLK96M_DOT_PCLK_PCIE_80D CLK_PCIEPCH_DIFFCLK_UNUSED_

USB3_PCH_TX USB3_SD_R2D_NUSB_80D

USB_80D USB3_SD_D2R_C_NUSB3_PCH_RX

USB3_EXTB_R2D_C_PUSB_80D USB3_PCH_TX

USB3_EXTB_D2R_RC_PUSB3_PCH_RXUSB_80D

USB3_PCH_RXUSB_80DUSB3_EXTB_RX USB3_EXTB_D2R_N

USB3_EXTB_TX USB3_EXTB_R2D_NUSB3_PCH_TXUSB_80D

USB3_EXTB_R2D_C_NUSB3_PCH_TXUSB_80D

USB3_SD_RX USB3_SD_D2R_NUSB3_PCH_RXUSB_80D

USB3_SD_TX USB3_SD_R2D_C_NUSB3_PCH_TXUSB_80D

PCIE_CLK100M_PCH_PCLK_PCIECLK_PCIE_80DPCH_DIFFCLK_UNUSED_

USB3_SD_R2D_PUSB3_PCH_TXUSB_80D

USB_80D USB3_PCH_RX USB3_SD_D2R_C_P

USB3_SD_TX USB3_SD_R2D_C_PUSB3_PCH_TXUSB_80D

USB3_SD_RX USB3_SD_D2R_PUSB3_PCH_RXUSB_80D

USB_HUB_UP_NUSB_80D USBUSB_HUB1_UP

USBUSB_80D USB_BT_CONN_N

USB USB_BT_WAKE_NUSB_80D

USBUSB_TPAD USB_TPAD_PUSB_80D

UART_45S UART SMC_DEBUGPRT_RX_L

USB_80D USB USB_TPAD_CONN_N

SPISPI_45S TPAD_SPI_MISOTPAD_SPI_MOSISPI_45S SPI

USB_SDCARD USB_80D USB USB_SDCARD_N

USBUSB_80D USB_BT_WAKE_P

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14 61 65

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ELECTRICAL_CONSTRAINT_SET

SIO Signal Constraints



SMBus Interface Constraints

SPI Interface Constraints

XDP Constraints

LPC Bus Constraints

NOTE: 25MHz system clocks very sensitive to noise.

HD Audio Interface Constraints

PHYSICAL

NET_TYPE

System Clock Signal Constraints

DisplayPort

NET_TYPE

PCH Net Properties

SPACING

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET

Clock Net Properties

=4x_DIELECTRICDP_2OTHER TOP,BOTTOM ?

DP_2DP =3x_DIELECTRIC* ?

=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARDCLK_SLOW_45S =45_OHM_SE

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARDCLK_25M_45S

DP_2OTHERHS*_TXDP_TX *

DP_2OTHER ?* =3x_DIELECTRIC

=3x_DIELECTRIC ?*DP_AUX

=4x_DIELECTRICDP_2OTHERHS ?*

=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD=45_OHM_SE =STANDARDCLK_SLOW_45S

=45_OHM_SE =45_OHM_SE* =STANDARD =STANDARD=45_OHM_SE=45_OHM_SECLK_LPC_45S

* ?=3x_DIELECTRICLPC

?CLK_LPC * =4x_DIELECTRIC

* =5x_DIELECTRIC ?CLK_25M

LPC_45S =45_OHM_SE=45_OHM_SE =45_OHM_SE =45_OHM_SE* =STANDARD =STANDARD

SMB_45S_R_50S TOP,BOTTOM =50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

SMB * =2x_DIELECTRIC ?

* =2x_DIELECTRIC ?HDA

* ?CLK_SLOW =2x_DIELECTRIC

* ?=4x_DIELECTRICCLK_SLOW

*PCH_ITP ?=2:1_SPACING

*SPI ?=4x_DIELECTRIC

=45_OHM_SE =45_OHM_SE =STANDARD* =45_OHM_SEPCH_45S =45_OHM_SE =STANDARD

SMB_45S_R_50S =45_OHM_SE =45_OHM_SE =45_OHM_SE* =STANDARD=STANDARD=45_OHM_SE

=45_OHM_SESPI_45S * =STANDARD=STANDARD=45_OHM_SE =45_OHM_SE=45_OHM_SE

=80_OHM_DIFF=80_OHM_DIFFDP_80D =80_OHM_DIFF=80_OHM_DIFF* =80_OHM_DIFF=80_OHM_DIFF

*DP_TX DP_TX DP_2DP

DP_2OTHERHSDP_TX **_RX

DP_2OTHER*DP_TX *

=4x_DIELECTRICDP_AUX TOP,BOTTOM ?

=4x_DIELECTRICTOP,BOTTOM ?DP_2DP

=6x_DIELECTRICDP_2OTHERHS TOP,BOTTOM ?


PCH Constraints 2SYNC_MASTER=J41_MLB

=STANDARD=45_OHM_SE=45_OHM_SE=45_OHM_SEHDA_45S * =45_OHM_SE =STANDARD

CLK25M_CAM_CLKPCLK_25MCLK_25M_45S

CLK_25MCLK_25M_45S CLK25M_CAM_CLKN

CLK_25M_45S CLK_25M SDCLK_CLK25M_X2_RCLK_25M_45S CLK_25M SDSCLK_CLK25M_X1

SYSCLK_CLK32K_RTCX1CLK_SLOWCLK_SLOW_45SSYSCLK_CLK32K_RTC

CLK_25M SYSCLK_CLK25M_CAMERACLK_25M_45SSYSCLK_CLK25M_SB

CLK_25M_45S CLK_25M SDCLK_CLK25M_X2SYSCLK_CLK25M_X2_RCLK_25M_45S CLK_25M

CLK25M_CAM_XTALP_RCLK_25MCLK_25M_45S

CLK_25M_45S CLK25M_CAM_XTALPCLK_25MCLK25M_CAM_XTALNCLK_25MCLK_25M_45S

SYSCLK_CLK25M_TBTCLK_25M_45S CLK_25MSYSCLK_CLK25M_TBT

CLK_25M SYSCLK_CLK25M_TBT_RCLK_25M_45S

CLK_25M_45S CLK_25MSYSCLK_CLK25M_XTAL SYSCLK_CLK25M_X1CLK_25M_45S SYSCLK_CLK25M_X2CLK_25M

PM_CLK32K_SUSCLK_RPM_SUS_CLK CLK_SLOW_45S CLK_SLOWSMC_CLK32KCLK_SLOWCLK_SLOW_45SSPI_CLK_RSPI_45S SPISPI_CLK

SPISPI_45S SPI_CLKSPISPI_45SSPI_MOSI SPI_MOSI_RSPISPI_45S SPI_MOSI

SMB_45S_R_50S SMB SML_PCH_0_DATASMBUS_PCH_0_DATA

SMB_45S_R_50S SMB SMBUS_PCH_DATASMBUS_PCH_DATA

SMBSMB_45S_R_50S SMBUS_SMC_1_S0_SCLSMBUS_SMC_1_S0_SCL

LPC_CLK24M_SMCLPC_CLK33M CLK_LPCCLK_LPC_45S

HDA_45S HDA HDA_SDIN0HDA_SDIN0

HDA_SYNC HDAHDA_45S HDA_SYNC

HDA_RST_LHDAHDA_45S

HDA_45S HDA_RST_R_LHDA_RST_L HDA

HDA_45S HDA_SDOUT_RHDA

HDAHDA_45S HDA_SDOUTHDA_SDOUT

HDAHDA_45S HDA_SYNC_R

SMBUS_SMC_1_S0_SDA SMBSMB_45S_R_50S SMBUS_SMC_1_S0_SDA

SMB SML_PCH_0_CLKSMB_45S_R_50SSMBUS_PCH_0_CLK

HDAHDA_45S HDA_BIT_CLK_R

SMB_45S_R_50S SMBSMBUS_PCH_CLK SMBUS_PCH_CLK

CLK_LPC_45S CLK_LPC LPC_CLK24M_SMC_R

LPCPLUS_RESET_LLPC_45S LPC

LPC_FRAME_L LPC_45S LPC_FRAME_LLPC

LPC_AD LPC_45S LPC LPC_AD<3..0>

CLK_LPCCLK_LPC_45S LPC_CLK24M_LPCPLUS_RCLK_LPCLPC_CLK33M CLK_LPC_45S LPC_CLK24M_LPCPLUS

HDA_45SHDA_BIT_CLK HDA HDA_BIT_CLK

CLK_PCIE_80D PCIE_CLK100M_CAMERA_C_NCLK_PCIE

PCIE_CLK100M_CAM CLK_PCIE_80D PCIE_CLK100M_CAMERA_NCLK_PCIE

CLK_PCIE_80D PCIE_CLK100M_CAMERA_C_PCLK_PCIE

PCIE_CLK100M_CAM PCIE_CLK100M_CAMERA_PCLK_PCIE_80D CLK_PCIE

PCIE_CAMERA_D2R_C_PPCIE_80D PCIE_PCH_RX

PCIE_80D PCIE_PCH_RX PCIE_CAMERA_D2R_C_N

PCIE_CAM PCIE_80D PCIE_PCH_RX PCIE_CAMERA_D2R_PPCIE_CAM PCIE_CAMERA_D2R_NPCIE_80D PCIE_PCH_RX

PCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_C_NPCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_C_P

PCIE_CAM PCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_NPCIE_CAM PCIE_80D PCIE_PCH_TX PCIE_CAMERA_R2D_P

XDP_PCH_TCKPCH_45S PCH_ITPXDP_TCK

PCH_45S PCH_ITPXDP_TMS XDP_PCH_TMSXDP_TDO PCH_ITPPCH_45S XDP_PCH_TDOXDP_TDI PCH_45S PCH_ITP XDP_PCH_TDI

CLK_PCIE_80D CLK_PCIE PEG_CLK100M_NCLK_PCIE_80D PEG_CLK100M_PCLK_PCIE

PCIE_CLK100M_TBT CLK_PCIE_80D CLK_PCIE PCIE_CLK100M_TBT_PPCIE_CLK100M_TBT CLK_PCIECLK_PCIE_80D PCIE_CLK100M_TBT_N

PCIE_80D PCIE_PCH_RX PCIE_TBT_D2R_C_N<3..0>

PCIE_80DPCIE_TBT_D2R PCIE_PCH_RX PCIE_TBT_D2R_N<3..0>PCIE_PCH_RXPCIE_80D PCIE_TBT_D2R_C_P<3..0>

PCIE_PCH_RXPCIE_80D PCIE_TBT_D2R_P<3..0>PCIE_TBT_D2R

PCIE_80D PCIE_PCH_TX PCIE_TBT_R2D_C_N<3..0>PCIE_PCH_TX PCIE_TBT_R2D_C_P<3..0>PCIE_80D

PCIE_80D PCIE_PCH_TX PCIE_TBT_R2D_N<3..0>PCIE_TBT_R2D

PCIE_PCH_TXPCIE_80DPCIE_TBT_R2D PCIE_TBT_R2D_P<3..0>

CLK_PCIE_80D PCIE_CLK100M_AP_NPCIE_CLK100M_AP CLK_PCIE

CLK_PCIE_80D PCIE_CLK100M_AP_PCLK_PCIEPCIE_CLK100M_AP

PCIE_80DPCIE_AP_D2R PCIE_PCH_RX PCIE_AP_D2R_PPCIE_AP_D2R_NPCIE_80DPCIE_AP_D2R PCIE_PCH_RX

PCIE_80D PCIE_PCH_TX PCIE_AP_R2D_C_NPCIE_80D PCIE_AP_R2D_C_PPCIE_PCH_TX

PCIE_AP_R2D_NPCIE_PCH_TXPCIE_80DPCIE_AP_R2D

PCIE_PCH_TXPCIE_80DPCIE_AP_R2D PCIE_AP_R2D_P

SPISPI_45S SPI_MLB_CS_L

SPISPI_45S SPI_MLB_MOSISPISPI_45S SPI_MLB_MISO

SPI_45S SPI SPI_SMC_CS_LSPI_45S SPI SPI_MLB_CLK

SPI_SMC_MISOSPI_45S SPI

SPI_45S SPI SPI_SMC_MOSISPI_SMC_CLKSPI_45S SPI

SPI_CS0 SPI SPI_CS0_R_LSPI_45S

SPI_45S SPI_CS0_LSPI

SPI_MISOSPISPI_45SSPI_MISO

SPI_45S SPI SPI_MISO_R

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TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM

















































PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD




















Spacing Rule Sets

Memory Bus Constraints

Memory to GND Spacing

Memory to Power Spacing

Memory Bus Spacing Group Assignments

SPACING

Memory Net Properties

PHYSICALNET_TYPE


MEM_A_DATA_1 MEM_2OTHER* *


MEM_2OTHERMEM_A_DATA_3 * *



MEM_2OTHERMEM_A_DATA_6 * *

MEM_2OTHER**MEM_A_DATA_7

MEM_B_DATA_0 MEM_2OTHER* *



MEM_2OTHERMEM_B_DATA_3 * *



MEM_B_DATA_7 * MEM_2OTHER*

MEM_2OTHER*MEM_B_DATA_6 *

* MEM_2OTHERMEM_B_DQS_4 *

MEM_2OTHER**MEM_A_DQS_4

** MEM_2OTHERMEM_A_DQS_3

MEM_CLK * MEM_CLK2CLKMEM_CLK

*MEM_B_DQS_7 MEM_DQS2OWNDATAMEM_B_DATA_7

MEM_B_DQS_6 * MEM_DQS2OWNDATAMEM_B_DATA_6

MEM_*_DATA_* *MEM_* MEM_DATA2OTHERMEM

MEM_CTRL2CTRLMEM_CTRL *MEM_CTRL

** MEM_2OTHERMEM_B_DQS_6

MEM_50SMEM_TERMMEM_40S

MEM_73DMEM_TERMMEM_70D

*MEM_B_DQS_7 MEM_2OTHER*

MEM_A_DQS_7 *MEM_A_DATA_7 MEM_DQS2OWNDATA

MEM_A_DQS_6 *MEM_A_DATA_6 MEM_DQS2OWNDATA

MEM_A_DATA_5MEM_A_DQS_5 * MEM_DQS2OWNDATA

MEM_A_DATA_4MEM_A_DQS_4 * MEM_DQS2OWNDATA

* ?MEM_2OTHER =6x_DIELECTRIC

* DEFAULTMEM_PWR *

*MEM_*MEM_PWR MEM_2PWR

*GND MEM_* MEM_2GND

* MEM_DQS2OWNDATAMEM_A_DQS_2 MEM_A_DATA_2

MEM_CMD2CTRLMEM_CMD *MEM_CTRL

*MEM_CTRL * MEM_2OTHER

MEM_2OTHER*MEM_CMD *

=70_OHM_DIFF=70_OHM_DIFF*MEM_70D =70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF

=73_OHM_DIFF=73_OHM_DIFF=73_OHM_DIFF=73_OHM_DIFF=73_OHM_DIFFMEM_73D * =73_OHM_DIFF

=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SEMEM_50S *

=40_OHM_SEMEM_40S =40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE*

* =2x_DIELECTRIC 10000MEM_2GND

* ?MEM_DATA2SELF =2x_DIELECTRIC

MEM_2OTHER* *MEM_CLK

=8x_DIELECTRIC ?*MEM_DATA2OTHERMEM

=3x_DIELECTRIC* ?MEM_DQS2OWNDATA

?=3x_DIELECTRIC*MEM_CMD2CMD

* ?=3x_DIELECTRICMEM_CMD2CTRL

=3x_DIELECTRIC* ?MEM_CTRL2CTRL

?* =6x_DIELECTRICMEM_CLK2CLK

=4x_DIELECTRIC* ?MEM_2OTHERMEM

* 10000MEM_2PWR =2x_DIELECTRIC

*MEM_A_DQS_3 MEM_DQS2OWNDATAMEM_A_DATA_3

MEM_A_DQS_1 * MEM_DQS2OWNDATAMEM_A_DATA_1

MEM_A_DQS_0 *MEM_A_DATA_0 MEM_DQS2OWNDATA ** MEM_2OTHERMEM_A_DQS_0


*MEM_*_DATA_* MEM_DATA2SELF=SAME

MEM_2OTHER* *MEM_A_DATA_0



MEM_B_DQS_3 * MEM_2OTHER*

* * MEM_2OTHERMEM_B_DQS_2






MEM_B_DQS_2 *MEM_B_DATA_2 MEM_DQS2OWNDATA


*MEM_B_DQS_0 MEM_B_DATA_0 MEM_DQS2OWNDATA

MEM_B_DQS_1 *MEM_B_DATA_1 MEM_DQS2OWNDATA


MEM_B_DQS_5 MEM_B_DATA_5 * MEM_DQS2OWNDATA

MEM_CMD2CMDMEM_CMD MEM_CMD *

*MEM_*MEM_* MEM_2OTHERMEM

SYNC_MASTER=CONSTRAINTS

Memory ConstraintsSYNC_DATE=09/25/2012

MEM_2OTHERMEMMEM_*_DATA_*MEM_A_DATA_1 *






MEM_2OTHERMEMMEM_*_DATA_* *MEM_A_DATA_7


MEM_2OTHERMEMMEM_*_DATA_*MEM_B_DATA_0 *








PP0V6_S3_MEM_VREFDQ_BMEM_PWRPP0V6_S3_MEM_VREFCA_BMEM_PWR

MEM_PWR PP0V6_S3_MEM_VREFDQ_AMEM_PWR PP0V6_S3_MEM_VREFCA_A

PP1V2_S3MEM_PWR

MEM_B_DQS_7MEM_B_DQS7 MEM_B_DQS_N<7>MEM_70DMEM_B_DQS7 MEM_B_DQS_P<7>MEM_B_DQS_7MEM_70D

MEM_B_DQS_N<6>MEM_B_DQS_6MEM_B_DQS6 MEM_70D

MEM_B_DQS_5MEM_B_DQS5 MEM_B_DQS_N<5>MEM_70DMEM_B_DQS_6 MEM_B_DQS_P<6>MEM_B_DQS6 MEM_70D

MEM_70D MEM_B_DQS_P<5>MEM_B_DQS_5MEM_B_DQS5MEM_B_DQS_4MEM_B_DQS4 MEM_B_DQS_N<4>MEM_70D

MEM_B_DQS4 MEM_B_DQS_4 MEM_B_DQS_P<4>MEM_70DMEM_B_DQS_3MEM_B_DQS3 MEM_B_DQS_N<3>MEM_70DMEM_B_DQS_3MEM_B_DQS3 MEM_B_DQS_P<3>MEM_70DMEM_B_DQS_2MEM_B_DQS2 MEM_B_DQS_N<2>MEM_70DMEM_B_DQS_2MEM_B_DQS2 MEM_B_DQS_P<2>MEM_70DMEM_B_DQS_1MEM_B_DQS1 MEM_B_DQS_N<1>MEM_70DMEM_B_DQS_1MEM_B_DQS1 MEM_B_DQS_P<1>MEM_70DMEM_B_DQS_0MEM_B_DQS0 MEM_B_DQS_N<0>MEM_70DMEM_B_DQS_0 MEM_B_DQS_P<0>MEM_70DMEM_B_DQS0MEM_B_DATA_7 MEM_B_DQ<63..56>MEM_40SMEM_B_DQ_BYTE7

MEM_B_DQ<55..48>MEM_B_DATA_6MEM_40SMEM_B_DQ_BYTE6MEM_B_DATA_5 MEM_B_DQ<47..40>MEM_40SMEM_B_DQ_BYTE5

MEM_B_DQ_BYTE4 MEM_40S MEM_B_DATA_4 MEM_B_DQ<39..32>MEM_B_DATA_3MEM_B_DQ_BYTE3 MEM_B_DQ<31..24>MEM_40S

MEM_B_DATA_1MEM_B_DQ_BYTE1 MEM_B_DQ<15..8>MEM_40SMEM_B_DQ_BYTE2 MEM_B_DATA_2 MEM_B_DQ<23..16>MEM_40S

MEM_B_DATA_0MEM_B_DQ_BYTE0 MEM_B_DQ<7..0>MEM_40SMEM_B_CMD1 MEM_B_CAB<9..0>MEM_CMDMEM_40SMEM_B_CMD0 MEM_B_CAA<9..0>MEM_CMDMEM_40SMEM_B_CKE1 MEM_B_CKE<3..2>MEM_CMDMEM_40S

MEM_B_CKE<1..0>MEM_B_CKE0 MEM_CMDMEM_40SMEM_B_CTRL MEM_B_ODT<0>MEM_CTRLMEM_40SMEM_B_CTRL MEM_B_CS_L<1..0>MEM_CTRLMEM_40SMEM_B_CLK1 MEM_B_CLK_N<1>MEM_CLKMEM_70D

MEM_B_CLK_P<1>MEM_CLKMEM_70DMEM_B_CLK1MEM_B_CLK_N<0>MEM_CLKMEM_70DMEM_B_CLK0MEM_B_CLK_P<0>MEM_CLKMEM_70DMEM_B_CLK0

MEM_A_DQS_7MEM_70D MEM_A_DQS_N<7>MEM_A_DQS7MEM_A_DQS_7MEM_70D MEM_A_DQS_P<7>MEM_A_DQS7

MEM_A_DQS6 MEM_A_DQS_6MEM_70D MEM_A_DQS_N<6>

MEM_A_DQS5 MEM_A_DQS_5MEM_70D MEM_A_DQS_N<5>MEM_A_DQS_6MEM_A_DQS6 MEM_70D MEM_A_DQS_P<6>

MEM_A_DQS_5MEM_70DMEM_A_DQS5 MEM_A_DQS_P<5>

MEM_A_DQS_4MEM_70DMEM_A_DQS4 MEM_A_DQS_P<4>MEM_A_DQS_4MEM_70DMEM_A_DQS4 MEM_A_DQS_N<4>

MEM_70DMEM_A_DQS3 MEM_A_DQS_3 MEM_A_DQS_N<3>

MEM_A_DQS_N<2>MEM_70DMEM_A_DQS2 MEM_A_DQS_2MEM_70DMEM_A_DQS3 MEM_A_DQS_3 MEM_A_DQS_P<3>

MEM_A_DQS_N<1>MEM_70DMEM_A_DQS1 MEM_A_DQS_1MEM_A_DQS_P<2>MEM_70DMEM_A_DQS2 MEM_A_DQS_2

MEM_A_DQS_P<1>MEM_70DMEM_A_DQS1 MEM_A_DQS_1MEM_A_DQS_N<0>MEM_70DMEM_A_DQS0 MEM_A_DQS_0MEM_A_DQS_P<0>MEM_70DMEM_A_DQS0 MEM_A_DQS_0

MEM_A_DQ<55..48>MEM_40SMEM_A_DQ_BYTE6 MEM_A_DATA_6MEM_A_DQ<63..56>MEM_40SMEM_A_DQ_BYTE7 MEM_A_DATA_7

MEM_40SMEM_A_DQ_BYTE5 MEM_A_DATA_5 MEM_A_DQ<47..40>

MEM_40SMEM_A_DQ_BYTE3 MEM_A_DATA_3 MEM_A_DQ<31..24>MEM_40SMEM_A_DQ_BYTE4 MEM_A_DATA_4 MEM_A_DQ<39..32>

MEM_40SMEM_A_DQ_BYTE1 MEM_A_DATA_1 MEM_A_DQ<15..8>MEM_40SMEM_A_DQ_BYTE2 MEM_A_DATA_2 MEM_A_DQ<23..16>

MEM_40SMEM_A_DQ_BYTE0 MEM_A_DATA_0 MEM_A_DQ<7..0>

MEM_40S MEM_A_CAA<9..0>MEM_CMDMEM_A_CMD0MEM_40S MEM_A_CAB<9..0>MEM_CMDMEM_A_CMD1

MEM_CMDMEM_40S MEM_A_CKE<3..2>MEM_A_CKE1MEM_A_CKE0 MEM_A_CKE<1..0>MEM_40S MEM_CMD

MEM_A_ODT<0>MEM_40S MEM_CTRLMEM_A_CTRLMEM_A_CS_L<1..0>MEM_A_CTRL MEM_CTRLMEM_40SMEM_A_CLK_N<1>MEM_70D MEM_CLKMEM_A_CLK1MEM_A_CLK_P<1>MEM_A_CLK1 MEM_CLKMEM_70D

MEM_A_CLK0 MEM_A_CLK_P<0>MEM_70D MEM_CLKMEM_A_CLK0 MEM_A_CLK_N<0>MEM_CLKMEM_70D

<BRANCH>

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Thunderbolt/DP Connector Signal Constraints

SPACINGPHYSICAL

NET_TYPE


NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

DisplayPort Signal Constraints Thunderbolt/DP Net Properties

Only used on hosts supporting Thunderbolt video-in

SPACING

Thunderbolt IC Net PropertiesNET_TYPE


Only used on dual-port hosts.

=STANDARD=STANDARD=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE*TBT_SPI_45S

TOP,BOTTOM ?TBTDP_TX2TX =6x_DIELECTRIC

*TBTDP_RX TBTDP_TX2RXTBTDP_TX

TBTDP_RX2RX*TBTDP_RXTBTDP_RX

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF*TBTDP_80D =80_OHM_DIFF

?=2x_DIELECTRIC*TBT_SPI

TBTDP_TX **_RX TBTDP_2OTHERHS

TBTDP_RX * TBTDP_2OTHERHS*_TX

?*TBTDP_2OTHERHS =6x_DIELECTRIC

* ?TBTDP_2OTHER =4x_DIELECTRIC

=4x_DIELECTRIC* ?TBTDP_RX2RX

=6x_DIELECTRIC* ?TBTDP_TX2RX

=4x_DIELECTRIC*TBTDP_TX2TX ?

*TBTDP_RXTBTDP_TX TBTDP_TX2RX

TOP,BOTTOM ?=6x_DIELECTRICTBTDP_2OTHER

TBTDP_RX * TBTDP_2OTHERHS*_RX

*TBTDP_TX * TBTDP_2OTHER

* *TBTDP_RX TBTDP_2OTHER

* TBTDP_2OTHERHS*_TXTBTDP_TX

TOP,BOTTOM ?TBTDP_RX2RX =6x_DIELECTRIC

?TOP,BOTTOM =10x_DIELECTRICTBTDP_2OTHERHS

TOP,BOTTOM ?TBTDP_TX2RX =10x_DIELECTRIC

SYNC_MASTER=CONSTRAINTS SYNC_DATE=09/25/2012

Thunderbolt Constraints

*TBTDP_TXTBTDP_TX TBTDP_TX2TX

DP_80D DP_TBTPA_ML_P<3..1:2>DP_TX

DP_80D DP_TBTPA_ML_N<3..1:2>DP_TX

DP_80D DP_TBTPA_ML_C_N<3>DP_TBTPA_ML3 DP_TX

DP_TX DP_A_LSX_ML_N<1>DP_80D

DP_TBTPA_ML_C_P<3>DP_TBTPA_ML3 DP_TXDP_80D

DP_TBTPA_ML_C_P<1>DP_TBTPA_ML1 DP_80D DP_TXDP_TBTPA_ML_C_N<1>DP_TBTPA_ML1 DP_80D DP_TX

DP_A_LSX_ML_P<1>DP_80D DP_TX

DP_A_AUXCH_DDC_NDP_80D DP_AUX

TBTDP_80D TBT_B_D2R1_AUXDDC_NTBTDP_RX

TBTDP_80D TBT_B_D2R1_AUXDDC_PTBTDP_RX

DP_80D DP_B_AUXCH_DDC_NDP_AUX

DP_80D DP_TBTPB_AUXCH_NDP_AUX

DP_80D DP_TBTPB_AUXCH_PDP_AUX

DP_80D DP_B_AUXCH_DDC_PDP_AUX

DP_80DTBT_B_AUXCH NC_DP_TBTPB_AUXCH_CNDP_AUX

DP_80DTBT_B_AUXCH NC_DP_TBTPB_AUXCH_CPDP_AUX

TBTDP_80DTBT_B_D2R TBT_B_D2R_N<1..0>TBTDP_RX

TBT_B_D2R TBTDP_80D TBT_B_D2R_P<1..0>TBTDP_RX

TBTDP_80D TBT_B_D2R_C_N<1..0>TBTDP_RX

TBT_B_D2R_C_P<1..0>TBTDP_80D TBTDP_RX

DP_B_LSX_ML_P<1>DP_TXDP_80DDP_B_LSX_ML_N<1>DP_TXDP_80D

DP_TXDP_80D DP_TBTPB_ML_N<3..1:2>

DP_TXDP_80DDP_TBTPB_ML NC_DP_TBTPB_ML_CN<3..1:2>DP_TXDP_80D DP_TBTPB_ML_P<3..1:2>

DP_TXDP_80D NC_DP_TBTPB_ML_CP<3..1:2>DP_TBTPB_ML

TBTDP_80D TBT_B_R2D_P<1..0>TBTDP_TX

TBTDP_80D TBT_B_R2D_C_P<1..0>TBT_B_R2D TBTDP_TX

TBT_SPI_CS_L TBT_SPITBT_SPI_45S TBT_SPI_CS_LTBT_SPITBT_SPI_45STBT_SPI_MISO TBT_SPI_MISOTBT_SPITBT_SPI_45STBT_SPI_MOSI TBT_SPI_MOSITBT_SPITBT_SPI_45STBT_SPI_CLK TBT_SPI_CLK

DP_AUXDP_80D DP_TBTSRC_AUXCH_C_NDP_AUXDP_80D DP_TBTSRC_AUXCH_C_PDP_TXDP_80D DP_TBTSRC_ML_C_N<3..0>DP_TXDP_80D DP_TBTSRC_ML_C_P<3..0>

TBTDP_80D TBT_A_R2D_P<1..0>TBTDP_TX

TBTDP_80D TBT_A_R2D_N<1..0>TBTDP_TX

TBTDP_80DTBT_A_R2D TBT_A_R2D_C_N<1..0>TBTDP_TX

TBTDP_80DTBT_A_R2D TBT_A_R2D_C_P<1..0>TBTDP_TX

TBTDP_80D TBT_B_R2D_N<1..0>TBTDP_TX

TBTDP_80DTBT_B_R2D TBT_B_R2D_C_N<1..0>TBTDP_TX

TBT_A_D2R1_AUXDDC_NTBTDP_80D TBTDP_RX

TBT_A_D2R1_AUXDDC_PTBTDP_80D TBTDP_RX

TBT_A_D2R_C_N<1..0>TBTDP_80D TBTDP_RX

DP_A_AUXCH_DDC_PDP_80D DP_AUX

DP_80D DP_TBTPA_AUXCH_NDP_AUX

DP_80D DP_TBTPA_AUXCH_PDP_AUX

DP_TBTPA_AUXCH_C_NTBT_A_AUXCH DP_80D DP_AUX

DP_TBTPA_AUXCH_C_PDP_80DTBT_A_AUXCH DP_AUX

TBTDP_80D TBT_A_D2R_N<0>TBT_A_D2R0 TBTDP_RX

TBTDP_80D TBT_A_D2R_P<0>TBT_A_D2R0 TBTDP_RX

TBTDP_80D TBT_A_D2R_N<1>TBT_A_D2R1 TBTDP_RX

TBT_A_D2R_P<1>TBT_A_D2R1 TBTDP_80D TBTDP_RX

TBT_A_D2R_C_P<1..0>TBTDP_80D TBTDP_RX

<BRANCH>

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Camera Net Properties

Memory Bus Spacing Group Assignments

MIPI Interface Constraints

Spacing Rule Sets

Memory to Power Spacing

Memory to GND Spacing

SPACINGPHYSICAL

NET_TYPE

Memory Bus Constraints

I101

I102

I103

I104

I106

I107

I108

I109

I110

I127

I128

I129

I130

I131

I132

I133

I134

I145

I146

I147

I148

I149

TOP,BOTTOM =10x_DIELECTRIC ?S2MEM_2OTHER

TOP,BOTTOM ?S2MEM_2PWR =4x_DIELECTRIC

=4x_DIELECTRICS2_CMD2CTRL ?TOP,BOTTOM

MIPICLK_2OTHER =10X_DIELECTRICTOP,BOTTOM ?

MIPI_2CLK =8X_DIELECTRIC ?TOP,BOTTOM

=6X_DIELECTRIC ?TOP,BOTTOMMIPI_2OTHER

S2_DATA2SELF ?=4x_DIELECTRICTOP,BOTTOM

=4x_DIELECTRICS2_DQS2OWNDATA ?TOP,BOTTOM

S2_CMD2CMD ?TOP,BOTTOM =4x_DIELECTRIC

TOP,BOTTOM =6x_DIELECTRIC ?S2_2OTHERMEM

?=4x_DIELECTRICTOP,BOTTOMS2MEM_2GND

S2_CTRL2CTRL ?TOP,BOTTOM =4x_DIELECTRIC=2x_DIELECTRICS2_CTRL2CTRL * ?

?* =4x_DIELECTRICS2_2OTHERMEM

S2_DQS2OWNDATA * ?=2x_DIELECTRIC

S2MEM_2PWR =2x_DIELECTRIC* ?

* ?S2_DATA2SELF =2x_DIELECTRIC

* S2_CMD2CTRLS2_MEM_CTRLS2_MEM_CMD

S2MEM_2OTHER* *S2_MEM_DQS*

**S2_MEM_DATA* S2MEM_2OTHER

S2_MEM_DATA* S2_DATA2SELF*=SAME

*S2_MEM_PWR S2_MEM_* S2MEM_2PWR

DEFAULT* *S2_MEM_PWR

*S2_MEM_DATA0 S2_DQS2OWNDATAS2_MEM_DQS0

S2_MEM_CMD * * S2MEM_2OTHER

**S2_MEM_CTRL S2MEM_2OTHER

* S2MEM_2OTHER*S2_MEM_CLK

*S2_MEM_CMD S2_CMD2CMDS2_MEM_CMD

* S2_CTRL2CTRLS2_MEM_CTRLS2_MEM_CTRL

S2_MEM_* S2_MEM_* * S2_2OTHERMEM

*S2_MEM_* S2MEM_2GNDGND

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFFMIPI_85D *

S2_MEM_85D =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF*

=45_OHM_SES2_MEM_45S * =45_OHM_SE =STANDARD=45_OHM_SE =STANDARD=45_OHM_SE

MIPICLK_2OTHER*CLK_MIPI *

MIPI_DATA CLK_MIPI MIPI_2CLK*

MIPI_DATA MIPI_2OTHER**

?=7X_DIELECTRIC*MIPICLK_2OTHER

?=6X_DIELECTRIC*MIPI_2CLK

=4X_DIELECTRIC* ?MIPI_2OTHER

=2x_DIELECTRICS2MEM_2GND * ?

?*S2MEM_2OTHER =6x_DIELECTRIC

*S2_MEM_DATA1 S2_DQS2OWNDATAS2_MEM_DQS1


Camera Constraints

S2_CMD2CMD * ?=2x_DIELECTRIC

=2x_DIELECTRICS2_CMD2CTRL ?*

MIPI_85D MIPI_CLK_CONN_PCLK_MIPI

S2_MEM_PWR PP0V675_MEM_CAM_VREFDQ

S2_MEM_DQS0 MEM_CAM_DQS_N<0>S2_MEM_85D S2_MEM_DQS0

S2_MEM_85DS2_MEM_DQS0 MEM_CAM_DQS_P<0>S2_MEM_DQS0

S2_MEM_45SS2_MEM_DATA_0 MEM_CAM_DM<0>S2_MEM_DATA0

S2_MEM_45SS2_MEM_A S2_MEM_CMD MEM_CAM_A<14..0>S2_MEM_DATA1 MEM_CAM_DM<1>S2_MEM_DATA_1 S2_MEM_45S

S2_MEM_PWR PP0V675_CAM_VREF

S2_MEM_45SS2_MEM_CMD MEM_CAM_BA<1>S2_MEM_CMD

MIPI_85D MIPI_CLK_CONN_NCLK_MIPI

MEM_CAM_ODTS2_MEM_45S S2_MEM_CTRLMEM_CAM_CAS_LS2_MEM_CTRLS2_MEM_45SS2_MEM_CMD

S2_MEM_45S MEM_CAM_CKES2_MEM_CTRLS2_MEM_CNTL

MEM_CAM_RAS_LS2_MEM_CMD S2_MEM_45S S2_MEM_CTRLMEM_CAM_WE_LS2_MEM_CMD S2_MEM_45S S2_MEM_CMD

MIPI_85DMIPI_CLK_S2 CLK_MIPI MIPI_CLK_P

S2_MEM_DATA_0 MEM_CAM_DQ<7..0>S2_MEM_45S S2_MEM_DATA0

MEM_CAM_CLK_NS2_MEM_CLKS2_MEM_85DS2_MEM_CLK

MEM_CAM_CS_LS2_MEM_CNTL S2_MEM_CTRLS2_MEM_45S

MEM_CAM_BA<0>S2_MEM_45SS2_MEM_CMD S2_MEM_CMD

S2_MEM_CMD S2_MEM_45S S2_MEM_CMD MEM_CAM_BA<2>

MIPI_85DMIPI_CLK_S2 MIPI_CLK_NCLK_MIPI

S2_MEM_PWR PP0V675_MEM_CAM_VREFCA

S2_MEM_DQS1 MEM_CAM_DQS_N<1>S2_MEM_DQS1S2_MEM_85D

S2_MEM_DATA_1 S2_MEM_45S MEM_CAM_DQ<15..8>S2_MEM_DATA1

PP1V35_CAMS2_MEM_PWR

MEM_CAM_DQS_P<1>S2_MEM_DQS1S2_MEM_85DS2_MEM_DQS1

MIPI_85D MIPI_DATA MIPI_DATA_CONN_NMIPI_85D MIPI_DATA MIPI_DATA_CONN_PMIPI_85DMIPI_DATA_S2 MIPI_DATA MIPI_DATA_NMIPI_85D MIPI_DATA_PMIPI_DATAMIPI_DATA_S2

MEM_CAM_CLK_PS2_MEM_85D S2_MEM_CLKS2_MEM_CLK

<BRANCH>

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SMC SMBus Net Properties

NET_TYPE

PHYSICAL

PHYSICAL

NET_TYPE

SPACING

SMBus Charger Net Properties

SPACING

SMC ConstraintsSYNC_MASTER=CONSTRAINTS SYNC_DATE=09/25/2012

0.1 MM*2TO1_DIFFPAIR 0.2 MM=STANDARD 0.1 MM =STANDARD 0.1 MM

0.1 MM* =STANDARD =STANDARD=STANDARD 0.1 MM=STANDARD1TO1_DIFFPAIR

CHGR_CSO_R_N2TO1_DIFFPAIR

CHGR_CSI_N2TO1_DIFFPAIRSENSE_DIFFPAIRCHGR_CSI_R_P2TO1_DIFFPAIR

CHGR_CSI_PSENSE_DIFFPAIR

CHGR_CSI_R_N2TO1_DIFFPAIR

SMBUS_SMC_1_S0_SDA SMB SMBUS_SMC_1_S0_SDASMB_45S_R_50S

SMBSMB_45S_R_50SSMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SCL

SMBUS_SMC_1_S0_SCL SMB SMBUS_SMC_1_S0_SCLSMB_45S_R_50S

SMBUS_SMC_0_S0_SCL SMB_45S_R_50S SMBUS_SMC_0_S0_SCLSMB

SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDASMB_45S_R_50S SMB

SMB_45S_R_50SSMBUS_SMC_5_G3_SDA SMBUS_SMC_5_G3_SDASMB

SMBUS_SMC_3_SCL SMB_45S_R_50S SMBUS_SMC_3_SCLSMB

SMBUS_SMC_5_G3_SCLSMB_45S_R_50SSMBUS_SMC_5_G3_SCL SMB

SMB_45S_R_50S SMBSMBUS_SMC_3_SDA SMBUS_SMC_3_SDA

SMBUS_SMC_2_S3_SDA SMBSMB_45S_R_50S SMBUS_SMC_2_S3_SDA

CHGR_CSO_NSENSE_DIFFPAIR 2TO1_DIFFPAIRCHGR_CSO_R_P2TO1_DIFFPAIR

CHGR_CSO_P2TO1_DIFFPAIRSENSE_DIFFPAIR

<BRANCH>

<SCH_NUM>

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36 37 40 44 64

37 40 48 50 64

36 37 40 44 64

37 40 61 65

50

43 50

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NET_TYPE

SPACINGPHYSICAL

J11/J13 Specific Net Properties

I348

I349

SB_POWER PWR_P2MMSATA* *

SB_POWER PWR_P2MM*CLK_PCIE

GND_P2MMCLK_PCIE *GND

* =2:1_SPACINGTHERM ?

USB* GND_P2MM*GND

GND *CPU_COMP GND_P2MM?=2:1_SPACING*SENSE

PWR_P2MM * 100000.20 MM

SATA*SB_POWER PWR_P2MM*

GND * ?=STANDARD

THERM_1TO1_45S =45_OHM_SE =1TO1_DIFFPAIR=45_OHM_SE* =45_OHM_SE=1TO1_DIFFPAIR =1TO1_DIFFPAIR

GND_P2MM*PCIE*GND

0.300 MM =1TO1_DIFFPAIR* =1TO1_DIFFPAIR=1TO1_DIFFPAIR 0.100 MMSPKR_DIFFPAIR =1TO1_DIFFPAIR

0.20 MMGND_P2MM * 10000

GND_P2MM*SATA*GND

CPU_VCCSENSE GND_P2MMGND *

0.100 MM =1TO1_DIFFPAIR*SENSE_1TO1_P2MM 0.200 MM=1TO1_DIFFPAIR =1TO1_DIFFPAIR =1TO1_DIFFPAIR

=45_OHM_SE=1TO1_DIFFPAIR*SENSE_1TO1_45S =45_OHM_SE =1TO1_DIFFPAIR=45_OHM_SE =1TO1_DIFFPAIR

GND_P2MM*LVDS*GND

AUDIO * =2:1_SPACING ?


Project Specific Constraints

SENSE_DIFFPAIR SENSE ISNS_LCDBKLT_NSENSE_1TO1_45SISNS_LCDBKLT_PSENSE_DIFFPAIR SENSESENSE_1TO1_45S

SB_POWER PP3V3_S5PP3V3_S0SB_POWER

SPKR_DIFFPAIR AUDIOSPKR_OUT SPKRAMP_ROUT_N

MAX98300_R_N1TO1_DIFFPAIR AUDIO

SPKR_DIFFPAIR AUDIOSPKR_OUT SPKRAMP_ROUT_P

MAX98300_R_P1TO1_DIFFPAIR AUDIO

SPKRAMP_INR_N1TO1_DIFFPAIR AUDIOAUD_DIFF

SPKRAMP_INR_P1TO1_DIFFPAIR AUDIOAUD_DIFF

CPUVR_ISNS1_N_RSENSE_1TO1_P2MM SENSE

SENSE_1TO1_45S ISNS_HS_OTHER_NSENSE_DIFFPAIR SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR ISNS_BMON_GAIN_NSENSE

SENSE_DIFFPAIR INLET_THMSNS_D1_NTHERM_1TO1_45S THERM

SENSE_DIFFPAIR INLET_THMSNS_D1_PTHERMTHERM_1TO1_45S

THERM_1TO1_45S THERM TBT_MLBBOT_THMSNS_NSENSE_DIFFPAIR

THERM_1TO1_45S THERM TBTTHMSNS_D2_NSENSE_DIFFPAIR

SENSESENSE_1TO1_P2MM CPUVCCIOS0_CS_PSENSE_DIFFPAIR

SENSE_1TO1_P2MMSENSE_DIFFPAIR CPUVCCIOS0_CS_NSENSE

THERMTHERM_1TO1_45S MLBBOT_THMSNS_D3_PSENSE_DIFFPAIR

THERMTHERM_1TO1_45SSENSE_DIFFPAIR MLBBOT_THMSNS_D3_N

SENSE_DIFFPAIR SENSE CPUTHMSNS_D2_PSENSE_1TO1_45S

SENSESENSE_1TO1_45SSENSE_DIFFPAIR CPUTHMSNS_D2_N

SENSE_DIFFPAIR SENSE TBDTHMSNS_D2_PSENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE TBDTHMSNS_D2_N

SENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE CPUVR_ISNS1_P

SENSE_1TO1_45SSENSE_DIFFPAIR SENSE ISNS_HS_COMPUTING_P

ISNS_1V05_S0_NSENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE

ISNS_BMON_GAIN_PSENSESENSE_DIFFPAIR SENSE_1TO1_45S

SENSE CPUVR_ISUM_R_PSENSE_1TO1_45S

CPUVR_ISNS1_NSENSE_DIFFPAIR SENSE_1TO1_P2MM SENSE

TBTTHMSNS_D2_PSENSE_DIFFPAIR THERMTHERM_1TO1_45S

SENSE_DIFFPAIR THERMTHERM_1TO1_45S TBTTHMSNS_D2_R_PSENSE_DIFFPAIR THERMTHERM_1TO1_45S TBTTHMSNS_D2_R_N

THERMTHERM_1TO1_45SSENSE_DIFFPAIR TBT_MLBBOT_THMSNS_P

SENSE_1TO1_45S CPUVR_ISNS2_PSENSE_DIFFPAIR SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE CPUVR_ISNS2_N

CPUVR_ISNS1_P_RSENSE_1TO1_P2MM SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S ISNS_SSD_PSENSE

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_P3V3_S0_P

SENSE_DIFFPAIR ISNS_P3V3S5_NSENSE_1TO1_45S SENSE

SENSE_DIFFPAIR SENSE ISNS_CAMERA_NSENSE_1TO1_45S

SENSE_1TO1_45S SENSE ISNS_CAMERA_PSENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_3V3_S0_N

SENSE_DIFFPAIR SENSESENSE_1TO1_P2MM ISNS_CPUDDR_N

CPUVR_ISUM_R_NSENSESENSE_1TO1_45S

SENSESENSE_DIFFPAIR ISNS_SSD_NSENSE_1TO1_45S

SENSE_DIFFPAIR SENSE_1TO1_45S ISNS_AIRPORT_PSENSE

SENSE_DIFFPAIR SENSE_1TO1_45S ISNS_AIRPORT_NSENSE

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_P3V3_S0_N

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_HS_COMPUTING_N

SENSE ISNS_HS_OTHER_PSENSE_1TO1_45SSENSE_DIFFPAIR

ISNS_1V2_S3_NSENSE_1TO1_45SSENSE_DIFFPAIR SENSEISNS_1V2_S3_PSENSE_1TO1_45SSENSE_DIFFPAIR SENSE

SENSE_1TO1_P2MM ISNS_1V05_S0_PSENSE_DIFFPAIR SENSE

SENSE_1TO1_45S ISNS_3V3_S0_PSENSESENSE_DIFFPAIR

ISNS_P3V3S5_PSENSESENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR SENSE ISNS_CPUDDR_PSENSE_1TO1_P2MM

ISNS_PANEL_PSENSE_DIFFPAIR SENSESENSE_1TO1_45S

ISNS_PANEL_NSENSE_DIFFPAIR SENSESENSE_1TO1_45S

ISNS_HS_GAIN_NSENSE_1TO1_45S SENSESENSE_DIFFPAIRISNS_HS_GAIN_PSENSE_1TO1_45S SENSESENSE_DIFFPAIR

GNDGND

<BRANCH>

<SCH_NUM>

<E4LABEL>

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41

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8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61

62 64 65

47 64

47

47 64

47

47 61 65

47 61 65

42 43

41

44

44

44

44

44

44

44

42 52

41 43

42 55

42

42 52

44

44

44

42 52

42 52

42 43

41

41

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41

41

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Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


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SPACING

SD Card Net PropertiesNET_TYPE


I346

I347

I348

I349

I350

I351

I352

I353

I354

I355

I356

Project Specific ConstraintsSYNC_MASTER=CONSTRAINTS SYNC_DATE=09/25/2012

*SD_45SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

SPISD_45SE SD_SPI_CLK

SDCLK_CLK25M_X2_RCLK_25M_45S

SDCONN_DETECT_LSD_45SE

SDSCLK_CLK_25M_X1CLK_25M_45S

SPI SD_SPI_MISOSD_45SE

SPI SD_SPI_MOSISD_45SE

SPI SD_SPI_CS_LSD_45SE

SDCONN_CMDSD_45SE

SD_45SE SDCONN_WP

SDCONN_CLKSD_45SESDCLK

SDCONN_DATA<0..3>SD_45SESDDATA

<BRANCH>

<SCH_NUM>

<E4LABEL>

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34

34 69

33 34

34

34

34

33 34

33 34

33 34

33 34

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Apple Inc.


124578

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D

8 7 6 5 4 3

C

B

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Useful Wiki Links:

<rdar://component/497585> MobileMac HW | New Bugs

Other Info:

<rdar://component/497591> MobileMac HW | TaskMobileMac HW Radar:

<rdar://component/497588> MobileMac HW | Layout

Kismet:afp://kismet.apple.com/Kismet-Projects/J41-J43

<rdar://component/497589> MobileMac HW | Architecture<rdar://component/497590> MobileMac HW | Investigation

Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions

<rdar://component/497587> MobileMac HW | Schematic

Page Allocations - <rdar://problem/11791318> 2012 Schematic Page Allocations

Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design

Change List:<RDAR://COMPONENT/508934> J43 HW EE SCHEMATIC | PROTO 0<RDAR://COMPONENT/508937> J43 HW EE SCHEMATIC | PROTO 1<RDAR://COMPONENT/508941> J43 HW EE SCHEMATIC | EVT<RDAR://COMPONENT/508945> J43 HW EE SCHEMATIC | DVT

ReferenceSYNC_MASTER=J41_MLB SYNC_DATE=07/03/2012

<BRANCH>

<SCH_NUM>

<E4LABEL>

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