pcbf, x200 mlb (c1)r2040 r2050 u2720 l2050 l2040 c8190 c8140 c8141 l5700 l8229 dz5700 r8100 c8149...
TRANSCRIPT
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R2040 R2050
U2720
L2050
L2040
C8190
C8140
C8141
L5700
L8229
DZ5700
R8100
C8149
DZ5703
DZ5704
DZ5702U1400
DZ8120
D8230
D8228
D8100
L2201
DZ5710
Q8104
Q8123
XW1902
XW1903
XW1900
C1026
C1004
C1405
C1007
C1404
C8210
U8550
L8103
L8100
L8104
L8106
L8105
L8102
L8101
L8111
L8108
L8107
L8109
U8100
L8110
C8145
Y8200
U1700
U2200
U0652
Y0602
C2800
C5701
C8233
C8237
C8307
C8139
C8201
C8136
C8200
C8203
C8230
DZ2963
DZ2961
DZ2962
DZ2960
J2201
J1700
D5700
D5702
D5701
D5703
U3000
U3001
U3002
U3003
J7500
C3432
C4235
C4100
C4101
C4232
C4322
C4323
R8323
R8324
R8321
R8322
R8327
L2962
L2961
L2960
L2963
L2901
L2900
L1800
L2602
L2800
L2903
L2902
L1920
L2601
L2600
L1700
L1701
L1702
FL7500
L4440
C1912 C1908
C1906
C1905
C1950
C1907
C1901
C1070
C2907
C2910
C2901
C2904
C1701
C1361
C8235
C2047
C2048
C1909
C2058
C2053
C2052
C2041 C2042
C2057
C2043
C8150
C8172
C8171
C8160
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C81A7
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C81A5
C81A6
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C1910
C8193
C8194
C5800
C5801
C3205
C3208
C3206
C3207
C3204
C2202
C2241
C8239
C8290
C8238
C8231
C8226
C8169
C8241
C8155
C8211
C8240
C8232
C8163
C8164
C8153
C8187
C8186C8185
C8183
C8181
C8179
C8177
C8176
C81A4
C8170
C8162 C8151
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C8152
C8234
C8188
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C4485
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R1951
R1950
R1952
R2051R2041
R5700
R5820
R5810
R5830
R8130
R8116
R8173
R8399
R8303R4739
R4607
R4139
R4608
R4437
R1953
R1931
R1930
L4801
R4801
R8172
R8146
R8170
R3702
C4058 C4049
L3817
C4048
L3821
R4605
R4701
L4747
L4746
R0770
R0765
R1207
R1454
R1260
R0870
R2450
R0753
R0752
R0871
R2727
R0832
R2750
R0617
R1250
R0705
R0704
R1211
R0703
R0702
R1052
R1051
R1000
R0738
R1940
R0646
R1920
R2757 R2405
R0831
R0655
R0720
R2400
R2406
R2747
R0640
R1461
R1912
R1913R1910
R1911
R1460
R2902
R2901
R2900
R2903
R0721
R1209
R1208
R0739
R1213
R8352
R1006
R1005
R1001
R0751
R1205
R1206
R0933
R0930R0941
R0940
R1201
R0701
R0931
R0750
R2801
R2601
R1850
R2800
R2241
R5790
R5791
R1790
R2243
R1753 R1752
R2242
R2250
R8240
R8231
R8232
R8235
R8239
R8227
R5706R5705
R0736
R5802
R5800
R5801
R5804
R5803
R3401
R8330
R3307R3305
R3306
R3304
R3301
R3300
R3530
R3531
R4500
R3002
R3003
R3502
R3402
R3403
R3400
R3303
R1751
R2205
R2290
R3000
R2291
R0651
R0771
R1370
R8411
R8435
R8410 R8445
R8450 R8451
R8430
R8420
R8425
R0735
R5805
R4534
R3604
C3905
C3904
C3914
C3913
C3903
R3600
C4146
C3910
R3602
L4029
R3603
R3601
L4012
R4064
L4044
L4030
R4065
L4070
R4300
L4435
L4802
L4803
L1900
L1901
L1902
L1903
L5702
L5701
C5824
C5821
C5814 L5811
C5811
L4765
L3814
L3815
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L3805
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L4097
C4320
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L4613
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C4807
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C4056
L3820
L2741
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L2660
L2950
L1904
L1905
L1760
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C1411
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C1410
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C5881
C3222
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C1015
C1009
C1100
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C1120
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C2726
C2046
C1914
C1904
C1920
C1932
C1930
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C2056
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C2093
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TOP SIDE ASSEMBLY
LAYER BOARDS) AS APPLICABLE.
062-0031 (DOUBLE-SIDED BOARDS) OR 062-0073 (MULTI-
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
NOTES:
ORIG DIV
APPLETHIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED
HURLEY
DESIGNER
01/08/13
DATE SCALE
1:1
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT
THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
PROPRIETARY PROPERTY OF APPLE
THE INFORMATION CONTAINED HEREIN IS THE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
TITLE
820-4124-A
X200 MLB (C1)
PCBF,
-
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
3
B
7
BRANCH
DRAWING NUMBER SIZE
D
SHEET
R
DATE
D
A
C
PAGE
A
C
3456
D
B
8 7 6 5 4 2 1
12
APPDCK
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DRAWING TITLE
DESCRIPTION OF REVISIONREV ECN
REVISION
PROPRIETARY PROPERTY OF APPLE INC.
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
DRAWING
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
SCH AND BOARD PART NUMBERS
MLB-C1X200 0002535199A
051-0886
A.0.0
2014-01-13PRODUCTION RELEASED
1 OF 121
1 OF 54
SCH,MLB-C1,X200
LAST_MODIFIED=Tue Oct 29 15:52:27 2013
J85 MLB_C12/05/20122218 VIDEO: EDP SUPPORT & CONN
BUTTON: CONN N/A N/A2117
AUDIO: CS35L19A AMPS KAVITHA 01/18/20122016
KAVITHA 01/18/20121915 AUDIO: L81 CODEC
AUDIO: HP FLEX CONN N/A1814
TOUCH: SUPPORT CKT & CONN N/A 06/21/20101713
IO: TRISTAR N/A N/A1311
SOC: MISC & ALIASES N/A 04/11/20111210
SOC: VDD, SRAM, CPU, GPU PWRS N/A 04/18/2011119
SOC: SRAM, IO PWRS N/A 04/18/2011108
SOC: DP,MIPI MLB 05/04/201297
SOC: NAND N/A 04/18/201186
N/A 05/05/201175
SOC: MAIN N/A 04/18/201164
BOM TABLES J72_MLB_C11/26/201243
BLOCK DIAGRAM: SYSTEM J85_MLB_B04/02/201322
11/26/201212154 POWER: ALIASES J72_MLB_C
J85 MLB_C12/03/129352J72_MLB_C11/26/20129051 SEP: EEPROM & SOC DEBUGJ85 MLB_C11/26/201285 POWER: PP1V8_SWJ72_MLB_C11/26/20128449 PMU: ANYA PAGE 4J72_MLB_C11/26/20128348 PMU: ANYA PAGE 3J85 MLB_C12/03/20128247 PMU: ANYA PAGE 2J72_MLB_C11/26/20128146 PMU: ANYA PAGE 1N/A N/A7545 POWER: BATTERY CONNECTORWIFI_DEV05/20/20135844 WIFI/BT: MODULEN/A 04/18/20115743 IO: FILTERS & HOTBAR CONNRADIO_MLB_8710/29/20134942 CELL: ANTENNA FEEDSRADIO_MLB_8710/29/20134841 CELL: GPSRADIO_MLB_8710/29/20134740 CELL: RX DIVERSITYRADIO_MLB_8710/29/20134639 CELL: ASM AND HB LTE FRONT-ENDRADIO_MLB_8710/29/20134538 CELL: PA DCDC CONVERTERRADIO_MLB_8710/29/20134437 CELL: 2G PARADIO_MLB_8710/29/20134336 CELL: BAND 5/8 PADRADIO_MLB_8710/29/20134235 CELL: BAND 7/20 PADRADIO_MLB_8710/29/20134134 CELL: BAND 2/3 PADRADIO_MLB_8710/29/20134033 CELL: PENTABAND PARADIO_MLB_8710/29/20133932 CELL: RF TRANSCEIVER (3 OF 4)RADIO_MLB_8710/29/20133831 CELL: RX MATCHINGRADIO_MLB_8710/29/20133730 CELL: RF TRANSCEIVER (2 OF 2)RADIO_MLB_8710/29/20133629 CELL: RF TRANSCEIVER (1 0F 2)RADIO_MLB_8710/29/20133528 CELL: BASEBAND (2 OF 2)RADIO_MLB_8710/29/20133427 CELL: BASEBAND (1 OF 2)RADIO_MLB_8710/29/20133326 CELL: BASEBAND PMU (2 OF 2)RADIO_MLB_8710/29/20133225 CELL: BASEBAND PMU (1 0F 2)RADIO_MLB_8710/29/20133024 CELL:AP INTERFACE & DEBUG CONNECTORSN/A N/A2923 CAMERA: REAR CONN & FILTERSJ85 MLB_C12/05/122822 SENSOR: PROX
CONTENTS DATESYNC MASTERPDF CSA
N/A N/A2721 SENSOR: ACCEL, COMPASS, GYROSYNC MASTERCONTENTS DATECSAPDF
TABLE OF CONTENTS N/A N/A11
PCB11820-4124 PCBF,MLB-C1,X200
1 SCH1051-0886 SCH,MLB-C1,X200
J72_MLB_C11/26/20129453 TEST: EE TP/PPCAMERA: FF-ALS CONN & FILTERS J85 MLB_C12/03/20122620
SENSOR: OSCAR J72_MLB_C11/26/20122419
NAND STORAGE 05/04/20121412
TEST: TP/HOLES/FIDUCIALS
50
03/31/2011
MLB
SOC: I/OS
-
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
HSIC2
HSIC1
I2C2I2S1
ALS
I2C3
CSA 27CSA 27CSA 27
BATTERY
I2S3
I2S4
CSA 13
SPI2
I2S2
CSA 14
CSA 28
1-3
CSA 17
HALL EFF
OSCAR
I2C0
CSA 24
FMI0
COMPASS
SPI1
I2C0
CUMULUS
CSA 81-84
FRONT CAMERA
UART3
DISPLAY/
BUTTON FLEX
AMP
LEFT
SPEAKER
USB2.0
WIFI/BT ANT
WIFI/BT ANTCSA 58
TRISTAR
REAR CAMERA
BT_I2S
MIPI1C
MIPI0C
ISP1_I2C
ISP0_I2C
UART2
UART6
SPI
XSP
HP
FMI1
NAND FLASH
UART4
DWI
UART5
EDP
CSA 75
I2C1
PMU
BACKLIGHT
TOUCH PANEL
SPI BUS
GYROACCELEROMETER
HOME BUTTON
PROX SENSOR
ANYA
PRIMARY CELLULAR ANT
NOT ONCELLULAR/
JTAG
GRAPE
GPS
DIVERSITY CELLULAR ANT
HSIC1
WIFI-ONLY CONFIG
WIFI/BTUART1
GPS ANT
SIM CARD
USART
ALCATRAZ
MBUS
CSA 31-46
MIMO
MIC1 MIC2
CSA 19
L81
CODECAUDIO
RIGHT
USB
ASPI2S0
CSA 20
CSA 20
UART0
AMP
SPEAKER
CUMULUS
SYNC_DATE=04/02/2013SYNC_MASTER=J85_MLB_B
BLOCK DIAGRAM: SYSTEM051-0886
A.0.0
2 OF 121
2 OF 54
-
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#TABLE_5_ITEM
WIFI 4.3UF CAP
U2200
338S1233 ST MICRO - DISQUAL’ED
PMU
338S1191 OLD ACCEL - ST MICRO338S1114 OLD ACCEL - ST MICRO
338S1158 OLD GYRO - ST MICRO
OLD INVENSENSE P/N 338S1200 (3/22/13)OLDER INVENSENSE P/N 338S1135
GYRO
MECHANICAL PARTS
Page Notes
ACCEL
Power aliases required by this page:
128GB_PROD
ANDGATE_TIFERRITE_TY
JTAG_DAPDEVELOPMENT_JTAG_TAP
COMMONBOM OPTIONS
64GB_PROD
ALTERNATE
MLB (WDOG TO PMU)
BOM options provided by this page:
32GB_PROD16GB_PROD
FERRITE_TDK
Signal aliases required by this page:
(NONE)
WIFI BOM OPTIONS
SOC
(NONE)
FLASH CONFIGURATIONS
BARCODE LABEL/EEEE CODES
NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES)
U5800339S0213339S0223 RDAR #13988471C1009,C1015,...138S0657138S0702
132S0288
1 CRITICAL338S1163 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U2700
CRITICALU81001343S0656 IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342
1 U1400TOS,19NM,PPN1.5,C,12DP,64GB 96GB335S0929
SYNC_DATE=11/26/2012SYNC_MASTER=J72_MLB_C
BOM TABLES
FENCE,RADIO,MLB,C BRD,X221806-7613 1 PD_CAN_RADIO CRITICAL
1 CRITICALPD_FENCE_MLB806-6207 FENCE,TALL,MLB,X221
BASIC COMMON,ALTERNATE
C2726CAP 0.1UF 16V 0201 CRITICAL GYRO_INVENSENSE1
C2726CAP 0.01UF 25V 0201132S0391 CRITICAL GYRO_STMICRO1
U27201 GYRO_INVENSENSECRITICAL338S1218
TOS,19NM,PPN1.5,C,QDP,32GB335S0922 32GB1 U1400
1 U1400 64GB335S0923 TOS,19NM,PPN1.5,C,ODP,64GB
CRITICAL EEEE_X200C_BETTER_IVSFNJFEEEE FOR 639-5389 (X200C1 BETTER IVS)1825-7639
CRITICAL GYRO_STMICRO338S1192 1 GYRO, ST MICRO U2720
U0652H6P + 1GB ELPIDA339S0207 1 CRITICAL
HYNIX DDRU0652339S0207339S0208
335S0923 HYNIX 20NM PPN1.5 64GB64GB U1400335S0932
335S0931 335S0922 HYNIX 20NM PPN1.5 32GB32GB U1400
U140016GB HYNIX 20NM PPN1.5 16GB335S0921335S0930
U14001 TOS,19NM,PPN1.5,C,16DP,128GB 128GB335S0924
EEEE FOR 639-5391 (X200C1 BEST+ IVS) EEEE_X200C_BEST+_IVSFNJ7 CRITICAL1825-7639
EEEE_X200C_ULTIMATEFNJ6EEEE FOR 639-5387 (X200C1 ULTIMATE)825-7639 1 CRITICAL
EEEE_X200C_BESTFNJ9EEEE FOR 639-5385 (X200C1 BEST)825-7639 1 CRITICAL
EEEE_X200C_BETTERFNJ5EEEE FOR 639-5394 (X200C1 BETTER) CRITICAL825-7639 1
EEEE_X200C_GOODFNJDEEEE FOR 639-5393 (X200C1 GOOD)1 CRITICAL825-7639
EEEE_X200C_GOOD_IVSFNJ8EEEE FOR 639-5388 (X200C1 GOOD IVS)825-7639 CRITICAL1
EEEE_X200C_ULTIMATE_IVSFNJGEEEE FOR 639-5392 (X200C1 ULTIMATE IVS) CRITICAL1825-7639
EEEE_X200C_BEST_IVSFNJCEEEE FOR 639-5390 (X200C1 BEST IVS) CRITICAL1825-7639
EEEE_X200C_BEST+FNJHEEEE FOR 639-5386 (X200C1 BEST+)825-7639 1 CRITICAL
U14001 16GB335S0921 TOS,19NM,PPN1.5,C,DDP,16GB
U2200IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8353S4272 1
GYRO, INVENSENSE
051-0886
A.0.0
4 OF 121
3 OF 54
-
SYM 1 OF 13
HSIC2_STB
USB_VSSA0
USB_ANALOGTEST
TESTMODE
USB_DP
USB_DM
WDOG
TST_CLKOUT
FAST_SCAN_CLK
USB_REXT
USB_VBUS
USB_ID
JTAG_SEL
JTAG_TRST*
JTAG_TDO
JTAG_TDI
HSIC_VSS120
JTAG_TCK
JTAG_TMS
JTAG_TRTCK
XI0
XO0
HSIC0_DATA
HSIC0_STB
HSIC2_DATA
HSIC_VSS121
HSIC_VSS122
RESET*
CFSB
HOLD_RESET
FUSE1_FSRC
HSIC1_DATA
HSIC1_STB
USB_VDD330
USB_DVDD
VDD_ANA_PLL_CCC
ANALOGMUXOUT
HSIC_VDD120
HSIC_VDD122
HSIC_VDD121
VDD_ANA_PLL
IN
BI
BI
OUT
IN
IN
IN
BI
BI
BI
BI
IN
IN
IN
IN
TP
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
H6P: JTAG, USB, PLL, HSIC, XTAL
USBHS ON/OFF TOLERANCE 5V/1.98V
NOTE: NEW USB_REXTVALUE FOR H6 = 200 OHM
TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD
OLD (H5) VALUE: 44.2 OHM
(REPLACE WITH XW LATER?)NOTE: CANDIDATE FOR COST-SAVINGS
(25MA)
(25MA)
(5.4MA)(6X 1MA)
(1MA)
VDDIO18_GRP4
VDDIO18_GRP1
(3X 13MA)
HSIC_VDD120
HSIC_VDD122
HSIC_VDD121
VDDIO18_GRP3
1.8V TOLERANT
C063020%0.1UF
01005X5R-CERM6.3V
R0642
MF
1%
01005
2001/32W
R0622010050.00
C0608
X5R
10%0.01UF6.3V
01005
C064810%
X5R6.3V
0.01UF
0100501005
0.1UF20%
C0651
6.3VX5R-CERM
C06900.22UF
6.3V20%
X5R0201
U0652H6P
FCMSP
POP-1GB-DDR
OMIT
C060712PF
16VCERM01005
5%
100K1%
R0617
01005MF1/32W
C061810%6.3VX5R-CERM01005
1000PF
R065168.1K
1/32WMF
1%
01005
46
11 52
11 52
10
8 10 11 24 48 52
10 52
C0613
5%16VCERM
12PF
01005
10 52
100KR06471%
01005MF1/32W
R0646
1/32WMF01005
1%100K
1/32WMF01005
1%100KR0645
44 53
44 53
24 27 53
24 27 53
4 11 52
4 11 52
Y06021.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
10
4 52
TP-P55
TP0600
10
10 52
C06910.22UF
6.3V20%
X5R0201
R0655
01005
1%1/32W
MF
1.00M
MF1/32W
1%01005
R06401.33K
C0627
6.3V10%
01005
0.01UF
X5R
SOC: MAINSYNC_DATE=04/18/2011SYNC_MASTER=N/A
=PP1V8_SOC
=PP1V0_USB_SOC
XTAL_SOC_24M_I
XTAL_SOC_24M_O
=PP3V3_USB_SOC
PP1V8_PLL_SOC_F
=PP1V2_HSIC_SOC
RESET_SOC_L
SOC_24M_O
USB_VBUS_DETECT
USB_REXT
=PP1V8_PLL_SOC
NC_USB_ANALOGTEST
SOC_TESTMODE
USB_SOC_P
USB_SOC_N
WDOG_SOC
SOC_TEST_CLKOUT
SOC_FAST_SCAN_CLK
USB_VBUS_DETECT_R
NC_USB_ID
TP_JTAG_SOC_TDO
NC_JTAG_SOC_TRTCK
NC_HSIC0_DATA
NC_HSIC0_STB
NC_ANALOGMUXOUT
JTAG_SOC_SEL
JTAG_SOC_TMS
JTAG_SOC_TDI
JTAG_SOC_TCK
SOC_HOLD_RESET
JTAG_SOC_TCK
JTAG_SOC_TMS
JTAG_SOC_TDI
=PP1V8_SOC
MAKE_BASE=TRUE
HSIC2_WLAN_STB
HSIC2_BB_STB
HSIC2_BB_DATA
HSIC1_WLAN_STB
MAKE_BASE=TRUE
HSIC1_BB_DATA
JTAG_SOC_TRST_L
HSIC1_BB_STBMAKE_BASE=TRUE
HSIC2_WLAN_DATAMAKE_BASE=TRUE
HSIC1_WLAN_DATA
6 OF 121
A.0.0
4 OF 54
051-0886
2
1
1
2
1 2
2
1
2
1
2
1
2
1
AM34
H23
D26
AB3
B29
A29
AD4
AC3
AD3
E23
D23
E24
D28
E28
E27
F27
H20
C28
F28
D27
F25
E25
A26
B26
AM33
H21
AM32
F29
E29
D29
H16
A27
B27
F23
F24
AE20
E26
G22
AM31
G23
U16
1 2
1
2
2
1
1 2
1
2
1
2
1
2
42
13
2
1
1
2
1 2
2
1
4 5 7 10 18 54
54
54
52
54
54
52
4 11 52
4 11 52
4 52
4 5 7 10 18 54
-
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
BI
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
SYM 2 OF 13GPIO4
UART6_TXD
UART6_RXD
UART5_RTXD
UART4_RTSN
UART4_CTSN
UART3_RXD
UART3_RTSN
UART3_CTSN
UART2_TXD
UART2_RXD
UART2_RTSN
UART2_CTSN
UART1_TXD
UART1_RXD
UART1_RTSN
UART1_CTSN
UART0_TXD
UART0_RXD
TMR32_PWM2
TMR32_PWM1
TMR32_PWM0
GPIO8
GPIO7
GPIO6
GPIO5
GPIO38
GPIO37
GPIO36
GPIO35
GPIO34
GPIO33
GPIO32
GPIO31
GPIO3
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO2
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO1
GPIO0
UART4_RXDGPIO29
GPIO30
UART3_TXD
UART4_TXD
GPIO10
GPIO9
SPI3_SSIN
SPI3_MOSI
SPI3_MISO
SPI2_SSIN
SPI2_SCLK
SPI2_MOSI
SPI2_MISO
SPI1_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPI0_SSIN
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
SOCHOT1
SOCHOT0
SIO_7816UART1_SCL
SIO_7816UART1_RST
SIO_7816UART0_SCL
SEP_7816UART1_SCL
SEP_7816UART0_RST
I2S4_MCK
I2S4_LRCK
I2S4_DOUT
I2S4_DIN
I2S4_BCLK
I2S3_MCK
I2S3_LRCK
I2S3_DOUT
I2S3_DIN
I2S3_BCLK
I2S2_MCK
I2S2_LRCK
I2S2_DOUT
I2S2_DIN
I2S2_BCLK
I2S1_MCK
I2S1_LRCK
I2S1_DOUT
I2S1_DIN
I2S1_BCLK
I2S0_MCK
I2S0_LRCK
I2S0_DOUT
I2S0_DIN
I2S0_BCLK
I2C3_SDA
I2C3_SCL
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
DWI_DO
DWI_DI
DWI_CLK
SIO_7816UART0_SDA
SIO_7816UART0_RST
SEP_7816UART1_SDA
SEP_7816UART1_RST
SEP_7816UART0_SCL
SEP_7816UART0_SDA
SIO_7816UART1_SDA
SPI3_SCLK
DISP_VSYNC
SYM 3 OF 13
OUT
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
OUT
IN
BI
OUT
IN
OUTOUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
VDDIO18_GRP2
VDDIO18_GRP2
(SCREEN ROTATION LOCK)
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP2
VDDIO18_GRP1
SOC I/OS
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP1
VDDIO18_GRP1
PMUTRISTAR
SPK AMPS
PROXALS
R0700
1/32W5%2.2K
MF01005
MF01005
2.2K5%1/32W
R0701
MF01005
1.8K1/32W5%
R0702
MF01005
1.8K1/32W5%
R0703
01005MF
2.2K5%1/32W
R0705R0704
5%1/32W
2.2K
MF01005
13
13 52
13 52
13 52
220K
1/32WMF
5%
01005
R0771
220K
5%1/32WMF
01005
R0770
R0765
5%
MF1/32W
220K
01005
1/32W1%
MF01005
R0738100K
1/32W
100K1%
MF01005
R0737100K1/32W1%
01005MF
R0736R0735
01005
1%100K
MF1/32W
5 13 48
5 17 48
22
24 26 52
10
10
11 24 28 52
11 24 28 52
15
15
15
15
15 53
15 53
15
15
10
10
10
10
48 53
48 52
1%
MF01005
33.21/32W
R0720
15 53
10
10
10
17
17
5 17 48
10
45 48
16 53
16 53
16 53
16 53
15 53
15 53
15 53
15
1%1/32W
33.2
01005MF
R0721
16 53
5 48
48
10
13 52
13 52
44
44
44 53
44 53
11 52
11 52
19 48
19
19 53
19 53
44 53
24 28
24 28
10
19
13 52
24 27 52
24 27 52
24 27 52
24 27 52
24 27 52
11 52
11 52
FCMSP
H6PPOP-1GB-DDR
U0652
OMIT
CRITICAL
OMIT
H6P
FCMSP
POP-1GB-DDR
CRITICAL
U0652
13
5 51
5 51
5 16 52
5 11 48 52
5 19
5 16 52
5 19
5 11 48 52
5 48
R0751
1/32W5%2.2K
MF01005
R0750
01005MF
2.2K1/32W5%
R0753NOSTUFF
1/32W5%2.2K
MF01005
R0752NOSTUFF
01005MF
2.2K1/32W5%
100K
5%
MF1/32W
01005
R0754
1/32W
100K
01005MF
5%
R0755
44 53
44 53
10
10
10
15 52
28 52
20
24 28
5 52
19
24 26 52
18
11 48
16
28
28
5 16
R0739
1/32WMF
100K1%
01005
28
5 20 22
5 20 22
16
5 16 52 14
14
SYNC_DATE=05/05/2011SYNC_MASTER=N/A
SOC: I/OS
GPIO_SOC2BEACON_EN
GPIO_SOC2AJ_HS3_SHUNT_EN
DISPLAY_SYNC
GPIO_SOC2AJ_HS4_SHUNT_EN
=PP1V8_SOC
NC_SPI1_NAVAJO_MISO
NC_SPI1_NAVAJO_MOSI
NC_SPI1_NAVAJO_SCLK
NC_GPIO_NAVAJO2SOC_INT
GPIO_SPKAMP_RST_LGPIO_SOC2PMU_KEEPACT
HSIC1_SOC2WLAN_HOST_RDY
HSIC2_BB2SOC_REMOTE_WAKE
HSIC2_BB2SOC_DEVICE_RDY
HSIC2_SOC2BB_HOST_RDY
SOCHOT1_L
SOCHOT0_L
I2C2_SCL_1V8
GPIO_BTN_VOL_UP_L
HSIC1_SOC2WLAN_HOST_RDYGPIO_FORCE_DFUGPIO_SPKAMP_KEEPALIVE
HSIC1_WLAN2SOC_REMOTE_WAKE
NC_SEP_7816UART1_SDA
DWI_AP_DO
PMU_GPIO_OSCAR2PMU_HOST_WAKE
UART3_SOC2BB_TX
UART2_WLAN2SOC_TXUART2_SOC2WLAN_TX
UART1_SOC2BT_TXUART1_BT2SOC_TX
UART1_BT2SOC_RTS_LUART1_SOC2BT_RTS_L
UART0_SOC_RXD
GPIO_OSCAR_RESET_L
GPIO_BTN_VOL_DOWN_L
GPIO_BTN_ONOFF_L
UART0_SOC_TXD
UART3_BB2SOC_TXUART3_SOC2BB_RTS_LUART3_BB2SOC_RTS_L
SOCHOT1_L
=PP1V8_S2R_MISC
GPIO_BTN_SRL_L
I2C1_SOC2OSCAR_SWDIO_1V8I2C1_SOC2OSCAR_SWDCLK_1V8
=PP1V8_SOCGPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
=PP1V8_S2R_MISC
=PP1V8_ALWAYS
NC_SEP_7816UART0_RST
SEP_I2C0_SDA
HSIC1_WLAN2SOC_DEVICE_RDY
NC_SEP_7816UART1_SCL
I2C0_SCL_1V8
I2C1_SOC2OSCAR_SWDIO_1V8
I2C0_SDA_1V8
I2S2_CODEC_XSP_LRCKI2S2_CODEC_XSP_DIN
I2S1_SPKAMP_DOUT
I2S1_SPKAMP_MCK
I2S0_CODEC_ASP_LRCK
SPI2_CODEC_CS_LSPI2_CODEC_SCLKSPI2_CODEC_MOSISPI2_CODEC_MISO
SPI1_GRAPE_CS_LSPI1_GRAPE_SCLKSPI1_GRAPE_MOSI
NC_SPI0_SSIN
GPIO_BOARD_ID1
BB_JTAG_TCK
BB_JTAG_TDI
BB_JTAG_TMS
I2S3_SOC2BT_DATAI2S3_BT2SOC_DATA
I2S2_CODEC_XSP_BCLK
I2S0_CODEC_ASP_MCK_R
I2S0_CODEC_ASP_DOUTI2S0_CODEC_ASP_DIN
I2S0_CODEC_ASP_BCLK
OSCAR_TIME_SYNC_HOST_INTGPIO_BTN_SRL_L
GPIO_BTN_HOME_L
I2S0_CODEC_ASP_MCK
I2S2_CODEC_XSP_DOUT
I2S3_SOC2BT_BCLK
SPI1_GRAPE_MISO
GPIO_BOARD_ID0
I2S1_SPKAMP_LRCKI2S1_SPKAMP_DIN
UART6_TS_ACC_RXDUART6_TS_ACC_TXD
UART4_SOC2OSCAR_TXD
CLK_32K_SOC2CUMULUS
UART5_BATT_RTXD
UART4_OSCAR2SOC_RXD
NC_UART2_CTS
NC_UART2_RTS
I2C3_SDA_1V8I2C3_SCL_1V8
SEP_I2C0_SDASEP_I2C0_SCL
BB_JTAG_TDO
BB_JTAG_TRST_L
I2C2_SCL_1V8
I2C0_SDA_1V8I2C0_SCL_1V8
I2C2_SDA_1V8
TP_SOC_TST_CPUSWITCH_OUT
SEP_I2C0_SCL
NC_SEP_7816UART1_RST
I2S3_SOC2BT_LRCK
GPIO_BOARD_REV0GPIO_BOARD_REV1GPIO_BOARD_REV2GPIO_CODEC_IRQ_LGPIO_SOC2BB_WAKE_MODEM
GPIO_GRAPE_IRQ_LBB_IPC_GPIOGPIO_ALS_IRQ_LGPIO_BOARD_ID3GPIO_BB2SOC_RESET_DET_L
GPIO_BOOT_CONFIG0GPIO_PMU2SOC_IRQ_LGPIO_SOC2PMU_KEEPACTGPIO_GRAPE_RST_LGPIO_BB2SOC_GPS_SYNCGPIO_SOC2BB_RADIO_ON_L
GPIO_BOOT_CONFIG1GPIO_FORCE_DFUTP_GPIO_DFU_STATUS
GPIO_SOC2OSCAR_DBGEN
GPIO_BOOT_CONFIG2GPIO_BOOT_CONFIG3
GPIO_SOC2BB_RST_LGPIO_PROX_IRQ_L
GPIO_SPKAMP_RST_L
GPIO_TS2SOC2PMU_INTGPIO_SPKAMP_LEFT_IRQ_L
GPIO_SOC2LCD_PWREN
GPIO_BT_WAKE
GPIO_BB2SOC_GSM_TXBURST
I2C1_SOC2OSCAR_SWDCLK_1V8
GPIO_BOARD_ID2
I2C2_SDA_1V8
I2C3_SCL_1V8I2C3_SDA_1V8
DWI_AP_CLK
GPIO_SPKAMP_RIGHT_IRQ_L
GPIO_SPKAMP_KEEPALIVE
NC_GPIO_BB_HSIC_DEV_RDY
NC_GPIO_GYRO_IRQ1
I2S1_SPKAMP_BCLKI2S1_SPKAMP_MCK_R
=PP1V8_S2R_MISC
SOCHOT0_L
051-0886
A.0.0
7 OF 121
5 OF 54
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
1 2
1 2
AD5
Y31
W31
AM5
AU3
AV3
AP1
AN4
AN3
AM1
AM2
AM3
AL5
AK3
AK4
AL4
AL2
AR18
AR19
AC32
AD34
AC31
AE5
AE2
AF1
AE4
AT17
AT16
AR16
AP16
AT15
AT14
AR14
AP15
AD1
AV13
AT13
AT12
AN14
AR13
AP12
AP13
AK2
AJ4
AB2
AJ5
AG5
AH4
AH2
AH3
AG4
AG3
AG1
AF2
AB1
AC5
AT3AP14
AU13
AN1
AT2
AF4
AF3
AP11
AN12
AV10
AN8
AP7
AR6
AU6
AR5
AU4
AV4
AU5
AV5
AT5
AP5
AN6
AP17
AP18
AA32
AA33
AA31
AR2
AR1
AE31
AE32
AE33
AD31
AF33
AG31
AH33
AG34
AF31
AG32
E30
AJ34
AH34
AH31
AJ33
AL33
AK33
AK34
AJ32
AL34
C30
AL31
AK31
AJ31
AL32
W32
W30
AR11
AT11
AU7
AP8
AR7
AV6
AT19
AT18
AP19
AB31
AB33
AP4
AR4
AP3
AP2
AA34
AT10
AN17
1
2
1
2
1
2
1
2
1 2
1 2
1
2
4 5 7 10 18 54
5 16
5 48
5 44 53
28
24 28
24 28
5 49 52
5 44 53
5 52
5 16 52
44 53
5 48
5 51 54
5 17 48
5 19
5 19
4 5 7 10 18 54 5 13 48
5 17 48
5 51 54
54
44 53
5 20 22
5 20 22
5 51
5 51
5 16 52
5 11 48 52
5 11 48 52
5 16 52
5 51 54
5 49 52
-
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
OUT
OUT
OUT
OUT
PPN0_ALE
PPN0_CEN0
PPN0_CEN1
PPN0_CLE
PPN0_DQS
PPN0_IO0
PPN0_IO1
PPN0_IO2
PPN0_IO3
PPN0_IO4
PPN0_IO5
PPN0_IO6
PPN0_IO7
PPN0_REN
PPN0_VREF
PPN0_WEN
PPN0_ZQ
PPN1_ALE
PPN1_CEN0
PPN1_CEN1
PPN1_CLE
PPN1_IO0
PPN1_IO1
PPN1_IO2
PPN1_IO3
PPN1_IO4
PPN1_IO5
PPN1_IO6
PPN1_REN
PPN1_VREF
PPN1_WEN
PPN1_ZQ
PPN1_DQS
PPN1_IO7
SYM 4 OF 13
VSS
VSS
SYM 11 OF 13
VSSVSS
SYM 12 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
VDDIO18_GRP3
12 52
12
12
12
12
12
12
12
12 53
12
12
12
12
100K1/32W1%
MF01005
R0831
MF
R0832
100K1%1/32W
01005
12 52
12
12
12
12
12
12
12
12
12 53 12
12
12
12
12
10%0.01UF
X5R01005
6.3V
C0860
C0861
10%0.01UF
X5R01005
6.3V
R086050K
MF1/32W
01005
1%
R086150K
MF1/32W1%
01005
U0652
POP-1GB-DDRH6P
FCMSP
OMIT
CRITICAL
01005
R0870
1%
240
1/32WMF
01005
R0871
1%
240
MF1/32W
FCMSPPOP-1GB-DDR
H6PU0652
OMIT
CRITICAL
FCMSPPOP-1GB-DDR
H6PU0652
OMIT
CRITICAL
SYNC_DATE=04/18/2011SYNC_MASTER=N/A
SOC: NAND
NC_PPN1_CEN1NC_PPN0_CEN1
FMI1_CE0_L
PPVREF_FMI_SOC
FMI0_AD
FMI0_AD
FMI0_CE0_L
FMI0_WE_L
FMI0_ADFMI0_ADFMI0_AD
FMI0_ADFMI0_AD
FMI0_DQS
FMI0_ALE
FMI1_ADFMI1_AD
FMI1_AD
FMI1_ADFMI1_AD
FMI1_ADFMI1_ADFMI1_AD
FMI1_CLEFMI1_ALE
FMI1_DQS
=PP1V8_NAND_SOC
FMI0_ZQ FMI1_ZQ
FMI1_WE_LFMI1_RE_LFMI0_RE_L
FMI0_CLE
FMI0_AD
=PP1V8_NAND_SOC
051-0886
A.0.0
8 OF 121
6 OF 54
1
2
1
2
2
1
2
1
1
2
1
2
A31
G32
H31
B31
D34
B32
C32
C33
C34
F32
F33
F34
G34
D33
D31
A32
E33
N34
R32
P32
P31
M34
M33
L32
M32
K32
J32
H33
L31
N31
N32
K33
L34
H34
1 2 1 2
A11
A1
AA3
AF29
AJ30
A3
A4
A5
A7
A9
A13
A14
A16
A18
A25
A28
A30
A33
A34
AA1
AA2
AA4
AA8
AA10
AA12
AA14
AA16
AA18
AA22
AA24
AA26
AA28
AA30
AB5
AB7
AB9
AB11
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AB29
AB32
AC4
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AC30
AC34
AD2
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD25
AD29
AD32
AE3
AE8
AE10
AE12
AE16
AE18
AE22
AE24
AE26
AE28
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF32
AG2
AG8
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AG30
AH5
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AH29
AH32
AJ1
AJ3
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ22
AJ24
AJ26
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK32
AL3
AL6
AL8
AL10
AL12
AL14
AL16
AL18
AL20
AL22
AL24
AL26
AL28
AL30
AM4
AM7
AM18
AM30
AN2
AN5
AN7
AB6
AM9
AM11
AM13
AN16
AM15
AN19
AN20
AN21
AN22
AN23
AN24
AJ28
A2
AB13
AE14
AN31
AP25
AP26
E10
E11
E12
G28
G26
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G1
F31
F30
F26
F15
F14
F13
F12
F10
F9
F8
F7
F6
F5
F4
F3
F2
E34
E32
E31
E22
E21
E20
E19
E18
E15
E14
E13
E8
E7
E5
E4
E3
E1
D22
D21
D20
D19
D18
D17
D15
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C31
C29
C27
C26
C23
C22
C19
C18
C17
C16
C15
C13
C11
C10
C9
C7
C6
C5
C3
C2
C1
B34
B33
B30
B28
B25
B19
B18
B17
B16
B15
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B2
B1
AV34
AV33
AV20
AV18
AV16
AV14
AV11
AV9
AV2
AV1
AU34
AU33
AU21
AU18
AU16
AU11
AU2
AU1
AT32
AT31
AT30
AT29
AT28
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
AT6
AT4
AT1
AR32
AR20
AR17
AR15
AR12
AR8
AR3
AP28
AP27
AP24
AN33
AN32
AR29
AR28
AR25
AR24
AR22
AR21
E9
C12
AP21
AP20
AP6
AN34
AP32
AR23
E6
C24
AP30
AP31
D32
D16
AP29
6 54
6 54
-
OUT
OUT
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
IN
IN
IN
IN
DP_PAD_AUXN
DP_PAD_AUXP
DP_PAD_AVDD_AUX
DP_PAD_AVDD0
DP_PAD_AVDD1
DP_PAD_AVDD2
DP_PAD_AVDD3
DP_PAD_AVDDP0
DP_PAD_AVDDX
DP_PAD_AVSS_AUX
DP_PAD_AVSS0
DP_PAD_AVSS1
DP_PAD_AVSS2
DP_PAD_AVSS3
DP_PAD_AVSSP0
DP_PAD_AVSSX
DP_PAD_DC_TP
DP_PAD_DVDD
DP_PAD_DVSS
DP_PAD_R_BIAS
DP_PAD_TX0N
DP_PAD_TX0P
DP_PAD_TX1N
DP_PAD_TX1P
DP_PAD_TX2N
DP_PAD_TX2P
DP_PAD_TX3N
DP_PAD_TX3P
EDP_HPD
SYM 6 OF 13
MIPI0C_DPDATA0
SENSOR1_RST
SENSOR1_CLK
MIPI1C_DPDATA0
SENSOR0_RST
SENSOR0_ISTRB
SENSOR0_CLK
MIPI1D_VREG_0P4V
MIPI1D_VDD18
MIPI1C_DPDATA1
MIPI1C_DPCLK
MIPI1C_DNDATA1
MIPI1C_DNDATA0
MIPI1C_DNCLK
MIPI0D_VREG_0P4V
MIPI0D_VDD18
MIPI0D_DPCLK
MIPI0D_DNCLK
MIPI0C_DPDATA2
MIPI0C_DPDATA1
MIPI0C_DNDATA2
MIPI0C_DNDATA1
MIPI_VSS
ISP0_SDA
ISP0_SCL
ISP1_SCL
MIPI0C_DPDATA3
MIPI0C_DNDATA3
MIPI0C_DPCLK
MIPI0D_DNDATA3
MIPI0D_DPDATA3
MIPI0D_DNDATA2
MIPI0D_DPDATA2
MIPI0D_DNDATA1
MIPI0D_DPDATA1
MIPI0C_DNCLK
MIPI0D_DPDATA0
MIPI0D_DNDATA0
MIPI_VDD10
SENSOR1_ISTRB
MIPI0C_DNDATA0
ISP1_SDA
SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN
SYM 5 OF 13
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(2MA)
(2MA)
(55MA)
VDDIO18_GRP1
VDDIO18_GRP1
MIPI_VDD10
(50MA)
(50MA)
(1MA)
(50MA)
(14MA)
(50MA)
VDDIO18_GRP3
(14MA)
(10MA)
DISPLAYPORT
20 52
20 52
20 52
20 52
20 53
20 53
R094049.901005
01005
5%2.2K1/32WMF
R0932
1/32W
R0933
01005
5%2.2K
MF
20 53
20 53
R094101005100
23 52
23 52
01005
5%2.2K1/32WMF
R0931
01005
2.2K5%1/32WMF
R0930
23 52
23 52
23 53
23 53
23 53
23 53
23 53
23 53
CRITICAL
OMIT
U0652
FCMSPPOP-1GB-DDR
H6P
C096220%0.1UF
X5R-CERM6.3V
01005
20%
0204
1UF4VX6S
C0930
CRITICAL
OMIT
U0652
POP-1GB-DDRH6P
FCMSP
C09571.0UF
0201-1
6.3VX5R
20%
18 53
18 53
18 53
18 53
18 53
18 53
18
18
18
18 53
18 53
R0900
01005MF1/32W
4.99K1%
NOSTUFF
01005
6.3VX5R
0.01UF10%
C0950
C0958
01005
16VNP0-C0G-CERM
8.2PF+/-0.5PF
1/32W0%
0.00
MF
R0901
01005C0951
16V
01005
5%56PF
NP0-C0G
C0952
01005
16VNP0-C0G-CERM
8.2PF+/-0.5PF
01005NP0-C0G
C095356PF5%16V
0201
20%
X5R6.3V
C09540.22UF
C0955
0201-1
6.3VX5R
1.0UF20%
C0956
0201-1
6.3VX5R
1.0UF20%
SOC: DP,MIPISYNC_MASTER=MLB SYNC_DATE=05/04/2012
=PP1V8_MIPI_SOC
NC_MIPI1D_VREG
NC_MIPI0D_VREG
NC_SENSOR1_XSHUTDOWN
NC_SENSOR1_ISTRB
NC_SENSOR0_ISTRB
NC_SENSOR0_XSHUTDOWN
NC_MIPI0C_CAM_REAR_DATA_P2
NC_MIPI0C_CAM_REAR_DATA_N2
MIPI0C_CAM_REAR_DATA_P
EDP_DATA_P
PP1V8_EDP_AVDD_AUX
=PP1V8_SOC
ISP0_CAM_REAR_SCLISP0_CAM_REAR_SDA
ISP0_CAM_REAR_CLK
ISP1_CAM_FRONT_CLK_R
MIPI1C_CAM_FRONT_DATA_P
ISP0_CAM_REAR_CLK_R
NC_MIPI1C_CAM_FRONT_DATA_P1
MIPI1C_CAM_FRONT_CLK_P
NC_MIPI1C_CAM_FRONT_DATA_N1
MIPI1C_CAM_FRONT_DATA_N
MIPI1C_CAM_FRONT_CLK_N
NC_MIPI0D_DPCLK
NC_MIPI0D_DNCLK
MIPI0C_CAM_REAR_DATA_PMIPI0C_CAM_REAR_DATA_N
NC_MIPI0C_CAM_REAR_DATA_P3
NC_MIPI0C_CAM_REAR_DATA_N3
MIPI0C_CAM_REAR_CLK_P
NC_MIPI0D_DNDATA3
NC_MIPI0D_DPDATA3
NC_MIPI0D_DNDATA2
NC_MIPI0D_DPDATA2
NC_MIPI0D_DNDATA1
NC_MIPI0D_DPDATA1
MIPI0C_CAM_REAR_CLK_N
NC_MIPI0D_DPDATA0
NC_MIPI0D_DNDATA0
MIPI0C_CAM_REAR_DATA_N
=PP1V0_MIPI_SOC
=PP1V8_EDP_SOC
SOC_EDP_R_BIAS
EDP_AUX_N
EDP_AUX_P
TP_EDP_PAD_DC_TP
EDP_DATA_N
EDP_DATA_P
EDP_DATA_N
EDP_DATA_N
EDP_DATA_P
EDP_DATA_N
EDP_DATA_P
EDP_HPD
ISP1_CAM_FRONT_SDAISP1_CAM_FRONT_SCL
ISP0_CAM_REAR_SHUTDOWN_L
ISP1_CAM_FRONT_CLKISP1_CAM_FRONT_SHUTDOWN_L
=PP1V0_EDP_PAD_DVDD_SOC
051-0886
A.0.0
9 OF 121
7 OF 54
1 2
1
2
1
2
1 2
1
2
1
2
B20
A20
F18
F19
F20
F21
F22
G18
F17
G17
H19
G19
G20
G21
H18
H17
E16
F16
G16
E17
B21
A21
B22
A22
B23
A23
B24
A24
D30
2
1
2
1
AU27
AT9
AU9
AT33
AN28
AT8
AN10
AV8
AR30
AR31
AP33
AR33
AP34
AT34
AR34
AR27
AR26
AU30
AV30
AU24
AU26
AV24
AV26
AM28
AM27
AM26
AM25
AN29
AV7
AT7
AU8
AU23
AV23
AU25
AV28
AU28
AV29
AU29
AV31
AU31
AV25
AU32
AV32
AN25
AN26
AN27
AM29
AL25
AR10
AV27
AP9
AR9
AP10
2
1
1
22
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
54
4 5 10 18 54
54
54
54
-
DDR1_VREF_CA
DDR0_VREF_CA
DDR1_RREF_DQ
VSS
DDR0_CKEIN
DDR0_VDD_CKE
DDR1_RREF_CA
DDR0_RREF_CA
DDR0_RREF_DQ
DDR0_VREF_DQ
DDR1_VREF_DQ
VDDCA
VDD2
VDD1
VDDQ
DDR1_VDD_CKE
DDR1_CKEIN
SYM 7 OF 13
VDDIOD_DDR1CA
VDDIOD_DDR0CA
VDDIO18_GRP4
VSS
VDDIO18_GRP2
VDDIO18_GRP1
VDDIOD_DDRDQ
VDDIO18_GRP3
SYM 9 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(DDR IMPEDANCE CONTROL)
ON 5/6/12, BY MANU GNOTE: CKEIN CONFIRMED 1.8V TOLERANT
CAPS FOR VDDIOD ARE SHARED WITH VDDQ
(45MA)
(500MA)
SHARED WITH VDDIOD)(CURRENT CONSUMPTION
(CURRENT CONSUMPTIONSHARED WITH VDDIOD)
(
-
VDD_SENSE
VDDVDD
SYM 10 OF 13
SYM 8 OF 13
VDD_ANA_TMPSADC0
VDD_ANA_TMPSADC1
VDD_ANA_TMPSADC2
VDD_ANA_TMPSADC3
VDD_SRAM_SOC
VSS
VDD_SRAM_CPU
VDD_GPUVDD_CPU
VDD_GPU_SENSE
VDD_SENSE_CPU
SYM 13 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(VDD BALLS = VDD_SOC PWR DOMAIN)
7,500MA FOR G3 GPU
@[email protected]/1.2GHZ
10,800MA FOR CPU0+1
@1.1V@125C
(2.5MA)
(2.5MA)
(2.5MA)
(2.5MA)
(1500MA)
1,500MA FOR CYCLONE + M$ SRAM
(THERMAL VIRUS)@1.0V@125C2,500MA FOR VDD_SOC
POP-1GB-DDRH6P
FCMSP
U0652
OMIT
CRITICAL
20%4V
0610
4.3UF
X5R-CERM
C1148
20%
C11511UF4VX6S0204
4V
0.47UF20%
C1153
X7S0204
0204X6S
C11501UF20%4V
X7S4V20%
0204
C11520.47UF
FCMSPPOP-1GB-DDR
H6PU0652
OMIT
CRITICAL
C116020%0.1UF
01005
6.3VX5R-CERM
OMIT
POP-1GB-DDRH6P
U0652
CRITICAL
FCMSP
CRITICALC1103
4VX5R-CERM
4.3UF
0610
20%
C1102
X5R-CERM
4.3UF
0610
20%4V
CRITICALC1101
4V20%
X5R-CERM
4.3UF
0610
CRITICALCRITICALC1100
0610
20%4VX5R-CERM
4.3UF
C1109CRITICAL
0204X6S4V20%1UF
C1114+/-0.5PF8.2PF
01005NP0-C0G-CERM16V
C1108CRITICAL
1UF20%4VX6S0204
C1107CRITICAL
1UF20%4VX6S0204
0201
0.22UF20%
X5R6.3V
C1113
C110620%1UF4V
0204X6S
CRITICAL
4V20%1UFC1105
0204X6S
CRITICAL
0201
0.22UF20%
X5R6.3V
C1112C11110.47UF20%
0204X7S4V
CRITICAL
0204X6S
20%
C11041UF4V
CRITICAL
0204
20%0.47UFC1110CRITICAL
X7S4V
C1118CRITICAL
4VX5R-CERM0610
4.3UF20%
C1117CRITICAL
4.3UF4V20%
0610X5R-CERM
C1122
4V20%
X5R-CERM
4.3UF
0610
CRITICALC112620%1UF4V
0204X6S
CRITICALC1121CRITICAL
4V20%
X5R-CERM
4.3UF
0610
C11251UF20%4VX6S0204
CRITICAL
C111620%
X5R4V
0402
15UFC111520%
X5R4V
0402
15UF 4.3UF
0610X5R-CERM
20%4V
CRITICALC1120
C112420%1UF4VX6S0204
CRITICAL
4.3UF
X5R-CERM0610
20%4V
CRITICALC1119
C112320%1UF4V
0204X6S
CRITICAL
C113020%1UF4VX6S0204
CRITICALC112920%1UF4VX6S0204
CRITICAL
C1134
01005
8.2PF
NP0-C0G-CERM16V+/-0.5PF
0201
0.22UF20%
C1133
6.3VX5R
C112820%1UF4V
0204X6S
CRITICALC11271UF20%4V
0204X6S
CRITICALC1132CRITICAL
0204X6S4V20%1UF
C1131CRITICAL
0204X6S4V20%1UF
C1138
4V
0204
0.47UF20%
CRITICAL
X7S
0.47UF4V20%
0204
CRITICALC1142
X7S
C1137
4V20%
0204
0.47UF
CRITICAL
X7S
CRITICAL
4V20%
0204
C11410.47UF
X7S0201
6.3VX5R
C11450.22UF20%
C113620%
0204
4V
0.47UF
CRITICAL
X7S
C1140CRITICAL
4V
0204
0.47UF20%
X7S
20%
CRITICALC11350.47UF4VX7S0204
C1139CRITICAL
20%0.47UF
0204
4VX7S
01005
20%6.3VX5R
0.22UFC1144
01005
20%6.3V
0.22UF
X5R
C1143
CRITICALC1187
X7S4V20%0.47UF
0204
CRITICALC118620%4V
0204
0.47UF
X7S
CRITICALC11850.47UF20%
0204X7S4V
CRITICALC118420%
0204X7S4V
0.47UF
CRITICALC1183
0204
4V
1UF20%
X6S
CRITICALC1182
4V
1UF20%
X6S0204
C11948.2PF+/-0.5PF
01005NP0-C0G-CERM16V
0.22UF
X5R6.3V20%
01005
C1193C1192
01005
20%6.3VX5R
0.22UFC1191
01005
20%6.3VX5R
0.22UFC1190
01005
20%6.3VX5R
0.22UF
CRITICAL
20%1UF4V
0204X6S
C1181
CRITICAL
20%
0204
1UF4VX6S
C1180CRITICAL
20%1UF4VX6S
C1179
0204
CRITICAL
X6S4V20%1UF
0204
C1178CRITICAL
0610
4V20%
X5R-CERM
4.3UFC1177
CRITICAL
4VX5R-CERM
4.3UF
0610
20%
C1176CRITICAL
20%
X5R-CERM
4.3UF
0610
4V
C1175CRITICAL
4.3UF
0610
4V20%
X5R-CERM
C1174CRITICAL
4V20%4.3UF
0610X5R-CERM
C1173CRITICAL
X5R-CERM4V20%4.3UF
0610
C117215UF
0402
4VX5R
20%
C117115UF
0402
4V20%
X5R
C1170
0.47UF
0204
4VX7S
20%
C1189CRITICAL
0204
4VX7S
20%0.47UF
CRITICALC1188
SOC: VDD, SRAM, CPU, GPU PWRS
SYNC_MASTER=N/A SYNC_DATE=04/18/2011
=PPVDD_CPU
=PPVDD_GPU
PPVDD_CPU_SOC_SENSE
PPVDD_GPU_SOC_SENSE
=PP1V8_VDDIO18_SOC
=PPVDD_SRAM_SOC
PPVDD_SOC_SOC_SENSE
=PPVDD_SOC
051-0886
A.0.0
11 OF 121
9 OF 54
P20
P22
K10
K8
K18
K16
K14
K12
K6
J29
J27
J23
J21
J19
J17
J15
J13
J11
AK6
AK20
R7
V31
R17
U23
R25
V22
J25
N27
N17
N15
N13
AN11
Y20
Y18
Y16
W19
W17
W7
V28
V26
V24
V20
V18
V16
V14
U27
U25
U21
U19
U17
U7
T28
T26
T24
T22
T20
T18
T16
T14
R27
R23
R21
R19
R15
R13
P28
P24
P18
P16
P14
P12
P10
P8
N29
N25
N23
N21
N19
N11
N9
N7
M26
M24
M22
M20
M18
M16
M14
M12
M10
L27
L25
L23
L21
L19
L17
L15
L13
L11
L9
L7
K28
J9
J7
H28
H24
AN9
AL23
AK30
AN18
AF30
AF20
AF6
AE21
AN15
AD20
AN13
AB20
AB14
AA17
K20
AA7
U15
P26
M28
L29
AA19
R11
R9
K26
K24
K22
H26
AH20
AB30
M8
2
1
2
1
2
1
2
1
2
1
R28
R30
R31
AJ20
AA20
AB4
H22
AA9
AA11
AA13
AA15
AB8
T10
T12
U11
L4
L5
L6
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
L30
L33
M1
M2
M3
M4
M5
M7
M9
M11
M13
M15
M17
M19
M21
N3
N5
N8
N10
N12
N14
N16
N18
N20
N22
N24
N26
N28
N30
P1
P2
P3
P4
P7
P9
P11
P13
P17
P19
P21
P23
P25
P27
P29
R2
R3
R4
R5
R8
R10
R16
R18
R24
R26
T8
U9
W13
V10
V8
U13
W15
W11
W9
V12
Y8
AD24
AD26
AD28
AE23
AE25
AE27
AF24
AF26
AF28
AK25
Y25
M23
M25
M27
M29
M31
N2
N4
N33
P5
P15
R12
R22
R14
R20
Y14
Y12
Y10
2
1
AL29
AL9
AL7
AL19
AC29
AD22
AL13
AL11
AK8
AK14
AK10
AJ9
AJ19
AJ17
AJ15
AH8
AH16
AH12
AG13
AB18
AF8
AF18
AF10
AE9
AE7
AE19
AE17
AB16
AE13
AE11
AD8
AD18
AD16
AD14
AD12
AD10
AB10
AB26
AB24
Y28
Y26
Y24
Y22
W27
W25
W21
AA29
AL27
AL21
AK28
AJ29
AJ25
AJ23
AA27
AJ21
AH26
AH24
AH22
AG21
AB12
AC9
AC19
AF27
AF25
AC27
AC25
AB28
AC23
AC21
AE15
AG9
AG7
AC11
AA25
AA23
AC17
AC15
AC13
AF12
AF14
AF16
AG23
AG27
AF22
AE29
AD27
AK12
AJ7
AJ13
AH18
AH14
AH10
AG15
AC7
AA21
AB22
AG11
AG17
AJ11
AK16
AK18
AL15
AL17
AA5
AM6
AN30
AG19
AG25
AG29
AH28
AJ27
AK22
AK24
AK26
W29
W23
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
54
54
53
8 54
54
53
54
-
OUT
CLK
RESET
DETGND
GND
GND
GND
GND
GND
I/O
DETECT
VCC VPP
OUT
BIIN
IN
SCHEMATIC DEFINED CONSTRAINTS (YES/NO)
CKPLUS RULE EXCEPTIONSTABLE_DASHBOARD_INFO
REQUIRED
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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D
8 7 6 5 4 3
C
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A
NOTICE OF PROPRIETARY PROPERTY:
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IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
EVT101
BOARD_ID[1]
MLB_C
SIM CARD
SPI0 TEST MODE
MLB
BOARD REVISION
S/W READ FLOW
2. DISABLE PU AND ENABLE PD
1. SET GPIO AS INPUT
BOARD_ID[0]
ID[3-0] SYSTEM
1. SET GPIO AS INPUT
BOOT_CONFIG[3-0]
2. DISABLE PU AND ENABLE PD
BOOT_CONFIG[3] (GPIO29)
S/W READ FLOW
BOOT_CONFIG[0] (GPIO18)
BOOT_CONFIG[2] (GPIO28)
BOARD ID
3. READ
BOARD_ID[3]
BOARD_ID[2]
BRD_REV[2-0]
3. READ
1. SET GPIO AS INPUT
S/W READ FLOW
3. READ
BOOT_CONFIG[1] (GPIO25)
BOOT CONFIG ID
1010 J85 AP1011 J85 DEV
1100 J86 AP1101 J86 DEV
1110 J87 AP1111 J87 DEV
MLB_B
0000
0010
JTAG
SPI0
0011
0001
2. ENABLE PU AND DISABLE PD
NAND
-
OUT
IN
OUT
OUT
OUT
DIG_DP
DVSS
DVSS
DVSS
DIG_DN
USB1_DP
USB1_DN
USB0_DP
UART0_TX
USB0_DN
UART1_TX
UART0_RX
UART2_TX
UART1_RX
JTAG_CLK
UART2_RX
JTAG_DIO
ACC_PWR
VDD_3V0
VDD_1V8
P_IN
ACC1
ACC2
DP1
DN1
DP2
DN2
CON_DET_L
HOST_RESET
SWITCH_EN
SDA
INT
SCL
BYPASS
POW_GATE_EN*
BRICK_ID
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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REVISION
BRANCH
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THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
343S0658 = TRISTAR 2, A1
TRISTAR
343S0614 = TRISTAR 1
TO USB BB MUX
(T’S OFF TO H4A UART4)
AP USB
ACCESSORY UART
AP DEBUG UART
TRISTAR BYPASS FOR 3V LDO
BB DEBUG UART
343S0639 = TRISTAR 2, A0 998-5855 = TRISTAR 2, TC
46
4 8 10 24 48 52
48
CRITICALC13031.0UF
X5R-CERM10V20%
0201-1
0.1UF6.3V
C1302
10%
CERM-X5R0201
0.1UF
X5R-CERM
C1300
01005
6.3V20%
0.1UF20%6.3VX5R-CERM01005
C1301
5 48
+/-0.5PF16V
01005
8.2PFC1321
NP0-C0G-CERM
C1320
16V
01005NP0-C0G-CERM
8.2PF+/-0.5PF
C1322
16VNP0-C0G-CERM01005
+/-0.5PF8.2PF
R1370
MF
0.00
0%1/32W
01005
15
C1360
10V20%
X5R-CERM
1.0UF
0201-1
CRITICALC1361
10%1UF
402X5R25V
CBTL1610A1UKU1300
CRITICAL
WLCSP
SYNC_DATE=N/ASYNC_MASTER=N/A
IO: TRISTAR
MIKEY_TS_PMIKEY_TS_N
USB_BB_PUSB_BB_N
USB_SOC_P
UART6_TS_ACC_TXD
USB_SOC_N
UART0_SOC_TXD
UART6_TS_ACC_RXD
UART3_BB2SOC_TX
UART0_SOC_RXD
JTAG_SOC_TCK
UART3_SOC2BB_TX
JTAG_SOC_TMS
=PP3V0_S2R_TRISTAR
PPVBUS_PROT
PPOUT_E75_ACC_ID1PPOUT_E75_ACC_ID2
E75_DPAIR1_PE75_DPAIR1_N
E75_DPAIR2_PE75_DPAIR2_N
TS_CON_DET_L
TS2PMU_RESET_INRESET_SOC_L
I2C0_SDA_1V8
GPIO_TS2SOC2PMU_INTI2C0_SCL_1V8
TRISTAR_BYPASS
NET_SPACING_TYPE=PWR
VOLTAGE=3VMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=0.5MM
OVP_SW_EN_L
PMU_USB_BRICKID
L81_MBUS_REF
=PP1V8_S2R_TRISTAR =PP3V3_ACC
051-0886
A.0.0
13 OF 121
11 OF 54
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2
1
2
1
C3
F5
C1
A6
C4
A1
B1
A3
E2
B3
F2
E1
D2
F1
A5
D1
B5
D5
F4
F3
F6
C5
E5
A2
B2
A4
B4
E3
B6
E4
D3
C6
D4
E6
D6
C2
15 52
15 52
24 52 53
24 52 53
4 52
5 52
4 52
5 52
5 52
5 24 28 52
5 52
4 52
5 24 28 52
4 52
54
46 52
43
43
43
43
43
43
43
5 48 52
5 48 52
48
54 54
-
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQVSS
VCCQVDDI
TMSC
TCKC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
ENSURE TRACE INDUCTANCE < 2NHLAYOUT NOTE FOR U1400 VDDI:
C14132.2UF
X5R-CERM0201
20%4V
20%
C141215UF4V
0402X5R
20%
C141115UF4V
0402X5R
20%
C1410
4VX5R
15UF
0402
C1404
20%4VX7S
0.47UF
0204
C14071UF20%
X5R6.3V
02010204
20%
C1405
X6S4V
1UF
6 52
6
6
6
6
6 53
6 52
6
6
6
6
6
R1454
MF
1%2431/32W
01005
0201
20%4V
C14502.2UF
X5R-CERM
6
6
6
6 53
6
6
6
6
6
6
6
6
6
6
6
6
OMIT
LGA-12X17U1400
CRITICAL
XXNM-XGBX8-MLC-PPN1.5-ODP
R1460
01005
1%1/32WMF
50K
R1461
01005
1%1/32WMF
50K
6.3V
01005
C1460
X5R
0.01UF10%
6.3V
01005
C1461
X5R
0.01UF10%
16V5%
01005NP0-C0G
C149127PF
16V5%
01005NP0-C0G
27PFC1490
27PF16V5%
01005NP0-C0G
C1492
NP0-C0G01005
5%16V
27PFC1494
27PF
NP0-C0G01005
5%16V
C1493
10UF6.3VCERM-X5R0402-2
20%
C1402
20%
CERM-X5R6.3V
0402-2
10UFC1401
6.3V20%10UF
CERM-X5R0402-2
C1400
20%
0402-2CERM-X5R6.3V
10UFC1480
1UF20%
C1406
6.3VX5R0201
SYNC_DATE=05/04/2012
NAND STORAGESYNC_MASTER=MLB
=PP3V3_NAND
FMI1_ADFMI1_AD
FMI0_AD
FMI0_CE0_L
NC_U1400_RE0
FMI1_CE0_L
FMI_ZQ_U1400
FMI0_AD
FMI0_RE_L
PPVREF_FMI_NAND
=PP1V8_NAND
FMI1_AD
FMI1_ADFMI1_ADFMI1_AD
FMI1_AD
FMI0_ADFMI0_AD
FMI0_ADFMI0_AD
FMI0_ADFMI0_AD
FMI1_CLE
FMI0_CLE
FMI0_WE_LFMI0_ALE
FMI0_DQS
FMI1_ALEFMI1_WE_L
NC_U1400_RE1
FMI1_RE_L
FMI1_DQSNC_U1400_DQS1
TP_TMSC_U1400
TP_TCKC_U1400
TP_U1400_RB0
NC_U1400_DQS0
TP_U1400_RB1
=PP1V8_NAND
PPVDDI_NAND
FMI1_AD
051-0886
A.0.0
14 OF 121
12 OF 54
2
1
2
1
2
1
2
12
1
2
1
2
1
1
2
2
1
G1
G7
J7
N3
N5
L7
J1
L1
H6
K6
J5
L5
J3
K2
H2
G3
F2
M6
B6
C3
C5
A3
A5
E3
C1
B4
C7
F4
E5
H4
D2
E1
D4
D6
M4
K4
E7
A1
G5
OA8
OF8
G0
OE0
OD8
OC8
N7
OE8
OD0
OC0
A7
M2
L3
F6
B2
OF0
G8
N1
OB8
OB0
OA0
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
12
1
2
1
2
1
2
1
2
1
54
12 48 54
53
53
53
53
12 48 54
-
CAP
ON S
D
VDD
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
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IV ALL RIGHTS RESERVED
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REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TOUCH SUBSYSTEM
(PLUG - FLEX 998-4527)
RCPT - MLB 998-4526 -> 516S1054
LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION
0.38 DCR
1/32WMF
R17520.000%
01005
J1700503304-2010
CRITICAL
F-ST-SM-1
MF
R1790
1/32W
1.00K
1%
01005
R17530.00
01005MF
0%1/32W NOSTUFF
C176127PF5%
NP0-C0G16V
01005
0201
C1702
X7R-CERM16V
1000PF10%
X5R10V10%1UF
402
C170127PF
01005
16VNP0-C0G
5%
C1700
L1700
0201
240OHM-350MA
1000PF16VX7R-CERM0201
C170510%
C1704
0201X5R6.3V20%1UF
0201
10%1000PF
X7R-CERM
C1708
16VX5R6.3V20%1UF
0201
C1707
5%27PF
NP0-C0G
C1703
16V
01005
240OHM-350MA
0201
L1701
0201-2
240-OHM-0.2A-0.8-OHML1702
01005
5%27PF
NP0-C0G16V
C1706
6.3VX5R
1UF20%
0201
C1752CRITICAL
SLG5AP302U1700
TDFN
CRITICALC1750
0201
10%0.1UF
X5R-CERM16V
CRITICAL
C1751
10%
X7R10V
4700PF
201
CRITICAL
1%100KR1751
MF1/32W
01005
X5R-CERM
10UFC1753
20%
0402-2
10V
CRITICAL
01005150OHM-25%-200MA-0.7DCR
L1760
C176027PF5%
NP0-C0G16V
01005
TOUCH: SUPPORT CKT & CONN
SYNC_MASTER=N/A SYNC_DATE=06/21/2010
PP1V8_GRAPE_SW
GPIO_BTN_HOME_L GPIO_BTN_HOME_FILT_LGPIO_BTN_HOME_R_L
PP3V0_S2R_HALL_FILTDISPLAY_SYNC_R
SPI1_GRAPE_MOSISPI1_GRAPE_MISO
GPIO_GRAPE_IRQ_LCLK_32K_SOC2CUMULUSSPI1_GRAPE_CS_L
PP1V8_GRAPE_FILTGPIO_GRAPE_RST_L
GPIO_BTN_HOME_FILT_L
NC_PMU_GPIO_HALL_IRQ_4
PMU_GPIO_MB_HALL3_IRQPMU_GPIO_MB_HALL2_IRQPMU_GPIO_MB_HALL1_IRQ
PP5V25_GRAPE_FILT
SPI1_GRAPE_SCLK_RSPI1_GRAPE_SCLKDISPLAY_SYNC
=PP3V0_S2R_HALL PP3V0_S2R_HALL_FILT
VCC_MAIN_GRAPE_RAMP
=PP1V8_GRAPE
=PPVCC_MAIN_GRAPE
=PP1V8_S2R_GRAPE
=PP5V25_GRAPE PP5V25_GRAPE_FILT
PP1V8_GRAPE_FILT
051-0886
A.0.0
17 OF 121
13 OF 54
1 2
13
17
24
23
19
11
15
9
7
5
1
3
18
20
12
14
16
8
10
6
4
2
22
21
1 2
1 2
2
1
2
1
2
1
2
1
21
2
1
2
1
2
1
2
1
2
1
21
21
2
1
2
1
7
2 5
3
18
2
1
2
11
2
2
1
21
2
1
52
5 48 13 52
13 52
52
5 52
5 52
5 52
5 52
5 52
13 52
5 52
13 52
48
48
48
13 52
52 5
5
54 13 52
54
54
54
54 13 52
13 52
-
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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8 7 6 5 4 3
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B
A
NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(P/N 510S0761 - FLEX)
P/N 510S0760 - MLB
AUDIO_JACK_FLEX RET1
AUDIO_JACK_FLEX MIC2
AUDIO_JACK_FLEX MIC1
AUDIO_JACK_FLEX RET2
PER DAVE BREECE
J1800CRITICAL
AA07A-S016VA1F-ST-SM-COMBO
0201-2
L1800
240-OHM-0.2A-0.8-OHM
C1800
NP0-C0G16V
27PF5%
01005
0.1UF10%6.3V
C1801
CERM-X5R0201
NP0-C0G16V
27PF5%
01005
C1802
R1850
0%
0.00
MF1/32W
01005NOSTUFF
NP0-C0G16V5%
C1850
01005
27PF
01005
5%16VNP0-C0G
56PFC1821
5%16VNP0-C0G
56PFC1820
01005 01005
C182256PF
NP0-C0G16V5%5%
16VNP0-C0G
56PF
01005
C1830
AUDIO: HP FLEX CONN
SYNC_DATE=03/31/2011SYNC_MASTER=N/A
MIN_NECK_WIDTH=0.06 MMVOLTAGE=2.65VPP_LDO14_2V65LAT_SW2_CTLGPIO_SOC2AJ_HS3_SHUNT_EN
PP1V8_DMIC_FILT
LAT_SW1_CTL
CONN_HP_LEFT_FILTCONN_HP_RIGHT_FILT
CONN_HP_HS3_FILT
CONN_HP_HEADSET_DET_FILT
CONN_HP_HS3_REF_FILTGPIO_SOC2AJ_HS4_SHUNT_EN
DMIC1_FF_SCLK_FILT
DMIC1_FF_SDCONN_HP_HS4_REF_FILT
CONN_HP_HS4_FILT
DMIC1_FF_SCLK
=PP1V8_DMIC
051-0886
A.0.0
18 OF 121
14 OF 54
20
19
18
17
15
13
11
9
7
1
16
14
12
10
8
6
4
2
5
3
21
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
25 32 33 39 40
28 52
5
24 28 52
15
15
15
15
15
5
15
15
15
15
54
-
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
BI
BI
OUT
OUT
SYM 2 OF 2
DMIC1_SCLK
DMIC2_SD
MCLK
GND13
GND0
TSTI2
TSTI1
TSTI0
GND18
GND17
GND16
GND15
GND14
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
RESET*
WAKE*
INT*
CDOUT
CDIN
CCLK
XSP_SDOUT
XSP_SDIN_DAC2_MUTE
XSP_LRCK_FSYNC
XSP_SCLK
ASP_SDOUT
ASP_SDIN
ASP_LRCK
ASP_SCLK
DMIC2_SCLK
DMIC1_SD
CS*
MBUS_REF
SYM 1 OF 2
FLYP
MIC4_BIAS_FILT
AIN3+
AIN1-
FLYN
GNDA
MIC1_BIAS
MIC2_BIAS_FILT_IN
MIC2_BIAS_FILT
MIC2_BIAS
AIN2+
AIN2M
MIC2_BIAS_IN
AIN3-
MIC3_BIAS
MIC3_BIAS_FILT
AIN4+
AIN4-
MIC4_BIAS
GNDP
GNDD
GNDHS
+VCP_FILT
FILT-
FILT+
LINEOUT_REF
LINEOUTB
LINEOUTA
HPDETECT
HS4_REF
HS3_REF
HS4
HS3
HPOUTB
HPOUTA
DN
DP
AOUT2-AOUT2+
AOUT1_M
AOUT1+
GNDCP
-VCP_FILT
VA
VCP1
VD
VP0
VL
VP1
VPROG_CP
VPROG_MB
SPEAKER_VQ
AIN1+
MIC1_BIAS_FILT
GNDHS
FLYC
VCP0
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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NOTICE OF PROPRIETARY PROPERTY:
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IV ALL RIGHTS RESERVED
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REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEADDIGITAL MIC
TO HEADPHONE JACK
TO THE HP CONNECTOR
U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846
NOTE:
PLACE R1930 & R1931 CLOSE TO U3600