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TECHNISCHEUNIVERSITÄTDARMSTADT

“Mikroelektronische Systeme”

Research Actitivies&

Education

Technische Universität DarmstadtFachgebiet Mikroelektronische SystemeProf. Dr. Dr. h.c. mult. Manfred Glesner

06. Juni 2009

Institute ofMicroelectronicSystems

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Source: Dennis Buss, TI

Technology Trend in the Internet Age

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The first Crew 1984 ...

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Staff

Prof. Dr. Dr. h.c. mult. M. GlesnerHead of Institute

Mrs. Silvia HermannMrs. Iselona Klenk

Secretary Office

Petru BacinschiLow Power and High Speed Design / VDSM

Dr. Thomas HollsteinDr. Leandro Soares IndrusiakLeandro MoellerEnkhbold OrchisurenFaizal A. Samman

SoC Design/CAD/Rapid Prototyping

Analog / RF CMOS Circuits / Smart Antenna Systems

Massoud MomeniOana CobianuHao WangPing Zhao

Networking and Technology

Andreas SchmidtRoland Brand

Andreas SchmidtReconfigurable Architectures & Signal Processing

Heiko HinkelmannFrancois PhilippChristopher SpiesPongyupinpanich Surapong

External PhD Candidates (Infineon Technologies AG)

Klaus Koch, Tideya KellaExternal PhD Candidate (Vitronic)

Kurt AckermannExternal PhD Candidate (GSI)

Martin Kumm

Printed Electronics

Dr. Thomas HollsteinHans-Peter Keil

Institute ManagementDr. Thomas Hollstein

Andre GuntoroAdaptronics

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Portfolio of Absolvents

Industry:

AlcatelBoschContinental TevesDaimler-ChryslerDeutsche BankDornier SatelliteEADSEricsson

Australia, Melbourne UniversityUniversität KaiserslauternUniversität KarlsruheUniversität KasselUniversität LübeckUniv. of YorkFH GießenFH JenaFH KarlsruheTechnische Universität DarmstadtKACST Ryadh...

University:

~ 1300 Study/Diploma/B.Sc./M.Sc.49 Ph.D.

1 Habilitation12 Professors

IBMInfineon TechnologiesIntelMotorola/FreescaleOpel Pepperl & FuchsSiemensT-Nova D. TelekomQuimonda...

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Graduiertenkollegs am Fachgebiet MES

GK „Intelligente Systeme für die Informations- und Automatisierungstechnik “

Beginn der Förderung: 1. Januar 1992Laufzeit: 9 JahreAuslauffinanzierung: 2001Förderung: 39 Doktorand(inn)en

GK „Systemintegration für ubiquitäres Rechnen in der Informationstechnik“

Beginn der Förderung: 1. Januar 2002Laufzeit: 3 JahreAuslauffinanzierung: 2005Förderung: 14 Doktorand(inn)en

Sprecher: Manfred Glesner

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Germany: DFG Excellence Initiative

In 2005, the german federal government & länder governments agreed on an excellence initiative ...

... to strengthen Germany´s position in a global market for higher education... to improve the international competitiveness of Germany´s educational institutions... to foster outstanding universities and research centers

This campaign is initially limited until 2011.1.9 Billions of € have been made available to foster ...

... graduate schools

... research clusters of excellence

... institutional strategies for advancing top-level university research

The goal is not to create one (or several) „elite university“; instead, outstanding institutes and faculties at universities across Germany are to be identified.

Source: DFG

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Germany: Graduate Schools

Postgraduate education is being centralized in graduate schools to achieve optimum conditions for PhD students.Graduate schools are supposed to be interdisciplinary, possibly spanning several faculties, departments or even including institutions outside the university.Financial aid is available for the construction of new organizational structures and for the acquisition of specialized equipment that can be jointly used by different groups within the graduate school.TU Darmstadt´s graduate school on Computational Engineering was approved in 2007.

This graduate school focuses on interdepartmental research topics in modeling and simulation.Mathematics, computer science, mechanical engineering and electrical engineering are all involved.

Source: DFG

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Germany: Excellence Clusters

Internationally competitive, world-class research is being centralized in excellence clusters.Excellence clusters are supposed to become a part of the strategic vision of a university and to define this university´s future research profile.Additional funding backs up the future competitiveness of research clusters.TU Darmstadt´s excellence cluster on Smart Interfaces / Fluid Boundaries was approved in 2007.

This research cluster focuses on the interaction of fluids with solidsat the phase interface in order to understand and design surfaceproperties in the area of fluid dynamics, aerodynamics and thermodynamics.

Source: DFG

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Institutional Strategies

Universities are called on to develop a strategy to improve their visibility and competitiveness on a global market for higher education and to hone their research profile.Funding is available for activities that sustainably evolve and complete those research areas of a university that already stand out.The goal is to establish competition among universities and to improve the competitiveness of german educational institutions on the world market.

Source: DFG

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Germany: BMBF-Spitzencluster-Wettbewerb

BMBF-Spitzencluster-WettbewerbGoals: Form a Link between science and industry

stratetic partnerships for R&D of technologies and products

5 final projects to be selected and promoted with 200 Mio € over max. 5 Years

Final Projects:The Biotechnology Cluster „Zellbasierte & Molekulare Medizin in der Metropolregion Rhein-Neckar“ (BioRN)

The Cluster „Cool Silicon - Energy Efficiency Innovations from Silicon Saxony“ in theRegion of Dresden, Freiberg and Chemnitz

The Cluster „Forum Organic Electronics“ in the „Metropolregion Rhein-Neckar“

The „Luftfahrtcluster Metropolregion Hamburg”

The Cluster „Solarvalley Mitteldeutschland” in local states of Sachsen-Anhalt, Sachsen and Thüringen.

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Forum Organic Electronics:

research within and around the Rhein-Main-Metropole

TU-Darmstadt

Heidelberger DruckSAP

BASF

Merck

Pepperl&Fuchs

Robert-Bosch

PolyIC

Uni Heidelberg

HS Mannheim/Uni Mannheim

Varta

Copaco

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Forum Organic Electronics

research and development of organic materials for electricand electronic applications

printed electronics

large areas

Backgroundlightning

TFT-displays

low-cost production

large and flexibleArea

IR-solar cells for windows

low cost circuits

flexible

e.g. RFID,Advertisement...

OLED OPV printed electronics

organic materials

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Research Fields

CAD Tools & Synthesis

Systems on Silicon

Mechatronics, Bionics

Reconfigurable Circuits

Printed Electronics

Analog/RF CMOS Circuits

Low Power DesignAdaptronics

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Currently Running Projects

TUD-Merck Labor: Printed ElectronicsVitronics: Reconfigurable Systems for Digital Image ProcessingDiehl Avionics: VHDL based design of high speed InterfacesAudi AG: Spezifikationen für zuverlässigen Chip- und Komponentenentwurf

GSI: Reconfigurable Real-Time Control Systems

DFG Project: Reconfigurable Sigma-Delta ModulatorsDFG Project: Communication Synthesis and Voltage Scaling (Low Power)DFG Schwerpunkt: Reconfigurable Computing SystemsDFG, Graduiertenkolleg:

TICMO (Steuerbare Komponenten f. Kommunikationssysteme)

Graduate School (DFG Excellence Initiative): Computational Engineering

Indu

stry

Aca

dem

ia

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Running Applications for new Projects

BMBF-Exzellenzinitiative: „Da Vinci“ (Merck, BASF, Heidelberger Druckmaschinen, Varta, PolyIC, Copaco; TU Darmstadt, KIT Karlsruhe, Uni Heidelberg, Uni Mannheim, FH Mannheim) (beantragt)

GSI: Reconfigurable Real-Time Control Systems (LOEWE-FAIR follow-up Project)

LOEWE AdRIA: Adaptronik (zus. Fraunhofer LBF)LOEWE Materialium: Neue Materialien Mikro- u. Nanoelektronik und MaschinenbauEU FP7 Mode: Wireless Sensor Networks

DFG Project: Multiprocessor System-on-Chip Design (zus. mit Dr. Leandro Indrusiak)DFG, Graduiertenkolleg:

TICMO (Steuerbare Komponenten f. Kommunikationssysteme) (2nd phase)

DFG, Graduiertenschule:Computational Engineering

Indu

stry

Aca

dem

ia

Status: June 1st 2009

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Gemeinsames Forschungslabor TUD – Merck KGaA, 2006

TUD - hoch3 April 2006

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Embedded SoC

Properties

• application specific• reactive• real-time capability

Micro-con-

troller

DSP

Memory

I/O-Module

ASIC

Design Tasks

• Mapping of the system specification on available implementation components

• Generation of Communication Architecture

Constraints

• costs• power consumption• latency

Actuators

SensorsEmbedded „System-on-Chip“

RFTransc.

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Ex. Of System-Level Design: H.264 Decoder

Block-based hybrid technique:

Compression through predictions and coding of the residues

101001110

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Low Power Design

Architecture explorationHigh level power estimationTransformations

Adiabatic techniquesLoad of off-chip capacitancesClock distribution

RF and analog low power design

Adiabatic load of off-chip lines

)2(3/2),( oioi

oi HHNN

HHAP ++

≈Analytical (entropy based) energy model

software energy model

Empirical (regression) energy macro-model

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RF and A/D Design

IF CONVERSION RECEIVER

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Organic Electronics: Applications (1)

Flexible active matrix e-paper SVGA display (Plastic Logic)

World‘s first 3mm thickflexible digital watch(Samsung)

Organic Electronics

Source: NanoMas Technologies, Inc

Pentacene organic circuits onpolymeric or cloth substrates

Plastic solar cell

First Fully Printed RFID-Tag (PolyIC)

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Organic Electronics: Applications (2)

Advantages Low Cost (Printing Process)Low Production TemperaturesLarge AreaHighly Flexible

DisadvantagesLow PerformanceHigh Voltages needed (>10V)Reliability

Costs

Performance

Organic Printed

Electronic

Silicon

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Organic Electronics: Applications (3)

Organic Electronics vs. Silicon

Source: SCIENCE

Source: IMS-Stuttgart

Ambitious Efforts to makeflexible Silicon.

Source: PolyIC(PDMS = Polydimethylsiloxan)

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Basics of Organic Electronics

Organic Transistor ArchitecturesDifferent Architectures for optimising Performance and Printability

Top – Gate Architectures imply Passivation of organic SemiconductorThe optimal architecture depend on the printability of the Material and the Printing-Technology used for the different Layers

BGTC: Bottom Gate, Top Contacts

TGBC: Bottom Gate, Top ContactsTGBC: Bottom Gate, Bottom Contacts

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Printing Technologies (1)

Printing TechnologiesHigh Flexibility

Ink-JetFlexibleNo Masks neededLow Throughput

Source: Kipphan, H.: Handbuch der Printmedien. Heidelberg: Springer Verlag, 2000

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Printing Technologies (2)

High Throughput R2R (Roll-2-Roll)High-Speed, High VolumeLow Cost per Unit

Flexo-printingScreen-printingGravureOffset printing

Source: PolyIC

Source: TUD-IDD

GravourOffset

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Printing Technologies (3)

Example for Printed Organic Transistor

1. Step:Screen - Printing

2. Step: 3. Step:Etching and cleaning

4. Step:Screen - Printing

5. Step:Screen - Printing

6. Step:

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Printing Technologies (4)

Printed Electronics at TUD-MESMerck-Lab

Cooperation between TUD and Merck AGPartners of the TUD:

Prof. Glesner (MES)Prof. Dörsam (IDD) Prof. Rehan (DKI)Prof. Schneider (Inorganic Chemistry)Prof. Rödel (Material Science – Nonmetallic-Inorganic materials)Prof. von Seggern (Material Science – Electronic materials)Prof. Jägermann ( Material Science – Surface science)

Printed Inorganic Electronic for RFID applications

PolytosPrinted Organic ElectronicsPartners:

TUD, BASF, Merck, PolyIC, SAP, Bosch, Heidelberger Druck…

Smart Labels

MES

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On-Chip Communication Synthesis: Challenges

Solution:Joint optimizationStatistical analysis and optimization for parameter variationsTechnology-accurate performance models

Communication Needs

( bandwidth)

HighPerformance

( delay)

Low Power( energy consumption)

Parameter Variability

( robustness)

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Variations-Aware Performance Macromodels

maxTi

start

+Ti

end

Tiex

Traditional approach: constant delay and energy values

Variability-aware analysis:random variables (RVs) and statistical operators

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Variations-Aware Performance Macromodels

Implementation of statistical operatorsSum operator: convolution product of PDFs

Max operator for independent RVs:

Other operators: discrete approximation of PDF through enumeration

Distribution propagation across the modelsDiscrete estimation and storage of PDFsEstimated first and second order momentsSampling from arbitrary distributionsOptimization decision (cost function) using quantilesParametrized accuracy across the complete flow

[Blaauw 2008 Trans. CAD]PDF CDF

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Correlation and Model Design

[Agarwal 2003 Trans. CAD]

[Bernstein IBM J.Res.&Dev. 2006]

[Blaauw 2008 Trans. CAD]

Nominal value Sensitivities

DecorrelatedRVs

Residualindependent

variationQuadraticdependences

Topological and spatial correlationsCorrelations from reconverging pathsSpatially-correlated process variations

Correlation tracking and reductionPrincipal Component Analysis

Nonlinear dependence on parameter variationsLinear approximation in canonical form or upper bound:

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Circuit-Level Models for Communication

Different signaling methodsVoltage-mode, reduced swing, pulsed current mode, hybrid etc.

Model parametersTransistor-level process parametersVoltage scaling and body biasingStatistical models for delay and power considering process parameter variations

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Technology-Aware Interconnect Models

Multistep extrapolated S-parameter model

Structural process model

Associated N-port model for an n-wire segment

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RFID Air Interface Standards - ISO/IEC 18000

ISO/IEC defines a series of RFID air interface standards from 18000-1 to 18000-7 for item identification world.

A diversity of RFID specifications is regulated:

Multi-standard: several frequency bands have been assigned to RFID applications, such as 125KHz, 13.56MHz, 433MHz, 910MHz and 2.45GHz.

Multi-mode: Each frequency band has an individual parameter definition.

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RFID: Prospective Future

The need of having a platform capable of multiple standard operation becomes obvious in order to:

take advantage of different frequency bandsincrease of the compatibility of RFID systemsreduce manufacturing costs

2.45GHz

ISO18000-4

910MHz

ISO18000-6

433MHz

ISO18000-7

Source: NORDICID

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Challenges in RFID

The principle challenges are:to limit the additional hardware with more integrated functionalityto reuse the common blocks between different frequencies and modes of operation

Frequency agile RFID systems are proposed to include tunable microwave frontends with characteristics as:Adjustable resonant frequency, impedance and phase delay are controlled by a DC voltage.High permittivity material in order to reduce sizePassively tunable in combination with ultra low power.

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Frequency Agile RFID Systems

Tunable matching networks guarantee the power harvesting efficiency over multiple frequency bands. It also stabilizes the load for more reliable transmission, e.g. when the consumed current varies.

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Frequency Agile RFID Systems

An antenna loaded with varactors can cover a wide frequency range within the same antenna dimension. The target bands are 433MHz, 910MHz and 2.45GHz.

-15

-10

-5

0

Ref

lect

ion

Coe

ffic

ient

(dB

)

Frequency

Multi-frequency

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RFID Colaboration: DFG GK TICMO

DFG Graduiertenkolleg 1037Steuerbare integrierbare Komponenten der Mikrowellentechnik und Optik

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Delta-Sigma: Motivation

Traditional opamp-based switched-capacitor (SC) circuit design becomes increasingly challenging in scaled CMOS technologies

Comparator-based switched-capacitor (CBSC) circuits as a novel class of discrete-time circuit approaches

Advantages:Completely eliminates opampUtilization of architectures very similar to opamp based circuitsLess problematic with continued scaling (rf. output swing)Widely applicable

Pipeline/Cyclic ADC'sDelta-sigma ADC'sSwitched-capacitor filtersSwitched-capacitor amplifiers

Basic principle:Detection of virtual ground rather than forcing it through feedback

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Lowpass and Bandpass Delta-Sigma Modulation

Using delay cells to implement reconfigurable delta-sigma modulators:

LP DSM

BP DSM

Integrator (DC) Resonator (fs /4)

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SC Integrator and Delay Cell

Half-delay SC integrator: Half-delay switched-capacitor S/H circuit:

Transfer function:

Nonidealities:

on-resistancecharge injectionclock feedthroughjunction leakagethermal noise

finite and nonlinear gaindynamic limitationslimited output rangethermal noise

nonlinearitymismatchingdistortion

Opamp

jitter

Switches ClockCapacitors

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CBSC Charge Transfer Phase

Ф1 = sampling phaseФ2 = charge transfer phase

P = PresetCoarse charge transfer (E1)Fine charge transfer (E2)

C2

Vo

CL

C1

VCM

VCM

VCM

Vx

VDD

Φ1 Φ2

E1 E2P

S

I2

I1E1

E2P

Vc

Vo

Vx

Φ2

E1

P

E2

S

Vc

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Circuit Implementation: Fully Differential MOD2

SC implementation of the 2nd-order CBSC ΔΣ modulator

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Output Spectrum: MOD2

Opamp vs. CBSC (N = 64 x OSR = 4096, NBW = 0.00037 Hz, –3 dBFS/33.20 kHz input)

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Sensor Networks

DFG research project on „Dynamically Reconfigurable Systems for Wireless Sensor Networks“

within the scope of a national priority program on „Reconfigurable Computing Systems“funded by the German Research Foundation (DFG)

Main research focus of this project:Energy-efficiency improvements for Wireless Sensor Networks (WSN)Design space exploration of different hardware architecturesregarding energy consumption, performance, area, and flexibility Special focus on run-time reconfigurable systems

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Sensor Networks: Project Motivation (1)

Sensor node platforms must meet stringent requirements:Extremely low energy consumptionSmall sizeFlexibility & adaptivity

The platform should be usable for a large variety of different sensor network applications

Of increasing importance: efficient data processing performed locally on the motes

Smart sensor networksReduction of wireless transmission costs by local data (pre-)processing

Problem: Not all requirements can be optimised at the same time

A good compromise must be obtained by designing suitable sensor node architectures

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Sensor Networks: Project Motivation (2)

But how to realise a sensor node platform which overcomes the natural trade-offs between high energy efficiency, small area and good flexibility?Microprocessors : too inefficient regarding energy consumptionASICs : too costly, because they lack programmabilityProposed solution: Hybrid architecture extending a RISC

processor with a coarse-grain, dynamicallyreconfigurable function unit (RFU)

general

purpose

process

ors

ASICs

Low

High

High

Low

DSPsCoars

e-grained

Reconfig

urable

Hardware

FPGAs

Flexibility

Energy-Efficiency

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Our Reconfigurable Mote Architecture

Reconfigurable architecture based on a hybrid computing coreA Reconfigurable Function Unit (RFU) is integrated into the microprocessor The RFU is used as accelerator for data processing at low energy costs

SensorSensor Interface

LEON2 processor core

Data Memory

Instruction Memory

Config. Memory

TransceiverInterface Transceiver

UART

TimerInterrupt-Controller

Bus Arbiter

Wishbone Bus

RFURFU Control

DataInstr.

can be realized as a single chip

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The Coarse-grain Data Path of the RFU

Multiply-accumulate module

Inversion module

Register module

Memory module

Memory Access

Unit

3 global buses

RFU Inputs RFU outputs

to m

ain

mem

ory

all interconnections on top-level are 32 bit wide (or 4x8 bit after splitting up within modules).

Multiply-Accumulate Module:

16 multipliers and 16 adders

8-bit operations each

four special inversion operators

256 byte local memory

LUT or FIFO

flexible bus system as top-level interconnect

All function blocks and interconnects are dynamically reconfigurable in every clock cycle

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Processor Integration

Our RFU is integrated into the data path of a regular RISC processorUsed as reconfigurable hardware accelerator for data processing

improved performance & efficiency

Control via instruction set extension

(a) Execution instructionsSingle-cycle stepMulti-cycle operation sequence

(b) Configuration instructionStart configurationOnly parameter = memory address of the profile

Pip

elin

e C

ontro

l Log

ic

ALU

ID

EX

ME

WBregfile

RFU

ConfigurationTables

ConfigurationControl

memoryinterface

control signals

IF

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Energy Consumption Results

Comparison of the RFU to regular ASIC and processor architectures

13,88,6

2,3

5,8

66,4

21,0

64,7

126,0

408,2

88,1

251,4

13,013,3

52,556,7

1,0

10,0

100,0

1000,0

CRC128 BCH(15,10,3) AES keygen. AES encrypt.

Ener

gy [n

J]

ASIC versionRFU versionRFU incl. reconfigurationSoftware version

Benchmark Tasks

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Flexible Prototypes

The complete digital part of the platform can be prototyped within a FPGA

not energy efficient, but ideal for functional verificationFlexible 868 MHz radio interface, up to 150 kbps2 slots for arbitrary sensor modules

Antenna

Radio Chip

Power Supply

Battery Box (4x AA Akkus)

Spartan3-2000 FPGA Board

0 cm 10 cm

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Challenges in Adaptronics

Evolution of the complex system design

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Adaptronic: Motivation

Colaboration with many technology experties:Chemicals, Materials, Printing, Sensors, Mechatronic, ControlSystems, System Design, Distributed Processing, etc.

Early integration of the concepts of controller to the conceptualdesign is very crucial

Boundary conditions are derived from the concepts of the controller for adjecent Technologies (Sensors, Actors, Electronics, System Reability, etc.)

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Application: Adaptive Bearing Network (1)

ModellingVibration ControlHigh QuantityDistributed & Centralized Controls

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Adaptive Bearing Network (2)

Introduction to Powers:

Support against Inertial Mass

Mass DamperInertial Mass Actor / Shaker

Additional System

Support against StructureAktive Rod

Structure Modification

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Adaptive Bearing Network (3)

Supporting different damping modes

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Application: Motor Stabilizer

Reduce the shaking and noise introduced by the motor

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Construction of Control Concept

Asynchronous/Synchronous: Data transfer from measurements between nodes, potentially with preprocessingto reduce the data transfer rate

N SensorsN Aktors (collocated)1 Controller, but distributes the computation in Nnodes

DistributedMIMO

Asynchronous: Communication with a centralized processing unit that controls and optimizes all controlex. over databus

N Sensors,N Actors (collocated)N SISO Control

Multiple SISO

Synchronous: Real-time data transfer from measurements(from the sensors) to the controller, ex. over analog wiring

N SensorsM Actors1 Controller

MIMO

Asynchronous: Justification for control parameters,ex. over databus

1 Sensor1 Actor (kollokiert)1 Controller

SISO

Possible Data ExchangeCharacterizationType

Combination among different control concepts are possible (ex. M-SISO-Active Damping + MIMO-Optimal)

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Ideas for System Configuration

In total, three different configurations (est.) for embeddedsystems are considered:

Simple local controller, asynchronous communication, central parameterizationCentral controllerDistributed computing of the centralized high-performance controller with local controller

Connection from Sensors with dynamic range is necessary toprovide an analog source voltageFrequency range of the elastic Modes for the function demonstrator:c.a 50..500 Hz – from numerical estimationNumber of actors / sensors TBD, min. 1, max. 16 x 3 degrees offreedom (x,y,z) = 48 or 12 active rods

Number and location are part of the optimization duringsystem design

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Generic Concept

Delivering fully customizable system design and integration

Sensor AktorLokaler Controller

(Energieversorgungper Kabel)

Sensor AktorLokaler Controller

(Energieversorgungper Kabel)

Kommunikations-netzwerk

(drahtgebunden) Zentraler Controller

Sensor AktorLokaler Controller

(Energieversorgungper Kabel)

Sensor AktorLokaler Controller

(Energieversorgungper Kabel)

Sensor AktorLokaler Controller

(Energieversorgungper Kabel)

Sensor AktorLokaler Controller

(Energieversorgungper Kabel)

...

Sensor AktorLokaler Controller

(inkl. Energy Harvesting)

Sensor AktorLokaler Controller

(inkl. Energy Harvesting)

WirelessSensorNetwork Zentraler Controller

Sensor AktorLokaler Controller

(inkl. Energy Harvesting)

Sensor AktorLokaler Controller

(inkl. Energy Harvesting)

Sensor AktorLokaler Controller

(inkl. Energy Harvesting)

Sensor AktorLokaler Controller

(inkl. Energy Harvesting)

...

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Adaptronic Partners

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Network-on-Chip for Chip-Level Multiprocesor Systems

• Each Tile consists of similar bus-based microprocessor system (homogeneous multiprocessorsystem)

Each Tile can send data to other tiles, or request data from other tiles.The architecture is typically used ingeneral purpose chip-level multiprocessor systems (CMP).

Router

MC

OCNI

IO

CPU

RCL

cache

RAM

Processor System

Tile

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Network-on-Chip for Embedded MPSoC

Each Tile consists of various/ different cores such as embedded shared memory, bus-based CPU/DSP system, ASIC, etc. (heterogeneous multiprocessor system)The architecture is used inembedded multiprocessorsystem-on-chip (MPSoC) running limited number of applications.The on-chip Network Interface (OCNI) assemblies anddisassemblies data between the NoC and the microprocessorsystem.

dma

cpu

mem

ocni ocni ocni ocni

ocni ocni

dma

cpu

mem

ocni ocni

dma

cpu

mem

ocniocniocniocni

ocni

dma

cpu

mem

ocniocniocni

ASIC 1 ASIC 2

ASIC 4

ASIC 3

Sharedmemory 1

Sharedmemory 2

Sharedmem 4

Sharedmem 5

Sharedmem 3

mem

dsp

dsp

mem

CPU

cache mem

ory

RRRR

R R RR

RRRR

R R R R

0,3 1,3 2,3 3,3

0,2 1,2 2,2 3,2

0,1 1,1 2,1 3,1

2,0 3,00,0 1,0

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Multiple Concurrent Tasks Application Mapping on a Network on Chip Platform

An application can be partitioned into several concurrent (parallel) tasks and is modelled into a task communication graph (TCG) and Resource CommunicationGraph (RCG).By using a mapping algorithm, the TCG/RCG is mapped into NoC platform.

T0

T1

T2

T3

T4

T5 T7

T6R R R R

R R R R

R R R R

R R R R

3,1

3,2

3,3

3,02,0

0,1

0,2

0,3

1,1

1,2

1,3

2,1

2,2

2,3

1,00,0

R0

R1

R2

R3

R4

R6

(TCG)

(RCG)

R5

Task Communication Graph

Resource Communication Graph

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Typical Router Architecture

Typically a Router (Switch)consists of:

1. Link Controller (LC): tocontrol inter-switch data transfer.

2. First-In First-Out (FIFO) Buffer.

3. Routing Machine: to routepackets in the NoC.

4. Arbiter Unit: to select a packet from an input portto be switched to an output port.

5. Crossbar Data Multiplexor.

I/O Unit

I/O Unit

CPU / DSP Core

Memory Unit

NetworkInterface

NetworkInterface

LC LC

LC

LC

LC

Cro

ssba

r

LC

LC

LC

LC

FIFO Buffer

Inte

rcon

nect

Inpu

t por

ts

LC

Out

put p

orts

FIFO Buffer

Arb.RE

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High-Level-Modelling for a Heavy Ion Synchrotron

About GSI:The Gesellschaft für Schwerionenforschung (GSI) is ascientific research institution near Darmstadt, GermanyIt operates a heavy-ion synchrotron with a circumference of 217 m (the SIS18)The GSI has successfully synthesized (and named) elements107 through 111 (Bohrium, Hassium, Meitnerium,Darmstadtium and Roentgenium)Another research area is the use of ion beams for cancer treatment

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Motivation: FAIR

The GSI is currently extended by the FAIR (Facility forAntiproton and Ion Research)projectA new synchrotron, theSIS100, is being builtSIS100 will be digitally controlled

this enables new featuresin past projects, digital systemswere not sufficiently performant

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Modelling & Simulation

We create a model of the accelerator ring and its distributed control systemsWe also create a model of afiber optical ring network connecting the distributed control componentsBoth models are jointly simulated

The feasibility of the proposed control algorithms needs to be shownSampling rates, delays andother parameters in the model can be varied in order to find minimal requirements for the communication networkFinally, custom communication hardware can be derived from those requirements

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73

Results

So far, we produced the following:An abstract, parametrized model of the acceleratorsystem

including multiple, spatially distributed componentsincluding local analog and digital control loopsincluding global digital synchronization controlincluding global beam phase controlincluding a linearized beam model

Insight into the feasibility of the proposed control algorithms

Synchronization and beam phase control work as expectedSimulation results are confirmed by experiments

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Internationale Partner

INPG/TIMA in Grenoble (Frankreich)Stanford University (USA)Georgia Tech (USA)Ohio University (USA)Virginia Tech (USA)University of Central Florida (USA)University Politehnica of Bucharest (Rumänien)King Saud University (Kingdom of Saudi Arabia) UFRGS Porto Alegre (Brasilien)CINVESTAV-Institut Mexico City (Mexiko)University of Lyngby (Dänemark)University of Linköping (Schweden)Tallinn University of Technology (Estland)Kaunas University (Litauen)Mongolian Technical University (Ulaanbaatar)Zhejiang University (China)Fudan University, ShanghaiCUHK, Hong KongCMC, KingstonALARI, LuganoSlovak Academy of SciencesSilesian University of Technology

KTH StockholmINESC, LisbonIMEC, LeuvenUniversity of SfaxPolitecnico de MilanoMelbourne UniversityCEERI, PilaniTU DelftTU EindhovenTU Iasi, Romania PUC Peru, LimaEPFL, LausanneUniversity of CreteKAIST, DaejeonTU WienTU BudapestCINVESTAV, MexicoUniversity of SharjahNCKU, TainanTampere University of TechnologyTU GdanskUniversity of Maribor

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25 years Anniversary of EUROPRACTICE September 2009 :

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Education: Lectures & Courses

ElectronicsMicroelectronic CircuitsVLSI-Design (Lehrbeauftragter: Dr. Hollstein)

Microprocessors and Microcontrollers (Lehrbeauftragter: Dr. Rychetsky)

VHDL Design CourseComputer Aided Design Methodology (Lehrbeauftragter: Dr. Zipf)

Advanced Computer Aided Design Methodology (Lehrbeauftragter: Dr. Zipf)

Multiprocessor System-on-Chip Design Automation (Lehrbeauftragter: Dr. Indrusiak)

VLSI-Design for Real-Time DSP (Lehrbeauftragter: Dr. Windirsch, Deutsche TelekomAG)VLSI Design for Wireless Communications (Lehrbeauftragter: Dr. Kabulepa, Conti Teves AG)CMOS Radio Frequency Integrated Circuit DesignLow Power High Speed Techniques for Very Deep Sub-Micron Technologies (Lehrbeauftragter: Dr. Garcia, Sevilla, Spain)

Architectures an Algorithms for Natural Computing (Lehrbeauftragter: Prof. Dogaru, University of Bucharest, Romania)Design for Testability (Lehrbeauftragter: Prof. Ubar, TU Tallinn, Estonia)

Lectures:

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Education: Labs & Seminars

System-on-Chip Design Seminar Design of Delta-Sigma ModulatorsSystem Design with Silicon CompilersAdvanced TimingDesign for TestabilityCircuit Design for Printable ElectronicsAdvanced Design Methods for Microelectronic Systems

Seminars:

Practical Labs:Fundamental of ElectronicsVLSI-Design LabCAD Lab (Application of Industrial CAD Systems)VHDL Design and Synthesis Lab

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Educational Background: ICE Master Program

International Master Program

Information and Communication Engineering

Start: WS 2001/02

Acceptance Quota:

40 to 60 Students per year

ca. 50% German participants

Prerequisite: Bachelor-Degree(Informationstechnik TU Darmstadt, Mathematics and Computer Science

TU Darmstadt)

Master-Program: 1st Year of Study

Master-Program: 2nd Year of Study

Master-Diploma

incl. 6 Month Master-Thesis(German/English)

(English)

Examination after the 1. Semester

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79

5,5%50%61,1%82,6%100%Grad/Reg. Exams

011111386Graduated

020480Failed

131511310Studying

13182218466Registered forExams

15212623597Enrolled

370495480812116018Applications

200620052004200320022001

Status: 07/2007

ICE Master Program: A Success Story

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&Joint European Master Program

• extended internationalization

iCE Alumni world-wide destinations

International Master Program in Information andCommunication Engineering

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http://www.mes.tu-darmstadt.de

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Summary: Future Perspectives

Microelectronics will run successfully on the ITRS Roadmap for the next 20 YearsAspects for System Integration and Design for Manufacturability will dominateAdapt to Rapid Changes of Semiconductor Industry Value ChainNew capabilities for SMEs: Improved Design Methods and Architectures for competitive Products on an international MarketWorldwide competition for the transition to NanoelectronicsLack of European Scientists and Engineers