request for proposal for development of drive & data ... · web viewthis system should enable a...

Request for Proposal

for

“Development of Drive & Video Acquisition Electronic Test Boards for CCD Image Sensor”

SPACE APPLICATIONS CENTREINDIAN SPACE RESEARCH ORGANISATION

DEPARTMENT OF SPACEGOVERNMENT OF INDIA

AHMEDABAD 380015

The information on this page is proprietary to Space Applications Centre, Indian Space Research Organization. This material should not be copied by any means or used for any other purposes except in connection with development of Drive and Video Acquisition Electronic Test Boards for CCD Image Sensor

Contents

1. Introduction:.............................................................................................................................2

2. System Description..................................................................................................................3

3. Devices for which separate Electronic Boards are required...................................................11

4. Environmental Conditions:.....................................................................................................12

5. General Terms & Conditions.................................................................................................12

6. Vendor Selection Criteria:......................................................................................................14

7. Development Plan and timeline:............................................................................................15

8. Scope of Work........................................................................................................................16

9. Deliverables:...........................................................................................................................18

10. Spares (Optional):...................................................................................................................21

11. Acceptance Criteria................................................................................................................22

12. Format of Commercial Bid.....................................................................................................22

The information on this page is proprietary to Space Applications Centre, Indian Space Research Organization. This material should not be copied by any means or used for any other purposes except in connection with development of Drive and Video Acquisition Electronic Test Boards for CCD Image Sensor Page 1

1. Introduction:

SAC is interested in development of drive electronics and data acquisition boards for Image Sensors. This system should enable a user to generate programmable high voltage, high capacitive drive Clock pulse for image sensor operation and should also acquire 16 channel of tri-level Pulse amplitude modulated CCD (Charge Coupled Device) output signal. The system consists of Front End System (FE) & Back-end System (BE). Front End System consists of Programmable clock pulse generation and CCD Analog video acquisition. The Back end system consists of CCD Video storage, processing & display system.

Proposals are invited from Manufacturers or its authorized representative for developing drive electronics & Data Acquisition module for Optical Image Sensor. This document gives detail requirements of the systems.

Manufacturer shall provide cost break-up including the aspects like NRE (if any), fabrication, testing charges.

It is very important for evaluation of the offer that the proposal includes sufficient technical data on form, fit and function. The proposal submitted in response shall be in conformity with requirements laid down in subsequent sections of this document. It shall also include the previous experience of the manufacturer and/ or authorized representatives (carrying out similar kind of developmental work) and the facilities available for design, fabrication and testing to meet the requirements. If this technical data is not provided along with the offer, SAC reserves the right to reject the proposal.

After the award of the contract, any modification will be done only as per terms of the contract. System Manufacturer may propose alternate tests / conditions and provide detailed analysis, in case of any deviation to the requirements.


2. System Description

The System should carry out the following functions

1. Clock Driver 2. Bias Generator3. Pattern Generator4. Video Data Acquisition5. Digitized Video Data Transfer to PC for Post processing.6. Digitized Video direct display 7. Control Command & DAQ Software

CCD: Charge Coupled Device Image Sensor

Block Diagram of the System (Vendor’s Responsibility)

The Optical Image Sensor Interface will provide 16 channels of Pulse Amplitude Modulated Analog Signal to the card for acquisition.


The system will have following detailed Specifications:

Bias and Clock Pulse Generation Interface (Front End System): This Board shall contain a socket in which Image sensor can be mounted. The CCD Video ground and the clocks ground shall have provision to be shorted in various places of this board to improve the noise performance.

A. Clock Driver Specifications

The Clock driver shall take logic input from the Pattern Generator and shall allow the users to adjust the output parameters (clock rate, pulse width, pulse amplitude, rise & fall times, etc.) to suit the device & testing requirements:

S.No. Parameter Specifications

1 Clock Output Parameters Low Level Tunable from -5V to +5V or better

High Level Tunable from + 5V to + 15 V(Each Channel shall have independent Levels Tunable through PC Based Interface)Resolution of voltage tuning ≤ 100 mV

Accuracy of High / Low Levels ≤ 100 mV

Amplitudes : 1V to 15V or better

Exact levels of low and high level will be defined for each detector & specified at T0 (table 1.1) within the defined range above.

*Type 2 Detector can have clock swings as high as 50 V.

2 Number of Clock Channels for clock driver

30-48

3 Clocks Slew Rate ≥ 1000 V / us


4 Clock Driver Load Driving capacity

≥ 1 nF

5 Clock Pulse Rise / fall time Edge Speed control (Programmable) for each channel Independently from 5ns - 5us.

6 Power Monitoring Each Channel Shall have current & Voltage Sense feature. This shall be communicated to PC based Software interface. Range of current monitoring shall be from micro Amperes.

7 Clock & Bias Sequencing Shall provide programmable clock & Bias Sequencing to control the order in which bias & clock signals are applied to the CCD.

8 Protection Feature Each Clock Channel shall have “Disconnect” feature for tristating the clock from the DUT.

9 Maximum Repetition Rate ≥ 70 MHz

10 Output Noise at High & Low levels

≤ 300 uV rms @ 500 MHz

B. Bias Generator Specifications

Bias Generator shall generate Independent low noise bias voltages as per the below specifications:


1 Number of independent Bias Voltage channels

≥ 20

2 Bias Voltage Range -20 to 20 V DC (Programmable through PC based LabVIEW interface)

Exact bias levels will be defined for each detector & specified at T0 (table 1.1) within the defined range above.

3 Noise on the bias lines ≤ 300 uV rms @ 500 MHz

4 Load Driving capability on ≥ ±100 mA (16 channels)


each channel

≥ ±200 mA (4 channels)

5 Bias Tunability Resolution ≤ 100 mV

6 Bias Accuracy ≤ ±100 mV

7 Power Monitoring Each Channel Shall have current & Voltage Sense feature. This shall be communicated to PC based Software interface. Range of current monitoring shall be from micro Amperes.

C. Pattern Generator


1 Clock Timing Generation Programmable Digital Output channels. There should be a GUI where a user can draw (or provide inputs in a defined format) the Clock pulse which shall be downloaded to the hardware through Standard PC Interface

2 Number of Channels for Clock Timing Generation

30-48

3 Synchronization There should be provision to synchronize & trigger the Timing Generation with other boards through external synchronization clock

4 Clock Timing Generation Programmability

The Clock Pulse should be programmable in the grid size of less than 5ns (Pattern Generator frequency shall be more than 200 MHz)

5 Clock Timing Interface The interface should be selectable in the following formats so that it is compatible to clock driver board: LVTTL / LVCMOS 3.3 V / 2.5 V / LVDS

6 Inter Clock Delay between different channels

Programmable in the range of 0- 5 ns or more.

7 Drive capability ≥ 20 mA ( Each I/O) ( Desirable)


8 Clock jitter ≤ 300 ps

9 Additional I/O ≥ 30 for future expansion.

( Frequency of better than 200 MHz in each I/O)

10 Clock Generation Logic Source code of LabVIEW &FPGA firmware shall be delivered to SAC. The User shall be able to modify the LabVIEW & FPGA code to generate the different variations in the timing.

11 Channel Tristate Each Channel shall independently be able to tristate on the fly.

12 Graphical Interface The entry point shall set up pattern sequencing, repeats and nested looping. User shall be able to define and draw/fill sub-patterns. Programming instructions shall then control the execution sequence, repeating and looping of the sub-pattern data. The Graphical interface permit single step/ multi steps or continuous generation of the pattern.

13 Sub-Pattern Length ≤ 256 Kbits

14 Maximum Number of sub-patterns

≥ 3000

15 Pattern Generator External Interface

SPI / I2C/ GPIB/ Ethernet/ USB

D. Video Acquisition Interface (Front End System) : Analog (CCD) / Digital (CMOS)

S. No. Parameter Specifications

1 CCD Analog Video Front end CCD Analog Front end With CDS ( Correlated Double Sampling) and ADC with 14 bit resolution or better

2 CCD Analog video rate Programmable 500 KHz to 11 MHz or better


3 CCD Differential Video Amplitude

0 V – 3V

4 Number of Analog CCD Output Channels to acquire

≥ 16

5 ADC Non-Linearity ≤ 0.5 % over 10% to 90% of Full scale Range

6 Input Analog Video Connector Interface

The system should have Coaxial connector having ≥ 16 Analog video interface connects. (Industrial grade connector with low noise performance to meet better than 11 bit performance)

7 Preamplifier Interface Vendor shall provide User CCD Active buffer/Preamplifier interface for driving the video signal up to 1ft (desirable up to 1m) for all 16 ports.

8 Power Supply Low noise Power supply should be designed such that it is suitable to meet better than 11-bit performance.

9 ADC Noise Performance ( System level)

Better than 11 bit performance @ 11MHz

10 CMOS Digital Video In Case of CMOS Digital Output , the Interface shall support SERDES/CML/Optical Input with data rate up to 4 Gbps.

E. Digitized Video Storage and processing (Back End System)


1 Number of Digitized Video Ports to store

≥ 16 Simultaneous

2 On Board Memory required Memory should support up to 1 second of continuous storage

3 On board Processing requirement

There should be user programmable Hardware which supports Stitching & averaging.

4 Data Loss There shall be no data loss during the Data


transmission to the PC. Vendor shall ensure this by demonstrating.

5 Latency End to End Latency of the data acquisition shall be better than 5 seconds in case of error free transmission over wired interface.

6 Data Acquisition Firmware Source code of LabVIEW and FPGA firmware shall be delivered to SAC. The User shall be able to modify the FPGA/LabVIEW code to change the different parameters like ADC frequency, gain, number of frames.

F. Digitized Video Data Transfer to PC for Post processing (Back End System)


1 Number of Digitized Video Ports to transfer

≥ 16

2 Data transfer Mode Two Options of Data transfer: (User selectable through software)

1. Ethernet2. Camera Link Frame Grabber

3 Data Transfer Hardware Manufacturer should provide a Compatible Portable Workstation (Branded OEM Dell/HP/IBM/etc.) with RAM to support 30s of data storage (> 256GB). The workstation shall include High Speed Ethernet and Camera Link Frame Grabber Card. Workstation shall Have Preinstalled Genuine Windows 10 OS with latest LabVIEW software, FPGA firmware tool and report generation tool.

G. Video direct display ( Back End System)


1 Display mode The area array RAW Grayscale format should be given to a display unit directly from the on board


acquisition without coming to the PC

2 Display format It is desirable to display the images by down sampling 2.6K * 200 pixel to HD format. However manufacturer can choose nearly matched formats also.

H. Device Motherboard

This Board shall interface with all other boards and shall consist of Device Socket, Decoupling Capacitor Network, Critical Clock Drivers and bias generators, Video Preamplifiers & High Signal Integrity Interconnects.


1 Device Socket Shall consist of Custom developed Zero Insertion Force (ZIF) Socket System with Lever, Copper cold finger for Thermal interface with external System, Flexi-rigid type PCB with Minimum Electronic components like Decoupling capacitors, Video Buffers and critical clock drivers ( < 8 nos.)

Separate ZIF socket may be required for each detector.

2 Motherboard Motherboard shall house Device socket, Electrical IC’s and Connectors.

3 Connectors High Speed Connectors shall be placed in motherboard to connect with clock driver, bias generator & Video Acquisition unit.

a) Differential as well as single end impedance matched

b) Existence of Ground plane (desirable)c) Rugged to support more than a million

mate-demate cyclesd) Shall support edge based board to board

interconnecte) Maximize pitch ( > 1mm) to facilitate easy

routing of the tracks f) High density to support the required number


of pins & High frequency.g) Ease of mount / demount & shall not cause

any stress to the PCB.h) Spare Contacts

I. Software


1 Software Shall Be made in LabVIEW (Only) for controlling GUI based timing pattern generation, data acquisition software for each detector, ADC Registers programming and Data transfer modes. LabVIEW Based Acquisition system to handle 2.8 Gbps of data shall be delivered. Software should support archival of test results and acquired data.

J. Packaging


1 Enclosure Vendor shall provide mechanical trays for handing the developed cards and the sensor along with mechanical hardware to place Optics & thermal control system.

3. Devices for which separate Electronic Boards are required

Vendor shall Develop Separate Electronics boards (complete test system has been described in Section 2) for each types of the detector mentioned below:

Type S.No./ Detector Type

Detector Name Type Format

Type 1 1 Quad Band CCD Linear Array CCD

4000 Pixels


4 Sub Arrays in a Chip

2 PAN TDI CCD-1 TDI Array CCD 15000*80 Pixels TDI

2 Sub Arrays in a chip

3 PAN TDI CCD-2 TDI Array CCD 8192*80 Pixels TDI

Type 2 4 EMCCD Area Array EMCCD

256*256 Area Array

Type 3 5 6 Band CMOS TDI Array

CCD/CMOS TDI 12000*80 Pixels Array

6 Sub Arrays in a chip

4. Environmental Conditions:

The system should work at 25±5 Degree C temperature range. All Front End electronics has to be made up of industrial grade or Mil grade components.Device Motherboard with socket (Section 2.H) should be vacuum compatible.

5. General Terms & Conditions

a) The vendor is requested to provide detailed development plan including system block

diagram, development schedule and previous experience of developing similar products.

Also the vendor shall provide development milestone linked payment option. The vendor

is requested to provide bi-weekly project progress report and report on completion of

proposed milestones.

b) Manufacturer will be required to present the detailed design during the PDR (Preliminary

design Review). During the reviews, vendor shall provide the schematic & Layout,

Failure analysis and detail design document. Only on obtaining the clearances after PDR,

the vendor shall go for the unit’s fabrication.


c) The manufacturer should provide Source code / Firmware of all the hardware / software

modules (including the IPs). This includes FPGA Source code (VHDL/Verilog).

d) The manufacturer should provide 3-year warranty and 3-year onsite technical support

from the date of acceptance on all the items listed above. During the technical support,

Vendor shall respond to SAC queries within 24 hours. Software updates shall be

available free of cost for the three years from the date of acceptance. Vendor shall also

quote for optional Additional warranty and technical support as per the deliverables for a

period of 2 years.

e) The manufacturer should provide point to point compliance to all above specifications

mentioned in Section 2. Manufacturer should justify the compliance to the specification

with proper technical reasons and expertise.

f) Integrated offer from A to J (Section 2) will only be accepted. Part offers will not be

accepted.

g) The manufacturer should provide the cost break up of each major component and

subsystem.

h) All the components and functionalities of software for each detector respectively should

be integrated into a single application and designed to work on only single PC.

i) Manufacturer should carry out the installation and commissioning of the system at SAC,

Ahmedabad. Vendor shall also provide user guide of all the delivered hardware/soft

wares.

j) Exact CCD/CMOS Electrical Interface shall be given to the vendor after the Purchase

order is released during the kick off meeting.

k) Vendor shall provide trained Man power in SAC during the support period to carry out

the Software & hardware integration of the Drive Electronics along with other test

Hardware present in the SAC Labs.

6. Vendor Selection Criteria:

Along with meeting the specifications as defined in this document, vendor shall also meet the following major requirements and provide full supporting details:


a) Vendor must be a reputed engineering company in existence for a minimum of 5 years,

with necessary technical facilities and experience.

b) Vendor must have experience to handle similar job (Integrated Specification from A to J

as defined in Section 2) for reputed clients. If the vendor has no previous experience in

building the integrated (as in Section 2) system, SAC reserves the right to reject the offer.

It may be noted that experience of building a few sub-systems out of the whole

specification does not qualify the vendor for this bid.


7. Development Plan and timeline:

Following table shows typical development plan for development of test System for each of the detector Types. Vendor may agree/suggest their development approach and milestones. Estimated delivery time is 8 months for each of the detector types.

Table 1: Development Plan

S.No. Development Stage Responsibility Remarks

1 Finalization of configuration.

Vendor + SAC Vendor will prepare configuration as per requirements of SAC and get approval from SAC. T0 = Configuration Finalization

2 Hardware and Software Design

Vendor MILESTONE 1: Vendor prepares design documents for hardware and software.

3 Preliminary Design Review (PDR) and finalization of Acceptance Test Plan (ATP)

Vendor+ SAC PDR will be conducted at SAC. Vendor has to present design and get approval from SAC.Any specific test setup requirement should be brought out.ATP should be generated by vendor and approved by SAC

4 Hardware, software development & fabrication.

Vendor Post CDR Development by vendor.

5 Demo of Proto type Vendor MILESTONE 2: T0 + 16 weeks

6 Development of Final Model

Vendor T0 +24 weeks

7 Functional and Burn in Testing

Vendor + SAC Vendor has to show functionality and testing of the unit at Vendor site along with burn in test of 168 hrs ( at room temperature).

8 Acceptance test and installation at SAC.

Vendor + SAC MILESTONE 3: Vendor has to conduct acceptance test at SAC premises with existing hardware.


As Mentioned in Section 3, Five Such systems have to be developed for five such Detectors. The time line of the complete project shall adhere to the below table

Table 2: Timeline of all DetectorsS.No. Test System Development Time Line

1 Detector 1 T0_1 + 8 Months





Following technical points apply to the timelines:

1. T0_1/2/3/4/5: Finalization of Configuration & Sharing of Interface details of the respective detector with the vendor (as mentioned in Section 8 Table 1.1).

2. Maximum 3 Phases shall be taken up at a time by SAC.3. T0 (Section 8 Table 1.1) of each detector can be decided by SAC based on project

requirements however maximum Timeline of the complete Contract is 5 Years.

8. Scope of Work

Following are the key elements defining the scope of the Work:

System Design

a) System Requirement Specification (SRS)

b) Preliminary Design Review (PDR)

c) Schematic design

d) PCB Stack-up definition

e) Thermal Analysis of module.

f) Signal integrity for high speed interfaces


g) Design for testability (DFT)

h) Mechanical Enclosure Design

i) Component placement for optimum thermal performance

j) PCB Layout following high speed design rules and EMI/EMC

k) Cable design

l) Critical Design Review (CDR)

m) Sets of Proto Fabrication and Assembly

n) Acceptance Test Plan (ATP)

o) User Manual (UM)

p) Board Bring Up & Interface Testing

a. FPGA for configuration and booting

b. All Memories (DDR3, Flash and EEPROM)

c. Processor/FPGA Bring-up

q) Processor/FPGA memories/interface configuration/test

a. Ethernet Configuration

b. Serial Interface

c. Loopback or equivalent testing for all I/O

r) Functional Acceptance Testing (FAT) with simulated Analog Input

s) Sets of Pre-Production Manufacturing

t) Enclosure fabrication


9. Deliverables:

The Deliverables constitute of Table 3, Table 4 and Table 5.

Each Detector shall have following Sets of Deliverables:

Table 3: DeliverablesS. No. Item Qty (Set)

1. System Requirement Specification document 01

2. Design Files Including Schematic, Layout , Gerber , FPGA RTL code, FPFA/SOC Bit File, Software Source codes

01

3. Design Document : Hardware, Software & FPGA/SOC 01

4. Software executables & Design files including Custom GUI for control & Data Acquisition, Relevant IPs & Firmware

01

5. Warranty and Onsite Technical Support 3 year

6. Hard Copy of all the User manuals 01

7. Design Files & custom developed firmware / Software code of all the cards

01

8. Operating software for PC system (Windows 10) 01

9. Detector specific hardware As per Table 5

Table 4: Software ToolsIndustry standard tools

NI LabVIEW latest, Device Drivers, LabVIEW FPGA/SOC Design tool including Synthesis/ Simulator & Programmer, Report generation tool

3 Nos.


S. No. Detector Name

Pattern Generator

& bias Generator

Clock Driver &

Bias Generator

Motherboard with Socket

Video Data Acq,

Storage

Video Data

Transfer to PC system

Video Direct

Display

Custom Developed Software/ Firmware

Packaging

1 Quad Band CCD

Type 1 3 3 3 3 1 1 1 As per the Number of

Cards2 PAN TDI

CCD-13 3 1

3 PAN TDI CCD-2

3 3 1

4 EMCCD Type 2 3 3 3 3 1 1 1

5 6 Band CMOS TDI Array

Type 3 5 - 5 5 2 1 1

Table 5: Deliverable cards

* Any two/ three cards of a particular test system can be combined in a single card.


10. Spares (Optional):

In addition to the above deliverables, Vendor shall also quote the following Optional Items for each system along with 3 year warranty at additional cost:

S. No.

Detector Name

Pattern Generator

Clock Driver

Mother board with

Socket

Video Data Acq, Storage

Video Data Transfer to PC system

Video Direct

Display

1 Quad Band CCD

Type 1

1 1 2 2 1 1

2 PAN TDI CCD-1

2 2

3 PAN TDI CCD-2

2 2

4 EMCCD Type 2

1 1 2 2 1 1

5 6 Band CMOS TDI Array

Type 3

1 - 2 2 1 1


11. Acceptance Criteria

ATP (Acceptance Test Plan) will be finalized jointly as per the development plan. Following points are proposed to be included:

1. Demonstration of functionality as defined in the specifications above including Analog video digitization, Digital video storage in memory and Video Display

2. ADC SNR and linearity as per Table-D.5.3. Data Transfer to PC through Camera Link & Ethernet Interface.4. Clock timing generation with 5 ns delay5. Simultaneous Digitization of the 16 ports with recording of 1s.6. CCD Direct Display Interface.7. Control & acquisition Programmability8. End to End Latency 9. Synchronization capability

12. Format of Commercial Bid

As per RFP, vendor shall submit the commercial and technical parts in separate volume and separate sealed covers. The quote shall include the details of milestones for payment requirements and associated guarantees. Copy of commercial bid without prices (Blank format) shall be provided along with the technical bid.


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