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RBB & FBB in FDSOIRBB & FBB in FDSOI
Philippe FLATRESSE, PhDFDSOI Expert, Business Development
Body Bias advantages
A key differentiator offering full flexibility in FD-SO I
Performance boost
Power optimization
2
Power optimization
Easy implementation
Process , T° and aging compensation
Extended Body Bias Range in UTBB FD -SOI
IGIDL(RBB)
IPN(FBB)
NMOS PMOS
3
BULK UTBB FD-SOI
noBB
FBBRBB
-300mV +300mV
noBB
FBBRBB-2V +2V
[Flatresse ISPLED 2014]
UTBB FD-SOI: Extended Body Voltage Range
• RVT: Conventional Well (CW) - RBB
p-Well n-Well
NMOS PMOSGndsn VddspnoBB
FBBRBB
+2V-2V
Vdd/2+ 300mV
4
-2V
• LVT: Flip Well (FW) - FBB
n-Well p-Well
NMOS PMOSGndsn Gndsp
Vdd/2+ 300mV
noBB
FBBRBB
+2V
-300mV[Flatresse et al. ISSCC 2013]
Body Bias Efficiency - Silicon Benchmark
FBB /LVT
5
RVT / RBB
[Pelloux-Prayer et al. S3S 2014]
Body Bias Usage – 6 different scenariosPerformance boosting
1.1V
Total Power
1.1VFBB
6
0.6V
Freq.FBB
Body Bias Usage – 6 different scenariosPerformance boosting
Power optimizationTotal Power
7
0.6V
0.9V
FBB
Freq.
0.8V0.9V
Body Bias Usage – 6 different scenariosPerformance boosting
Power optimization
Leakage saving
8
Body Bias Usage – 6 different scenariosPerformance boosting
Power optimization
Leakage saving
9
Area saving
Body Bias Usage – 6 different scenariosPerformance boosting
Power optimization
Leakage saving
10
Area saving
Yield recovery
Body Bias Usage – 6 different scenariosPerformance boosting
Power optimization
Leakage saving
11
Area saving
Yield recovery
P,T,A Compensation
Or any combination …
Body -Bias Product Use Case
12* Benchmarked with respect to noBB
ULV � Low power � Best mW/MHz � High performance
Courtesy STMicroelectronics
Body Bias - Key deployment steps
Body Bias IPs & Architecture
Product specification
13
Design implementation
Silicon engineering
Trade-off & Choices for Energy Efficiency
(Vdd, PB, BB ) choice becomes a
14
(Vdd, PB, BB ) choice becomes a power-delay trade-off exercise
Built-in Body Bias in your design flow is key !〉ARM Processor
〉Target frequency: 1GHz @ WC/0.85V
〉Two FD-SOI implementations comparison〉Standard WC methodology
〉SS corner compensated with 600mV FBB
15
Sign-off Standard Built-in BB
Area 1 0.95x
Total Power @ Vmax, 125C, RCmax
1 0.75x
Leakage @ Vmax, 125C
1 0.7x
Courtesy STMicroelectronics
FBB “Process Compensation” principle
FBB(to accelerate transitors speed)
NO FBB
CORNER BB
FF 0.0V
16
FFFFSS
TTTT
SS
Slow partFrequency, Power and area Gain
Fast parts unchanged
FF 0.0V
TT 0.3V
SS 0.6V
Body Bias - Key deployment steps
Body Bias IPs & Architecture
Product specification
17
Design implementation
Silicon engineering
Body-Bias Generator – a key IP
L
E
V
EchN
chP
nwell
VDD1V8
Neg.
Boot-
Strap
VDD1V8
GND
φ1
φ
φ2
φ
Cfly
pwellCharger
nwellChargerL
E
V
E
VDD1V0
VDD1V8
VDD1V0
VDD1V8
ON OFF
• Fully integrated generator for the NMOS/PMOS body voltage generation
• 50/100 mV FBB steps up to 1.8 V
gnds grid
PW
NM
OS
NWNW
18
E
L
S
H
I
F
T
dchN
dchP
pwell
GND
GND
Neg.
Boot-
Strap
GND
φ1 φ2
pwellDischarger
nwellDIscharger
E
L
S
H
I
F
T
ON OFF
ON OFF
ON OFF
ON OFF
• Charging and discharging well capacitances, challenge –Vss
• Switched capacitors generate negative bias and pump substrate
[Blagojevic et al. VLSI 2016]
PW
PW
NM
OS
PM
OS
D-N
WP
-SU
BNW
vdds grid
BB generators offer 19
〉Compact, Fully-Integrated
〉 Low-Power, High-Precision
〉Wide-Range, Positive and Negative
〉Towards a Body-Bias Compiler:
BB Brain
- DAC- Samplers- Comparators- Decision logic- Digital interface
BB DRIVER
- Positive & Negative charge pumps
High Level PMU
Version LVT HP LVT Comp RVT IoT
BB Well Area 1mm 2 1mm 2 1mm 2
Settling time 0.1us 100us 1000µs
Frequency 1GHz 500MHz 100MHz
Avg. Power 100uW 10uW 0.1µW
IP Area total 0.02mm² 0.01mm² 0.005mm²
[Flatresse LETI Days 2015]
IP requirement for Body-Bias
Open loop with On-chip BBG
IPs
BBgen
On Chip Sensors
BBG
control
bb-fing
driver #1
pwell
nwell
chP
chN
dchP
dchN
Power
Management
Unit (PMU)bb-fing
driver #1BBG
driver #1pwell-nwell
power grid
Debug & Trace
Registers (DTR)
I/O
20
Voltage sensor
Temperature sensor
OTP memory
FBBmin + NvsP search algo
Body Bias compensation Type vs VDD
21[Mhira et al. TCAS 2017]
Body-Bias Architecture SelectionOpen loop with
Off-chip BBGOpen loop with
On-chip BBGClosed loop with
On chip BBG
22
• For >0.9V
• FBB/Power
• For >0.9V
• FBB/Power/Process Comp.
• For full voltage range
• FBB/Power/PTA Comp
Body Bias - Key deployment steps
Body Bias IPs & Architecture
Product specification
23
Design implementation
Silicon engineering
Process compensation with Body Bias Implementation example
〉Multi-cores running @1GHz
〉Complexity ~50M gates
〉Body Bias Area: 80%
24
On Chip Monitors V/T SensorBBGen OTP
〉Body Bias Area: 80%
〉Power Supply 0.9V – Temp Inversion
Body Bias Island
Body-Bias for Process compensation - SpeedAfter
TrimmingBefore
Trimming
25
SSSS
FF
SS
FF
Freq (MHz) Freq (MHz)
+15% Speed increase wrt no BB
4X process spread reduction
15% Yield recovery
Courtesy STMicroelectronics
Frequency and leakage control with body bias
Leakage limit
IDD
Q
Trimmed
Untrimmed
26
〉Spread reduced for both frequency (4X) and leakage (2X)
IDD
Q
SS
FF
Courtesy STMicroelectronics
Full Vddmin control with FBBPre/Post TRIM
Before Trimming After PMB
Trimming
Vddmin reduction thanks to BB
27
Vm
inV
ddm
in
Vdd
min
FF SS
Courtesy STMicroelectronics
FF SS
Body Bias - Key deployment steps
Body Bias IPs & Architecture
Product specification
28
Design implementation
Silicon engineering
FBB “Process Compensation” calibration
Store BB in Store BB in
Search BB
Begin EWS
Production Test at ST(EWS)
Application (at
Optimal Body Bias level is defined Die by Die depending on Speed/Power characteristic
measured on “on chip monitors”
29
Normal operation
Read OTP BB
Set BB
Start-upEnd EWS
Store BB in OTP
Store BB in OTP Application (at
Boot)Optimal Body Bias level is stored in One Time
Programmable memoryTHEN
Read at Boot
An Embedded circuit (Body Bias Generator) set that Bias
level
VBB min Search
VDD and Temp condition for calibration Algorithm setting via frequency target and max allowable VBB
Algorithms to find common VBBN/VBBP, only used at EWS and start-up
VDD, tempVBBmax, Ftarget
Begin
VBBN=VBBP min search
NMOS vs PMOS
30
NMOS and PMOS separate measurement
Final VBBN and VBBP adjust by +/- 1 or 2 step;Guaranties minVBB with F >Ftarget
Stored in OTP for EWS calibration then in BBgen register for others
NMOS vs PMOSVBB offset calculation
+/- 1 or 2 VBB stepFinal adjust
Store VBBN, VBBP
end
BB compensation based on on -chip monitorsF
requ
ency
Frequency Target
31
BB codes distribution per wafer
SS
TT
Body-Bias code
Full distribution within target range. Thanks to FBB based Process compensation
TT
FF
Courtesy STMicroelectronics
The future is body bias adaptive ! 〉Adaptive voltage control will also be used to maximize performance and yields
32
Dynamic Body-Bias for P, T,A compensation
[Flatresse NEWCAS 2015]
Adaptive Body -Bias for Aging compensation〉Progressive degradation modes (BTI, HCI, TID) are captured by canary FF solutions
〉Compensation through ABB is possible under real-tim e conditions
33[Mhira et al. IRPS 2017]
PULPv3 SoC – RVT Conventional well
SOCDOMAIN T
CD
PROCESSMONITORINGBLOCKS
TEMPERATURE SENSORBODY BIAS GENERATORS
ROM
� PULP: Parallel Ultra-Low-Power Platform
� 4-cores near-threshold processor
� Frequency Range:
� 20 MHz @ 0.5V - 200 MHz @ 0.7V
� On-Chip Body Bias Generator
� Average power: 4,15 µW
� Body Bias Range: -1.5V to 0.4VCLUSTERDOMAIN
DM
L2
� Body Bias Range: -1.5V to 0.4V
RVT-based design with Body-Biasing Key flavor for IoT
PULP
35
Figure of merit @ 0.5V Vdd
FBB 0.5V � 160% Higher Freq RBB -1.8V � 10X Less Leakage
[Rossi , HCS 2015]
PULP: RBB/FBB frequency boosting
〉Body Bias varying from -1.0V to +0.5V
Frequency100Mhz
300Mhz
0.5V FBB
36
Body Bias
Leakage
-1.0V FBB
0.5V FBB
30µA
3000 µA
FDSOI & Body Biasing - Take away
〉True back gate solution for ultimate Vt control
〉Built-in Body Bias in the design is key, easy to implement !
〉Up to 200% performance boost and 10X leakage reduction at low voltage
〉Significant Vddmin reduction, leading to power saving and reliability relaxation
〉Variability spread reduction
〉FDSOI offers unique Body Bias control loop solutions for P,T,A compensation
〉Enabling/Disabling BB allows to create several product variants
Thank you !