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DSL Development Board Rev 2/01/011
Purdue Digital Systems Labs Development BoardK. Otte and D. Meyer
School of Electrical & Computer EngineeringPurdue University
West Lafayette, Indiana
ObjectiveThe objective of this project was to develop a robust instructional tool for the Digital
Systems Labs in the School of Electrical & Computer Engineering at Purdue University. For anintroductory microprocessor course like EE 362, Microprocessor System Design and Interfacing,it provides a Motorola 68HC12 with built-in debugger. It also has a large FPGA, which can beused autonomously or in conjunction with the 68HC12. Up to 128 KB of RAM is available forprototyping and debugging software-intensive embedded applications, such as those studentscomplete for EE 477, Digital Systems Senior Design Project. A Liquid Crystal Display (LCD)and expansion connectors are also available, which include full access to the address and databus along with sixteen programmable pins to facilitate custom interfaces.
For a computer architecture course like EE 437, Computer Design and Prototyping, ahardware platform based on an Altera FPGA is provided to prototype and exercise amicroprocessor core. The on-board RAM can be loaded by the 68HC12 with instructions for theexperimental core to execute, and then switched to the experimental core’s bus for execution.The 68HC12 can then reclaim the bus for a post-run analysis of the memory. The developmentboard is designed to accommodate a simple microcontroller or multi-cycle microprocessor. It istheoretically possible to implement a pipelined microprocessor with a larger FPGA so an internalsplit cache could be created. The board was designed with upward compatibility for this option,but the current design is focused on implementation of a multi-cycle processor. Seven byte-widelogic analyzer ports are provided for monitoring critical signals. Several clocking methods areavailable to provide a wide range of clocking options: an external function generator, on-board25MHz and 16 MHz oscillators, and the 68HC12 pulse width modulator.
For a future “System on a Chip” course, an FPGA-based hardware platform is providedwith several interfacing options. 128 KB of external RAM is available for lookup tables or otherapplications that have large memory requirements. Two PS/2 style connectors are provided for akeyboard and mouse interface. A standard VGA connector is available for a monitor interface.A serial charge pump is provided to create an RS232 style serial port. For example, all of theseinterfaces could be pulled together to make a terminal, which has a VGA interface, a keyboardinterface, and a custom serial port. The platform is flexible and robust enough to handle manydifferent interface combinations. A daughter board is available which contains buttons,switches, and lights for system debugging and control.
For senior design project courses, a platform is provided that has a robustmicrocontroller-based core with many flexible interfacing options. The options availablefacilitate projects that focus on the development of feature boards and software. In a single-semester design course it often takes the better part of the time available to get the core running,thus delaying the development of software and feature boards. The development platformprovided here makes it possible for these tasks to begin earlier in the design cycle by providing acore that has a microcontroller, RAM, programmable logic, and a plethora of interfaces.
DSL Development Board Rev 2/01/012
AbstractThe board is divided into four principal sections. The first section is the Motorola
68HC12 debugger. This section requires a minimal set of circuitry for the 68HC12 to run inbackground debug mode for the main 68HC12. The second section is the main 68HC12. Thismicrocontroller can be used in single chip mode or in expanded mode. It has the ability tocommunicate with the “glue logic” PLD, the FPGA, the RAM, the LCD, and several expansionconnectors. The third section is the glue logic. Its purpose is to provide all of the necessaryinterfaces with and meet the timing requirements of each device. It performs bus switching toallow for multiple bus masters, de-multiplexes the 68HC12 signals, and creates the necessarytiming for the LCD. The last section is the Altera FPGA (“FLEX” chip). This large FPGA canbe used as a peripheral to the main 68HC12, or loaded with a microprocessor core and run on itsown. It has access to a series of external interfaces: VGA, PS2 keyboard, PS2 mouse, serial port,and RAM. It also has seven byte-wide logic analyzer ports that can also serve as expansionconnectors.
Serial Port
Serial Port
Serial Port
KeyboardMouse
BNC
JTAGRAM LCD
Main HC12
Debugger HC12 BDM
BDM
Glue Logic
Altera Flex
VGA
Analyzer Ports
Expansion Port
i
Figure 1. Board Block Diagram.
DSL Development Board Rev 2/01/013
Hardware Design
Power Supply
D5
LED
MIC29300U10
123
InGndVcc
Ext_Pwr
R1015K
D4
1N4001
12
VCC
J2
DC Power
1
2
C3010uF
F1 2A
Figure 2. Power Supply Schematic.
The power supply is designed to provide regulated 5 VDC with a current draw around 2amps. The input power is expected to be an unregulated 6 VDC power supply. A low-drop-outregulator is used to minimize heat dissipation (in contrast, a conventional 7805 regulator requiresa minimum input of 7.5 VDC to produce a regulated 5 VDC output, and thus dissipatesconsiderably more heat than a low-drop-out regulator using a lower input voltage). An effortwas made to keep the power supply components as close to room temperature as possible toavoid safety hazards. The current draw of the board is dynamic: the minimum draw is around0.7A for a fully populated board, but increases as peripherals are attached. The daughter boardwith seven-segment displays and dual banks of LEDs increases the load significantly.
Additional features are also provided for protection. A fuse is placed in series with thesupply. In an overload condition the fuse will sacrifice itself to save the board. A diode isincluded to protect the board from becoming reverse-biased.
ClockingThe primary clock domain of the board is based on a 16 MHz oscillator. An oscillator
was used to avoid having several redundant crystal circuits on the board. In order for the gluelogic to be able to correctly create some of the needed bus timing, a free-running clock wasrequired, phase-locked to the clock used by the microcontrollers. Therefore, an oscillator wasused to provide a clocking signal to both 68HC12s as well as the glue logic.
An on-board 25.125 MHz oscillator provides the timing necessary for the VGA interface.This clock is directly connected to the Altera FPGA for low delay and clock skew, and also fedto the “glue logic” EPLD so it can be used in other clock chains.
68HC12 DebuggerThe 68HC12 has a background debug mode (BDM) that makes it possible to use one
68HC12 to debug another one. To avoid the need for additional hardware, a 68HC12 is providedon board to act as the debugger for the main 68HC12. Headers are provided so externaldebuggers can be used if necessary. By default, the processor is set to boot up in single chipmode, and the debugger software is set to background debug mode. The jumper configurationfor the debugging headers and processor interconnection is shown below.
DSL Development Board Rev 2/01/014
Table 1. Debugger Jumper Configuration.
JP 604 JP 605Debugger External 1-2 1-2Debugger On-board 2-3 2-3
68HC12 Main
VCC
PA5
PA3
PS2
PT6
PDLC3
C80.1uF
PE0
PAD6
Y216Mhz
5O
UT
PAD2
PB3
C19
0.1uF
VCC
VCC
VCC
VDDX78
R915K
PE1
PDLC5
Alt Part
VRH
PB2
PS6
PA2
PP0
PT3
VSSX30
PS7
PS0
XTAL
PT7
PA1
PA7
PT5
VDDX31
D2
1N4001
1 2
U2
MC68HC912B32
3940414243444546
5152535455565758
6162636465666768
76757473727170
11304877
654321
8079
789
1213141516
1819202122232425
3837363529282726
17323334
495069
5960
10314778
PA0PA1PA2PA3PA4PA5PA6PA7
PAD0PAD1PAD2PAD3PAD4PAD5PAD6PAD7
PS0PS1PS2PS3PS4PS5PS6PS7
PDLC0PDLC1PDLC2PDLC3PDLC4PDLC5PDLC6
VSSVSSXVSS
VSSX
PP0PP1PP2PP3PP4PP5PP6PP7
PT0PT1PT2PT3PT4PT5PT6PT7
PB0PB1PB2PB3PB4PB5PB6PB7
PE0PE1PE2PE3PE4PE5PE6PE7
BKGDnResetEXTALXTAL
VRHVRLVFP
VDDADVSSAD
VDDVDDXVDD
VDDX
nRESET
VSSAD
C18
0.1uF
Alt Part
PE6
PA6PP5
PB4
PP3
PB7
PT1
VRL
PAD4
VCC
R715K
PDLC4
PS4
VCC
PT4
U3MC34164
2 1
3
IN RSET
GN
D
VCC
PT0
EXTAL
PS1
PAD5
PP4
VDD10
PAD1
MODB
PE2
PT2
JH1
Flash Prog
11
PA0
PE6
C21
0.1uF
VSS11
PB0
PP2
VCC
PS5
R815K
R1
1K
PP6
VFP
VSSX77
PE7
D1
1N4148
PAD7
R315K
PP1
PDLC0
SW1
PB1
PDLC1
PB5
PA4
PS3
PAD0
VDD47
PP7
PB6
PE5
C20
0.1uF
R515K
VSS48
PDLC6
BKGD
PDLC2PE4PE5
PAD3
PE3
MODA
16Mhz
VDDAD
Figure 3. Main HC12 Schematic.
The main 68HC12 is modeled after the M68HC12B32EVB Evaluation Board. It has allof its signals pulled out to headers for observation. The headers are in the exact sameconfiguration as the evaluation board so any test fixtures designed to connect with the evaluationboard will also mate with this board. By default, the processor is set to boot up in single chipmode; however, its external bus is connected to the glue logic FPGA and expected to be able to
DSL Development Board Rev 2/01/015
run in expanded wide mode. To enter this mode, the MODE register ($0B) is set to $71 and theMISC register ($13) is set to $74. Through the glue logic EPLD, the microcontroller has accessto many different peripherals, including 128K of external RAM. An LCD display may beoptionally mapped into the 68HC12’s memory space; the timing needed to operate the display ismanaged by the EPLD. The Altera Flex 10K FPGA may also be memory mapped in to the68HC12’s memory space. This FPGA could be used as a custom-designed peripheral such as aUART, SPI, USB, Ethernet controller, etc. A front-end interface (FI) would be requireddepending on the desired interface, but all of the headers are present to make the addition of sucha FI as painless as possible.
68HC12 Flash Programming
VFPD1
1N4148JH1
Flash Prog
11
VCC
D2
1N4001
1 2
Figure 4. Flash Programming Voltage Circuit.
The flash programming circuit is rather basic, but addresses some critical issues. First, asmall-signal diode (1N4148) is provided to ensure that the flash programming pin will always beat approximately 5VDC (or higher). If the flash programming voltage is absent, the diode isforward biased and holds the 68HC12’s VFP pin at about 4.5VDC. If the flash programmingvoltage is present, it isolates the main power plane (5 VDC) from the programming voltage. Theflash programming voltage required for optimal performance is critical: it must be between11.4VDC and 11.8VDC (12VDC is too much and will damage the flash). A 1N4001 diode isplaced in series with the flash programming header and the VFP pin of the 68HC12. Thisprovides one diode drop of about 0.5V, making it possible to use a standard 12VDC supply forflash programming power.
NOTE: Motorola claims the flash is good for about 100 programming cycles. Experimentally ithas been found to be much less than that. It is good practice not to program the flash any morethan necessary and do not leave the flash programming voltage applied any longer than strictlynecessary. It has been found the flash can usually be programmed reliably using backgrounddebug mode at 1200 baud.
Glue Logic
The glue logic chip is an Altera Max EPM7256SRC208 EPLD. Its primary function is toact as a bus arbiter and timing manager for the different interconnected peripherals. It has acomplete 16-bit independent address and data path to the 68HC12, RAM, and the Altera FPGA.It also manages the clocking for the Altera FPGA and creates the bus timing that is needed for
DSL Development Board Rev 2/01/016
the LCD interface. The details of its operation are covered in depth in a later section devoted tothe software.
JTAG Programmer
TMS_Port
TCK
R2621K
VCC
JTAG Port
TDI_Port
TDO
TDO
R2401K
TMS_Port
VCC
R2631K
HC12_JTAG
R2411K
R261 1K
PDLC2
JP204
HEADER 5X2
1 23 45 67 89 10
TCK_Port
PDLC3
TDI_Port
PDLC4
Port_JTAG
TDI
R260 1K
R2421K
R2651K
VCC
TMS
TMS
TDO_Port
TCK_PortTDI
VCC
R2431K
PDLC5
C2100.1uF
TDO_Port
R2641K
TCK
TDO
74ALS244
U5
3579
12141618
17151311
8642
20
191
2Y42Y32Y22Y1
1Y41Y31Y21Y1
2A42A32A22A1
1A41A31A21A1
VCC
2OE1OE
Figure 5. JTAG Programming Circuit.
The programming circuit for the two Altera devices (glue logic EPLD and applicationFPGA) is a JTAG chain. JTAG is a four-wire serial style interface. The Altera Byte Blaster isused to interface the board with a host computer through a ten-pin header that is provided. Thesignals are then conditioned and passed through a line driver. The line driver functions like a tri-state style multiplexer. In one configuration, this “multiplexer” passes the signals from theJTAG header to the Altera devices; in the other configuration, the JTAG signals are masteredfrom the 68HC12. This makes it possible to use the 68HC12 as the programmer rather than theByte Blaster, and for the 68HC12 (via its serial port) to program the Altera devices. This featureallows the Altera devices to be programmed in a UNIX environment (where PC style serial portsare not available, or not supported by Altera). In addition to being able to select theprogramming source, the JTAG chain can be configured as a two-device chain, or any of thedevices may be configured independently.
DSL Development Board Rev 2/01/017
Table 2. JTAG Chain Jumper Configuration.
JP 405 (TDI) JP 406 (TDO) JP 407Altera Max 1-2 1-2 1-2Altera Flex 2-3 2-3 1-2Altera Flex & Max 2-3 1-2 2-3
Table 3. JTAG Chain Master Configuration.
JP 408 (Ext) JP 409 (HC12)External Port 1-2 2-3HC12 2-3 1-2
Ram Interface
Address14
Address9
Address0
Address11
R303
1K
Address3
Address0
Data4
VCC
Address14
Address7Data6
Address13
Address16
Ram_nOE
Data1
Address13
U302
CY7C109
22
23
24
25
2627
28
29
30
31
131415
12111098765
4
3
2
1718192021
CS1
A10
OE
A11
A9A8
A13
WE
CS2
A15
I/O0I/O1I/O2
A0A1A2A3A4A5A6A7
A12
A14
A16
I/O3I/O4I/O5I/O6I/O7
Address3
Address10 Address10
Ram_nCS
R306
1K
VCC
Address4Address5
Address11
Address2Address1
Address5Data12
Address12
Ram_nWE_High
Address6
R305
1K
VCC
Address2
Data5 Data13
Data9
Address16Address15
Address4Data11
R30010K
Address15
Data0
Address8
R30110KVCC
Address7
Ram_nWE_Low
Data2
Data14Address6Data15
Data3
Data8
VCC
R304
1K
Address9
U301
CY7C109
22
23
24
25
2627
28
29
30
31
131415
121110
98765
4
3
2
1718192021
CS1
A10
OE
A11
A9A8
A13
WE
CS2
A15
I/O0I/O1I/O2
A0A1A2A3A4A5A6A7
A12
A14
A16
I/O3I/O4I/O5I/O6I/O7
Data7
Address1
VCCAddress12
Address8
Data10
Figure 6. RAM Schematic.
The memory consists of two 128Kx8 SRAM chips. All of the control signals are createdby the glue logic EPLD. The bus itself is isolated from the hosts by the EPLD to support theswitching of the driving hosts. To combat noise and signal integrity issues that were found inrepeated high-speed accesses, pull-up resistors are applied to all signals. All of the signals arepulled out to headers for debugging or expansion.
DSL Development Board Rev 2/01/018
LCD Interface
Data15
LCD_nCS
LCD_Contrast_Filtered
R2541K
LCD_Contrast_Filtered
R2191K
C22310uF
VCC
R2511K
R2211K
Data11
Data13
LCD_RSLCD_nWE
R2521K
LCD_Contrast
Data10
R2561K
R2531K
R2551K
VCC
Data8
R2571K
R223
1K
R2201K
Data9
JP202
HEADER 14
1234567891011121314
Data14
R2501K
Data12
Figure 7. LCD Schematic.
The LCD interface is a standard 14-pin interface. The timing for the LCD isautomatically generated in the EPLD so the display can be both read and written. The timing forthe LCD is different than the rest of the bus timing. Notching of several of the control signals isrequired on both the rising and falling edge. The contrast for the LCD is controlled by areference signal that varies from 0 to 5 VDC. This signal is created digitally with one of theHC12’s pulse width modulators and a large capacitor. This makes it possible to create thedesired analog reference voltage from the digital pulse width modulator.
Altera FlexThe Altera “Flex” FPGA serves as a large, programmable resource for prototyping digital
systems. It can be used to implement a microprocessor core and run as a master of its ownbuses, or it can serve as a peripheral of the HC12. Logic analyzer headers are provided as ameans of monitoring its status, which can also be used for expansion connectors. Severalperipherals are also directly connected to the Altera FPGA. A simple VGA interface is providedwith a couple of diodes and resistors. Two PS/2 connectors, a serial port, and a coax connectorare available. A 25MHz oscillator is provided to meet the strict timing requirements of the VGAinterface.
DSL Development Board Rev 2/01/019
Daughter BoardThe daughter board is a “button, switches, and lights” board for the Altera FPGA. It
provides four push buttons, 16 DIP switches, four 7-segment displays, and 16 LEDs. Its purposeis to provide a variety of human interfaces to the FPGA for VHDL design and development.
7Seg_DP
Dig111
7421
1053
12
9
8
6
ABCDEFGDp
Dig1
Dig2
Dig3
Dig4R7 100
7Seg_E7Seg_F
7Seg_A
R4 100
7Seg_B
R6 100
7Seg_C
7Seg_Dig4
R2 100
7Seg_Dig1
R8 100
R1 100
7Seg_Dig3
Q2
IRF7104
1
3
2
45
6
7
8
VCC
7Seg_Dig2
R3 100
Q1
IRF7104
1
3
2
45
6
7
8
U5
74ACT541
23456789
119
1817161514131211
A1A2A3A4A5A6A7A8
G1G2
Y1Y2Y3Y4Y5Y6Y7Y8
7Seg_DR5 100
7Seg_G
Figure 8. 7 Segment Display Schematic.
To save on the number of signals necessary to run a quad 7-segment display, amultiplexed version is used. A transistor controlled by the EPLD supplies the voltage source foreach segment. Only one of the transistors should be on at a time, and it should be pulsed at a ratearound 10KHz to avoid overdriving the segments. A driver in the EPLD should be created thatscans the display pulsing the necessary segments for each one of the digits in a repeated fashion.
Button Button Button ButtonDip Switch BankDip Switch Bank
Quad Seven Segment Display
LEDs LEDs
Con
nect
orC
onne
ctor
Con
nect
orC
onne
ctor
ConnectorConnectorConnector Connector
Figure 9. Daughter Board Assembly Drawing.
DSL Development Board Rev 2/01/0110
Programmable Logic
Altera Max 7KThe Altera Max 7K is the glue logic EPLD that provides the necessary interfaces and
flexibility to make the board design extendible. Since the chip is in the middle (crossroads) ofthe board, the original developer of the code (Mike Faulhaber) code-named the project Indiana.Indiana has many different independent functions, which in most cases are controlled by aregister file presented to the main HC12. From this register file, the HC12 can manage theinternal interfaces of the chip. Due to size constraints some of the functionality of the design isconstrained. It is possible to recompile the code to provide other options, but the mostcommonly used options are run-time controllable through the register file. By default theregister file entries are four bits based at address at $0200 in the main HC12's address space.
Table 4. Indiana's Register File
Offset Register0 Upper Address1 MIPS Clock2 Bus Control3 LCD Contrast
The board architecture is based around a 16-bit bus. This makes it possible to address 216
or 64K byte locations. There are two 128K byte memories available on the board. To access theremaining locations in memory outside of the bus width, a windowing technique is used. A fixed4K window at $C000 in the main HC12's address space can be moved through the upper addressranges by concatenating the value of this register with the existing address bus.
From Indiana's point, the FPGA contains a MIPS-like microprocessor core. The clockpin for this core is configurable from Indiana. It can be clocked from the HC12 with either theHC12 or a custom clock frequency generated by the HC12's pulse width modulator. Otheroptions are to pass it a 25 MHz clock signal from an on-board oscillator, which it can usedirectly or divide down. The last choice is a custom signal from an external function generator.
Table 5. MIPS Clock Register Values.
Value Clock Source0 HC12 ECLK1 Hc12 PWM2 External Connector3 25MHz
A memory-space LCD interface is provided that can be dynamically mapped to any ofthe system buses. One issue with making an LCD a memory-mapped device is managing thetiming. The LCD expects its signals to be setup prior to receipt of an enable signal pulse. Theenable signal pulse must be asserted for at least the specified minimum duration, and must be“notched in” from both the beginning and end of the cycle. Indiana has an internal state machine
DSL Development Board Rev 2/01/0111
that handles this timing. Indiana takes the value off of the system bus, freeing the micro from theburden of the timing differences and then moves the data to the LCD with the necessary timing.The main microprocessor must wait until the LCD transaction is finished before anothertransaction may be requested. There is no built in queuing. Also the LCD has adjustablecontrast which is an analog signal ranging between zero and five volts. A counter in Indiana isprocessed through a filter to create a ranging analog signal. By varying the duty cycle of thedigital signal, an analog reference voltage can be created across the full range. This duty cycle iscontrolled by the contrast register making it possible for the HC12 to digitally manage thecontrast of the LCD.
The Bus register is used to select the master of the peripheral bus. When the value is azero, the HC12 is the master of the peripheral bus and the RAM. When the value is a one, theMIPS core has control of the peripheral bus. Through this register the HC12 can load imagesinto RAM for the MIPS core to be able to access.
Another feature that facilitates implementation of a MIPS core is a forced jumpinstruction, placed at address zero in the MIPS address space. This allows code to be loaded at ahigher address (such as $C000). When the MIPS core executes, it will automatically jump to theinsertion point.
In addition to these interfaces, there are several interfaces provided for expansion. Thecomplete peripheral address and data bus is available on headers for expansion purposes. Also,sixteen bits of user customizable signals are provided on an expansion header. This makes itpossible for development board to easily interface with other boards.
Table 6. Indiana Pin Assignments.
Signal Pin Signal Pin Signal PinRAMData15 49 MipsData15 153 HC12Data15 99RAMData14 55 MipsData14 154 HC12Data14 98RAMData13 56 MipsData13 159 HC12Data13 97RAMData12 57 MipsData12 160 HC12Data12 96RAMData11 58 MipsData11 161 HC12Data11 95RAMData10 59 MipsData10 162 HC12Data10 93RAMData9 60 MipsData9 163 HC12Data9 100RAMData8 61 MipsData8 164 HC12Data8 101RAMData7 62 MipsData7 166 HC12Data7 115RAMData6 64 MipsData6 167 HC12Data6 117RAMData5 65 MipsData5 168 HC12Data5 118RAMData4 66 MipsData4 169 HC12Data4 119RAMData3 67 MipsData3 170 HC12Data3 120RAMData2 68 MipsData2 171 HC12Data2 121RAMData1 69 MipsData1 172 HC12Data1 149RAMData0 70 MipsData0 173 HC12Data0 150RAMAddr16 21 MipsAddr15 175 HC12_PP7 133RAMAddr15 22 MipsAddr14 177 HC12_PP6 132RAMAddr14 24 MipsAddr13 178 HC12_PP5 131RAMAddr13 25 MipsAddr12 187 HC12_PP4 130RAMAddr12 26 MipsAddr11 188 HC12_PP3 129
DSL Development Board Rev 2/01/0112
Signal Pin Signal Pin Signal PinRAMAddr11 27 MipsAddr10 190 HC12_PP2 128RAMAddr10 28 MipsAddr9 192 HC12_PP1 126RAMAddr9 29 MipsAddr8 193 HC12_PP0 124RAMAddr8 31 MipsAddr7 194 HC12_PE7 114RAMAddr7 33 MipsAddr6 195 HC12_PE6 113RAMAddr6 34 MipsAddr5 196 HC12_PE5 112RAMAddr5 35 MipsAddr4 197 HC12_PE4 111RAMAddr4 36 MipsAddr3 198 HC12_PE3 110RAMAddr3 37 MipsAddr2 199 HC12_PE2 109RAMAddr2 38 MipsAddr1 201 HC12_PE1 108RAMAddr1 39 MipsAddr0 202 HC12_PE0 102RAMAddr0 40 Mips_RnW 19 Expansion15 71Ram_nWE_L 43 Mips_nOE 18 Expansion14 73Ram_nWE_H 44 Mips_nCS 20 Expansion13 76RAM_nOE 45 Mips_Input4 146 Expansion12 77RAM_nCS_Out 42 Mips_Input3 145 Expansion11 78OE2_out 142 Mips_Ctrl15 3 Expansion10 79OE1_out 140 Mips_Ctrl14 4 Expansion9 80OE1 183 Mips_Ctrl13 6 Expansion8 81nReset 204 Mips_Ctrl12 7 Expansion7 84LCD_RS 137 Mips_Ctrl11 8 Expansion6 86LCD_nWE 136 Mips_Ctrl10 9 Expansion5 87LCD_CS_Out 135 Mips_Ctrl9 10 Expansion4 88LCD_Contrast 122 Mips_Ctrl8 11 Expansion3 89Alt_nCS2 48 Mips_Ctrl7 12 Expansion2 90Alt_nCS1 47 Mips_Ctrl6 13 Expansion1 91GCLRN_out 141 Mips_Ctrl5 15 Expansion0 92GCLRN 182 Mips_Ctrl4 16GCLK2 181 Mips_Ctrl3 17GCLK_out 139 Mips_Clk 144GCLK 184Ext_Osc 205Ext_Clk 206
Altera Flex 10KThe Altera Flex FPGA can be programmed to act as an independent system. In this
mode, with the daughter board attached, it can be used for a variety of stand-alone applications.It can also implement a microprocessor core and access the RAM through the glue logic. Asidefrom running in stand-alone mode, it can be a member of the HC12's bus and provide anopportunity to develop a large single-chip peripheral. Seven test ports are provided which aredesigned to interface directly to a logic analyzer. These ports also serve as expansion connectorsto the daughter board.
DSL Development Board Rev 2/01/0113
Table 7. Pin Assignments for MIPS Core.
Signal Pin Signal Pinclock 91 test_port_one7 88rnw 221 test_port_one6 87proc_halt 72 test_port_one5 86nrst 62 test_port_one4 84noe 222 test_port_one3 83ncs 220 test_port_one2 82data15 61 test_port_one1 81data14 56 test_port_one0 80data13 55 test_port_two7 94data12 54 test_port_two6 95data11 53 test_port_two5 97data10 51 test_port_two4 98data9 50 test_port_two3 99data8 49 test_port_two2 100data7 48 test_port_two1 101data6 46 test_port_two0 102data5 45 test_port_three7 136data4 44 test_port_three6 137data3 43 test_port_three5 138data2 41 test_port_three4 139data1 40 test_port_three3 141data0 39 test_port_three2 142addr15 38 test_port_three1 143addr14 36 test_port_three0 144addr13 35 test_port_four7 146addr12 34 test_port_four6 147addr11 33 test_port_four5 148addr10 31 test_port_four4 149addr9 30 test_port_four3 151addr8 29 test_port_four2 152addr7 28 test_port_four1 153addr6 25 test_port_four0 154addr5 24 test_port_five7 156addr4 21 test_port_five6 157addr3 20 test_port_five5 158addr2 19 test_port_five4 159addr1 18 test_port_five3 161addr0 17 test_port_five2 162
test_port_five1 163test_port_five0 164
DSL Development Board Rev 2/01/0114
Table 8. Altera Flex Pin Assignments for Daughter Board.
Table 9. Altera Flex Pin Assignments for On-Board Connectors.
Signal Pin Signal PinMouse Data 174 VGA Horizontal Sync 191Mouse Clock 175 VGA Vertical Sync 192Keyboard Data 184 VGA Blue 193Keyboard Clock 187 VGA Green 194Serial Port TX 119 VGA Red 195Serial Port RX 120 25 MHz Clock 211Clock (Indiana Selectable) 91
Signal Pin Signal Pin25MHz 211 Switch One 1 219Display One Enable 136 Switch One 2 218Display Two Enable 137 Switch One 3 217Display Three Enable 138 Switch One 4 215Display Four Enable 139 Switch One 5 214Segment A 94 Switch One 6 208Segment B 95 Switch One 7 207Segment C 97 Switch One 8 206Segment D 98 Switch Two 1 204Segment E 99 Switch Two 2 203Segment F 100 Switch Two 3 202Segment G 101 Switch Two 4 201Segment DP 102 Switch Two 5 200Button 1 83 Switch Two 6 199Button 2 82 Switch Two 7 198Button 3 81 Switch Two 8 196Button 4 80 Led 8 154Led 0 164 Led 9 153Led 1 163 Led 10 152Led 2 162 Led 11 151Led 3 161 Led 12 149Led 4 159 Led 13 148Led 5 158 Led 14 147Led 6 157 Led 15 146Led 7 156
DSL Development Board Rev 2/01/0115
Main Board - Bill of MaterialsItem Quantity Reference Part Supplier1 35 C8, C18, C19, C20, C21, C200,
C201, C202, C203, C204, C205,C206, C207, C208, C209, C210,C500, C501, C502, C503, C504,C505, C506, C507, C508, C509,C510, C511, C512, C513, C600,C601, C602, C603, C604
0.1uF Mouser#140-CC502B104K
2 2 C30, C223 10uF Mouser#140-XRL10V10
3 5 C101, C102, C103, C105, C106 0.33uF Mouser#74-199D35V0.33
4 1 C104 0.68uF Mouser#74-199D35V0.68
5 5 D1, D500, D501, D502, D600 1N4148 Mouser# 625-1N41486 3 D2, D4, D601 1N4001 Mouser# 625-1N40017 1 D5 LED8 1 F1 1.5A DigiKey#
F1236CT-ND9 2 JH1, JH600 Flash Prog Mouser#
571-4103185010 1 JH2 Ext_Pwr Mouser#
571-4103185011 1 JH200 Ext_Clk Mouser#
571-4103185012 1 JP202 HEADER 14 Mouser
#571-4103185013 1 JP204 HEADER 5X2 Mouser#
571-4103186014 1 JP300 HEADER 17X215 1 JP302 HEADER 6X2 Mouser#
571-4103186016 1 JP400 HEADER 20 Mouser
#571-4103185017 7 JP405, JP406, JP407, JP408,
JP409, JP604, JP605HEADER 3 Mouser
#571-4103185018 1 JP500 HEADER 4X2 Mouser#
571-4103186019 7 JP501, JP502, JP503, JP504,
JP505, JP506, JP507HEADER 8X2 Mouser#
571-4103186020 1 JP508 CONN CIR 6-P Digikey #
CP-2460-ND21 1 JP509 CONN CIR 6-P Digikey#
CP-2460-ND22 2 JP602, JP603 HEADER 3X2 Mouser#
571-4103186023 1 J2 DC Power Digi-Key
#SC1152-ND24 1 J210 BNC Digikey#
ARF1065NW-ND25 1 J211 CON15 Digikey# A2091-ND
DSL Development Board Rev 2/01/0116
Item Quantity Reference Part Supplier26 4 P2, P3, P4, P6 HEADER 10X2 Mouser#
571-4103186027 3 P100, P101, P102 CONNECTOR DB9 Mouser #571-747844428 66 R1, R219, R220, R221, R223,
R240, R241, R242, R243, R250,R251, R252, R253, R254, R255,R256, R257, R260, R261, R262,R263, R264, R265, R303, R304,R305, R306, R311, R312, R320,R321, R322, R323, R324, R325,R326, R327, R328, R329, R330,R331, R332, R333, R334, R335,R340, R341, R342, R343, R344,R345, R346, R347, R348, R349,R350, R351, R352, R353, R354,R355, R503, R504, R505, R506,R600
1K Mouser# ME263-1K
29 15 R3, R5, R7, R8, R9, R10, R603,R605, R607, R608, R609, R610,R611, R612, R613
15K Mouser# ME263-15K
30 7 R100, R101, R102, R103, R104,R300, R301
10K Mouser# ME263-10K
31 17 R230, R270, R271, R272, R273,R274, R275, R276, R277, R278,R279, R280, R281, R282, R283,R284, R285
33 Mouser# ME263-33
32 3 R500, R501, R502 10K Mouser# 271-10K33 2 SW1, SW600 SW_PUSHBUTTON Digikey# P8066S34 2 U2, U600 MC68HC912B32 Motorola35 2 U3, U603 MC34164 Newark# 66F130736 1 U5 74ACT244 Digikey#
74ACT244SC-ND37 1 U10 MIC29300 Newark #83F591538 1 U101 MAX562 Maxium39 1 U200 EPM7256SRC208 Sampled40 2 U301, U302 CY7C109 Cypress41 1 U501 EPF10K40 Sampled42 1 Y2 16Mhz Digikey# CTX166-ND43 1 Y201 25.175Mhz Digikey# CTX172-ND
DSL Development Board Rev 2/01/0117
Feature Board - Bill of MaterialsItem Quantity Reference Part Supplier1 1 Dig1 4-7seg Mouser#
512-MSQ6911C2 2 D1, D2 IRF7104 Digikey#
IRF7104-ND3 16 D7, D8, D9, D10, D11, D12,
D13, D14, D15, D16, D17, D18,D19, D20, D21, D22
RED Mouser# 550-2404
4 7 JP1, JP2, JP3, JP4, JP5, JP6, JP7 HEADER 8X2 SOCKET5 1 JP8 HEADER 4X2 SOCKET6 8 R1, R2, R3, R4, R5, R6, R7, R8 1007 6 R10, R11, R12, R13, R40, R41 10K8 16 R20, R21, R22, R23, R24, R25,
R26, R27, R30, R31, R32, R33,R34, R35, R36, R37
1K
9 4 SW1, SW2, SW3, SW4 FSM102 Mouser#107-DS662-5BLK
10 2 SW6, SW5 DipSwitch Mouser# 106-120811 1 U5 74ACT541 Digikey#
TC74ACT541FW-ND
DSL Development Board Rev 2/01/0118
Max 7K (Indiana) Source
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - C r e a t e d o n : 4 - 4 - 0 0- - C r e a t e d b y : M i k e F a u l h a b e r , K u r t O t t e- - V e r s i o n 1 . 1- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -l i b r a r y i e e e ;u s e i e e e . s t d _ l o g i c _ 1 1 6 4 . A L L ;u s e i e e e . s t d _ l o g i c _ a r i t h . A L L ;u s e i e e e . s t d _ l o g i c _ u n s i g n e d . A L L ;
e n t i t y I n d i a n a i s
p o r t ( n R e s e t : i n s t d _ l o g i c ; E x t _ C l k : i n s t d _ l o g i c ; E x t _ O s c : i n s t d _ l o g i c ;
- - L o o p B a c k G C L R N : i n s t d _ l o g i c ; O E 1 : i n s t d _ l o g i c ; G C L K 2 : i n s t d _ l o g i c ; G C L K : i n s t d _ l o g i c ;
G C L R N _ o u t : o u t s t d _ l o g i c ; O E 1 _ o u t : o u t s t d _ l o g i c ; O E 2 _ o u t : o u t s t d _ l o g i c ; G C L K _ o u t : o u t s t d _ l o g i c ;
- - H C 1 2 P o r t s H C 1 2 D a t a : i n o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; H C 1 2 _ P E : i n s t d _ l o g i c _ v e c t o r ( 7 d o w n t o 0 ) ; H C 1 2 _ P P : i n s t d _ l o g i c _ v e c t o r ( 7 d o w n t o 0 ) ;
- - M i p s M i p s D a t a : i n o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; M i p s A d d r : i n s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ;
M i p s _ n C S : i n s t d _ l o g i c ; - - C t r l 0 M i p s _ R n W : i n s t d _ l o g i c ; - - C t r l 1 M i p s _ n O E : i n s t d _ l o g i c ; - - C t r l 2 M i p s _ C t r l : i n s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 3 ) ;
M i p s _ C l k : o u t s t d _ l o g i c ; M i p s _ I n p u t 3 : o u t s t d _ l o g i c ; M i p s _ I n p u t 4 : o u t s t d _ l o g i c ;
- - P e r f . R a m _ n W E _ L : o u t s t d _ l o g i c ; R a m _ n W E _ H : o u t s t d _ l o g i c ; R A M _ n C S _ O u t : o u t s t d _ l o g i c ; R A M _ n O E : o u t s t d _ l o g i c ; R A M A d d r : o u t s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; R A M D a t a : i n o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ;
A l t _ n C S 1 : o u t s t d _ l o g i c ; A l t _ n C S 2 : o u t s t d _ l o g i c ;
E x p a n s i o n : o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ;
L C D _ C o n t r a s t : o u t s t d _ l o g i c ; L C D _ C S _ O u t : o u t s t d _ l o g i c ; L C D _ n W E : o u t s t d _ l o g i c ; L C D _ R S : o u t s t d _ l o g i c ) ;e n d I n d i a n a ;
DSL Development Board Rev 2/01/0119
a r c h i t e c t u r e s t r u c t u r e o f I n d i a n a i s
- - S i g a l s u s e d i n n a m e t r a n s l a t i o n
s i g n a l E C l k : s t d _ l o g i c ; s i g n a l n L S T R B : s t d _ l o g i c ; s i g n a l H C 1 2 R n W : s t d _ l o g i c ;
s i g n a l P W M : s t d _ l o g i c ; s i g n a l B N C : s t d _ l o g i c ; s i g n a l O S C : s t d _ l o g i c ;
- - P L D A d d r e s s s e l e c t
s i g n a l I n t _ n C S : s t d _ l o g i c ;
- - P L D A d d r e s s R e g i s t e r s
s i g n a l U p p e r _ A d d r e s s _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l C L K _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l B u s _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l C o n t r a s t _ R e g : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ;
- - F o r A d d r e s s / D a t a R o u t i n g
s i g n a l H C 1 2 A d d r _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l H C 1 2 A d d r _ I n t _ E x t e n d e d : s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; s i g n a l H C 1 2 D a t a _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l P l d _ D a t a : s t d _ l o g i c _ v e c t o r ( 3 d o w n t o 0 ) ; s i g n a l E x t D e v i c e _ D a t a : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l R A M D a t a _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l R A M D a t a _ F i l t e r e d : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l R A M A d d r _ I n t : s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; s i g n a l M i p s D a t a _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l M i p s A d d r _ I n t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; s i g n a l M i p s A d d r _ I n t _ E x t e n d e d : s t d _ l o g i c _ v e c t o r ( 1 6 d o w n t o 0 ) ; s i g n a l C r o p p e d _ M i p s _ A d d r : s t d _ l o g i c _ v e c t o r ( 5 d o w n t o 0 ) ; - - M i p s C l o c k S o u r c e
s i g n a l M i p s _ C l k _ I n t : s t d _ l o g i c ;
- - C o n t r o l S i g n a l s
s i g n a l H c 1 2 _ R a m _ n C S : s t d _ l o g i c ; s i g n a l M i p s _ R a m _ n C S : s t d _ l o g i c ;
s i g n a l R A M _ n C S : s t d _ l o g i c ; s i g n a l L C D _ C S : s t d _ l o g i c ; s i g n a l L C D _ S e l e c t : s t d _ l o g i c ;
s i g n a l H C 1 2 _ n O E : s t d _ l o g i c ;
s i g n a l H C 1 2 _ D a t a b u s _ E n : s t d _ l o g i c ; s i g n a l M i p s _ D a t a b u s _ E n : s t d _ l o g i c ;
s i g n a l H C 1 2 _ n W E : s t d _ l o g i c ; s i g n a l H C 1 2 _ n W E _ L : s t d _ l o g i c ; s i g n a l H C 1 2 _ n W E _ H : s t d _ l o g i c ;
t y p e s t a t e _ t y p e i s ( W a i t i n g , P u l s e , H o l d ) ; s i g n a l S t a t e : s t a t e _ t y p e ; s i g n a l c o u n t : i n t e g e r r a n g e 0 t o 7 ; s i g n a l c o n t r a s t _ c o u n t e r : s t d _ l o g i c _ v e c t o r ( 7 d o w n t o 0 ) ;
b e g i n
- - - - - - - - - - - - - - - - - - S i g n a l R e m a p i n g - - - - - - - - - - - - - - - - - - - - - - - - - - - - I n o r d e r t o r e s e r v e s o m e s i g n a l s f o r l a t e r u s e a n d t o m a k e t h e - - p i n o u t o f t h e c h i p m a t c h t h e s c h e m a t i c s i g n a l s h a v e b e e n - - r e m a p p e d . T h e m a j o r i t y o f t h e f o l l o w i n g e q u a t i o n s w i l l n o t
DSL Development Board Rev 2/01/0120
- - - r e s u l t i n a n y l o g i c s y n t h e s i s j u s t n a m e t r a n s l a t i o n .
E C l k < = H C 1 2 _ P E ( 4 ) ; n L S T R B < = H C 1 2 _ P E ( 3 ) ; H C 1 2 R n W < = H C 1 2 _ P E ( 2 ) ;
P W M < = H C 1 2 _ P P ( 0 ) ; B N C < = E x t _ C l k ; O S C < = E x t _ O s c ;
- - - - - - - - - - - - - - - - - - - G l o b a l S i g n a l s L o o p b a c k - - - - - - - - - - - - - - - - - - - - G C L R N _ o u t < = n R e s e t ; O E 1 _ o u t < = ' 1 ' ; O E 2 _ o u t < = E C l k ; G C L K _ o u t < = ' Z ' ;
- - - - - - - - - - - - R e s e r v e d S i g n a l - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T h i s s i g n a l s a r e r e s e r v e d f o r f u t u r e e x p a n s i o n s M i p s _ I n p u t 3 < = ' 0 ' ; M i p s _ I n p u t 4 < = ' 0 ' ; A l t _ n C S 1 < = G C L K ; A l t _ n C S 2 < = G C L K 2 ;
E x p a n s i o n < = " 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 " ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - M I P S C l o c k S o u r c e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - D e p e n d i n g o n t h e v a l u e s s e t i n C l k _ R e g , t h e C l o c k s e n t t o t h e M I P S- - C h i p g e t s t h e c o o r e s p o n d i n g c l o c k
M i p s _ C l k < = M i p s _ C l k _ I n t ;
w i t h C l k _ R e g ( 1 d o w n t o 0 ) s e l e c t M i p s _ C l k _ I n t < = ( E C l k ) w h e n " 0 0 " , - - ( t o M I P S ) H C 1 2 e c l k ( P W M ) w h e n " 0 1 " , - - M i p s _ C l k _ I n t ( t o M I P S ) g e t s H C 1 2 P W M ( B N C ) w h e n " 1 0 " , - - M i p s _ C l k _ I n t ( t o M I P S ) g e t s B N C ( O S C ) w h e n " 1 1 " , - - M i p s _ C l k _ I n t ( t o M I P S ) g e t s O S C ' 0 ' w h e n o t h e r s ;
- - - - - - - - - - * e n d * - M I P S C l o c k S o u r c e - * e n d * - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - T r a n s p a r e n t L a t c h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H C 1 2 A d d r _ I n t < = H C 1 2 D a t a w h e n ( E C l k = ' 0 ' ) e l s e H C 1 2 A d d r _ I n t ;
- - - - - - - - - - - - - - - - - - - - - P L D I n t e r n a l A d d r e s s S p a c e - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - T h i s p r o c e s s e f f e c t s t h e C o n t r o l R e g i s t e r s - - W h e n t h e A d d r e s s b e i n g w r i t t e n f r o m t h e H C 1 2 i s 0 x 2 0 0 [ 0 - 3 ] - - T h e D a t a i s m a p p e d t o a C o n t r o l R e g i s t e r P L D _ R e g i s t e r _ W r i t t i n g : p r o c e s s ( G C L K 2 , G C L R N ) b e g i n i f G C L R N = ' 0 ' t h e n U p p e r _ A d d r e s s _ R e g ( 3 d o w n t o 0 ) < = " 0 1 1 0 " ; C l k _ R e g ( 3 d o w n t o 0 ) < = " 0 0 0 0 " ; B u s _ R e g ( 3 d o w n t o 0 ) < = " 0 0 0 0 " ; C o n t r a s t _ R e g ( 3 d o w n t o 0 ) < = " 1 1 0 0 " ;
e l s i f ( G C L K 2 ' e v e n t a n d G C L K 2 = ' 0 ' ) t h e n i f ( H C 1 2 R n W = ' 0 ' a n d I n t _ n C S = ' 0 ' ) t h e n - - P L D w r i t e m o d e c a s e H C 1 2 A d d r _ I n t ( 1 d o w n t o 0 ) i s w h e n " 0 0 " = > - - A d d r e s s S p a c e M a p p i n g R e g U p p e r _ A d d r e s s _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n " 0 1 " = > - - M i p s C l o c k S o u r c e R e g C l k _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n " 1 0 " = > - - B u s F l o w D i r e c t i o n R e g B u s _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n " 1 1 " = > - - L C D C o n t r a s t C o n t r a s t _ R e g < = H C 1 2 D a t a ( 1 1 d o w n t o 8 ) ; w h e n o t h e r s = > e n d c a s e ;
DSL Development Board Rev 2/01/0121
e n d i f ; - - c h i p s e l e c t e n d i f ; - - r e s e t / c l k e n d p r o c e s s P L D _ R e g i s t e r _ W r i t t i n g ;
L C D _ C o n t r o l : p r o c e s s ( G C L K ) b e g i n i f ( G C L K ' e v e n t a n d G C L K = ' 0 ' ) t h e n c a s e S t a t e i s w h e n W a i t i n g = > - - W a i t i n g f o r c h i p s e l e c t L C D _ C S < = ' 0 ' ; i f ( L C D _ S e l e c t = ' 1 ' ) t h e n S t a t e < = P u l s e ; c o u n t < = 0 ; e n d i f ;
w h e n P u l s e = > - - p u l s e e n a b l e s i g n a l L C D _ C S < = ' 1 ' ; i f ( c o u n t = 3 ) t h e n s t a t e < = H o l d ; e l s e c o u n t < = c o u n t + 1 ; e n d i f ;
w h e n H o l d = > L C D _ C S < = ' 0 ' ; i f ( L C D _ S e l e c t = ' 0 ' ) t h e n s t a t e < = W a i t i n g ; e n d i f ;
e n d c a s e ; e n d i f ; e n d p r o c e s s L C D _ C o n t r o l ;
- - L C D _ C o n t r a s t < = P W M ; C o n t r a s t : p r o c e s s ( G C L K ) b e g i n i f ( G C L K ' e v e n t a n d G C L K = ' 0 ' ) t h e n c o n t r a s t _ c o u n t e r < = c o n t r a s t _ c o u n t e r + 1 ; i f ( c o n t r a s t _ c o u n t e r = C o n t r a s t _ R e g & " 1 1 1 0 " ) t h e n L C D _ C o n t r a s t < = ' 1 ' ; e l s i f ( c o n t r a s t _ c o u n t e r = " 1 1 1 1 1 1 1 1 " ) t h e n L C D _ C o n t r a s t < = ' 0 ' ; e n d i f ; e n d i f ; e n d p r o c e s s C o n t r a s t ;
- - T h e L C D R e g i s t e r S p a c e i s a t A d d r 0 x 0 2 1 0 t o 0 x 0 2 1 F ( R e g i s t e r - - F o l l o w i n g A r e a o f H C 1 2 ) t h e f o l l o w i n g l i n e c o n t r o l s r e a d i n g - - a n d w r i t t i n g t o t h e p l d r e g i s t e r s p a c e .
L C D _ S e l e c t < = ' 1 ' w h e n ( H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 4 ) = " 0 0 0 0 0 0 1 0 0 0 0 1 " a n dG C L K 2 = ' 1 ' ) e l s e ' 0 ' ; L C D _ C S _ O u t < = L C D _ C S a n d L C D _ S e l e c t ;
- - * * * * D a t a B u s M a n a g e m e n t * * * * - - ( P L D R e g i s t e r R e a d i n g ) w i t h H C 1 2 A d d r _ I n t ( 1 d o w n t o 0 ) s e l e c t P l d _ D a t a < = ( U p p e r _ A d d r e s s _ R e g ) w h e n " 0 0 " , - - A d d r S p a c e M a p p i n g R e g ( C l k _ R e g ) w h e n " 0 1 " , - - M i p s C l o c k S o u r c e R e g ( B u s _ R e g ) w h e n " 1 0 " , - - B u s F l o w D i r e c t i o n R e g ( C o n t r a s t _ R e g ) w h e n " 1 1 " , - - C o n t r a s t R e g ( " 1 0 1 0 " ) w h e n o t h e r s ;
- - t h e a b o v e o n l y d r i v e s t h e H C 1 2 D a t a b u s w h e n a r e a d o c c u r s o n - - t h e P L D A d d r e s s S p a c e H C 1 2 D a t a _ I n t < = ( " 0 0 0 0 " & P l d _ D a t a & " 0 0 0 0 " & P l d _ D a t a ) w h e n ( I n t _ n C S =' 0 ' ) e l s e E x t D e v i c e _ D a t a ;
DSL Development Board Rev 2/01/0122
- - - - - - - - * e n d * - P L D I n t e r n a l A d d r e s s S p a c e - * e n d * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - B u s F l o w D i r e c t i o n - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D e p e n d i n g o n t h e v a l u e s s e t i n B u s _ R e g , t h e D i r e c t i o n o f t h e - - B u s F l o w o f t h e m a y c h a n g e .
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t E x t D e v i c e _ D a t a < = ( R A M D a t a ) w h e n " 0 0 " , - - H C 1 2 I s C o n n e c t e d t o R A M / L C D - - w h e n " 0 1 " , - - H C 1 2 I s N o t C o n n e c t e d ( M i p s D a t a ) w h e n " 1 0 " , - - H C 1 2 I s C o n n e c t e d t o M i p s ( " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m D a t a _ I n t < = H C 1 2 D a t a w h e n " 0 0 " , - - H C 1 2 I s C o n n e c t e d t o R A M M i p s D a t a w h e n " 0 1 " , - - M i p s I s C o n n e c t e d t o R A M - - w h e n " 1 0 " , - - R A M I s N o t C o n n e c t e d " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m A d d r _ I n t < = ( H C 1 2 A d d r _ I n t _ E x t e n d e d ) w h e n " 0 0 " , - - H C 1 2 t o R A M ( M i p s A d d r _ I n t _ E x t e n d e d ) w h e n " 0 1 " , - - M i p s t o R A M - - w h e n " 1 0 " , - - R A M N o t C o n n e c t e d ( " 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t M i p s D a t a _ I n t < = - - w h e n " 0 0 " , - - M i p s N o t C o n n e c t e d ( R a m D a t a _ F i l t e r e d ) w h e n " 0 1 " , - - M i p s t o R A M ( H C 1 2 D a t a ) w h e n " 1 0 " , - - M i p s t o H C 1 2 ( " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
- - W e r o u t e t h e a d d r e s s b u s t o t h e t w o p a r t s t h a t a r e w r i t t e n t o( w r i t e e s ) w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t M i p s A d d r _ I n t < = - - w h e n " 0 0 " , - - M i p s I s N o t C o n n e c t e d ( M i p s A d d r ) w h e n " 0 1 " , - - M i p s I s C o n n e c t e d t o R A M ( H C 1 2 A d d r _ I n t ) w h e n " 1 0 " , - - M i p s I s C o n n e c t e d t o H C 1 2 ( " 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 " ) w h e n o t h e r s ;
C r o p p e d _ M i p s _ A d d r < = M i p s A d d r ( 1 5 d o w n t o 1 3 ) & M i p s A d d r ( 3 d o w n t o 1 ) ;- - T h i s w a s d o n e t o c u t d o w n o n n u m o f l i n e s n e e d i n g t o b e m a t c h e d- - w i t h ( C r o p p e d _ M i p s _ A d d r ) s e l e c t s o t h e d e s i g n w o u l d f i t
R a m D a t a _ F i l t e r e d < = - - 0 x D 7 C 0 L U I r 7 0 x c 0 0 0 m a t c h e s 0 0 0 x x x x x x x x x 0 0 0 x " 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 " w h e n " 0 0 0 0 0 0 " , " 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 " w h e n " 0 0 0 0 0 1 " , - - 0 x 9 F 0 0 J R r 7 R a m D a t a w h e n o t h e r s ;
R a m A d d r < = R a m A d d r _ I n t ;
R a m D a t a < = R a m D a t a _ I n t w h e n ( ( B u s _ R e g ( 1 d o w n t o 0 ) = " 0 0 " a n d H C 1 2 _ n W E = ' 0 ' ) o r ( B u s _ R e g ( 1 d o w n t o 0 ) = " 0 1 " a n d M i p s _ R n W = ' 0 ' ) ) e l s e " Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z " ;
H C 1 2 D a t a < = H C 1 2 D a t a _ I n t w h e n ( H C 1 2 _ D a t a b u s _ E n = ' 1 ' ) e l s e " Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z " ; M i p s D a t a < = M i p s D a t a _ I n t w h e n ( M i p s _ D a t a b u s _ E n = ' 1 ' )
DSL Development Board Rev 2/01/0123
e l s e " Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z " ;
- - - - - - - * e n d * - B u s F l o w D i r e c t i o n - * e n d * - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - A d d r e s s S p a c e M a p p i n g - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - W i n d o w 0 x C 0 0 0 t h r o u g h m e m o r y d e p e n d i n g o n t h e v a l u e o f - - U p p e r A d d r e s s R e g
w i t h ( H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 1 2 ) ) s e l e c t H C 1 2 A d d r _ I n t _ E x t e n d e d < = U p p e r _ A d d r e s s _ R e g ( 3 d o w n t o 0 ) & H C 1 2 A d d r _ I n t ( 1 3 d o w n t o 1 ) w h e n " 1 1 0 0 " , " 0 0 " & H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 1 ) w h e n o t h e r s ;
w i t h ( M i p s A d d r _ I n t ( 1 5 d o w n t o 1 2 ) ) s e l e c t M i p s A d d r _ I n t _ E x t e n d e d < = U p p e r _ A d d r e s s _ R e g ( 3 d o w n t o 0 ) & M i p s A d d r _ I n t ( 1 3 d o w n t o 1 ) w h e n " 1 1 0 0 " " 0 0 " & M i p s A d d r _ I n t ( 1 5 d o w n t o 1 ) w h e n o t h e r s ;
- - - - - - - - * e n d * - A d d r e s s S p a c e M a p p i n g - * e n d * - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - C o n t r o l S i g n a l s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - T h e P L D R e g i s t e r S p a c e i s a t A d d r 0 x 0 2 0 0 t o 0 x 0 2 0 F - - ( R e g i s t e r F o l l o w i n g A r e a o f H C 1 2 ) - - t h e f o l l o w i n g l i n e c o n t r o l s r e a d i n g a n d w r i t t i n g t o - - t h e p l d r e g i s t e r s p a c e .
I n t _ n C S < = ' 0 ' w h e n ( H C 1 2 A d d r _ I n t ( 1 5 d o w n t o 4 ) = " 0 0 0 0 0 0 1 0 0 0 0 0 " a n d G C L K 2 = ' 1 ' ) e l s e ' 1 ' ;
H c 1 2 _ R a m _ n C S < = ' 0 ' w h e n ( H C 1 2 A d d r _ I n t ( 1 5 ) = ' 1 ' a n d G C L K 2 = ' 1 ' ) e l s e ' 1 ' ;
M i p s _ R a m _ n C S < = M i p s _ n C S ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m _ n C S < = H C 1 2 _ R a m _ n C S w h e n " 0 0 " , - - H C 1 2 M i p s _ R a m _ n C S w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
R A M _ n C S _ O u t < = R A M _ n C S w h e n ( ( L C D _ C S = ' 0 ' ) a n d ( I n t _ n C S = ' 1 ' ) ) e l s e ' 1 ' ;
- - O u t p u t E n a b l e s H C 1 2 _ n O E < = N O T ( G C L K 2 A N D H C 1 2 R n W ) ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R A M _ n O E < = H C 1 2 _ n O E w h e n " 0 0 " , - - H C 1 2 M i p s _ n O E w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
H C 1 2 _ D a t a b u s _ E n < = H C 1 2 R n W a n d G C L K 2 ; M i p s _ D a t a b u s _ E n < = M i p s _ R n W a n d N o t M i p s _ n C S ;
- - W r i t e E n a b l e s - - D o n ' t a l l o w R n W t o g o l o w w h e n A d d r i n f o i s o n t h e b u s H C 1 2 _ n W E < = H C 1 2 R n W O R ( N o t G C L K 2 ) ;
- - S e l e c t t h e l o w b y t e R A M f o r a w r i t e H C 1 2 _ n W E _ L < = H C 1 2 _ n W E O R n L S T R B ;
- - S e l e c t t h e h i g h b y t e R A M f o r a w r i t e H C 1 2 _ n W E _ H < = H C 1 2 _ n W E O R H C 1 2 A d d r _ I n t ( 0 ) ;
DSL Development Board Rev 2/01/0124
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R A M _ n W E _ L < = H c 1 2 _ n W E _ L w h e n " 0 0 " , - - H C 1 2 M i p s _ R n W w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
w i t h B u s _ R e g ( 1 d o w n t o 0 ) s e l e c t R a m _ n W E _ H < = H c 1 2 _ n W E _ H w h e n " 0 0 " , - - H C 1 2 M i p s _ R n W w h e n " 0 1 " , - - M i p s ' 1 ' w h e n o t h e r s ;
L C D _ n W E < = H C 1 2 _ n W E ; L C D _ R S < = H C 1 2 A d d r _ I n t ( 1 ) ;
e n d s t r u c t u r e ;
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Alt PartAlt Part
MODA MODB
D
Purdue Digital Labs - Main HC12
A
1 1Sunday, February 11, 2001
Kurt Otte Kurt Otte
Title
Size Rev
Date: Sheet of
Designed By Drawn By:
PAD3
PA6
PP2PA1
PDLC4
PA5
PDLC2
PAD2
PA0
PS3
PAD1
PDLC1PDLC0
PS4
PAD0
PA7
PP3
PS7
PAD5
PP5
PDLC3
PS5
PP6
PP0
PDLC6
PAD6
PA2
PDLC5
PAD4
PAD7
PA4PA3
PP4
PP1
PS6
PS2PS1PS0
PP7
PT7PT6PT5PT4PT3PT2PT1PT0
PB7PB6PB5PB4PB3PB2PB1PB0
PE7PE6PE5PE4PE3PE2PE1PE0
BKGD
VDDX78
PE5 PE6
PA[7..0]
PB[7..0]
PE[7..0]
PT[7..0]
PS0
PAD[7..0]
PS1
VRL VDDX31
VDDAD
PP[7..0]
nReset
BKGD
PB0
PP1
VDDAD
PE1
VSSAD
PAD3PT4
PB6
PAD1
PA6
PT3
PT6PT5
PA1
PT7
PE7
PA7
PB1
PAD0
PE5
PAD6
PA0
PT1PT2
PB7
PA3
PE0
BKGDPB2
nRESET
PP4
PAD4
PA5PA2
PP3
PB4
PAD2
PE3
PE6
VRHVSS48
PA4PP2
PT0
PAD7
PB3
PAD5
VRL
XTALVDDX31
VDD47
VSSX30
PE2EXTAL
PP0
VSS11
PE4
VDD10
PP5
PB5
XTAL16Mhz EXTAL
VRH
PDLC1PDLC3
PS5PS4
VDD47
PS1
VFP
PDLC2PDLC4PDLC5
nRESET
PS6
PP7
PS2
PP6VDDX78
VDD10
VSSX77
VFP
PS3PS0
PDLC6PS7
PDLC0
Ext_Pwr
VSS11
VSS48
VSSAD
VSSX30
VSSX77
16Mhz
PDLC[6..2]
PS[7..4]
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
JH1
Flash Prog
11
R1015K
MIC29300U10
123
InGndVcc
D1
1N4148D2
1N4001
1 2
R1
1K
C3010uF
R315K
P6
HEADER 10X2
1 23 45 67 89 1011 1213 1415 1617 1819 20
R715K
R815K
D4
1N4001
12
P4
HEADER 10X2
1 23 45 67 89 1011 1213 1415 1617 1819 20
D5
LED
C80.1uF
P3
HEADER 10X2
1 23 45 67 89 1011 1213 1415 1617 1819 20
C21
0.1uF
Y216Mhz
5O
UT
C20
0.1uF
P2
HEADER 10X2
1 23 45 67 89 1011 1213 1415 1617 1819 20
C19
0.1uF
U3MC34164
2 1
3
IN RSET
GN
D
J2
DC Power
1
2
C18
0.1uF
JH2Ext_Pwr
11
F1 2.5A
U2
MC68HC912B32
3940414243444546
5152535455565758
6162636465666768
76757473727170
11304877
654321
8079
789
1213141516
1819202122232425
3837363529282726
17323334
495069
5960
10314778
PA0PA1PA2PA3PA4PA5PA6PA7
PAD0PAD1PAD2PAD3PAD4PAD5PAD6PAD7
PS0PS1PS2PS3PS4PS5PS6PS7
PDLC0PDLC1PDLC2PDLC3PDLC4PDLC5PDLC6
VSSVSSX
VSSVSSX
PP0PP1PP2PP3PP4PP5PP6PP7
PT0PT1PT2PT3PT4PT5PT6PT7
PB0PB1PB2PB3PB4PB5PB6PB7
PE0PE1PE2PE3PE4PE5PE6PE7
BKGDnResetEXTALXTAL
VRHVRLVFP
VDDADVSSAD
VDDVDDX
VDDVDDX
R515K
SW1
R915K
PA[7..0]
PB[7..0]
PE[7..0]
PT[7..0]
PS0
PAD[7..0]
PS1
PP[7..0]
nReset
BKGD
16Mhz
PDLC[6..2]
PS[7..4]
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
D
Purdue Digital Labs - Serial Ports
A
1 1Sunday, February 11, 2001
Kurt Otte Kurt Otte
Title
Size Rev
Date: Sheet of
Designed By Drawn By:
HC12_Tx
HC12_Rx
Mips_Tx
Mips_Rx
Debugger_Tx
Debugger_Rx
HC12_RxDebugger_RxMips_Rx
Mips_Tx
HC12_TxDebugger_Tx
VCC
VCC
VCC
U101
MAX562
1920212223
1
678910
181716
111213
15
14
25
34
2524
2826
R5INR4INR3INR2INR1IN
VCC
R1OUTR2OUTR3OUTR4OUTR5OUT
T1OUTT2OUTT3OUT
T1INT2INT3IN
SHDN
EN
C1A+C1A-
C1B+C1B-
C2+C2-
V+V-
C102 0.33uF
C103 0.33uF
R10010K
R103
10K
P102
CONNECTOR DB9
594837261
R102
10K
R101
10K
P100
CONNECTOR DB9
594837261
C1040.68uF
C105 0.33uF
C1060.33uF
P101
CONNECTOR DB9
594837261
C101 0.33uFR10410K
PS1
Mips_Tx
PS0
Mips_Rx
Debugger_Rx
Debugger_Tx
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA Po rt
Keyboa rdPort
Mouse P ort
Alt
D
Purdue Digital Labs - Altera Flex
C
1 1Sunday, February 11, 2001
Kurt Otte Kurt Otte
Title
Size Rev
Date: Sheet of
Designed By Drawn By:
VGA_Vert_SyncVGA_Horiz_Sync
Feature_Four4
Feature_One3
Feature_Four3
Feature_Three3
Feature_One7
Feature_Two5
Feature_Two3
Feature_Two7
Feature_Three0
Feature_Four2
Feature_Four0
Feature_One6
Feature_Four5
Feature_Three4
Feature_Five5
Feature_One5
Feature_Five0
Feature_One2
Feature_Five1
Feature_Two0
Feature_Three2
Feature_Four1
Feature_Five7Feature_Five6
Feature_Four6
Feature_Two1
Feature_Five3
Feature_Three5
Feature_Two4
Feature_Five2
Feature_Five4
Feature_Two6
Feature_Four7
Feature_Three7
Feature_One4
Feature_Three1
Feature_One0Feature_One1
Feature_Two2
Feature_Three6
Keyboard_DataMouse_Data
Keyboard_ClkMouse_Clk
PS[7..4]
VGA_Blue
Conf_Done
10K_TDO
Pgm_Data
VGA_Red
TCK
VGA_Green
EPC_TDO
nTrst
TMS
nStatusnConfig
DClk
Mips_Addr13
Mips_Addr10
Mips_Addr7
Mips_Addr0Mips_Addr1
Mips_Data5
Mips_Data10
Mips_Data2
Mips_Data0Mips_Data1
Mips_Addr12
Mips_Data12Mips_Data13
Mips_Data9
Mips_Addr8
Mips_Addr3
Mips_Data15
Mips_Data8
Mips_Addr11
Mips_Addr6
Mips_Data4
Mips_Data7
Mips_Addr5
Mips_Data11
Mips_Data3
Mips_Addr2
Mips_Addr4
Mips_Addr15
Mips_Data14
Mips_Addr14
Mips_Data6
Mips_Addr9
PT7PT6
PAD0
PAD2
PAD4PAD5PAD6
PAD3
PAD1
PAD7
Feature_Two4
Feature_One1
Feature_One7
Feature_Two3
Feature_Two1
Feature_One6
Feature_Two6
Feature_One2Feature_One3
Feature_Two2
Feature_One5
Feature_One0
Feature_Two0
Feature_One4
Feature_Two7
Feature_Two5
Mips_Ctrl10
Mips_Ctrl15
Mips_Ctrl8Mips_Ctrl9
Mips_Ctrl12Mips_Ctrl11
Mips_Ctrl13Mips_Ctrl14
Mips_Ctrl5
Mips_Ctrl3
Mips_Ctrl6
Mips_Ctrl4
Mips_Ctrl2
Mips_Ctrl7
Mips_Ctrl0Mips_Ctrl1
Mips_Input3Mips_Input4
Feature_Six3Feature_Six4
Feature_Six0
Feature_Six6
Feature_Six2
Feature_Six5
Feature_Six1
Feature_Six7
Feature_Seven3Feature_Seven4
Feature_Seven0
Feature_Seven6
Feature_Seven2
Feature_Seven5
Feature_Seven1
Feature_Seven7
Keyboard_Clk
Mouse_Data
Keyboard_DataMouse_Clk
VGA_Vert_SyncVGA_Horiz_Sync
VGA_GreenVGA_Blue
VGA_Red
Feature_Five2
Feature_Four3
Feature_Five0
Feature_Five6
Feature_Four5
Feature_Three3
Feature_Three7
Feature_Three5
Feature_Three0
Feature_Four1
Feature_Five3
Feature_Three4
Feature_Four0
Feature_Four7Feature_Four6
Feature_Three2Feature_Three1
Feature_Four4
Feature_Five5Feature_Five4
Feature_Three6
Feature_Five7
Feature_Five1
Feature_Four2
Feature_Six6
Feature_Seven5
Feature_Seven3
Feature_Seven0
Feature_Six4
Feature_Six1
Feature_Seven6
Feature_Seven2
Feature_Six5
Feature_Seven4
Feature_Six3
Feature_Seven7
Feature_Six0
Feature_Six2
Feature_Six7
Feature_Seven1
Mips_RxMips_Tx
PS6PS7
PS5PS4
Conf_Done
TMS
TCK
10K_TDI Pgm_Data
EPC_TDO
DClk
nConfignStatus
10K_TDI EPC_TDO
PT5PT4PT3PT2PT1PT0
VCC
VCC
VCCVCC
VCC
VCC VCC
VCC
C510
0.1uF
C506
0.1uF
C508
0.1uF
U502
EPC2
317
2327
2
710
13
1516
25
28
31
32
VCCSELVPPSEL
VPPVCC
DCLK
OECS
TDI
CASCINIT_CONF
TMS
TDO
DATA
TCK
C512
0.1uF
C507
0.1uF
JP508
CONN CIR 6-P
1
2
3
4
5
6
U501
EPF10K40
6789
12131415
1718192021242528
2930313334353638
3940414344454648
4950515354555661
6263646566676870
7172737475767879
8081828384868788
9495979899
100101102
105106107
109
113114
110
117118
126
133
136
134
128
137138
103
108
115116
156
166
199
119120
139
111
151
132
154
129
152
157158
127
131
153
141142143144
146147148149
159161162163164
167168169171172173174
175184187191192193194195
196198
200201202203204
206207208214215217218219
220221222223225226227228
229230231233234235237
180181182183185186188190
9092
210212
91211179
111
17758
236238240
59178121
209213
124123239
602342623
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/O
I/O
I/OI/O
I/O
I/OI/O
I/O
I/O
I/O
I/O
I/O
I/OI/O
I/O
I/O
I/OI/O
I/O
I/O
I/O
I/OI/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OI/O
I/O
I/O
I/O
I/OI/OI/OI/O
I/OI/OI/OI/O
I/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/O
I/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/O
DATA0DATA1DATA2DATA3DATA4DATA5DATA6DATA7
INPUTINPUTINPUTINPUT
CLKCLKDCLKTCKCLKUSR
TDITMSNRSNWSNCSNTRSTNCENCONFIG
DEV_CLRNDEV_OE
MSEL0MSEL1CS
NSTATUSCONF_DONE
NCEOTDO
INIT_DONERDYNBUSY
JP501
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
JP502
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
JP507
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
C504
0.1uF
D500
1N4148
D501
1N4148
R599
33
JP503
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
D502
1N4148
C503
0.1uF
JP504
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
C500
0.1uF
JP500
HEADER 4X2
1 23 45 67 8
C509
0.1uF
JP505
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
C505
0.1uF
R5031K
JP509
CONN CIR 6-P
1
2
3
4
5
6
R502
10K
C513
0.1uF
JP506
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
R501
10K
R500
10K
C502
0.1uF
C511
0.1uF
R5041K
C501
0.1uF
J211
CON15
123456789101112131415
R5051K
R5061K
Mips_Data[15..0]
Mips_Ctrl[15..0]
PAD[7..0]
PT[7..0]
Mips_Addr[15..0]
PS[7..4]
TMS
10K_TDO
TCK
Mips_Input3Mips_Input4
Ext_OscMips_Clk
Mips_TxMips_Rx
10K_TDI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
D
Purdue Digital Labs - Ram
A
1 1Sunday, February 11, 2001
Kurt Otte Kurt Otte
Title
Size Rev
Date: Sheet of
Designed By Drawn By:
Ram_nWE_Low
Data12
Data6
Ram_nCS
Address14
Address4
Address12
Address9
Data3
Address7
Address11
Data8Data9Data10
Address10
Data14
Address8
Data2Address3
Address15
Address6
Address2
Data5
Address14
Address8
Ram_nWE_High
Address15
Address9
Address1
Address10
Data1
Address13
Address3
Data13
Data7
Address16
Address2
Data15
Address5
Address13
Data11
Address1
Address11
Address7
Data0
Address6
Address12
Address0
Address4
Address0
Address16
Data4Address5
Ram_nCS
Ram_nWE_LowRam_nWE_High
Ram_nOEAlt_nCS1Alt_nCS2
Address2
Address11
Address15
Address4
Address6
Address10
Address0
Address14
Address7Address8
Address1
Address3
Address13
Address5
Address9
Address12 Data12
Data7
Data0
Data8
Data15
Data6
Data9
Data2
Data13
Data5
Data3
Data10
Data4
Data11
Data14
Data1
Ram_nOE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCVCC
R351 1K
R326 1K
R355 1K
JP300
HEADER 17X2
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 34
R328 1K
R311
1K
R354 1K
R329 1KR348 1K
U301
CY7C109
22
23
24
25
2627
28
29
30
31
131415
12111098765
4
3
2
1718192021
CS1
A10
OE
A11
A9A8
A13
WE
CS2
A15
I/O0I/O1I/O2
A0A1A2A3A4A5A6A7
A12
A14
A16
I/O3I/O4I/O5I/O6I/O7
R330 1K
R312
1K
R331 1K
R341 1K
R345 1K
R332 1K
R349 1K
R333 1K
R320 1K
R334 1KR335 1K
R340 1K
R306
1K
R321 1K
R30110K
R343 1KR322 1K
R347 1KR346 1K
R323 1K
R30010K
JP302
HEADER 6X2
1 23 45 67 89 1011 12
R303
1K
R324 1K
R353 1KR304
1K
U302
CY7C109
22
23
24
25
2627
28
29
30
31
131415
12111098765
4
3
2
1718192021
CS1
A10
OE
A11
A9A8
A13
WE
CS2
A15
I/O0I/O1I/O2
A0A1A2A3A4A5A6A7
A12
A14
A16
I/O3I/O4I/O5I/O6I/O7
R342 1K
R305
1K
R325 1K
R352 1K
R350 1K
R344 1K
R327 1K
Address[16..0]
Data[15..0]
Ram_nCSRam_nWE_HighRam_nWE_Low
Ram_nOEAlt_nCS1Alt_nCS2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
JTAG Po rt
PLD Sel ect
Alt Par t
D
Purdue Digital Labs - Glue Logic
C
1 1Sunday, February 11, 2001
Kurt Otte Kurt Otte
Title
Size Rev
Date: Sheet of
Designed By Drawn By:
GCLRNOE1
16Mhz
7000S_TDI7000S_TDOTMS
TCK
PE4
PA3
PB3
PP2
PB7
PA1
PP1
PB2
PB[7..0]
PE6
PB4
PE[7..0]
PP[7..0]
PA4
PE0
PE3
PP3
PE7
PP0
PB6
PA7
PB5
PE5
PA6
PA2
PP5PP4
PP6PP7
PA5
Address9
Address8
Address5
Address11
Address14Address13
Address2
Address10
Address7
Address3
Address0
Address4
Address12
Address15
Address1
Address6
Ram_nCS
Ram_nWE_HighRam_nWE_Low
Ram_nOE
Alt_CS1Alt_CS2
Mips_Data4
Mips_Data12
Mips_Data14Mips_Data15
Mips_Data3
Mips_Data13
Mips_Data0
Mips_Data8
Mips_Data5
Mips_Data11
Mips_Data2
Mips_Data6
Mips_Data10
Mips_Data7
Mips_Data1
Mips_Data9
Expansion15Expansion14Expansion13Expansion12Expansion11Expansion10Expansion9Expansion8
Expansion7Expansion6Expansion5Expansion4Expansion3Expansion2Expansion1Expansion0
Data9
Data12Data11
Data15
Ext_ClkExt_Osc
Ext_Osc
TDI_Port
TMS_Port
7000S_TDO
7000S_TDI
10K_TDO
TCK
10K_TDI
7000S_TDI10K_TDO
TMS
TDI
TDO
LCD_nWELCD_nCS
PE1PE2
Address16
Data3
Data8
Data12Data13
Data5
Data10
Data15
Data2
Data14
Data9
Data11
Data6
Data0Data1
Data4
Data7
LCD_nWELCD_RS
GCLK2
Mips_Clk
GCLRN
LCD_nCS
OE1
Mips_Input3Mips_Input4
GCLK2GCLRN
GNDVCC
Mips_Addr4
Mips_Addr7
Mips_Addr13
Mips_Addr6
Mips_Addr11
Mips_Addr3
Mips_Addr0
Mips_Addr14
Mips_Addr9
Mips_Addr5
Mips_Addr1
Mips_Addr15
Mips_Addr12
Mips_Addr10
Mips_Addr2
Mips_Addr8
Mips_Ctrl9
Mips_Ctrl4
Mips_Ctrl15
Mips_Ctrl2
Mips_Ctrl10
Mips_Ctrl3
Mips_Ctrl13
Mips_Ctrl11
Mips_Ctrl1
Mips_Ctrl8
Mips_Ctrl0
Mips_Ctrl12
Mips_Ctrl14
Mips_Ctrl5Mips_Ctrl6Mips_Ctrl7
nReset
PB1PB0
PA0
PA[7..0]
LCD_Contrast_FilteredLCD_RS
Data14Data13
Data10
Data8
GCLK2Ext_Clk
LCD_Contrast
LCD_Contrast LCD_Contrast_Filtered
TDOTDI_PortTCK_PortTMS_Port TMS
TCK
TDO_Port
TDOPDLC3PDLC4PDLC5
PDLC2TDITCKTMS
Port_JTAG HC12_JTAG
Port_JTAGHC12_JTAG
TDI
PDLC[6..2]
Expansion15Expansion14Expansion13Expansion12Expansion11Expansion10Expansion9Expansion8Expansion7Expansion6Expansion5Expansion4Expansion3Expansion2Expansion1Expansion0
TCK_PortTDO_Port
TDO
VCC
VCC
VCC
VCC
VCC
VCCVCC
VCC
VCC
C206
0.1uF
R284 33
R2431K
C203
0.1uF
R285 33
C208
0.1uF
R270 33
R2421K
C207
0.1uF
JP204
HEADER 5X2
1 23 45 67 89 10
R271 33
C22310uF
JP409
HEADER 3
123
JH200Ext_Clk
11
C205
0.1uF
C202
0.1uF
R272 33
Y201
25.175Mhz
5OUT
R2501K
C201
0.1uF
74LS244
U5
3579
12141618
17151311
8642
20
191
2Y42Y32Y22Y1
1Y41Y31Y21Y1
2A42A32A22A1
1A41A31A21A1
VCC
2OE1OE
JP400
HEADER 20
1234567891011121314151617181920
R2411K
R2511K
C200
0.1uF
R273 33
R2521K
R223
1K
JP202
HEADER 14
1234567891011121314
R2531K
R274 33
R2541K
R2401K
R275 33
R2551K
J210BNC
1
2
R2561K
C2100.1uF
R276 33
C209
0.1uF
R230
33
R2571K
R2631K
R277 33
JP408
HEADER 3
123
R278 33
U200
EPM7256SRC208
346789
1011
1213151617181920
2122242526272829
3133343536373839
4042434445464748
4955565758596061
6264656667686970
7173767778798081
8486878889909192
939596979899100101
102108109110111112113114
115117118119120121122123
124126128129130131132133
135136137138139140141142
144145146147148149150151
153154159160161162163164
166167168169170171172173
175177178187188190192193
194195196197198199201202
203204205206
182183181184
523416385
107125143165191
127
17630
189
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/O
INPUT/GCLRNINPUT/OE1INPUT/OE2/GCLK2INPUT/GCLK1
VCCIOVCCIOVCCIOVCCIOVCCIOVCCIOVCCIOVCCIOVCCIOVCCIO
I/O(TMS)
I/O(TDI)I/O(TCK)
I/O(TDO)
R2621K
R279 33
R2641K
R2651K
R280 33
R260 1K
C204
0.1uF
R281 33
R2201K
R2211K
R282 33
R261 1K
JP405
HEADER 3
123
JP406
HEADER 3
123
JP407
HEADER 3
123
R2191K
R283 33
7000S_TDO
TCK7000S_TDI
TMS
PP[7..0]
PB[7..0]
PE[7..0]
Address[16..0]
Alt_nCS1
Ram_nCS
Ram_nWE_High
Alt_nCS2
Mips_Addr[15..0]
Mips_Data[15..0]
Mips_Ctrl[15..0]
7000S_TD0
TCK
7000S_TDI
TMS
10K_TDO
10K_TDI
Data[15..0]
Mips_Input3Mips_Clk
Mips_Input4
nReset
Ram_nWE_Low
Ram_nOE
PA[7..0]
16Mhz
Ext_Osc
PDLC[6..2]
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MODBMODA
Debugger BDM I N
Alt Part Alt Part
BDM IN
Main HC12 BDM I NMain HC12 BDM i n
Debugger Selectio n
Alt Part
MODA MODB
Alt Part
D
Purdue Digital Labs - HC12 Debugger
A
1 1Sunday, February 11, 2001
Kurt Otte Kurt Otte
Title
Size Rev
Date: Sheet of
Designed By Drawn By:
DBG_PE6
DBG_nResetDBG_BKGD
HC12_BKGDHC12_nReset
BKGD
nResetHC12_nReset
DBG_PT6
HC12_BKGD
DBG_PT7
DBG_PAD1 DBG_PAD0
DBG_BKGD
Debugger_TxDebugger_Rx
DBG_nReset
DBG_PE5
DBG_PT6
16Mhz
DBG_PT7
DBG_PE6
DBG_PE5
DBG_PAD0DBG_PAD1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
JP604
HEADER 3Mouser #571-41031850
123
R61015K
JP605
HEADER 3Mouser #571-41031850
123
D601
1N4001Mouser# 625-1N4001
1 2
R600
1KC603
0.1uF
R61315K
C602
0.1uF
R60815K
U600
MC68HC912B32
3940414243444546
5152535455565758
6162636465666768
76757473727170
11304877
654321
8079
789
1213141516
1819202122232425
3837363529282726
17323334
495069
5960
10314778
PA0PA1PA2PA3PA4PA5PA6PA7
PAD0PAD1PAD2PAD3PAD4PAD5PAD6PAD7
PS0PS1PS2PS3PS4PS5PS6PS7
PDLC0PDLC1PDLC2PDLC3PDLC4PDLC5PDLC6
VSSVSSX
VSSVSSX
PP0PP1PP2PP3PP4PP5PP6PP7
PT0PT1PT2PT3PT4PT5PT6PT7
PB0PB1PB2PB3PB4PB5PB6PB7
PE0PE1PE2PE3PE4PE5PE6PE7
BKGDnResetEXTALXTAL
VRHVRLVFP
VDDADVSSAD
VDDVDDX
VDDVDDX
R60915K
R60515K
R60715K
JH600
Flash Prog
11
R60315K
SW600
JP602
HEADER 3X2
1 23 45 6
C604
0.1uF
U603MC34164
2 1
3
IN RSET
GN
D
JP603
HEADER 3X2
1 23 45 6
C600
0.1uF C601
0.1uF
R61115K
D600
1N4148
R61215K
BKGD
nReset
Debugger_RxDebugger_Tx
16Mhz