puf phase2
TRANSCRIPT
PUF DESIGN PHASE 2 LAYOUT EXTRACTION AND SIMULATION
BY:
VENKATA KISHORE KAJULURI, ANUSHA GORLA, AKSHITHA PEDDI
ECE 520 VLSI DESIGN
VERSION [0.0]
MAY 1, 2015
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5/1/2015 PUF Design phase 2 1
PUF DESIGN PHASE 2
RING OSCILLATOR PUF:
Circuit Description:
For this PUF 16 Ring oscillators (11 stage) are connected to a 16/1 MUX and the output of the mux is connected to a 16 BIT counter. The counter bits are read out through a parallel in serial out shift register.
The counter counts the frequency of oscillation of the selected ring oscillator (using mux select bits).
Changes since phase1:
In phase 1 we used a 15 but counter and 15 bit PISO shift register, but here we used 16 bit counter and 16 bit shift register.
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5/1/2015 PUF Design phase 2 2
LAYOUT:
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5/1/2015 PUF Design phase 2 3
Simulation Results:
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5/1/2015 PUF Design phase 2 4
Measurement result summary:
Measurement result summary
bit1 = 304.6890n
bit2 = -4.2550u
bit3 = -4.2545u
bit4 = -4.2546u
bit5 = -4.2521u
bit6 = -3.7074u
bit7 = 1.8000
bit8 = -2.9128u
bit9 = -2.9151u
bit10 = -1.9777u
bit11 = 1.8000
bit12 = 1.8000
bit13 = 18.3936u
bit14 = -45.3913m
bit15 = 1.2800
bit16 = 37.2657m
time = 966.6934p
frequency = 1.0345G
SupplyCurrent = -3.4336m
SupplyPower = 5.1504m
risetime = 34.8413p
falltime = -21.3732p
R0rise = 201.9782
R0fall = -123.9026
cinRise = 100.9891p
cinFall = 100.9891p
cIntrinsic = 100.9891p
Output but sequence of the shift register:
0100110001000000 which gives count of 562 for enable time 500n. This gives frequency=1.12GHZ
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5/1/2015 PUF Design phase 2 5
ARBITER PUF:
Circuit Description:
For this PUF 16 Challenge bits are given as input through a Serial in Parallel out shift register to the challenge blocks. An input signal is given to the PUF which will traverse through the challenge blocks and arrive at D flipflop’s clock and D ports. Based on which arrived first, the output of the PUF will vary
Changes since phase1:
No changes
Circuit:
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5/1/2015 PUF Design phase 2 6
LAYOUT:
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5/1/2015 PUF Design phase 2 7
Simulation Results for challenge bit sequence(0101010101010101)
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5/1/2015 PUF Design phase 2 8
Measurement result summary:
risetime = 36.7821p
cIntrinsic = 106.6147p
delay = 5.5326n
SupplyCurrent = -152.0306u
SupplyPower = 228.0459u
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5/1/2015 PUF Design phase 2 9
SRAM PUF:
Circuit Description:
For this PUF one of the 16 SRAM initial states is read through a 16 by 1 multiplexer
Changes since phase1:
SRAM bits is changed from 256 to 16. As 256 bit SRAM PUF needed 16 16By1 multiplexers and is occupying almost half area of the chip
Circuit:
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5/1/2015 PUF Design phase 2 10
LAYOUT:
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5/1/2015 PUF Design phase 2 11
Simulation Results for SRAM PUF (MUX OUTPUT showing data stabilizing at vdd)
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5/1/2015 PUF Design phase 2 12
Measurement result summary:
risetime = 72.1513p
SupplyCurrent = -46.4085u
SupplyPower = 69.6127u
OUTPUT PAD CONNECTOR(INVERTER CHAIN ) :
N=4, CL= 20p Cin =19.5F. Which gives scaling factor as 5.6
TPchain simulated:
TESTING STRATEGY:
RING OSCILLATOR PUF TESTING:
Input Ports: Enable, S0, S1, S2, S3, Shift Register Clock, Shift Register Clear, SHIFT
Output Ports: PISO Shift register output
Strategy:
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5/1/2015 PUF Design phase 2 13
Ring oscillators start to oscillate when enable is set to high. We can measure the frequency of one of the 16 ring oscillators using the select bits. Ouput port gives the counter bits with the 2^16th bit coming out first.
ARBITER PUF TESTING:
Input Ports: SERIAL_IN, SR_CLEAR, SR_CLK, R_CLK, R_CLEAR, ARBITER_INPUT, ARBITER_CLEAR
Output Ports: ARBITER_Q
Strategy:
The challenge bit sequence is passed through the SERIAL_IN once 16 bits are passed, R_CLK is enabled to transfer the serial bit states to parallel output. Based on the input, the Arbiter will output either 0 or 1
SRAM PUF TESTING:
Input Ports: select bits S0,S1,S2,S3
Output Port: Mux OUT
Based on the select bits, the initial state of the 16 bits can be read