prometeo workshop (valencia) november 17-18, 2011 a. boujrad numexo2 mother board design status...
TRANSCRIPT
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2 Mother Board Design StatusExogam Collaboration
Abderrahman BOUJRAD
GANIL France
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
EXOGAM2
Agenda NUMEXO2_P1
Design goals Status
NUMEXO2_P2 Introduction Block diagrams Status
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P1-Design Goals
Early prototype: NUMEXO2 Phase 1
a simple digitizer (14 bits /100MHz) without GTS
The design goals were essentially three fold:
Validation of the critical components, particularly the FADC Ads6244
Validation of the PowerPC architecture for Slow Control and data
readout flow
Testing and validation of the analysis tools developed by the GAP
(Groupe d’Acquisition pour la Physique)
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P1The NIM digitizer prototype (phase1)
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P1 - Status
Better Knowledge on PowerPC Architecture & Embedded Linux Peripherals: SRAM, SDRAM, Flash, SPI, UART, Ethernet
Conversion chain (14b / 100 MHz & 200 MHz) validated 14b / 100 Mhz, NUMEXO2_P1 14b / 200Mhz, ML605 Xilinx Evaluation Kit for NEDA
Vigru (Analysis tools) validated Energy Algorithms (MWD) & trigger concept validated
Knowledge on high speed serial links validated
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2-Introduction
NUMEXO2 Phase 2 (NUMEXO2_P2) : full digitizer & GTS implementation
16 Channels digital conversion system
Mezzanine card concept more flexibility
Up to 16 Triggers,Time Stamping and Clock tree
PCI Express (4x) for NEDA and ADONIS
High counting rate ( 50 to 100 KHz)
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2-Introduction
NUMEXO2 phase 2 started on February 24, 2011
The Architecture is now completely defined
CAD was shared between the different contributors :
GANIL, IPNO, IFJPAN
Firmware developments :
PCIexpress , IP_oscilloscope IPNO / Orsay
ADC_Interface_IP HIL / Warsaw
Gts_leaf_IP IFJPAN / krakow
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2- Bloc Diagram
ADC Logic- FADC samples collection- Digital Processing
- Trigger- Data formatting- Inspection control
PPC
Common Logic
GTS Fanin ADC Logic Interface
Clocks(Local &
Recovered)
Delay Line
OpticalLink
Flash (Linux)
PROM(VHDL)
PROM(VHDL)
Ethernet Gigabit
PCIe(4 Lane)
DACs(Test, control,
inspection)
Seriallink
DDR2
Mux
4 2*FADC14 bits
200MHz
FIFO
--------
RAW DATA(event parameters)
Samples
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2 Virtex5 Block diagram
IFJPAN krakow
IUAC New Delhi
GANIL Caen
IPNOOrsay
HILWarsaw
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2 assignment of Virtex5 banks
PCIe
GTS
IserdesParallel data
GTS
FIFO_PCIe
FIFO_PCIe
FIFO_PCIe GTS
Preliminary
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2 Virtex6 Block diagram
GANIL Caen
IPNOOrsay
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2 assignment of Virtex6 banks
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2-Firmware Status
The architecture is approved
Elements such as the DDR2, the flash, Ethernet, PCI Express 8X (developed
by IPNO), the serial bus (RS232, SPI and IIC) and the serial link for data
recovery for NEDA and ADONIS were implemented in the PPC440 architecture
It remains the implementation of GTS and data readout on V5:
GTS IPs (Global Trigger Systems, Dulny & Czermak / IFJPAN)
Clock recovery IP developed by ET (IUAC)
Data readout IP (Radeck, HIL)
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2 - CAD Status
90 % of CAD is done but need to be verified :
The embedded Linux CAD (DDR2,Flash, ethernet…) associated to the PPC
440 is done GANIL
The CAD for the GTS features GANIL & IFJPAN
The CAD associated to the Virtex6 and its peripherals is done GANIL
CAD of PCI Express and its peripherals IPNO
CAD of power management almost finished GANIL
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
Principal IPs => validated on numexo2_P1 & on the Xilinx ML605 evaluation kit
RTL view from SYNPLIFY PRO synthesis tool
ISERDES Energy Embedded Histogram
NUMEXO2_P2 V6 Firmware
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2 – Energy visualisation
= 1.3 1 LSB = 0.802 mV
Embedded logic analyser
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
EXOGAM clover
CM2DM signal box
ADS62P49@250MHz
ML605
Co60 source spectrumFWHM = 2.7 keV @ 1.3 MeV
CSP outputMWD output
FADC 14 bits @ 250MHz + MWD
NUMEXO2_P2 - Co60 spectrum
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2-Digital TDC
TEST BENCH
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2 - Digital TDC
Resolution obtained with the vernier alone without the DFC
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2- Front and Back sidesFRONTSIDE BACK
SIDE
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
FRONTSIDE
BACKSIDE
NUMEXO2_P2- mother card ImplementationThe implementation of the components on the motherboard is in progress
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
NUMEXO2_P2- mezzanine card positions
Pro
me
teo
Wo
rks
ho
p (
Va
len
cia
) N
ov
em
be
r 1
7-1
8,
20
11
A.
Bo
ujr
ad
Thank you for your attention