programmable solutions for consumer handheld
TRANSCRIPT
May 2008 1
Programmable Solutions for
Consumer Handheld
SiliconBlue Technologies iCE65 Architecture
7-MAY-2008 (v1.1)
SiliconBlue ™
SiliconBlue Technologies iCE65 Architecture
Agenda
May 2008 2
iCE65 Architecture
Overview
Programmable Logic Blocks (PLBs)
Programmable Input/Output Blocks (PIOs)
RAM4K Blocks
Interconnect
Powering iCE65 Devices
iCE65 Configuration
Modes and Methods
SPI Serial Flash
NVCM
May 2008 3
iCE
Architecture
4
iCE65 Low Power NV FPGAs
iCE65L02 iCE65L04 iCE65L08 iCE65L16
Logic Cells (LUT4 + FF) 1,792 3,520 7,680 16,896
Programmable I/O (max.) 128 176 222 384
Differential I/O Pairs (max) 16 20 25 54
RAM4K blocks 16 20 32 96
RAM4K bits 64K 80K 128K 384K
Core voltage options 1.2V, 1.0V
Static current (typical, 1.2V) 25 µA 50 µA 100 µA 250 µA
I/O Banks 4 + SPI mini bank
Global Buffers 8
iCEGATE input disables 4
*2010 Volume Quantities
May 2008
iCE65 FPGA Architecture Ultra-low power
Array of Programmable
Logic Blocks (PLB)
Surrounded by four
I/O Banks
4Kbit RAM Blocks
Programmable
interconnect
Non-Volatile
Configuration
Memory (NVCM)
SPI interface May 2008 5
I/O Bank 0
I/O Bank 2
I/O
Ba
nk
1
I/O
Ba
nk
3
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLBP
rogra
mm
able
Inte
rconnect
Pro
gra
mm
able
Inte
rconnect
Programmable Interconnect
25+ µA Typical Standby Current
NVCM
PLB
PLB
PLB
4K
bit
RA
M4
Kb
it R
AM
PLB
PLB
PLB
PLB
Nonvolatile Configuration Memory (NVCM)P
LB
PLB
PLB
PLB
JT
AG
SPI Config
Four-input Look-Up Table
(LUT4)
Carry logic
Flip-flop with enable and reset controls
Programmable Logic Block (PLB)
8 L
og
ic C
ell
s =
Pro
gra
mm
ab
le L
og
ic B
lock
PLB
PLB
PLB
PLB
Programmable Interconnect
PLB
PLB
Power Consumption
Total Power = Static + Dynamic
Static power is almost entirely controlled by IC
design
Dominated by leakage current
Controlled by IC design techniques, transistor
choices, device-level architecture
Choose the right device: SiliconBlue iCE65 FPGAs!
Only User controls are voltage and temperature
Lower core voltage helps
User has many levers to control dynamic power
May 2008 6
Dynamic Power
Dynamic Power = AfCV2 A = Activity: If it moves, it burns dynamic
power. Corollary: If it moves, kill it.
f = Frequency: The slower it moves, the less
power it uses.
C = Capacitance: High fanout routes have
more capacitance.
V2 = Voltage: Power scales with the square of
the voltage. Operate at lowest possible
voltage.
May 2008 7
PLB
Programmable Logic Block
May 2008 8
Programmable Logic Block Programmable Logic
Block (PLB)
Eight 4-input Look-up
Tables (LUT4)
Eight ‘D’ flip-flops with
shared clock, clock
enable, set/reset control
Fast carry logic
Familiar, well supported
by logic synthesis tools
May 2008 9
= Statically defined by configuration program
LUT4
Carry Logic
Logic Cell
SR
END Q
DFF
Flip-flop with optional enable and set or reset controls
Four-input Look-Up Table(LUT4)
Clock
Enable
Set/Reset
Shared Block-Level Controls
0
Programmable Logic Block (PLB)
8 L
ogic
Cells
(LCs)
I0
I1
I2
I3
O
1
What is a LUT4?
May 2008 10
4-input Look-Up Table
A 16x1 PROM
Locations loaded during
configuration with desired logic
value
Popular method to create
logic in SRAM-based FPGAs
Altera, Lattice, Xilinx
Widely supported
Four inputs select 1 of 16
memory locations
Any possible function of
between 0 to 4 inputs
Alternate View: Karnaugh Map Karnaugh maps
commonly taught in
digital design courses
LUT4 is essentially a
four-input Karnaugh map
Programmed by
configuration bitstream
Any possible function of
between 0 to 4 inputs
May 2008 11
0 0 0 0
0 0 0 0
0 0 1 0
0 0 0 0
00 01 11 10
00
01
11
10
I3, I2
I1, I0
0 = I3 ● I2 ● I1 ● I0
Flip-flop Options Select LUT4 or flip-flop as
Logic Cell output
Clock is shared
Rising-edge triggered, or
Falling-edge triggered
Enable is shared
Always enabled, or
Selectively enabled
Set/Reset is shared
None
Set or Reset (per Logic Cell)
Synchronous or Asynchronous
(per Logic Cell)
Flip-flops reset to ‘0’ after
power-on, CRESET_B
May 2008 12
LUT4
Carry Logic
Logic Cell
SR
END Q
DFF
Flip-flop with optional enable and set or reset controls
Four-input Look-Up Table(LUT4)
Clock
Enable
Set/Reset
Shared Block-Level Controls
0
I0
I1
I2
I3
O
1
Flip-flop Packing in PLB
Due to shared controls, only flip-flops sharing
common controls pack into a single PLB
Eight possible groupings
May 2008 13
Group
Active Clock
Edge Clock Enable
Set or Reset
(Sync. Or Async.)
1
None (always enabled)
None 2
3
4
5
Selective (controlled by
enable input)
None 6
7
8
Carry Logic (Adder Ladder) Each Logic Cell includes special
logic to build arithmetic functions
~ 10X faster than LUT alone
Carry logic + LUT required to build
useful functions
Carry in, initialization input to each
PLB
May need a Logic Cell to initialize
chain in some cases
May need a Logic Cell to exit the chain
Carry logic cascade through the
Logic Cells in a PLB, up a column
Carry Logic driven High when not
used (low power)
I1, I2, I3 inputs shared/borrowed
May 2008 14
LUT4
I0
I1
I2
I3
CarryLogic
To upper adjacent Logic Cell
From lower adjacent Logic Cell
Carry Logic initialization into Programmable Logic Block (PLB)
Adjacent PLB
Adjacent PLB
configuration program= Statically defined by
10
Shared
Either
Carry Logic Example Two-bit Adder with Carry
In and Carry Out
Each logic cell produces a
1-bit Sum using a LUT4
Carry using the Carry Logic
The carry propagates up
the chain to the next bit
Final carry output tapped
out of a LUT
Carry In
Initialized within PLB, or
Created using a LUT4 to
start
May 2008 15
I0
I1
I2
I3
LUT4
CARRY_OUT
CARRY_IN
GND
GND
I0
I1
I2
I3
LUT4
A[0]
B[0]
SUM[0]
CarryLogic
I0
I1
I2
I3
LUT4
A[1]
B[1]
SUM[1]
CarryLogic
Other Arithmetic Functions Carry Logic (Adder
Ladder) only generates
carry for add operations
Adder
Accumulator
Incrementer
Binary Up Counter
What about other
functions?
Subtracter
Decrementer
Down Counter
Using 2s complement
arithmetic, invert carry
May 2008 16
PIO
Programmable Input/Output
May 2008 17
Programmable I/O
Four independent I/O banks
Independent voltage inputs
Multi-standard support May 2008 18
VC
CIO
_1
I/O Bank 0
I/O Bank 2
I/O
Ba
nk
1
I/O
Ba
nk
3
PIO OUT
OE_B
VCCIOI/O Bank 0, 1, or 2
Voltage Supply3.3V, 2.5V, 1.8V, 1.5V, or 1.2V
= Statically defined by configuration program
‘1’‘0’
0 = Output Enabled1 = Hi-Z
PAD
LEI/O Bank
Input Enable
DisabledEnabled
Latch inhibits switching for lowest power
IN
VCCIO_0
VCCIO_2
VC
CIO
_3
VCC
2.5
V, 1.8
V
Internal Core
SPI_VCC
DD
R/D
iffe
rential I/
O
General-Purpose I/O
General-Purpose I/O
Genera
l-Purp
ose
I/O
General-Purpose Input/Output
SPI Config
Input, Output,
or
Bi-directional
Flip-flops on
all paths
DDR option
Low-power latch
option
JTAG boundary
scan
Four+ I/O Banks
I/O Bank 5V tolerant 3.3V 2.5V 1.8V 1.5V
0 (top) Yes Yes Yes Yes —
1 (right) Yes Yes Yes Yes —
2 (bottom) Yes Yes Yes Yes —
3 (left) — — Yes Yes Yes
SPI Yes Yes Yes Yes —
May 2008 19
Support up to four different I/O
voltages
Ideal for voltage level translation
Almost pay for voltage translation get a
free FPGA
Supported on iCEman65 board
iCE65 I/O Bank Voltage Support
VC
CIO
_1
I/O Bank 0
I/O Bank 2
I/O
Ba
nk
1
I/O
Ba
nk
3
VCCIO_0
VCCIO_2V
CC
IO_
3SPI_VCC
DD
R/D
iffe
rential I/
O
General-Purpose I/O
General-Purpose I/O
Genera
l-Purp
ose
I/O
SPI Config
Application
Processor (I/O Limited)
Device B
Device A
iCE65
Bank 0
Bank 2
SPI
I2C
Device C (Data Format)
(Timing)
May 2008
Voltage Level Translation
GPIO Pin Expansion
Bridging
Incompatible
Devices
iCE65 Advantages
More resources
4 I/O banks
Differential I/O
Internal memory
Serial Parallel
20
Voltage Level Translation
Ban
k 1
Ban
k 3
VCCIO_1=? VCCIO_0=?
VCCIO_3=?
VCCIO_2=?
Specialty Standards in Bank 3
Application I/O Standard
VCCIO_3 Supply
Voltage
Drive Current
(mA)
DDR1 SDRAM SSTL2_II 2.5V ± 16.2
SSTL2_I 2.5V ± 8.1
DDR2 SDRAM SSTL18_II 1.8V ± 16.2
SSTL18_I 1.8V ± 8.1
Mobile DDR MDDR 1.8V
Differential LVDS 2.5V
May 2008 21
All specialty voltage standard support is in
I/O Bank 3
Programmable I/O Pair
I/O pair shares
control signals
Input clock
Output clock
Enable
Input and output flip-
flops are optionally
Double Data Rate
(DDR) (described later)
May 2008 22
PIO Pair
1
= Statically defined by configuration program
OUTCLK
INCLK
IOENA
Outp
ut
Clo
ckI/O
Regis
ter
Enable
0 = Output Enabled1 = Hi-Z
PAD
IN
OUT
OE_BEN
EN
EN
0 = Output Enabled1 = Hi-Z
PAD
IN
OUT
OE_BEN
EN
EN
Input
Clo
ck
Double Data Rate (DDR)
Basic Idea: Communicate twice as much data
over a pin by using both edges of the clock
Keeps internal frequency more manageable
Saves power because clock transitions at half
the frequency
Commonly used in DDR, DDR2 memories and
with LVDS differential signaling
May 2008 23
Dynamic Power = Activity ● Frequency ● Capacitance ● (Voltage)2
iCE65 DDR Flip-Flops in PIO Every PIO has two sets of DDR flip-flops
Input pair
Output
Cannot be used when using JTAG boundary scan
May 2008 24
Output DDR Pair Input DDR Pair
LVDS Differential I/O
Basic Idea: Send data over a few high-speed,
carefully controlled traces than over many,
lower-speed traces
Low-voltage Differential Signaling (LVDS)
Low-power, high-speed I/O standard
Excellent noise immunity
Reduced EMI noise
Popular for some applications
Higher-resolution graphic displays
Telecommunications
High-speed cameras May 2008 25
iCE65 LVDS
Supported in I/O Bank 3, VCCIO_3 = 2.5V
Receiver requires external 100Ω resistor
May 2008 26
iCEGATE Input Latch
Configuration image determines
whether an input freezes with
iCEGATE or not
Pin-by-pin control
Really only applicable to asynchronous input signals
Clocked inputs are already frozen until the next clock edge
May 2008 27
Save power: Selectively
freeze input signals
One HOLD control per
I/O Bank
Internal routing connection
Connect to a PIO, logic, or
other HOLD signals
PAD HOLD Input
PAD 0 PAD
X 1 Last value of PAD
Pin Naming
May 2008 28
1
A
B
C
PIO0_12
PIO3_14/
DP07A
PIO3_15/
DP07B
PIO0_12
I/O bank number
Ball column number
Ball row number
Ball number A1
DifferentialI/O Pair
Indicators
PIO0_14/
DP07A
Single-ended PIO Numbering
Differential I/O Pair Numbering
PIO number in bank
Pair pin polarity
Pair number
Differential Pair
Dot indicates unconnected pin for iCE65L04 in CB284 package
Diamond indicates unconnected pin for iCE65L02 in CB200
package1 2
PIO0_13PIO0_12
PIO3_14/
DP07A
W
Y
VCCIO_3
GND
GND
VCCIO_3
GND
GND
PIO3_15/
DP07B
PIO3_16/
DP08A
PIO3_17/
DP08B
PIO3_18/
DP09A
PIO3_19/
DP09B
PIO3_20/
DP10A
PIO3_21/
DP10B
VREF
PIO3_24/
DP12A
PIO3_25/
DP12B
PIO3_26/
DP13A
PIO3_27/
DP13B
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PIO0_14 PIO0_15 PIO0_16 PIO0_17 PIO0_18 VCCIO_0 PIO0_29 PIO0_30 PIO0_31 PIO0_32 PIO0_33 PIO0_42PIO0_28 PIO0_43 PIO0_44 PIO0_45 PIO0_46 PIO0_47
21 22
AA
AB
PIO1_43
PIO2_46 PIO2_47
21 22
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
W
Y
U
V
VCCIO_0 PIO1_11
VCCIO_1
PIO1_12
PIO1_13
PIO1_14
PIO1_15
PIO1_16
PIO1_17
PIO1_18
PIO1_25
PIO1_26
PIO1_27
PIO1_28
PIO1_29
PIO1_30
PIO1_31
PIO1_39
PIO1_40
PIO1_41
PIO1_42
I/O
Ba
nk
1
AA
AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GND
PIO3_28/
DP14A
PIO3_29/
DP14BPIO2_25 PIO2_26 PIO2_27 PIO2_28 PIO2_29 PIO2_30 PIO2_31 PIO2_32 PIO2_33 PIO2_34 PIO2_45PIO2_00 PIO2_13 PIO2_14 PIO2_15 PIO2_16 PIO2_17 PIO2_18
I/O Bank 2
VCC
VCC
GNDPIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 PIO0_25 PIO0_26 PIO0_35 PIO0_36 PIO0_37 PIO0_38 PIO0_39 PIO0_40 PIO0_41
GND
VCCIO_3
VCCIO_3
GND
VCC VCCIO_2 GND GND
GND
VCC
VCCIO_1
PIO3_10/
DP05A
PIO3_11/
DP05B
PIO3_12/
DP06A
PIO3_13/
DP06B
PIO3_22/
DP11A
PIO3_31/
DP15B
PIO3_32/
DP16A
PIO3_33/
DP16B
PIO3_34/
DP17A
PIO3_35/
DP17B
PIO3_36/
DP18A
PIO3_37/
DP18B
PIO1_19
PIO1_20
PIO1_21
PIO1_22
PIO1_23
PIO1_24
PIO1_32
PIO1_35
PIO1_36
PIO1_37
PIO1_38
PIO1_44
PIO1_45
PIO1_46
PIO2_38 PIO2_39 PIO2_40 PIO2_41PIO2_35 PIO2_36 PIO2_37PIO2_21 PIO2_22PIO2_11 PIO2_12 PIO2_19 PIO2_20
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VCCIO_0 GNDVPP_
FAST
VPP_
33PIO0_00 PIO0_01 PIO0_02 PIO0_00 PIO0_05
GBIN0/
PIO0_27
GBIN1/
PIO0_34PIO0_54 PIO0_57 PIO0_59
PIO0_03 PIO0_06
PIO0_04
PIO0_09
PIO0_07
PIO0_11
PIO0_10
PIO0_49
PIO0_48
PIO0_51
PIO0_50
PIO0_53
PIO0_52
PIO0_56
PIO0_55
PIO0_58
VCCIO_0 GND VCC VCCIO_1
GND GND GND
GND GND GND
GND
VCC
VCC
VCC
VCCIO_3 VCCIO_2
GND
VCCIO_3
VCC
VCCIO_3
GND
VCCIO_2
GND SPI_VCC
GND
VCCIO_1
TCK
TDI
TDO
TMS
TRST_B
CRESET_B
CDONE
PIO3_00/
DP00A
PIO3_01/
DP00B
PIO3_06/
DP03A
PIO3_07/
DP03B
PIO3_02/
DP01A
PIO3_03/
DP01B
PIO3_04/
DP02A
PIO3_05/
DP02B
PIO3_08/
DP04A
PIO3_09/
DP04B
PIO3_39/
DP19B
PIO3_38/
DP19A
PIO3_41/
DP20B
PIO3_40/
DP20A
GBIN6/
PIO3_23/
DP11B
GBIN7/
PIO3_30/
DP15A
PIO3_42/
DP21A
PIO3_43/
DP21B
PIO3_45/
DP22B
PIO3_44/
DP22A
PIO3_46/
DP23A
PIO3_47/
DP23B
PIO3_48/
DP24A
PIO3_49/
DP24B
PIO1_00
PIO1_01
PIO1_04
PIO1_07
PIO1_02
PIO1_05
PIO1_08
PIO1_03
PIO1_06
PIO1_10PIO1_09
GBIN3/
PIO1_20
GBIN2/
PIO1_33
PIO1_48/
PSDI2
PIO1_47/
PSDI1
PIO1_50/
PSDI4
PIO1_49/
PSDI3
PIO1_52/
PSDI6
PIO1_53/
PSDI7
PIO1_51/
PSDI5
PIO1_54/
PSDO1
PIOS_55/
SPI_SO
PIOS_56/
SPI_SI
PIOS_57/
SPI_SCK
PIOS_58/
SPI_SS_B
PIO2_51/
CBSEL0
PIO2_50/
PSDO7
PIO2_49/
PSDO6
PIO2_48/
PSDO5
PIO2_44/
PSDO4
PIO2_43/
PSDO3
PIO2_08
PIO2_10
PIO2_06PIO2_03
PIO2_05PIO2_02
PIO2_01 PIO2_04 PIO2_07 PIO2_09GBIN4/
PIO2_23
GBIN5/
PIO2_24
PIO2_42
PSDO2
PIO2_52/
CBSEL1
SPI Bank
I/O Bank 0
I/O
Ba
nk
3
CB284
CB132
CB132/284 Common Footprint
May 2008 29
1 2
PIO0_13PIO0_12
PIO3_14/
DP07A
W
Y
VCCIO_3
GND
GND
VCCIO_3
GND
GND
PIO3_15/
DP07B
PIO3_16/
DP08A
PIO3_17/
DP08B
PIO3_18/
DP09A
PIO3_19/
DP09B
PIO3_20/
DP10A
PIO3_21/
DP10B
VREF
PIO3_24/
DP12A
PIO3_25/
DP12B
PIO3_26/
DP13A
PIO3_27/
DP13B
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PIO0_14 PIO0_15 PIO0_16 PIO0_17 PIO0_18 VCCIO_0 PIO0_29 PIO0_30 PIO0_31 PIO0_32 PIO0_33 PIO0_42PIO0_28 PIO0_43 PIO0_44 PIO0_45 PIO0_46 PIO0_47
21 22
AA
AB
PIO1_43
PIO2_46 PIO2_47
21 22
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
W
Y
U
V
VCCIO_0 PIO1_11
VCCIO_1
PIO1_12
PIO1_13
PIO1_14
PIO1_15
PIO1_16
PIO1_17
PIO1_18
PIO1_25
PIO1_26
PIO1_27
PIO1_28
PIO1_29
PIO1_30
PIO1_31
PIO1_39
PIO1_40
PIO1_41
PIO1_42
I/O
Ba
nk
1
AA
AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GND
PIO3_28/
DP14A
PIO3_29/
DP14BPIO2_25 PIO2_26 PIO2_27 PIO2_28 PIO2_29 PIO2_30 PIO2_31 PIO2_32 PIO2_33 PIO2_34 PIO2_45PIO2_00 PIO2_13 PIO2_14 PIO2_15 PIO2_16 PIO2_17 PIO2_18
I/O Bank 2
VCC
VCC
GNDPIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 PIO0_25 PIO0_26 PIO0_35 PIO0_36 PIO0_37 PIO0_38 PIO0_39 PIO0_40 PIO0_41
GND
VCCIO_3
VCCIO_3
GND
VCC VCCIO_2 GND GND
GND
VCC
VCCIO_1
PIO3_10/
DP05A
PIO3_11/
DP05B
PIO3_12/
DP06A
PIO3_13/
DP06B
PIO3_22/
DP11A
PIO3_31/
DP15B
PIO3_32/
DP16A
PIO3_33/
DP16B
PIO3_34/
DP17A
PIO3_35/
DP17B
PIO3_36/
DP18A
PIO3_37/
DP18B
PIO1_19
PIO1_20
PIO1_21
PIO1_22
PIO1_23
PIO1_24
PIO1_32
PIO1_35
PIO1_36
PIO1_37
PIO1_38
PIO1_44
PIO1_45
PIO1_46
PIO2_38 PIO2_39 PIO2_40 PIO2_41PIO2_35 PIO2_36 PIO2_37PIO2_21 PIO2_22PIO2_11 PIO2_12 PIO2_19 PIO2_20
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VCCIO_0 GNDVPP_
FAST
VPP_
33PIO0_00 PIO0_01 PIO0_02 PIO0_00 PIO0_05
GBIN0/
PIO0_27
GBIN1/
PIO0_34PIO0_54 PIO0_57 PIO0_59
PIO0_03 PIO0_06
PIO0_04
PIO0_09
PIO0_07
PIO0_11
PIO0_10
PIO0_49
PIO0_48
PIO0_51
PIO0_50
PIO0_53
PIO0_52
PIO0_56
PIO0_55
PIO0_58
VCCIO_0 GND VCC VCCIO_1
GND GND GND
GND GND GND
GND
VCC
VCC
VCC
VCCIO_3 VCCIO_2
GND
VCCIO_3
VCC
VCCIO_3
GND
VCCIO_2
GND SPI_VCC
GND
VCCIO_1
TCK
TDI
TDO
TMS
TRST_B
CRESET_B
CDONE
PIO3_00/
DP00A
PIO3_01/
DP00B
PIO3_06/
DP03A
PIO3_07/
DP03B
PIO3_02/
DP01A
PIO3_03/
DP01B
PIO3_04/
DP02A
PIO3_05/
DP02B
PIO3_08/
DP04A
PIO3_09/
DP04B
PIO3_39/
DP19B
PIO3_38/
DP19A
PIO3_41/
DP20B
PIO3_40/
DP20A
GBIN6/
PIO3_23/
DP11B
GBIN7/
PIO3_30/
DP15A
PIO3_42/
DP21A
PIO3_43/
DP21B
PIO3_45/
DP22B
PIO3_44/
DP22A
PIO3_46/
DP23A
PIO3_47/
DP23B
PIO3_48/
DP24A
PIO3_49/
DP24B
PIO1_00
PIO1_01
PIO1_04
PIO1_07
PIO1_02
PIO1_05
PIO1_08
PIO1_03
PIO1_06
PIO1_10PIO1_09
GBIN3/
PIO1_20
GBIN2/
PIO1_33
PIO1_48/
PSDI2
PIO1_47/
PSDI1
PIO1_50/
PSDI4
PIO1_49/
PSDI3
PIO1_52/
PSDI6
PIO1_53/
PSDI7
PIO1_51/
PSDI5
PIO1_54/
PSDO1
PIOS_55/
SPI_SO
PIOS_56/
SPI_SI
PIOS_57/
SPI_SCK
PIOS_58/
SPI_SS_B
PIO2_51/
CBSEL0
PIO2_50/
PSDO7
PIO2_49/
PSDO6
PIO2_48/
PSDO5
PIO2_44/
PSDO4
PIO2_43/
PSDO3
PIO2_08
PIO2_10
PIO2_06PIO2_03
PIO2_05PIO2_02
PIO2_01 PIO2_04 PIO2_07 PIO2_09GBIN4/
PIO2_23
GBIN5/
PIO2_24
PIO2_42
PSDO2
PIO2_52/
CBSEL1
SPI Bank
I/O Bank 0
I/O
Ba
nk
3
CB284
CB132
RAM4K
4Kbit Block RAM Memory
May 2008 30
On-Chip RAM Blocks RAM4K memory blocks
256 by 16-bit
Other formats available
using programmable logic
Separate read / write ports
Optionally pre-initialized
during configuration
May 2008 31
WDATA[15:0]
MASK[15:0]
WADDR[7:0]
WE
WCLK
RDATA[15:0]
RADDR[7:0]
RE
RCLK
RAM4KRAM Block(256x16)
Write Port Read Port
Device RAM4K Blocks
Default
Configuration
RAM bits per
Block Total RAM Bits
iCE65L02 16
256 locations x
16 bits/location 4K (4,096)
64K
iCE65L04 20 80K
iCE65L08 32 128K
iCE65L16 96 384K
RAM4K Applications Data buffering
First-in, First-Out (FIFO)
Last-in, First-Out (LIFO,
stack)
Circular buffers
Line buffers
Register files
Waveform generator
256 x 16 ROM
Function generator
“Super, synchronous
PLB”
8-inputs, 16 outputs
Pattern matcher,
correlator
Counter
Shift register
May 2008 32
RAM Competitive Advantage
SiliconBlue Actel Altera Xilinx Lattice
Family iCE65 Igloo MAX IIZ CoolRunner-II MachXO
Block RAM Yes In some parts None None None
Block RAM Size 4Kx1 4Kx1 + parity — — —
Number of RAM
blocks 16 to 96
0: AGL015, 030
4 to 32 in larger
devices
0 0 0
Block RAM bits
64K to 384K
0: AGL015,030
18K to 144K in
larger devices
0 0 0
May 2008 33
Write Operations
MASK input masks off specific bits, prevents
write to the specific bits in the RAM location
All write operates are synchronized to clock
input
Write Clock is invertible (rising edge operation shown)
May 2008 34
Operation
WDATA MASK WADDR WE WCLK
RAM Location Data Bit Mask Address Enable Clock
Disabled X X X X 0 No change
Disabled X X X 0 X No change
Write Data WDATA[i] MASK[i]=0 WADDR 1
RAM[WADDR][i] =
WDATA[i]
Masked
Write X MASK[i]=1 WADDR 1
RAM[WADDR][i] =
No Change
Read Operations
RAM contents optionally loaded during configuration
RDATA output register not cleared by configuration
reset
Valid read operation makes RDATA valid
Write Clock is invertible (rising edge operation shown)
May 2008 35
Operation
RADDR RE RCLK
RDATA Address Enable Clock
Immediately
after
configuration,
before first
Read operation
X X X
Undefined. Output
register not cleared by
configuration reset.
Disabled X 0 X No change
Read Data RADDR 1 RAM[RADDR]
PROGRAMMABLE
INTERCONNECT
May 2008 36
Programmable Interconnect
Specially designed
for ultra-low power
Connections to
Nearest Neighbors
Connections that
span four blocks
Connections that
span 12 blocks
Global connections
May 2008 37
I/O Bank 0
I/O Bank 2
I/O
Ba
nk
1
I/O
Ba
nk
3
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLBP
rogra
mm
able
Inte
rconnect
Pro
gra
mm
able
Inte
rconnect
Programmable Interconnect
25+ µA Typical Standby Current
NVCM
PLB
PLB
PLB
4K
bit
RA
M4
Kb
it R
AM
PLB
PLB
PLB
PLB
Nonvolatile Configuration Memory (NVCM)P
LB
PLB
PLB
PLB
JT
AG
SPI Config
Four-input Look-Up Table
(LUT4)
Carry logic
Flip-flop with enable and reset controls
Programmable Logic Block (PLB)
8 L
og
ic C
ell
s =
Pro
gra
mm
ab
le L
og
ic B
lock
PLB
PLB
PLB
PLB
Programmable Interconnect
PLB
PLB
Nearest Neighbor Connections Each PLB has
connections to:
Itself
Eight nearest neighbors
Fastest connections
May 2008 38
PLB = Programmable Logic Block
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
8 wires
PLB
Span4 Connections
May 2008 39
PLB = Programmable Logic Block
12
48 Span4 Lines per Column
48
Sp
an
4 L
ine
s
pe
r R
ow
Span4 line spans across four PLBsSwithbox: Span4 lines are switched every four intersections
Each PLB receives inputs from and sends outputs to Span4 Horizontal lines and from the left and right Span4 Vertical lines.
12
12
12
12121212
PLB PLB
PLB PLB PLB
RAM4K
PLB
Span12 Connections
May 2008 40
24 Span12 Lines per Column
24
Sp
an
12
Lin
es p
er
Ro
w
PLB = Programmable Logic Block
Swithbox: Span12 lines are switched every 12 intersections
Span12 line spans across twelve PLBs
4444
4
4
4
4
4
4
44
RAM4K
PLB
PLB PLB
PLB
Each PLB receives inputs from and sends outputs to Span12 Horizontal lines and from the left Span12 Vertical lines. The PLB sends outputs to the right-side Span12 Vertical lines but does not receive inputs from there.
iCE65 Global Resources Eight high-drive, low-skew
buffers
Potentially connect to all PLB,
RAM4K, and PIO blocks
Clock drivers
High-fanout signals
Global set/reset
Automatic at power-up
Resets all flip-flops to a known
state
May 2008 41
I/O Bank 0G
BIN
1
GB
IN0
Glo
bal
Buffe
r
Glo
bal
Buffe
r
I/O
Ba
nk
3
GBIN7
GBIN6
Global Buffer
Global Buffer
I/O Bank 2
GB
IN4
GB
IN5
Glo
bal
Buff
er
Glo
bal
Buff
er
I/O
Ba
nk
1
GBIN2
GBIN3
Global Buffer
Global BufferGBUF2
GBUF3
GBUF7
GBUF6
GB
UF1
GB
UF0
GB
UF5
GB
UF5
Global Buffer Inputs (GBIN) Global buffers (GBUFs)
have two potential input
sources
Special Global Buffer
Input (GBIN) associated
with a GBUF
From programmable
interconnect
Special GBIN pins also
available for general-
purpose I/O
May 2008 42
GBIN
Global BufferGBUF
Programmable interconnect
Global buffer input (GBIN) pin
Can also be a general-purpose PIO pin
Global Buffer to PLB
May 2008 43
Global Buffer LUT4 Inputs PLB Clock PLB Enable PLB Set/Reset
GBUF0 Yes, any 4 of
the 8 global
buffers
N/A
GBUF1 N/A
GBUF2 N/A
GBUF3 N/A
GBUF4 N/A
GBUF5 N/A
GBUF6 N/A
GBUF7 N/A
GBUFs available as LUT4 inputs
GBUFs available to all clock inputs
Even-numbered GBUFs available to Set/Reset
Odd-numbered GBUFs available to Enable
Global Buffer to PIO
May 2008 44
Global Buffer PIO Output Input Clock Output Clock Clock Enable
GBUF0 Not available
(connect
through Logic
Cell first)
GBUF1 N/A
GBUF2
GBUF3 N/A
GBUF4
GBUF5 N/A
GBUF6
GBUF7 N/A
GBUFs cannot directly connect to PIO output
Must connect through Logic Cell first
GBUFs available to all input and output clocks
Even-numbered GBUFs available to Clock Enable
CONFIGURATION
SPI and NVCM
May 2008 45
iCE65 Device Configuration
iCE65 FPGAs offer multiple configuration
options to meet your application requirements
Secure, on-chip Non-Volatile Configuration
Memory (NVCM)
Self-loading from an external, commodity SPI
serial Flash PROM
Downloaded from external processor using SPI-
like serial interface
SPI interface has separate voltage supply to
simplify system interface
Internal oscillator and power-on reset
May 2008 46
iCE65 Configuration Models
May 2008 47
iCE65 NVCM
Self-Contained Model (ASIC, Microcontroller)
• Lowest-cost
• Single-chip, secure; loads from internal NVCM memory
• Permanently programmed (with reprogrammable options)
iCE65 SPI
Serial
Flash
Processor Model • Boot at power-up from external SPI serial Flash
• Optionally store additional application data in Flash
• Changeable program
iCE65 Controller
Peripheral Model • Download to iCE65 using a controller/processor
• Simple SPI interface
• iCE65 bitstream stored in any form of memory
• Internal Flash, Disk drive
• Over network, RF link
• Changeable program
Memory
How Many Bits to Program?
Device Kbits Mbits Kbytes
iCE65L02 314 Kb 0.31 Mb 39.3 KB
iCE65L04 533 Kb 0.52 Mb 62.7 KB
iCE65L08 1,057 Kb 1.03 Mb 132.2 KB
iCE65L16 2,404 Kb 2.35 Mb 300.5 KB
May 2008 48
Regardless of design complexity, configuration
image size is the same per device
iCE65 Configuration Image Size
Internal Oscillator Clock source for self-loading modes
NVCM
SPI serial Flash
Mode determines operating frequency, but wide
variance
Maximum frequency determines which PROM is required
Minimum frequency determines how fast configuration
completes
Turned off after configuration to save power
May 2008 49
Mode Minimum Maximum Description
Default 3.3 MHz 10 MHz Works with any SPI PROM
Low 11 MHz 33 MHz Works with most SPI PROMs
High 17 MHz 50 MHz Supported by some high-speed SPI PROMs
How Long to Configure?
Speed depends on internal oscillator setting or
external clock frequency
Maximum configuration time depends on
Configuration image size
Lowest frequency for configuration clock
May 2008 50
Device
Internal Oscillator Download Clock
Default
Low
Frequency
High
Frequency 25 MHz 40 MHz
iCE65L02 98 ms 30 ms 19 ms 13 ms 9 ms
iCE65L04 166 ms 50 ms 33 ms 22 ms 14 ms
iCE65L08 328 ms 99 ms 64 ms 44 ms 28 ms
iCE65L16 746 ms 224 ms 145 ms 99 ms 62 ms
iCE65 Maximum Configuration Time
NVCM Programming NVCM memory is large enough to completely program
device plus initialize on-chip RAM
Low cost; permanently programmed
Completely internal, secure
Programming interface similar to 25-series SPI PROM
External programming support
In-system programming (ISP) also available
2.5V-only with on-chip programming circuitry
Faster programming using separate 6.5V supply
May 2008 51
Pin Voltage Description
VDDP_2V5 2.5V Charge pumped programming voltage supply.
VPP_6V5 6.5V Direct, faster programming voltage supply.
Selecting Mode
Configuration mode
decided by a few
variables
Is NVCM enabled for
configuration?
What is the logic value
on the SPI_SS_B pin?
Low: Peripheral mode
High: SPI Flash PROM
May 2008 52
Configuration Control Built-in Power-On Reset
(POR)
Internal oscillator for
self-loading mode
Three frequency ranges
CRESET_B:
Asynchronous, active-
Low reset
Keep Low to postpone
start of configuration
Configuration starts when
CRESET_B returns High
May 2008 53
SiliconBlue ICE
CDONECRESET_BLow resets ICE configuration.
Rising edge starts configuration process.
I/O Bank 2
Unconfigured
Configured
CDONE: Low during
configuration, High when
configuration complete
Low-current output
SPI Serial PROM Interface Separate I/O bank to
simplify system design
Supports multiple
commodity SPI Flash
vendors
Competitive pricing
Multi-sourcing security
May 2008 54
SiliconBlue iCE65
(SPI bank)Commodity SPI
Serial Flash PROM
SPI_SO
SPI_SI
SPI_VCC
SPI_SS_B
SPI_SCK
+3.3V
Same SPI interface for peripheral mode configuration
Signal
Name
Flash
Mode
Peripheral
Mode
After
Configuration Configuration Function
SPI_SO Output Output User-defined PIO Serial Output
SPI_SI Input Input User-defined PIO Serial Input
SPI_SS_B Output Input User-defined PIO Slave Select, active Low
SPI_SCK Output Input User-defined PIO Slave Clock
Low-Power SPI Configuration
May 2008 55
1 0 1 0 1 0 1 1
0xABRelease from Deep Power-down
SPI_SCK
SPI_SS_B
SPI_SO
X X X X X X X X
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A00 0 0 0 1 0 1 1
0x0BFast Read
24-bit Start Address
D7
D6
D5
D4
D3
D2
D1
D0
D7
Dummy ByteDon’t Care
Data Byte 0
D6
SPI_SCK
SPI_SS_B
SPI_SO
SPI_SIPROM output is Hi-Z. Pulled High in SPI_SI pin via internal pull-up resistor.
1 0 1 1 1 0 0
0xB9Deep Power-down
D7
D6
D5
D4
D3
D2
D1
D0
Last Data Byte
1
Fast Read data
SPI_SCK
SPI_SS_B
SPI_SO
SPI_SI
1
2
Wake up PROM from
low-power mode
Send 0x0B Fast Read Command, 24-bit Start Address,
Read Required Configuration Data
3 Return PROM to low-power
mode (default, optional)
SPI PROM Requirements
iCE65 optional loads from commodity SPI serial
Flash
Multiple vendors with compatible devices
Lowest pricing; supply security
Innovative features and packaging
Requirements
25- or 45-series SPI PROM
Large enough to hold a bitstream (512K to 4M)
Supports the Fast Read command (0x0B)
Fast enough power-up to ready time
May 2008 56
Programming SPI Flash Hold CRESET_B Low
Tri-states all pins
Allows external programmer
access to SPI Flash
Built into iCEman65 board
TotalPhase
Aardvark (lower-speed)
www.totalphase.com/products/aardvark_i2cspi
Cheetah (high-speed)
www.totalphase.com/products/cheetah_spi
Free Flash Center software
www.totalphase.com/products/flash_center
Digilent
JTAG-USB Cable www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-USB&Nav1=Products&Nav2=Cables
Works with Adept/ICEUTIL
May 2008 57
SiliconBlue iCE65
Commodity SPI Serial
Flash PROM
SPI_SO
SPI_SI
SPI_SS_B
SPI_SCKCRESET_B
ProgrammerHold CRESET_B Low to keep iCE65 SPI pins in high impedance state. Programmer then has full access to PROM.
SPI Serial PROM Vendors
Numonyx
Formerly STMicro/Intel
M25P40, M25P80
Atmel
AT45DB081D
Spansion
Formerly AMD/Fujitsu
Winbond
NexFlash
Silicon Storage
Technology (SST)
Chingis
Macronix
Eon Silicon Solution
AMIC Technology
May 2008 58
Tested Not Yet Tested
Cold/Warm Boot
Usually, iCE65 device programmed using a
single configuration image
Optionally select one of up to four iCE65
configuration images
ColdBoot: At power-on or after CRESET_B
returns High, read value on CBSEL[1:0] pins to
select four possible configuration bitstreams
WarmBoot: FPGA application selects one of four
possible bitstreams, controls when to jump to next
bitstream using SB_WARMBOOT primitive
May 2008 59
Cold/Warm Boot Procedure
May 2008 60
Cold/Warm Boot Examples
Single hardware design has multiple functions
Board loads self-test design, then jumps to user
application if test passes
Based on a card slot ID, the iCE65 FPGA is loaded
with required hardware design
Time-share hardware, saves costs
NVCM with Field Upgrade/Expansion Path
Load from NVCM
Optionally jump to SPI configuration image if
available
May 2008 61
JTAG/Boundary Scan Primarily used during PCB
assembly
Open/short test
Especially useful with aggressive
packaging
Optional configuration interface
(though many details are yet to be
determined)
Powered by VCCIO_1
May 2008 62
SiliconBlue iCE65
(I/O Bank 1)
TDI
TRST_B
TRST_B must be Low during normal operation.
TDO
TMS
TCK
Signal
Name Description
TDI Test Data Input
TDO Test Data Output
TMS Test Mode Select
TCK Test Clock
TRST_B Test Reset (active Low)
Powering iCE65 FPGAs
Core Voltage
1.2 V: Standard
1.0 V: Ultra-low power
Up to five different I/O voltages
Four I/O bank voltages
Banks 0, 1, 2 can be 3.3V, 2.5V, 1.8V
Bank 3 can be 2.5V, 1.8V, or 1.5V
SPI “mini-bank” voltage
3.3V when configuring from SPI Flash
2.5V and 1.8V options when configuring from NVCM or
peripheral mode
May 2008 63
Dynamic Power = Activity ● Frequency ● Capacitance ● (Voltage)2