programmable logic architecture verilog hdl fpga...
TRANSCRIPT
Programmable Logic Architecture
Verilog HDL FPGA Design
Jason Tseng
Class-10
Abstract
Previous class: examples discussion
Today’s class:
– Functions
– Tasks
– Functions calling functions
– Tasks calling functions and tasks
Function Declaration
Functions are declared within a module and can be called from
continuous assignment, always blocks or other functions.
Evaluation:
– Continuous assignment: when any of its declared inputs change
– Procedure: when they are invoked.
Syntax:
function [msb:lsb] function_name;
input[ [msb:lsb] input_arguments;
reg[msb:mls] reg_variable_list;
parameter [msb;lsb] parameter_list;
integer [msb:lsb] integer_list;
… statements…
endfunction
Functions’ General Rules
The following are some of the general rules for functions:
– Functions must contains at least one input argument.
– Functions cannot contain an inout or output declaration.
– Functions cannot contain time controlled statement (e.g. #,@,wait)
– Functions cannot enable tasks.
– Functions must contain a statement that assigns the return value to
the implicit function name register.
– If more than one return value is required, the outputs should be
concatenated into one vector before assigning it to the function
name. The calling module program can then extract (unbundle) the
individual outputs from the concatenated form
Function Calls
The return value of a function can be used directly in an expression without first assigning it to a register or wire variable.
Example:
assign a= b &c & chk_bc(c, b); /* chk_bc is a function defined
below. */
/*-----------------------------------------------------------------*/
function chk_bc(c, b); // function definition
input b,c;
chk_bc=b^c;
endfunction
Shift left/right with 3-bit for a decoder/divider
Shift left with 8-bits for a 3-8 decoder Shift right with 2,3,5-bit for 4,8,32 divider
16-bit even parity generator using function
Method 1:
Calling for two 8-bit
even-parity generators
Method 2:
Calling for a 16-bit
even-parity generators
Examples: Ex1: Transmission sent using even parity:
• A transmits: 1001
• A computes parity bit value: 1^0^0^1=0 (i.e. 0 means even number of ‘1’)
• A adds parity bit and sends: 10010 error detecting code
• B receives: 1001
• B computes parity: 1^0^0^1^0=0 (the same as the one computed by A)
• B reports correct transmission after observing expected even result.
Ex2: transmission sent using odd parity:
• A transmits: 1001
• A computes parity bit value: ~(1^0^0^1)=1 (i.e. 1 means even number of ‘1’)
• A adds parity bit and sends: 10011
• B receives: 10011
• B computes parity: 1^0^0^1^1=1
• B reports correct transmission after observing expected odd result.
Ex3: transmission sent using even parity:
• A transmits: 1001
• A computes parity bit and sends: 10010
**** transmission error ***
• B receives: 11010
• B computes parity: 1^1^0^1^0=1 (different from the one computed by A)
• B reports incorrect transmission after observing unexpected odd results
( cannot do the even number of corrupted bits, e.g., 1001011011)
Method 1: boolean algebra (5-12)
Method 2: if block (6-8)
Method 3: conditional operator
Method 4: case block
Method 5: shift left operator
Method 6: function call (7-3)
Y0=[0 I]
Y1=[ I 0]
10
10
1-4 demultiplexer
3-8 decoder1. Boolean algebra (5-9)
2. Shift-left operator
3. Function call
d2 d1 d0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Function call
[0,0][0001]
[0,1][0010]
[1,0][0100]
[1,1][1000]
Shift from right to left
Task
Task is not synthesizable.
The syntax of Task is similar to that of function, but unlike the
function it has both input and output. Thus, tasks do not return
values.
Task’s functions are similar to procedures in most programming
languages.
General rules for task are those specified for functions.
Syntax:
16-bit odd parity generator using task
16-bit comparator based on
4-bit comparator4-bit comparator
A[15:12] > (<) B[15:12]A>(<) B otherwise A==B
A[11:8] > (<) B[11:8]A>(<) B
A[7:4] >(<) B[7:4]A >(<) B
A[3:0] >(<) B[3:0]A >(<) B
16-bit even parity generator using functions call
16-bit comparator based on 4-bit comparator
Verilog system’s
Task and Function
Display: $display, $strobe, $monitor
Get simulation time: $time (64-bit), $stime (32-
bit), $realtime (real number)
Reset the simulation: $rest, $rest_count,
$rest_value, $stop, $finish
Set heirachy scope: $scope, $showscope
Numerical setting: $random, $itor, $bitstoreal,
$realtobits, $rtoi
Write to file: $fopen, $fdisplay, $fstrobe,
$fmonitor, $fwrite, $