programable pld s

7/31/2019 Programable Pld s

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Implementation of LogicCircuits


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Types of ICs

Different types of ASICs are:

Full-custom ASICs

Semi-custom ASICs

Standard-cellbased ASICs (CBIC) Gate-arraybased ASICs

Channeled gate arrays

Channelless gate arrays

Structured gate arrays

Programmable ASICs

Programmable Logic Devices (PLD)

Field Programmable Gate Array (FPGA)


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TYPES OF CHIPS

Three main types of chips

Standard chips

Programmable Logic Devices

Custom Chips


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Standard Chips

Fixed Functionality

7400-series standard chips

SSI (Small Scale Integrated circuit) :less than 10 gates

MSI (Medium Scale Integrated circuits) : about 10 to 100gates

LSI (Large Scale Integrate circuits) : about 100 to 10,000gates

VLSI (Very Large Scale Integrated circuits) : over 10,000to 100,000 gates

ULSI (Ultra Large Scale Integrated Circuits) : over100,000 gates


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Programmable Logic Device

Problems of using standard ICs in logic design:

require hundreds or thousands of these ICs

require a considerable amount of circuit board space

require a great deal of time and cost in inserting, soldering, andtesting

require to keep a significant inventory of ICs


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Programmable Logic Device

What is a Programmable Logic Device (PLD)?

an IC that contains large numbers of gates, flip-flops and registers

that are interconnected on the chip

can be configured by the user to perform a logic function

many of the connections are fusible links that can be broken


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Programmable Logic Device Basic Ideas of PLD

A PLD consists of an array of AND gates and an array of OR gates

Each input feeds both a non-inverting buffer and an inverting buffer to produce thetrue and inverted forms of each variable. (i.e. the input lines to the AND-gate array)

The AND outputs are called the product lines

Each product line is connected to one of the inputs of each OR gate

Three fundamental types of standard PLDs: PROM, PAL, and PLA


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Advantages of using PLDs

Advantages of reducing the no. of ICs using PLD:

less board space

fewer printed circuit boardssmaller enclosureslower power requirements (i.e., smaller power supplies)faster and less costly assembly processes

higher reliability (fewer ICs and circuit connections =>easier troubleshooting)

availability of design software


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Internal Structures of PLDA B

Input lines

AND array

Fuse

Product

lines

ORarray

Sum of product outputs

O O O O

AB

AB

AB

AB

A A B B AB

AB

AB

AB

1 2 3 4

Example of a programmable logic device

2-to-4 decoder

If blown, OR

input is logic 0.


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Internal Structures of PLDA B

Input lines

AND array

Fuse

Product

lines

ORarray

Sum of product outputs

O O O O

AB

AB

AB

AB

A A B B AB

AB

AB

AB

1 2 3 4

Example of a programmable logic device

2-to-4 decoder

If blown, OR

input is logic 0.


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Pre-fabricated building block of many AND/OR gates (or NOR, NAND)

"Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array ofAND gates Productterms

Dense array ofOR gates

Outputs

The two major types of PLD:

field programmable gate arrays (FPGAs)

complex programmable logic devices (CPLDs).


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PROGRAMMABLE LOGIC DEVICES

PLDs give improved performance over random logic and significant

cost saving over Very Large-scale integrated circuits. They consume

less power, take fewer ICs and are more reliable than random logic

designs. The real advantage of PLD designs over random logic is inthe ease of design and the resulting design time saving.

The different types of PLDs available are:

ROM and EPROM.

Programmable Logic Arrays (PLA)

Programmable Array Logic (PAL)

Field Programmable Gate Arrays (FPGA)


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Classifications of PLDs

Depending on which of the AND/OR logic arrays is programmable, we have three

basic organizations


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PROGRAMMABLE LOGIC

DEVICES


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Conventions


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Read-Only Memories

A read only memory (ROM) is essentially a device in

which permanent binary information is stored. The

information must be specified by the designer and is then

embedded into the ROM to form the requiredinterconnection or electronic device pattern. Once the

pattern is established, it stays within the ROM even when

the power is turned off and on again; that is ROM is

nonvolatile.


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Read-Only Memories

Classification:

EPROM:EPROMs allow the modification of the data stored as they

use a special charge storage mechanism to enable or disable the

switching elements in the memory array. The data stored in theEPROM is generally permanent until erased using ultraviolet light.

EEPROM:The electrically erasable PROM (EEPROM) is similar to

EPROM except that the erasure of data is accomplished using

electrical pulses instead of ultraviolet light. An EEPROM can be

erased and reprogrammed only a limited number of times.


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Read-Only Memories

Block diagram


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Logical

Structure

of a PROM

Output of

AND gate = ?

Output of

OR gate = ?O3 O2 O1 O0

programmable connections

A4A5CSA2A3 A0A1

address control signaloutput data

fixed connections

.

.

.

.

.

.

.

.

.


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Read-Only Memories

. ROM Realization of Code Converter


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. Programmable Logic Array Structure


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PLA (Programmable Logic Array)

In PLAs, instead of using a decoder as in PROMs, anumber (k) of AND gates is used where k < 2n, (n is thenumber of inputs).

Each of the AND gates can be programmed to generate a

product term of the input variables and does not generateall the minterms as in the ROM.

The AND and OR gates inside the PLA are initiallyfabricated with the links (fuses) among them.

The specific Boolean functions are implemented in sum ofproducts form by opening appropriate links and leaving thedesired connections.


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PLA

A block diagram of the PLA is shown in the figure. It consists ofn inputs, m outputs, and k product

terms.


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The product terms constitute a group ofk AND gates eachof 2n inputs.

Links are inserted between all n inputs and theircomplement values to each of the AND gates.

Links are also provided between the outputs of the ANDgates and the inputs of the OR gates.

Since PLA has m-outputs, the number of OR gates is m.

The output of each OR gate goes to an XOR gate, wherethe other input has two sets of links, one connected to logic

0 and other to logic 1. It allows the output function to be generated either in thetrue form or in the complement form.

PLA Contd.,


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The output is inverted when the XOR input is connected to1 (since X 1 = X).

The output does not change when the XOR input is

connected to 0 (since X 0 = X).

The size of the PLA is specified by the number of inputs(n), the number of product terms (k), and the number of

outputs (m), (the # of sum terms is equal to the number of

outputs).

PLA Contd.,


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PLA - Example


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PLA- Example


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. PLA with Three Inputs, Five Product Terms, and Four Outputs


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Table. PLA Table

Product

Term

Inputs Outputs

A B C F0 F1 F2 F3

AB

AC

B

BC

AC

0

1

-

-

1

0

-

1

1

-

-

0

-

0

1

1

1

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

1

0

1

ACBF

BCBAF

BACF

ACBAF

3

2

1

0

'''

'

'''


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. PLA Realization of Equations

a b c d f 1 f2 f3

0

1

1

-

-

-

1

1

0

0

-

1

-

-

0

1

1

1

1

1

-

-

-

-

1

1

1

1

0

0

1

0

0

0

1

0

0

1

1

0

0

1

(a) PLA table


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PLA Implementation

F0 = m(0,1,4,6) = AB+AC

F1 = m(2,3,4,6,7) = B+AC

F2 = m(0,1,2,6) =AB+BC

F3 = m(2,3,5,6,7) =AC+B


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PLA implementation

PLA STRUCTURE


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PLA Implementation using minimum rows

F1 = m(2,3,5,7,8,9,10,11,13,15) .(1)

F2 = m(2,3,5,6,7,10,11,14,15) . (2)

F3 = m(6,7,8,9,13,14,15) . (3)


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PLA Implementation using

minimum rows K_map


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F1 = BD+BC+AB .(4)

F2 = C+ABD .(5)

F3 = BC+ABC+ABD


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F1 = BD + BC + AB(C+C)

= BD + BC + ABC + ABC

= BD + BC (1+ A) + ABC

= BD + BC + ABC


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PLA TABLE


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PLA STRUCTURE


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Programmable Array Logic

The PAL device is a special case of PLA which has a programmable

AND array and a fixed OR array.

The basic structure of PAL is same as PLA. It is cheap compared toPLA as only the AND array is programmable.

It is also easy to program a PAL compared to PLA as only AND must

be programmed.


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The symbol of Figure

logically equal


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Connections to the AND gate inputs in a PAL



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Implementation of a Full Adder Using a PAL

ininininXYCCXYYCXCYX ''''''

XYYCXCinin


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Q+ = D = ABQ + ABQ


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Complex Programmable Logic Devices

A CPLD contains a bunch of PLD blocks whose inputs andoutputs are connected together by a global interconnectionmatrix.

Thus a CPLD has two levels of programmability: each PLDblock can be programmed, and then the interconnections

between the PLDs can be programmed.


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FPGA Die


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9.8 Field Programmable Gate Arrays

Equivalent OR Gate for F0


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Field Programmable Gate Arrays

The FPGA consists of 3 main structures:

1. Programmable logic structure,

2. Programmable routing structure, and

3. Programmable Input/Output (I/O).

P bl l i t t


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Programmable logic structure

The programmable logic structure FPGA consists of a2-dimensional array of configurable logic blocks (CLBs)


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Programmable routing structure

To allow for flexible interconnection of CLBs, FPGAs have 3programmable routing resources:

Vertical and horizontal routing channels which consist of differentlength wires that can be connected together if needed. These channelrun vertically and horizontally between columns and rows of CLBs asshown in the Figure.

Connection boxes, which are a set of programmable links that canconnect input and output pins of the CLBs to wires of the vertical orthe horizontal routing channels.

Switch boxes, located at the intersection of the vertical and horizontalchannels. These are a set of programmable links that can connect wiresegments in the horizontal and vertical channels.


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Programmable I/O

These are mainly buffers that can be configured either as

input buffers, output buffers or input/output buffers.

They allow the pins of the FPGA chip to function either as

input pins, output pins or input/output pins.


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Advantages of FPGA Design

Faster time-to-market

No NRE (Non Recurring Expenses)

Simpler design cycle

Field Reprogramability

More predictable project cycle

Reusability


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Disadvantages of FPGA Design

Power consumption in FPGA is more.

You don't have any control over the power optimization. This is

where ASIC wins the race !

You have to use the resources available in the FPGA.

Thus FPGA limits the design size.

Good for low quantity production.

As quantity increases cost per product increases compared to the

ASIC implementation.


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FPGA Summary

FPGAs are good for prototyping and limited production. If you are going to make 100-200 boards it isn't worth to make an

ASIC.

Generally FPGAs are used for lower speed, lower complexity andlower volume designs.

But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other

features, such as embedded processors, DSP blocks, clocking, andhigh-speed serial at ever lower price, FPGAs are suitable for almostany type of design.

In FPGA you need not do floor-planning, tool can do it efficiently. In

ASIC you have do it.


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FPGA's have special hardwares such as Block-RAM, DCM modules,MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can

be used to get better performace. Advanced FPGAs usually come with phase-locked loops, low-voltage

differential signal, clock data recovery, more internal routing, high speed,hardware multipliers for DSPs, memory,programmable I/O, IP cores andmicroprocessor cores.

Remember Power PC (hardcore), Microblaze (softcore) in Xilinx and ARM(hardcore), Nios(softcore) in Altera.

There are FPGAs available now with built in ADC ! Using all thesefeatures designers can build a system on a chip. Now, dou yo really need anASIC ?

programable pld s

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