program interference in mlc nand flash memory: characterization, modeling, and mitigation
DESCRIPTION
Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation. Yu Cai 1 Onur Mutlu 1 Erich F. Haratsch 2 Ken Mai 1. 1 Carnegie Mellon University 2 LSI Corporation. Flash Challenges: Reliability and Endurance. P/E cycles (provided). A few thousand. - PowerPoint PPT PresentationTRANSCRIPT
Program Interference in MLC NAND Flash Memory:
Characterization, Modeling, and Mitigation
Yu Cai1 Onur Mutlu1 Erich F. Haratsch2 Ken Mai1
1 Carnegie Mellon University2 LSI Corporation
Flash Challenges: Reliability and Endurance
E. Grochowski et al., “Future technology challenges for NAND flash and HDD products”, Flash Memory Summit 2012
P/E cycles (required)
P/E cycles (provided)
A few thousand
Writing the full capacity
of the drive 10 times per day
for 5 years (STEC)
> 50k P/E cycles
2
NAND Flash Memory is Increasingly Noisy
Noisy NANDWrite Read
3
Future NAND Flash-based Storage Architecture
MemorySignal
Processing
ErrorCorrection
Raw Bit Error Rate
Uncorrectable BER < 10-15
NoisyHighLower
4
Model NAND Flash as a digital communication channel
Design efficient reliability mechanisms based on the model
Our Goals:
NAND Flash Channel Model
Noisy NANDWrite
(Tx Information)Read
(Rx Information)
Simplified NAND Flash channel model based on dominant errors
Erase operation Program page operation
Neighbor page program
Retention
Cell-to-CellInterference
Time VariantRetention
Additive WhiteGaussian Noise
Write Read
Cai et al., “Threshold voltage distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling”, DATE 2013
Cai et al., “Flash Correct-and-Refresh: Retention-aware error management for increased flash memory lifetime”, ICCD 2012?
5
Outline
Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference
Read Reference Voltage Prediction Conclusions
6
How Current Flash Cells are Programmed Programming 2-bit MLC NAND flash memory in two
steps
7
Vth
ER(11)
LSB Program
Vth
ER(11)
Temp(0x)
MSBProgram
Vth
ER(11)
P1(10)
P2(00)
P3(01)
1
1 1
0
0 0
Basics of Program Interference
Traditional model of victim cell threshold voltage changes when neighbor cells are programmed
Victim Cell
WL<0>
WL<1>
WL<2>
(n,j)
(n+1,j-1) (n+1,j) (n+1,j+1)
LSB:0
LSB:1
MSB:2
LSB:3
MSB:4
MSB:6
(n-1,j-1) (n-1,j) (n-1,j+1)
∆Vx∆Vx
∆Vy∆Vxy ∆Vxy
∆Vxy ∆Vxy∆Vy
totalxyxyyyxxvictim CVCVCVCV /)22(
8
Previous Work Summary No previous work experimentally characterized and
modeled threshold voltage distributions under program interference
Previous modeling work Assumes linear correlation between the program
interference induced threshold voltage change of the victim cell and the threshold voltage changes of the aggressor cells
Coupling capacitance and total capacitance of each flash cell are the key coefficients of the model, which are process and design dependent random variables
Their exact capacitance values are difficult to determine Previously proposed model cannot be realistically applied in
flash controller
9
Outline
Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference
Read Reference Voltage Prediction Conclusions
10
Characterization Hardware Platform
11
Cai et al., “FPGA-Based Solid-State Drive Prototyping Platform”, FCCM 2011
Characterization Studies
Bitline to bitline program interference Wordline to wordline program interference
Program in page order Program out of page order
12
Bitline to Bitline Program Interference
Vth distributions of victim cells under 16 ( 4 x 4) different neighbor values {L, R} almost overlap
Bitline to bitline program interferences are small
P1 State P2 State P3 State
Wordline( N )
Wordline( N+1 )
Wordline( N-1 )
Victim Cell
XL R
L= { P0, P1, P2, P3 }
R= { P0, P1, P2, P3 }
13
WL to WL Interference with In-Page-Order Programming
Victim Word-line
Wordline( N+1 )
Wordline( N )
Wordline( N-1 )
14
Program interference increases the threshold voltage of victim cells and causes threshold voltage distributions shift to the right and become wider
Program interference depends on the locations of aggressor cells in a block Direct neighbor wordline program interference is the dominant source
of interference Neighbor bitline and far-neighbor wordline interference are orders of
magnitude lower
WL to WL Interference with Out-of-Page-Order Programming
Victim Word-line
Wordline( N+1 )
Wordline( N )
Wordline( N-1 )
15
The amount of program interference depends on the programming order of pages in a block In-page-order programming likely causes the least amount of interference Out-of-page-order programming causes much more interference
Comparison under Various Program Interference Signal-to-noise ratio comparison
Out-of-page-order Programming
16
Data Value Dependence of Program Interference
0
20
40
60
80
aggressor <11> aggressor<10> aggressor<00> aggressor <01>
Victi
m V
th In
crea
se
MSB Page programmed in aggressor cellVictim <10> Victim <00> Victim <01>
17
The amount of program interference depends on the values of both the aggressor cells and the victim cells
Outline
Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference
Read Reference Voltage Prediction Conclusions
18
Feature extraction for Vth changes based on characterization Threshold voltage changes on aggressor cell Original state of victim cell
Enhanced linear regression model
Maximum likelihood estimation of the model coefficients
Linear Regression Model
Kj
Kjy
Mn
nx
beforevictimneighborvictim jnVyxVyxjnV
10 ),(),(),(),(
XY (vector expression)
)(minarg1
2
2
YX
19
Model Coefficient Analysis
Direct above cell dominance Direct diagonal neighbor second Far neighbor interference exists Victim cell’s Vth has negative affect
20
Model Accuracy Evaluation
21
Ideal if no interference
(x,y)=(measured before interference, measured after interference)
Ideal if prediction is 100% accurate
(x,y)=(measured before interference, predicted with model)
With Systematic Deviation
Without Systematic Deviation
Distribution of Program Interference Noise
22
Program interference noise follows multi-modal Gaussian-mixture distribution
Program Interference vs P/E Cycles
23
Program interference noise distribution does not change significantly with P/E cycles
Outline
Background on Program Interference Characterization of Program Interference Modeling and Predicting Program Interference Mitigation of Program Interference
Read Reference Voltage Prediction Conclusions
24
Optimum Read Reference for Flash Memory Read reference voltage can affect the raw bit error
rate
There exists an optimal read reference voltage Predictable if the statistics (i.e. mean, variance) of
threshold voltage distributions are characterized and modeled
Vth
f(x) g(x)
v0 v1vref
ref
ref
v
vdxxgdxxfBER )()(1
ref
ref
v
vdxxgdxxfBER
'
')()(2
Vth
f(x) g(x)
v’refv0 v1
State-A State-AState-B State-B
25
Optimum Read Reference Voltage Prediction
Learning function (periodically, every ~1k P/E cycles) Program known data pattern and test Vth Program aggressor neighbor cells and test victim Vth after interference
Optimum read reference voltage prediction Default read reference voltage + Program interference noise mean
Evaluation Results
Read reference voltage prediction can reduce raw BER and increase the P/E cycle lifetime
32k-bit BCH Code(acceptable BER = 2x10-3)
30% lifetime improvement
No read reference voltage predictionWith read reference voltage prediction
Outline
Background of Program Interference Program Interference Characterization Modeling and Predicting Program Interference Read Reference Voltage Prediction to Mitigate
Program Interference Conclusions
28
Key Findings and Contributions
Methodology: Extensive experimentation with real 2Y-nm MLC NAND Flash chips
Amount of program interference is dependent on Location of cells (programmed and victim) Data values of cells (programmed and victim) Programming order of pages
Our new model can predict the amount of program interference with 96.8% prediction accuracy
Our new read reference voltage prediction technique can improve flash lifetime by 30%
29
Program Interference in MLC NAND Flash Memory:
Characterization, Modeling, and Mitigation
Yu Cai1 Onur Mutlu1 Erich F. Haratsch2 Ken Mai1
1 Carnegie Mellon University2 LSI Corporation