Vice President

Flash Product Planning Group

Hynix Semiconductor Inc.

Seaung Suk Lee

August 10, 2011

Emerging Challenges

in NAND Flash Technology

1

Presentation Agenda

NAND Flash Market Overview

Technology Scaling Trend & Forecast

Technology Scaling Limitation & Hurdle

Future Technology Development Direction

2

Presentation Agenda

NAND Flash Market Overview

Technology Scaling Trend & Forecast

Technology Scaling Limitation & Hurdle

Future Technology Development Direction

3

Market Revenue Forecasting

[Source; WSTS2011]

4

Prospective Application Trend

[Source; Hynix Marketing 2011]

5

General Market Requirement

Low Cost

Bit growth

High Performance

+ Controller SW solution

High Reliability

+ Controller SW solution

6

Standard Interface Trend; Performance

1.6GB/s

7

Presentation Agenda

NAND Flash Market Overview

Technology Scaling Trend & Forecast

Technology Scaling Limitation & Hurdle

Future Technology Development Direction

8

Further Scaling Solution?

‘98 ‘02 ‘06 ‘10 ‘14 ‘18

10

100

1,000

10,000

100,000

1,000,000

[ E

ffe

cti

ve

Ce

ll S

ize

: n

m2

]

64M

256M

512M1G

2G4G

8G16G

32G

1G2G

4G8G

16G32G

32G64G

250 160 130 90 70 4X 3X 2X 2Y5X 1X 1Y 1Znm …… ??

▶ 0.7um → 2Xnm (Cell size : ~1/2000)

▶ 1.5year/gen. (18 years / 12 gen.)

Conventional FG NAND cell has been scaled down over 18 years.

[ Year ]

MLC

SLC

?

9

Presentation Agenda

NAND Flash Market Overview

Technology Scaling Trend & Forecast

Technology Scaling Limitation & Hurdle

Future Technology Development Direction

10

Scaling Limitation of FG Cell

Physical Limitation;

Patterning

Structure formation : FG, CG, IPD …

Electrical Limitation;

Interference

Capacitive coupling ratio

No. of electron in FG

Dielectric leakage

11

Cell Scaling Limitation; x-direction

R R

M1

ILD

SAC NIT

SPACER

WSix

POLY2

ONO

POLY1

Tunnel Ox

ISO HDP

P-Substrate

ASA-FG Advanced Self-Aligned Floating Gate

CG

FG

M1

IPD

ILD

STI Active

• BL Loading;

RC • IPD & CG gap-fill;

Space

• Cell Current ∝ W

Width

12

Cell Scaling Limitation; y-directionM1

ILD

SAC NIT

SPACER

WSix

POLY2

ONO

POLY1

Tunnel Ox

P-Sub

DCT

••• •••

DSL DSL WL31 WL30 WL15 WL1 WL0 SSL SSLDCT SCT

• WL Loading;

RC delay

• Cell S/D Punch;

0ff leakage

ILD

CG

FG

So

urc

e

Dra

in

• Interference;

Vt distribution

13

NAND Program Speed

Program Speed = t (PROG + Verify) X N• tPROG ; unit program & verify time

• N ; no. of ISPP

NAND

Program

Speed

t (PROG)

t (Verify)

W/L loading

B/L loading

No. of Pulse PGM Vt

Distribution

@ fixed bias

1/∝ ∝

1/∝ ∝

∆ ISPP∝ 1/∝

14

WL & BL Loading Improvement

WL Loading

– Material; Poly- Si CoSix W

– WL Space; Vertical Profile Low-k dielectric Air Gap

0 10 20 30 40 50 60 700.2

0.4

0.6

0.8

1.0

Norm

aliz

ed U

nit

Airgap Portion between WLs[%]

WL Capacitance

0 10 20 30 40 50 60 70-3

0

3

6

Cell

Vth

[V]

Airgap Portion between WLs [%]

PGM Vth

UV Vth

(a) (b)

WL

BL Loading

– Material; W Al Cu

– BL Space; Vertical Profile Low-k dielectric Air Gap

15

P- Well

Oxide

ee eheeee

eeee

ee eeeeeeee

ONO

FG

eh eh eh eh eh eh

CG (Positive)

eeeeeeeeeeee ee

No. of stored electrons in FG

eeeeeeeeeeee ee

10010

10

100

1000

Flash Technology Node [nm]

Num

ber

of

Ele

ctr

on p

er

bit

, [N

]

1xnm

2xnm

2ynm

NOR Flash Projection

(ITRS 2003) ●

◎◇

■▲

□

NOR Flash Projection

(ITRS 2003)

IEDM Papers

∆Vth-max= 3V Program Operation

16

Read Window Margin Solution

Vt Distribution Overlap due to;

Process Variation

Data Retention Shift

FG-FG Interference0V

L1 L2 L3

~2xnm

0V

1xnm ~

L0

Controller Solution

Smart Read Algorithm Strong ECC

17

Enhanced Solution Products

Hynix; E2NAND

[embedded-ECC]

Embedded Strong ECC Engine

18

Presentation Agenda

NAND Flash Market Overview

Technology Scaling Trend & Forecast

Technology Scaling Limitation & Hurdle

Future Technology Development Direction

19

Planar FG with High-k IPD

CG Gap-filling & Interference Thin FG structure with High-k IPD

FG vertical scaling

Conventional FG Structure

STI

FGHigh-k IPD

CG

Active

Planar FG Structure

20

3D Cell Structure Approach

Stacked 3D with SONOS structure

Stacked 3D with FG structure

Si Pillar 3D with wafer bonding technology

21

History of 3D NAND Flash

~2006 2007 2008 2009 2010 2011

FG

High Process Cost Low Process Cost

S-SGT IEDM 2001

SO

NO

S /

TA

NO

S

Stacked NANDIEDM 2006

Multi TFTIEDM2006

BiCSVLSI Symp

TCATVLSI Symp

VG-NANDVLSI Symp

VSATVLSI Symp

VG TFT VLSI Symp

Hybrid 3D IMW

DC-SF IEDM

P-BiCSVLSI Symp

: Macronix

: The University of Tokyo

Si Pillar 3D NANDSemi. International 2007

22

Stacked 3D NAND Flash Concept

3D NAND Cell string

SCT

String 1 String 2 String 3 String 4

DCT

DSL

WL

SSL

Block

23

P-BiCS

[VLSI 2009 by Toshiba]

CG

Charge Trap Layer

Poly-SiChannel

Stacked 3D Cell Structures

TCAT

W Gate

Charge Trap Layer

Poly-SiChannel

[VLSI 2009 by Samsung]

24

Stacked 3D Cell Structures

Hybrid Stacked 3D

3D Cell Structure with Horizontal Poly-Si Channel

[IMW 2011 by Hynix]

25

Dual CG – Surrounding 3D FG Cell

New 3D Structure Concept with FG cell

Surrounding FG is controlled by two control gates.

Surrounding FG

CG(upper)

CG(lower)

IPD

Channel polyTunnel oxide

Single cell

*) Sung Jin Whang, et al, IEDM. 2010, pp.668-671

[IEDM 2010 by Hynix]

26

Si Pillar 3D Structure

[Semi. International 2007 by BeSang Tech.]

PeripheralRegion

Cell StringsSi Pillar

27

Future Technology Analysis

Technology Strong Points Weak Points

Planar FG Friendly Structure High-k Dielectric Stability

FG-3DReliability

Small Interference

Scaling Limitation

Stacking Limitation

Stacked 3DLow Cost

Small Interference

New Materials

SONOS Reliability

Si PillarApproved Materials

Scalability

Wafer Bonding Cost

SONOS Reliability

28

What are Decision Points ?

ProcessCost

Production YieldReliability

29

Who is Winner at Post 1x or 1y nm ?

?

Thank you!

Somebody will find a solution.