processor structure and function chapter8:. cpu structure cpu must: fetch instructions –read...
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Processor Structure and
Function
Chapter8:
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CPU Structure
CPU must: Fetch instructions
– Read instruction from memory
Interpret instructions– Instruction decoded to determine the action
Fetch data – Execution Instruction may require reading data from
memory/ I/O module
Process data– Execution Instruction may require performing some
arithmetic/ logical operation on data
Write data– Result from execution may require writing data to
memory/ I/O module
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CPU With Systems Bus
Major component of processor:
ALU CU Registers (internal memory)
ALU does the actual computation/processing of data CU controls the data and instruction movement into and out of the processor. Also controls ALU operation
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CPU Internal Structure
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Registers
CPU must have some working space (temporary storage) called registers
Number and function vary between processor designs
One of the major design decisionsTop level of memory hierarchy
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User Visible Registers
Enable machine/assembly language programmer to minimize main memory reference by optimizing use of register
Category : General Purpose Data Address Condition Codes
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General Purpose Registers (1)
May be true general purposeMay be restricted (eg. For floating point /
stack operation)May be used for data or addressing
Data – only hold data Accumulator
Addressing Segment pointer Index register Stack pointer
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General Purpose Registers (2)
Make them general purpose—Increase flexibility and programmer options—Increase instruction size & complexity
Make them specialized—Smaller (faster) instructions—Less flexibility
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How Many GP Registers?
Between 8 - 32Fewer = more memory referencesMore does not reduce memory references
and takes up processor real estateSee also RISC
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How big?
Large enough to hold full addressLarge enough to hold full wordOften possible to combine two data
registers—C programming—double int a;—long int a;
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Condition Code Registers
Sets of individual bits—e.g. result of last operation was zero
Can be read (implicitly) by programs—e.g. Jump if zero
Can not (usually) be set by programs
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Control & Status Registers
Variety of processor registers that are employed to control operation of processor
4 registers are necessary to instruction execution:1. Program Counter2. Instruction Decoding Register3. Memory Address Register4. Memory Buffer Register
Revision: what do these all do?
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Program Status Word
Processor design include register or set of registers and known as PSW, that contain information
contains condition codes + other status info Common field or flags include:
Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor
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Supervisor Mode
Intel ring zeroKernel modeAllows privileged instructions to executeUsed by operating systemNot available to user programs
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Other Registers
May have registers pointing to:—Process control blocks (see O/S)—Interrupt Vectors (see O/S)
N.B. CPU design and operating system design are closely linked
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Example Register Organizations
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Instruction Cycle
RevisionStallings Chapter 3
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Indirect Cycle
May require memory access to fetch operands
Indirect addressing requires more memory accesses
Can be thought of as additional instruction subcycle
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Instruction Cycle with Indirect
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Instruction Cycle State Diagram
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Data Flow (Instruction Fetch)
Depends on CPU designIn general:
Fetch– PC contains address of next instruction– Address moved to MAR– Address placed on address bus– Control unit requests memory read– Result placed on data bus, copied to MBR, then
to IR– Meanwhile PC incremented by 1
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Data Flow (Fetch Diagram)
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Data Flow (Data Fetch)
IR is examinedIf indirect addressing, indirect cycle is
performed—Right most N bits of MBR transferred to MAR—Control unit requests memory read—Result (address of operand) moved to MBR
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Data Flow (Indirect Diagram)
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Data Flow (Execute)
May take many formsDepends on instruction being executedMay include
—Memory read/write—Input/Output—Register transfers—ALU operations
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Data Flow (Interrupt)SimplePredictableCurrent PC saved to allow resumption
after interruptContents of PC copied to MBRSpecial memory location (e.g. stack
pointer) loaded to MARMBR written to memoryPC loaded with address of interrupt
handling routineNext instruction (first of interrupt handler)
can be fetched
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Data Flow (Interrupt Diagram)
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Prefetch
Fetch accessing main memoryExecution usually does not access main
memoryCan fetch next instruction during
execution of current instructionCalled instruction prefetch
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Improved Performance
But not doubled:—Fetch usually shorter than execution
– Prefetch more than one instruction?
—Any jump or branch means that prefetched instructions are not the required instructions
Add more stages to improve performance
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Computer Performance(1)
Understanding computer performance: Algorithm – determines number of operations executed Programming language, compiler, architecture – determines number of machine instructions executed per operation Processor and memory system – determine how fast instruction are executed I/O system (incl. OS) – determines how fast I/O operations are executed
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Computer Performance(2)
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Performance – Let’s look at this…
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Computer Performance(3)
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Response Time and Throughput
Response Time how long it takes to do a task
Throughput total of work done per unit time
How are Response Time and Throughput affected by
replacing the processor with a faster version? adding more processors?
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CPU Clocking Operation of computer hardware governed by constant-rate of clock
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Execution Time(1)
The execution time is defined in terms of:
Elapsed Time counts everything a useful number, but often not good for comparison purposes
CPU Time does not count I/O or time spent running other programs
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Execution Time(2)
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Basic Definition of Performance(1) For some program running on machine X, (Performance)x = 1/(execution time)x
When X is n times faster than Y machine (Performance)x / (Performance)y = n
Problem: Machine A runs a program in 20s Machine B runs the same program in 25s
How to improve performance - everything else being equal we can either:
reduce the number of required cycle for a program, or reduce the clock cycle time (clock rate)
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Basic Definition of Performance(2)
Hardware Designer must often trade off clock rate against clock count Can we assume: # of cycle = # of instructions?
multiplication takes more time than addition floating-point operations take longer than integer accessing memory takes more time than registers
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CPU Time – proportional to instruction count(1)
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CPU Time – proportional to instruction count(2)
Any additional instruction you execute takes time.
CPU Time: proportional to clock period - how can architects reduce clock period?
Instruction’s execution time in “number of cycles” - short clock period => short execution time.
What ultimately limits an architect’s ability to reduce the clock periods?
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CPU Time – Example(1)
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CPU Time – Example(2)
Solution:
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Aspects of CPU Performance(1)
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Aspects of CPU Performance(2)
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Performance Equation
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Amdahl’s Law(1)
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Amdahl’s Law(2)
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Enhancement by Multiple CPUs
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Experimental Example
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Points to remember…..