processor structure and function chapter 12
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Processor Structure and Function Chapter 12. TEAM MEMBERS: CARLOS CANEDO ALEX CRUZ DIEGO ROZO. Team #5. - 12.1 Processor Organization - 12.2 Register Organization - 12.3 Instruction Cycle - 12.4 Instruction Pipelining/ Dealing with Branches. 12.1 Processor Organization. - PowerPoint PPT PresentationTRANSCRIPT
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TEAM MEMBERS:• CARLOS CANEDO• ALEX CRUZ• DIEGO ROZO
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Team #5Team #5 - 12.1 Processor Organization - 12.2 Register Organization - 12.3 Instruction Cycle - 12.4 Instruction Pipelining/ Dealing with
Branches
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12.1 Processor OrganizationFetch InstructionInterpret instructionFetch DataProcess DataWrite Data
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THINGS TO REMEBER….1. The processor needs to store some
data temporally. 2. It must remember the location of the
last instruction so that it can know where to get the next instruction.
3. It needs to store instructions and data temporally while an instruction is being executed.
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CPU with System Bus
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CPU Internal Structure
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Register Organization
User-visible registers
Control and status registers
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User Visible Registers
General PurposeDataAddressCondition Codes
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General Purpose Registers
DataAccumulator
AddressingSegment pointersIndex registersStack Pointer
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Control & Status Registers
Program CounterInstruction Decoding RegisterMemory Address RegisterMemory Buffer Register
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Program Status WordSign ZeroCarryEqualOverflowInterrupt enable/disableSupervisor
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Example Register Org.
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Instruction Cycle
It is the time in which a single instruction is fetched from memory, decoded, and executed
An Instruction Cycle requires the following sub-cycle:
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Instruction Cycle Fetch
Read next instruction from memory into the processor
Indirect Cycle (Decode Cycle)May require memory access to fetch operands, therefore more memory accesses.
Interrupt Save current instruction and service the
interrupt Execute
Interpret the opcode and perform the indicated operation
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Instruction Cycle
Fetch
Execute
Fetch
Execute
Indirect
Fetch
Execute
Interrupt
Fetch
Execute
IndirectInterrupt
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Data Flow (Fetch Diagram)
PC
ControlUnit
PC MARMAR
MemoryMemory
ControlUnit
MBR
Memory
IR MBR
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Data Flow (Indirect Diagram)
MBR
MARMAR
Memory
ControlUnit
Memory
MBR
Memory
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Data Flow (Execute)May take many formsDepends on instruction being executed
May includeMemory read/writeInput/OutputRegister transfersALU operations
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Data Flow (Interrupt Diagram)
ControlUnit
PC
MBR
PC
ControlUnit
MARMAR
Memory
MBR
MemoryMemory
ControlUnit
ControlUnit
PC
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12.4 Instruction Pipelining
Instruction processing is subdivided:- Fetch/ Execute instruction
Pipeline has two independent stages:1st Stage – Fetch an instruction and buffers it.2nd Stage – Temporarily free until first stage passes it the buffered instruction.While the second stage is executing the instruction, the first stage fetches and buffers the next instruction.
Instruction prefetch or fetch overlap.- Purpose? To speed up instruction execution.
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Two-Stage Instruction Pipeline
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Instruction Processing
Fetch instruction (FI)Decode instruction (DI)Calculate operands (CO)Fetch operands (FO)Execute instruction (EI)Write operand (WO)
Successive instructions in a program sequence will overlap in execution.
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Timing Diagram for Instruction Pipeline Operation
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Six-Stage CPU Instruction PipelineThe logic needed for pipelining to account for branches, interrupts, and arising problems.
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Alternative Pipeline Depiction
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RISC Pipeline1.Instruction fetch2.Instruction decode and register
fetch3.Execute4.Memory Access5.Register write back
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Branches
Branch- group of instructions
Branch Instructions – (Jump Instruction) One of it’s operands is the address of the next instruction to be executed.
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BranchesTwo Types of Branch Instructions
1. Unconditional – Branch always happens2. Conditional – Branch only happens if
certain condition is met.The PC is updated to the address specified in the operand of the conditional branch instruction.
A conditional branch instruction is similar to an if statement.
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Conditional Branch Instructions
Condition CodesBRP X
Branch to location X if result is positive
BRZ XBranch to location X if result is zero
BRE R1,R2,XBranch to location X if contents of R1
= R2
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Conditional Branch Instructions
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Dealing with BranchesA major problem in designing an
instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.
Since conditional branches alter the steady flow of instructions, we must come up with ways to execute them efficiently.
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Dealing with Branches5 Approaches to Dealing with
Conditional BranchesMultiple StreamsDelayed BranchPrefetch Branch targetLoop BufferBranch Prediction
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Dealing with Branches• Multiple Streams (IBM 370/168 and IBM 3033)
Pipeline fetches both instructions. Leads to contention delays, and branches
can lead to too many streams.• Delayed Branch
Branch Instruction occurs later than desired.• Prefetch Branch Target (360/91 IBM)
The target of the branch is prefetched, along with the instruction following the branch, so if the branch is taken this will speed up performance.
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Dealing with BranchesLoop buffer ( Motorola 68010)
Memory containing the n most recently fetched instructions.
Useful with if-then and if-then-else statements, as well as loops
Branch PredictionDifferent techniques are used to predict
whether the branch will be taken or notIf the prediction is correct this will speed
up performance
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Dealing with Branches
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Intel Pentium BranchThe prediction of whether a jump will occur or not, is based on the branch’s previous behavior. There are four possible states that depict a branch’s disposition to jump:
Stage 0: Very unlikely a jump will occurStage 1: Unlikely a jump will occurStage 2: Likely a jump will occurStage 3: Very likely a jump will occur
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Intel Pentium BranchIt is actually believed that Pentium’s original algorithm for branch prediction was incorrect. (Left)
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Researchhttp://www.it.jcu.edu.au/Subjects/cp1300/resourc
es/lectnotes/system/fde.htmlhttp://dr-pisit.com/csc331/Lec10-
CPU&Pipeline.pdf http://en.wikipedia.org/wiki/Instruction_pipeli
ninghttp://www.itreviews.co.uk/hardware/h738.ht
m
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Review Questions1. What are the major components of a processor?
Arithmetic and Logic Unit (ALU) and the Control Unit (CU).
2. What is the function of the ALU?
3. What is the function of the control unit?
The ALU does the actual computation or processing of data.
The control unit controls the movement of data and instructions into and out of the processor and controls the operations of the ALU.
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4. What are the two roles that registers in the processor perform?
User-visible registers, and control and status registers.
The ALU does the actual computation or processing of data.
It is the time in which a single instruction is fetched from memory, decoded, and executed.
5. What are bits set by the processor hardware as a result of operations?
6. What is an instruction cycle?
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7. What are the four sub-cycle of an instruction cycle?
Fetch, Indirect (if any) , execute, and interrupt (if any).
No, it depends on the CPU’s design.
PC MBR Address of Stack MAR
MAR Memory PC Memory Control Unit request memory write via Control Bus PC is loaded with address of Interrupt handler
8. Is the fetch or execute cycle the same for all CPU?
9. What is the sequence of an interrupt cycle?
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10. What is the main purpose for instruction pipelining?
To speed up the instruction execution rate.
To gain further speedup, the pipeline must have more stages for decomposition.
A statement that if true will allow the branch to be executed.
11. How can you make the pipelining more efficient?
12. What is a condition code?
13. What is another name for a branch instruction?
A jump instruction.