Processor Memory

I/O device 1 I/O device n

Bus

Figure 4.1. A single-bus structure.

I/O

Bus

Address lines

Data lines

Control lines

Figure 4.2. I/O interface for an input device.

interfacedecoderAddress Data and

status registersControlcircuits

Input device

KEN

SOUT

CONTROL

DATAIN

Figure 4.3. Registers in keyboard and display interfaces.

DEN

DATAOUT

7

KIRQ SINSTATUS

6 5 4 3 2 1 0

DIRQ

Move #LINE,R0 Initializememorypointer.WAITK TestBit #0,STATUS Test SIN.

Branch=0 WAITK Wait forcharactertobeentered.Move DATAIN,R1 Readcharacter.

WAITD TestBit #1,STATUS Test SOUT.Branch=0 WAITD Wait fordisplay to becomeready.Move R1,DATAOUT Sendcharactertodisplay.Move R1,(R0)+ Storecharacterandadvance pointer.

Compare #$0D,R1 Check ifCarriageReturn.Branch0 WAITK Ifnot,getanothercharacter.Move #$0A,DATAOUT Otherwise,sendLine Feed.Call PROCESS Call asubroutineto process

theinputline.

Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display.

Figure 4.5. Transfer of control through the use of interrupts.

here

Interruptoccurs

M

i

2

1

PRINT routine

Program 2Program 1

COMPUTE routine

i 1+

Processor

INTR

R

Figure 4.6. An equivalent circuit for an open-drain bus usedto implement a common interrupt-request line.

INTR1 INTR2 INTRn

Vdd

INTR

Priority arbitration

Device 1 Device 2 Device p

circuit

Pro

cess

or

Figure 4.7. Implementation of interrupt priority using individual

INTA1

INTR1 INTRp

INTA p

interrupt-request and acknowledge lines.

Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

Figure 4.8. Interrupt priority schemes.

(b) Arrangement of priority groups

Device Device

circuitPriority arbitration

Pro

cesso

r

Device Device

(a) Daisy chain

Pro

cesso

r

Device 2

INTR

INTA

INTR1

INTR p

INTA1

INTA p

Device nDevice 1

MainProgram

Move #LINE,PNTR Initializebufferpointer.Clear EOL Clearend-of-lineindicator.BitSet #2,CONTROL Enable keyboard interrupts.BitSet #9,PS Set interrupt-enablebit in the PS....

Interrupt-serviceroutine

READ MoveMultiple R0-R1, (SP) SaveregistersR0andR1onstack.Move PNTR,R0 Loadaddresspointer.MoveByte DATAIN,R1 GetinputcharacterandMoveByte R1,(R0)+ storeit inmemory.Move R0,PNTR Updatepointer.

CompareByte #$0D,R1 Check ifCarriageReturn.Branch0 RTRNMove #1,EOL Indicateend ofline.BitClear #2,CONTROL Disablekeyboard interrupts.

RTRN MoveMultiple (SP)+,R0-R1 RestoreregistersR0and R1.Return-from-interrupt

Figure 4.9. Using interrupts to read a line of characters from a keyboard via the registers in Figure 4.3.

–

Done

IE

IRQ

Status and control

Starting address

Word count

WR/

31 30 1 0

Figure 4.18. Registers in a DMA interface.

Figure 4.19. Use of DMA controllers in a computer system.

memoryProcessor

Keyboard

System bus

Main

InterfaceNetwork

Disk/DMAcontroller Printer

DMAcontroller

DiskDisk

Figure 4.19. Use of DMA controllers in a computer system.

Processor

DMAcontroller

1

DMAcontroller

2BG1 BG2

BR

BBSY

Figure 4.20. A simple arrangement for bus arbitration using a daisy chain.

BBSY

BG1

BG2

Busmaster

BR

Processor DMA controller 2 Processor

Figure 4.21. Sequence of signals during transfer of b us mastership

for the devices in Figure 4.20.

Time

Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.

Figure 4.22. A distributed arbitration scheme.

Interface circuitfor device A

0 1 0 1 0 1 1 1

O.C.

Vcc

Start-Arbitration

ARB0

ARB1

ARB2

ARB3

Figure 4.23. Timing of an input transfer on a synchronous bus.

Bus cycle

Data

Bus clock

commandAddress and

t0 t1 t2

Time

Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.

Data

Bus clock

commandAddress and

t0 t1t2

commandAddress and

Data

Seen by master

Seen by slave

tAM

tAS

tDS

tDM

Time

Figure 4.25. An input transfer using multiple clock cycles.

1 2 3 4

Clock

Address

Command

Data

Slave-ready

Time

Figure 4.26. Handshake control of data transfer during an input operation.

Slave-ready

Data

Master-ready

and commandAddress

Bus cycle

t1 t2 t3 t4 t5t0

Time

Figure 4.27. Handshake control of data transfer during an output operation.

Bus cycle

Data

Master-ready

Slave-ready

and commandAddress

t1 t2 t3 t4 t5t0

Time

Valid

Data

Keyboardswitches

Encoderand

debouncingcircuit

SIN

Inputinterface

Data

Address

R /

Master-ready

Slave-ready

W

DATAIN

Processor

Figure 4.28. Keyboard to processor connection.

DATAIN

Keyboarddata

ValidStatusflag

Read-

1Slave-

Read-

SIN

ready

A31

A1

A0

Addressdecoder

Q7 D7

Q0 D0

D7

D0

R/ W

Figure 4.29. Input interface circuit.

data

status

ready

Master-

CPU SOUT

Outputinterface

Data

Address

R /

Master-eady

Slave-ready

ValidW

DataDATAOUT

Figure 4.31. Printer to processor connection.

PrinterProcessor

Idle

D A TAIN

1

SIN

Ready

A31

A1

A0

Addressdecoder

D7

D0

R / W

Figure 4.33. Combined input/output interface circuit.

A2

D A TA OUT

Inputstatus

BusPA7

PA0

CA

PB7

PB0

CB1CB2

SOUT

D1

RS1

RS0

My-address

Handshak econtrol

Master -

ReadySla v e-

DATAIN

DATAOUT

DataDirectionRegister

Register

select

Statusand

control

Accept

ReadyR/W

RS0

RS1RS2

My-address

INTR

C1

C2

P7

P0

D7

D0

Figure 4.34. A general 8-bit parallel interface.

Handshak econtrol

DAT A OUT

Printerdata

Idle

ValidRead Load

SOUT

ready

A31

A1

A0

Addressdecoder

D7 Q 7

D0 Q 0

D7

D0

Figure 4.35. A parallel point interface for the bus of Figure 4.25,with a state-diagram for the timing logic.

status data

D1 Q 1D0

T imingLogic

Clock

My-address

R/ W

Sla v e-

Idle Respond

My-address

Go

Go=1

Figure 4.36. T iming for the output interf ace in Figure 4.35.

1 2 3

Clock

Address

R/W

Data

Slave-ready

Go

Time

INTR

Chip andregisterselect

Statusand

control

Accept

Ready

R/W

RS0

RS1

My-address

Receiving clock

Transmission clock

Figure 4.37. A serial interface.

D7

D0

Output shift register

DATAOUT

DATAIN

Input shift register

Serialoutput

Serialinput