L5991L5991A

PRIMARY CONTROLLER WITH STANDBY

CURRENT-MODE CONTROL PWMSWITCHING FREQUENCY UP TO 1MHzLOW START-UP CURRENT (< 120µA)HIGH-CURRENT OUTPUT DRIVE SUITABLEFOR POWER MOSFET (1A)FULLY LATCHED PWM LOGIC WITH DOU-BLE PULSE SUPPRESSIONPROGRAMMABLE DUTY CYCLE100% AND 50% MAXIMUM DUTY CYCLE LIMITSTANDBY FUNCTIONPROGRAMMABLE SOFT STARTPRIMARY OVERCURRENT FAULT DETEC-TION WITH RE-START DELAYPWM UVLO WITH HYSTERESISIN/OUT SYNCHRONIZATIONLATCHED DISABLEINTERNAL 100ns LEADING EDGE BLANK-ING OF CURRENT SENSEPACKAGE: DIP16 AND SO16

DESCRIPTIONThis primary controller I.C., developed in BCD60IItechnology, has been designed to implement off

line or DC-DC power supply applications using afixed frequency current mode control.Based on a standard current mode PWM control-ler this device includes some features such asprogrammable soft start, IN/OUT synchronization,disable (to be used for over voltage protection andfor power management), precise maximum DutyCycle Control, 100ns leading edge blanking oncurrent sense, pulse by pulse current limit, over-current protection with soft start intervention, andStandby function for oscillator frequency reductionwhen the converter is lightly loaded.

August 2001

®

+

-

+

-

TIMING2

3

+

-14

T

Vref

CLK

2.5V

+

-1.2V

13

BLANKING

PWM

FAULTSOFT-START

R

S Q

25V

15V/10V

VREF OK

DIS

+

-E/A

1V R

2R

DIS

2.5V7

6

5

11

10

9

48151

13V

PWM UVLO

12

SGND COMP

SS

ISEN

DIS

DC

RCT

SYNC DC-LIM VCC VREF

D97IN725A

VFB

PGND

OUT

VC

OVER CURRENT

STAND-BY ST-BY

VREF

16

BLOCK DIAGRAM

ORDERING NUMBERS: L5991/L5991A (DIP16) L5991D/L5991AD (SO16)

MULTIPOWER BCD TECHNOLOGY

DIP16 SO16

1/23

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value UnitVCC Supply Voltage (ICC < 50mA) (*) selflimit VIOUT Output Peak Pulse Current 1.5 A

Analog Inputs & Outputs (6,7) -0.3 to 8 VAnalog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16) -0.3 to 6 V

Ptot Power Dissipation @ Tamb = 70°C (DIP16) @ Tamb = 50°C (SO16)

10.83

WW

Tj Junction Temperature, Operating Range -40 to 150 °CTstg Storage Temperature, Operating Range -55 to 150 °C

(*) maximum package power dissipation limits must be observed

THERMAL DATA

Symbol Parameter Value UnitRth j-amb Thermal Resistance Junction -Ambient (DIP16) 80 °C/W

Thermal Resistance Junction -Ambient (SO16) 120 °C/W

PIN FUNCTIONS

N. Name Function1 SYNC Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct2 RCT Oscillator pin for external CT, RA, RB components3 DC Duty Cycle control4 VREF 5.0V +/-1.5% reference voltage @ 25°C5 VFB Error Amplifier Inverting input6 COMP Error Amplifier Output7 SS Soft start pin for external capacitor Css8 VCC Supply for internal "Signal" circuitry 9 VC Supply for Power section

10 OUT High current totem pole output11 PGND Power ground12 SGND Signal ground13 ISEN Current sense14 DIS Disable. It must never be left floating. TIE to SGND if not used.15 DC-LIM Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is

imposed16 ST-BY Standby. Connect a resistor to RCT. Connect to VREF or floating if not used.

SYNC

RCT

DC

VREF

VFB

SS

COMP

1

3

2

4

5

6

7 OUT

SGND

PGND

ISEN

DIS

DC-LIM

ST-BY16

15

14

13

12

10

11

VCC 8 VC9

PIN CONNECTION

L5991 - L5991A

2/23

ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105°C; RT = 13.3kΩ (*) CT = 1nF;unless otherwise specified.)

Symbol Parameter Test Condition Min. Typ. Max. UnitREFERENCE SECTION

VREF Output Voltage Tj = 25°C; IO = 1mA 4.925 5.0 5.075 VLine Regulation VCC = 12 to 20V; Tj = 25°C 2.0 10 mVLoad Regulation IO = 1 to 10mA; Tj = 25°C 2.0 10 mV

TS Temperature Stability 0.4 mV/°CTotal Variation Line, Load, Temperature 4.80 5.0 5.130 V

IOS Short Circuit Current Vref = 0V 30 150 mAPower Down/UVLO VCC = 6V; Isink = 0.5mA 0.2 0.5 V

OSCILLATOR SECTIONInitial Accuracy pin 15 = Vref; Tj = 25°C; Vcomp = 4.5V 95 100 105 kHz

pin 15 = Vref; VCC = 12 to 20V Vcomp = 4.5V

93 100 107 kHz

pin 15 = Vref; VCC = 12 to 20V Vcomp = 2V

46.5 50 53.5 kHz

Duty Cycle pin 3 = 0,7V, pin 15 = VREFpin 3 = 0.7V, pin 15 = OPEN

00

%%

pin 3 = 3.2V, pin 15 = VREFpin 3 = 3.2V, pin 15 = OPEN

4793

%%

Duty Cycle Accuracy pin 3 = 2.79V, pin 15 = OPEN 75 80 85 %Oscillator Ramp Peak 2.8 3.0 3.2 VOscillator Ramp Valley 0.75 0.9 1.05 V

ERROR AMPLIFIER SECTIONInput Bias Current VFB to GND 0.2 3.0 µA

VI Input Voltage VCOMP = VFB 2.42 2.5 2.58 VGOPL Open Loop Gain VCOMP = 2 to 4V 60 90 dBSVR Supply Voltage Rejection VCC = 12 to 20V 85 dBVOL Output Low Voltage Isink = 2mA 1.1 VVOH Output High Voltage Isource = 0.5mA, VFB = 2.3V 5 6 VIO Output Source Current VCOMP > 4V, VFB = 2.3V 0.5 1.3 2.5 mA

Output Sink Current VCOMP = 1.1V, VFB = 2.7V 2 6 mAUnit Gain Bandwidth 1.7 4 MHz

SR Slew Rate 8 V/µsPWM CURRENT SENSE SECTION

Ib Input Bias Current Isen = 0 3 15 µAIS Maximum Input Signal VCOMP = 5V 0.92 1.0 1.08 V

Delay to Output 70 100 nsGain 2.85 3 3.15 V/V

Vt Fault Threshold Voltage 1.1 1.2 1.3 VSOFT START SECTION

ISSC SS Charge Current Tj = 25°C 14 20 26 µAISSD SS Discharge Current VSS = 0.6V Tj = 25°C 5 10 15 µA

VSSSAT SS Saturation Voltage DC = 0% 0.6 VVSSCLAMP SS Clamp Voltage 7 V

LEADING EDGE BLANKINGInternal Masking Time 100 ns

OUTPUT SECTIONVOL Output Low Voltage IO = 250mA 1.0 VVOH Output High Voltage IO = 20mA; VCC = 12V 10 10.5 V

IO = 200mA; VCC = 12V 9 10 VVOUT CLAMP Output Clamp Voltage IO = 5mA; VCC = 20V 13 V

Collector Leakage VCC = 20V VC = 24V 2 20 µA

(*) RT = RA//RB, RA = RB = 27kΩ, see Fig. 23.

L5991 - L5991A

3/23

6

8

2 0

3 0

V 1 4 = 0 , P in 2 = o p e nT j = 2 5 °C

0 4 8 1 2 1 6 2 0 2 400 .0 5

0 .1

0 .1 5

0 .2

4

V cc [V ]

Iq [m A ]

2 8

X Y

Figure 1. L5991 - Quiescent current vs. inputvoltage.(X = 7.6V and Y= 8.4V for L5991A)

0 4 8 1 2 1 6 2 0 2 40

5 0

1 0 0

1 5 0

2 0 0

2 5 0

3 0 0

3 5 0

V c c [V ]

Iq [µ A ]

V 1 4 = V re fT j = 2 5 ° C

X Y

Figure 2. L5991 - Quiescent current vs. inputvoltage (after disable).(X = 7.6V and Y= 8.4V for L5991A)

ELECTRICAL CHARACTERISTICS (continued.)

Symbol Parameter Test Condition Min. Typ. Max. UnitOUTPUT SECTION

Fall Time CO = 1nFCO = 2.5nF

2035

60 nsns

Rise Time CO = 1nFCO = 2.5nF

5070

100 nsns

UVLO Saturation VCC = VC = 0 to VCCON; Isink = 10mA 1.0 VSUPPLY SECTION

VCCON Startup voltage L5991L5991A

147.8

158.4

169

VV

VCCOFF Minimum OperatingVoltage

L5991L5991A

97

107.6

118.2

VV

Vhys UVLO Hysteresis L5991L5991A

4.50.5

50.8

VV

IS Start Up Current Before Turn-on at:VCC = VC = VCCON -0.5V

40 75 120 µA

Iop Operating Current CT = 1nF, RT = 13.3kΩ, CO =1nF 9 13 mAIq Quiescent Current (After turn on), CT = 1nF,

RT = 13.3kΩ, CO =0nF7.0 10 mA

VZ Zener Voltage I8 = 20mA 21 25 30 VSTANDBY FUNCTIONVREF-VST-BY IST-BY = 2mA 45 mV

VT1 Standby Threshold Vcomp Falling 2.5 VVcomp Rising 4.0 V

SYNCHRONIZATION SECTIONMaster Operation

V1 Clock Amplitude ISOURCE = 0.8mA 4 VI1 Clock Source Current Vclock = 3.5V 3 7 mA

Slave OperationV1 Sync Pulse Low Level 1 V

High Level 3.5 VI1 Sync Pulse Current VSYNC = 3.5V 0.5 mA

OVER CURRENT PROTECTIONVt Fault Threshold Voltage 1.1 1.2 1.3 V

DISABLE SECTIONShutdown threshold 2.4 2.5 2.6 VInput Bias Current Vpin14 = 0 to 3V -1 1 µA

IqSH Quiescent current AfterDisable

VCC = 15V 330 µA

L5991 - L5991A

4/23

8 10 12 14 16 18 20 22 24

7 .0

7 .5

8 .0

8 .5

9 .0

Vcc [V ]

Iq [m A]

V 14 = 0, V5 = V ref

R t = 4.5Kohm ,T j = 25°C

500K hz300K hz

1M hz

100K hz

Figure 3. Quiescent current vs. input voltage.

0 5 10 15 20 254.9

4.95

5

5.05

5.1

Iref [mA]

Vref [V]

Vcc=15V

Tj = 25°C

Figure 7. Reference voltage vs. load current.

-50 -25 0 25 50 75 100 125 1504.9

4.95

5

5.05

5.1

Tj (°C)

Vref [V])

Vcc = 15V

Iref = 1mA

Figure 8. Vref vs. junction temperature.

8 10 12 14 16 18 20 22

0

6

12

18

24

30

36

Vcc [V ]

Iq [m A]

C o = 1nF, T j = 25°C

D C = 0%

1M Hz

500KHz

300KHz

100KHz

Figure 4. Quiescent current vs. input voltageand switching frequency.

8 10 12 14 16 18 20 220

6

12

18

24

30

36

Vcc [V]

Iq [mA]

Co = 1nF, Tj = 25°C

DC = 100%

1MHz

500KHz

300KHz

100KHz

Figure 5. Quiescent current vs. input voltageand switching frequency.

-50 -25 0 25 50 75 100 125 1500.01

0.1

1

10

100

Junction temperature [˚C]

[mA]

Start-up current Vc=Vcc= Vccon-0.5V, before turn-on

Operating currentVcc =15V, after turn-on

RT=13.3kΩ, CT=1nF DC=75%, Co=1nF

Quiescent currentVcc =15V, after turn-on

RT=13.3 kΩ, CT=1nF DC = 0

Figure 6. IC Consumption vs. Temperature.

L5991 - L5991A

5/23

10

0 0.2 0.4 0.6 0.8 1 1.26

8

10

12

14

16

Isource [A]

Vsat = V [V]

Vcc = Vc = 15V

Tj = 25°C

Figure 11. Output saturation.

0 0.2 0.4 0.6 0.8 1 1.20

0.5

1

1.5

2

2.5

Isink [A]

10Vsat = V [V]

Vcc = Vc = 15VTj = 25°C

Figure 12. Output saturation.

1 10 100 1000 100000

40

80

120

fsw (Hz)

SVRR (dB)

Vcc=15V

Vp-p=1V

Figure 10. Vref SVRR vs. switching frequency.

0 200 400 600 800 1,000 1,200 1,4000

10

20

30

40

50

Vpin10 [mV]

Ipin10 [mA]

Vcc < Vcconbefore turn-on

Figure 13. UVLO Saturation

10 20 30 4010

20

50

100

200

500

1000

2000

5000

Rt (kohm)

fsw (KHz)

100pF

220pF

470pF

1nF2.2nF5.6nF

Tj = 25°C

Vcc = 15V, V15 =0V

Figure 14. Timing resistor vs. switching frequency.

-50 -25 0 25 50 75 100 125 1504.9

4.95

5

5.05

5.1

Tj (°C)

Vref [V]

Vcc = 15V

Iref= 20mA

Figure 9. Vref vs. junction temperature.

L5991 - L5991A

6/23

0.01 0.1 1 10 100 1000 10000 100000

0

50

100

150

20

40

60

80

100

120

140

f (KHz)

G [dB] Phase

Figure 20. E/A frequency response.

-50 -25 0 25 50 75 100 125 15028

30

32

34

36

38

40

42

Tj (°C)

Delay to output (ns)

PIN10 = OPEN1V pulse on PIN13

Figure 19. Delay to output vs junction temperature.

-50 -25 0 25 50 75 100 125 150280

290

300

310

320

Tj (°C)

fsw (KHz)

Rt= 4.5Kohm, Ct = 1nF

Vcc = 15V, V15= 0

Figure 16. Switching frequency vs. temperature.

2 4 6 8 10

300

600

900

1,200

1,500

Timing capacitor Ct [nF]

Dead time [ns]

Rt =4.5Kohm

V15 = 0V

V15 = Vref

Figure 17. Dead time vs Ct.

0 10 20 30 40 50 60 70 80 90 1001

1.5

2

2.5

3

3.5

Duty Cycle [%]

DC Control Voltage Vpin3 [V]

Rt = 4.5Kohm,

Ct = 1nF

V15 = 0VV15 = Vref

Figure 18. Maximum Duty Cycle vs Vpin3.

-50 -25 0 25 50 75 100 125 150280

290

300

310

320

Tj (°C)

fsw (KHz)

Rt= 4.5Kohm, Ct = 1nF

Vcc = 15V, V15=Vref

Figure 15. Switching frequency vs. tempera-ture.

L5991 - L5991A

7/23

STANDBY FUNCTIONThe standby function, optimized for flyback topol-ogy, automatically detects a light load conditionfor the converter and decreases the oscillator fre-quency on that occurrence. The normal oscillationfrequency is automatically resumed when the out-put load builds up and exceeds a defined thresh-old. This function allows to minimize power losses re-lated to switching frequency, which represent themajority of losses in a lightly loaded flyback, with-out giving up the advantages of a higher switchingfrequency at heavy load. This is accomplished by monitoring the output ofthe Error Amplifier (VCOMP) that depends linearlyon the peak primary current, except for an offset. If the the peak primary current decreases (as a re-sult of a decrease of the power demanded by theload) and VCOMP falls below a fixed threshold(VT1), the oscillator frequency will be set to alower value (fSB). When the peak primary currentincreases and VCOMP exceeds a second threshold(VT2) the oscillator frequency is set to the normalvalue (fosc). An appropriate hysteresis (VT2-VT1)prevents undesired frequency change whenpower is such that VCOMP moves close to thethreshold. This operation is shown in fig. 21.Both the normal and the standby frequency areexternally programmable. VT1 and VT2 are inter-nally fixed but it is possible to adjust the thresh-olds in terms of input power level.

APPLICATION INFORMATIONDetailed Pin Function DescriptionPin 1. SYNC (In/Out Synchronization). This func-tion allows the IC’s oscillator either to synchronizeother controllers (master) or to be synchronized toan external frequency (slave).As a master, the pin delivers positive pulses dur-ing the falling edge of the oscillator (see pin 2). Inslave operation the circuit is edge triggered. Referto fig. 23 to see how it works. When several ICwork in parallel no master-slave designation isneeded because the fastest one becomes auto-

matically the master. During the ramp-up of the oscillator the pin ispulled low by a 600µA internal sink current gener-ator. During the falling edge, that is when thepulse is released, the 600µA pull-down is discon-nected. The pin becomes a generator whosesource capability is typically 7mA (with a voltagestill higher than 3.5V).In fig. 22, some practical examples of synchroniz-ing the L5991 are given.Since the device automatically diminishes its op-erating frequency under light load conditions, it isreasonable to suppose that synchronization willrefer to normal operation and not to standby.

Pin 2. RCT (Oscillator). Two resistors (RA and RB)and one capacitor (CT), connected as shown infig. 23, allow to set separately the operating fre-quency of the oscillator in normal operation (fosc)and in standby mode (fSB).CT is charged from Vref through RA and RB in nor-mal operation (STANDBY = HIGH), through RAonly in standby ( STANDBY = LOW). See pin 16description to see how the STANDBY signal is gen-erated. When the voltage on CT reaches 3V, the capaci-tor is quickly internally discharged. As the voltagehas dropped to 1V it starts being charged again.

1 2 3 4

VCOMP

Pin

fosc

fSB

Stand-by

Normal operation

VT1

PNO

PSB

VT2

Figure 21. Standby dynamic operation.

L5991 L5991

RA

VREF

SYNCSYNC

RCTRCT

L4981A(MASTER) L5991

(SLAVE)

RA

VREFSYNC

RCT

ROSC COSC CT

L5991(MASTER)

L4981A(SLAVE)

SYNC

ROSCCT COSC

SYNC

(a) (b) (c)

RA

D97IN728A

CT

VREF

4

1

2

1

2

16

1817

4

2

1

RCT12

4

16 17 18

ST-BY

16

RB

ST-BY

16 RB

RB

16

ST-BY

Figure 22. Synchronizing the L5991.

L5991 - L5991A

8/23

The oscillation frequency can be established withthe aid of the diagrams of fig. 14, where RT will beintended as the parallel of RA and RB in normaloperation and RT = RA in standby, or consideringthe following approximate relationships:

fosc ≅ 1

CT ⋅ (0.693 ⋅ (RA // RB) + KT (1),

which gives the normal operating frequency, and:

fSB ≅ 1

CT ⋅ (0.693 ⋅ RA + KT) (2),

which gives the standby frequency, that is the onethe converter will operate at when lightly loaded. In the above expressions, RA // RB means:

RA//RB = RA ⋅ RB

RA + RB,

while KT is defined as:

KT = 90 V15 = VREF160 V15 = GND/OPEN

(3),

and is related to the duration of the falling-edge ofthe sawtooth:

Td ≈ 30 ⋅ 10−9 + KT ⋅ CT (4).

Td is also the duration of the sync pulses deliv-ered at pin 1 and defines the upper extreme of theduty cycle range, Dx (see pin 15 for DX definitionand calculation) since the output is held low dur-ing the falling edge.In case V15 is connected to VREF, however, theswitching frequency will be a half the values taken

from fig. 14 or resulting from (1) and (2).To prevent the oscillator frequency from switchingback and forth from fosc to fSB, the ratio fosc / fSBmust not exceed 5.5.If during normal operation the IC is to be synchro-nized to an external oscillator, RA, RB and CTshould be selected for a fosc lower than the masterfrequency in any condition (typically, 10-20% ),depending also on the tolerance of the parts.

Pin 3. DC (Duty Cycle Control). By biasing thispin with a voltage between 1 and 3 V it is possibleto set the maximum duty cycle between 0 and theupper extreme Dx (see pin 15).If Dmax is the desired maximum duty cycle, thevoltage V3 to be applied to pin 3 is:

V3 = 5 - 2(2-Dmax) (5)

Dmax is determined by internal comparison be-tween V3 and the oscillator ramp (see fig. 24),thus in case the device is synchronized to an ex-ternal frequency fext (and therefore the oscillatoramplitude is reduced), (5) changes into:

V3 = 5 − 4 ⋅ exp −

Dmax

RT ⋅ CT ⋅ fext

(6)

A voltage below 1V will inhibit the driver outputstage. This could be used for a not-latched devicedisable, for example in case of overvoltage pro-tection (see application ideas).If no limitation on the maximum duty cycle is re-quired (i.e. DMAX = DX), the pin has to be left float-ing. An internal pull-up (see fig. 24) holds the volt-age above 3V. Should the pin pick up noise (e.g.

+

-

R2R3

R1

CLAMP

D1

50Ω

RA

CT

D

RQ

600µA

D97IN729A

VREF

RCT

SYNC

CLK2

41

16ST-BY

RB

STANDBY

Figure 23. Oscillator and synchronization internal schematic.

L5991 - L5991A

9/23

during ESD tests), it can be connected to VREFthrough a 4.7kΩ resistor.

Pin 4. VREF (Reference Voltage). The device isprovided with an accurate voltage reference(5V±1.5%) able to deliver some mA to an externalcircuit.A small film capacitor (0.1 µF typ.), connectedbetween this pin and SGND, is recommended toensure the stability of the generator and to preventnoise from affecting the reference.Before device turn-on, this pin has a sink current ca-pability of 0.5mA.

Pin 5. VFB (Error Amplifier Inverting Input). Thefeedback signal is applied to this pin and is com-pared to the E/A internal reference (2.5V). TheE/A output generates the control voltage whichfixes the duty cycle.The E/A features high gain-bandwidth product,which allows to broaden the bandwidth of theoverall control loop, high slew-rate and current ca-pability, which improves its large signal behavior.Usually the compensation network, which stabi-lizes the overall control loop, is connected be-tween this pin and COMP (pin 6).

Pin 6. COMP (Error Amplifier Output). Usually,this pin is used for frequency compensation andthe relevant network is connected between thispin and VFB (pin 5). Compensation networks to-wards ground are not possible since the L5991E/A is a voltage mode amplifier (low output im-pedance). See application ideas for some exam-ple of compensation techniques.It is worth mentioning that the calculation of thepart values of the compensation network musttake the standby frequency operation into ac-count. In particular, this means that the open-loopcrossover frequency must not exceed fSB/4 ÷fSB/5.The voltage on pin 6 is monitored in order to re-

duce the oscillator frequency when the converteris lightly loaded (standby).Pin 7. SS (Soft-Start). At device start-up, a ca-pacitor (Css) connected between this pin andSGND (pin 12) is charged by an internal currentgenerator, ISSC, up to about 7V. During thisramp, the E/A output is clamped by the voltageacross Css itself and allowed to rise linearly, start-ing from zero, up to the steady-state value im-posed by the control loop. The maximum time in-terval during which the E/A is clamped, referred toas soft-start time, is approximately:

Tss ≅ 3 ⋅ Rsense ⋅ IQpk

ISSC ⋅ Css (7)

where Rsense is the current sense resistor (see pin13) and IQpk is the switch peak current (flowingthrough Rsense), which depends on the outputload. Usually, CSS is selected for a TSS in the or-der of milliseconds.As mentioned before, the soft-start intervenesalso in case of severe overload or short circuit onthe output. Referring to fig. 25, pulse-by-pulsecurrent limitation is somehow effective as long as

the ON-time of the power switch can be reduced(from A to B). After the minimum ON-time isreached (from B onwards) the current is out ofcontrol.To prevent this risk, a comparator trips an over-current handling procedure, named ’hiccup’ modeoperation, when a voltage above 1.2V (point C) isdetected on current sense input (ISEN, pin 13).Basically, the IC is turned off and then soft-startedas long as the fault condition is detected. As a re-sult, the operating point is moved abruptly to D,creating a foldback effect. Fig. 26 illustrates theoperation. The oscillation frequency appearing on the soft-start capacitor in case of permanent fault, referredto as ’hiccup" period, is approximately given by:

Thic ≅ 4.5 ⋅

1ISSC

+ 1

ISSD

⋅ Css (8)

+

-

R2

R1

RA

CT

D97IN727A

VREF

RCT

DC

TO PWM LOGIC

4

3

2

23K

28K

3µA

RB

ST-BY16

Figure 24. Duty cycle control.

VOUT

TON

D.C.M. C.C.M.

D

A

BC

IQpk

TON(min)

1-2 ·IQpk

IQpk(max)

IOUTISHORT IOUT(max)D97IN495

Figure 25. Regulation characteristic and re-lated quantities.

L5991 - L5991A

10/23

Since the system tries restarting each hiccup cy-cle, there is not any latchoff risk."Hiccup" keeps the system in control in case ofshort circuits but does not eliminate power com-ponents overstress during pulse-by-pulse limita-tion (from A to C). Other external protection cir-cuits are needed if a better control of overloads isrequired.

Pin 8. VCC (Controller Supply). This pin suppliesthe signal part of the IC. The device is enabled asVCC voltage exceeds the start threshold andworks as long as the voltage is above the UVLOthreshold. Otherwise the device is shut down andthe current consumption is extremely low(<150µA). This is particularly useful for reducingthe consumption of the start-up circuit (in the sim-plest case, just one resistor), which is one of themost significant contributions to power losses instandby.An internal Zener limits the voltage on VCC to25V. The IC current consumption increases con-siderably if this limit is exceeded.A small film capacitor between this pin and SGND(pin 12), placed as close as possible to the IC, isrecommended to filter high frequency noise.

Pin 9. VC (Supply of the Power Stage). It suppliesthe driver of the external switch and therefore ab-sorbs a pulsed current. Thus it is recommended toplace a buffer capacitor (towards PGND, pin 11,as close as possible to the IC) able to sustainthese current pulses and in order to avoid theminducing disturbances.This pin can be connected to the buffer capacitordirectly or through a resistor, as shown in fig. 27,to control separately the turn-on and turn-offspeed of the external switch, typically a Power-

MOS. At turn-on the gate resistance is Rg + Rg’, atturn-off is Rg only.

Pin 10. OUT (Driver Output). This pin is the out-put of the driver stage of the external powerswitch. Usually, this will be a PowerMOS, al-though the driver is powerful enough to driveBJT’s (1.6A source, 2A sink, peak).The driver is made up of a totem pole with a high-side NPN Darlington and a low-side VDMOS, thusthere is no need of an external diode clamp toprevent voltage from going below ground. An in-ternal clamp limits the voltage delivered to thegate at 13V. Thus it is possible to supply thedriver (Pin 9) with higher voltages without any riskof damage for the gate oxide of the external MOS.The clamp does not cause any additional in-crease of power dissipation inside the chip sincethe current peak of the gate charge occurs whenthe gate voltage is few volts and the clamp is notactive. Besides, no current flows when the gatevoltage is 13V, steady state.Under UVLO conditions an internal circuit (shown

7V

Thictime

SHORTIOUT

ISEN

FAULT

SS5V

0.5V

D98IN986

Figure 26. Hiccup mode operation.

OUT Rg

DRIVE &CONTROL

13V

VCVCC

Rg'

PGND

Rg(ON)=Rg+Rg'Rg(OFF)=Rg

D97IN726

L5991

9

10

11

8

Figure 27. Turn-on and turn-off speeds adjust-ment.

L5991 - L5991A

11/23

in fig.28) holds the pin low in order to ensure thatthe external MOS cannot be turned on acciden-tally. The peculiarity of this circuit is its ability tomantain the same sink capability (typically, 20mA@ 1V) from VCC = 0V up to the start-up threshold.When the threshold is exceeded and the L5991starts operating, VREFOK is pulled high (refer to fig.28) and the circuit is disabled.It is then possible to omit the "bleeder" resistor(connected between the gate and the source ofthe MOS) ordinarily used to prevent undesiredswitching-on of the external MOS because ofsome leakage current.

Pin 11. PGND (Power Ground). The current loopduring the discharge of the gate of the externalMOS is closed through this pin. This loop shouldbe as short as possible to reduce EMI and runseparately from signal currents return.

Pin 12 . SGND (Signal Ground). This ground refer-ences the control circuitry of the IC, so all theground connections of the external parts relatedto control functions must lead to this pin. In layingout the PCB, care must be taken in preventingswitched high currents from flowing through theSGND path.

Pin 13. ISEN (Current Sense). This pin is to beconnected to the "hot" lead of the current senseresistor Rsense (being the other one grounded), toget a voltage ramp which is an image of the cur-rent of the switch (IQ). When this voltage is equalto:

V13pk = IQpk ⋅ Rsense = VCOMP − 1.4

3 (9)

the conduction of the switch is terminated.To increase the noise immunity, a "Leading EdgeBlanking" of about 100ns is internally realized asshown in fig. 29. Because of that, the smoothingRC filter between this pin and Rsense could be re-moved or, at least, considerably reduced.

Pin 14. DIS (Device Disable). When the voltageon pin 14 rises above 2.5V the IC is shut downand it is necessary to pull VCC (IC supply voltage,pin 8) below the UVLO threshold to allow the de-vice to restart.The pin can be driven by an external logic signalin case of power management, as shown in fig.30. It is also possible to realize an overvoltageprotection, as shown in the section " ApplicationIdeas".If used, bypass this pin to ground with a fil-ter capacitor to avoid spurious activation due tonoise spikes. If not, it must be connected toSGND.

Pin 15. DC-LIM (Maximum Duty Cycle Limit). Theupper extreme, Dx, of the duty cycle range de-pends on the voltage applied to this pin. Approxi-mately,

Dx ≅ RT

RT + 230 (10)

if DC-LIM is grounded or left floating. Instead,

+

-

I

D97IN503

ISEN

0

3V

CLK

2V

+

-

+

-

1.2V

FROM E/A

OVERCURRENTCOMPARATOR

PWMCOMPARATOR TO PWM

LOGIC

TO FAULTLOGIC

13

Figure 29. Internal LEB.

10

12SGND

OUT

VREFOK

D97IN538

Figure 28. Pull-Down of the output in UVLO.

L5991 - L5991A

12/23

connecting DC-LIM to VREF (half duty cycle op-tion), Dx will be set approximately at:

Dx ≅ RT

2 ⋅ RT + 260 (11)

and the output switching frequency will be halvedwith respect to the oscillator one because an in-ternal T flip-flop (see block diagram) is activated.Fig. 31 shows the operation.The half duty cycle option speeds up the dis-charge of the timing capacitor CT (in order to getduty cycles as close to 50% as possible) so theoscillator frequency - with the same timing compo-nents will be slightly higher.

Pin 16 . S-BY (Standby Function). The resistor RB,along with RA, sets the operating frequency of theoscillator in normal operation (fosc). In fact, as longas the STANDBY signal is high, the pin is inter-nally connected to the reference voltage VREF bya N-channel FET (see fig. 32), so the timing ca-pacitor CT is charged through RA and RB. Whenthe STANDBY signal goes low the N-channel FETis turned off and the pin becomes floating. RB is

+

-

C

D97IN502

DISD

RQ

DISABLE

UVLO

2.5V

14

DISABLESIGNAL

Figure 30. Disable (Latched).

V15=GNDV5=V13=GND

V15=VREFV5=V13=GND

td

td

tc

tc

V2

V10

V2

V10

DX =tc

tc + td

DX =tc

2 ·tc + td

D97IN498

Figure 31. Half duty cycle option.

-

+ -

+

2.52.5/4

R

STANDBY

10V

LEVEL SHIFT

COMP

FB VREF

ST-BY

4

16

6

RCTCT

RARB

2

5

LOW

HIGH

STANDBY

D97IN752B

VT12.5V

VT24V

VCOMP

-

+

ISEN

13

R DRIVER OUT

STANDBY BLOCK

2R

Figure 32. Standby function internal schematic and operation.

L5991 - L5991A

13/23

now disconnected and CT is charged through RAonly. In this way the oscillator frequency (fSB) willbe lower. Refer to pin 2 description to see how tocalculate the timing components.Typical values for VT1 and VT2 are 2.5 V and 4Vrespectively. This 1.5V hysteresis is enough toprevent undesired frequency change up to a 5.5to 1 fosc/ fSB ratio. The value of VT1 is such that in a discontinuousflyback the standby frequency is activated whenthe input power is about 13% of the maximum. Ifnecessary, it is possible to decrease the powerthreshold below 13% by adding a DC offset (Vo)on the current sense pin (13, ISEN). This will alsoallow a frequency change greater than 5.5 to 1.The following equations, useful for design, apply:

PinSB = 12

⋅ LP ⋅ ƒosc ⋅

0.367 − Vo

Rsense

2

(12),

PinNO = 12

⋅ LP ⋅ ƒSB ⋅

0.867 − Vo

Rsense

2

(13),

ƒosc

ƒSB <

0.867 − Vo

0.367 − Vo

2

(14),

where PinSB is the input power below which theL5991 recognizes a light load and switches theoscillator frequency from ƒosc to fSB, PinNO is theinput power above which the L5991 switchesback from ƒSB to ƒosc and Lp the primary induc-tance of the flyback transformer.Connect to Vref or leave open this pin whenstand-by function is not used.

Layout hintsGenerally speaking a proper circuitboard layout isvital for correct operation but is not an easy task.Careful component placing, correct traces routing,appropriate traces widths and, in case of highvoltages, compliance with isolation distances arethe major issues. The L5991 eases this task byputting two pins at disposal for separate currentreturns of bias (SGND) and switch drive currents(PGND) The matter is complex and only few im-portant points will be here reminded.1) All current returns (signal ground, power

ground, shielding, etc.) should be routed sepa-rately and should be connected only at a singleground point.

2) Noise coupling can be reduced by minimizingthe area circumscribed by current loops. Thisapplies particularly to loops where high pulsedcurrents flow.

3) For high current paths, the traces should bedoubled on the other side of the PCB wheneverpossible: this will reduce both the resistanceand the inductance of the wiring.

4) Magnetic field radiation (and stray inductance)can be reduced by keeping all traces carryingswitched currents as short as possible.

5) In general, traces carrying signal currentsshould run far from traces carrying pulsed cur-rents or with quickly swinging voltages. Fromthis viewpoint, particular care should be takenof the high impedance points (current sense in-put, feedback input, ...). It could be a good ideato route signal traces on one PCB side andpower traces on the other side.

6) Provide adequate filtering of some crucialpoints of the circuit, such as voltage references,IC’s supply pins, etc.

L5991 - L5991A

14/23

APPLICATION IDEASHere follows a series of ideas/suggestions aimed at

either improving performance or solving commonapplication problems of L5991 based supplies.

C02

0.1µ

FC

010.

1µF

F01

AC

250

V T

3.15

A

88 to

270

VA

C

BD

01

R01

3.3

C03

220

µF40

0VR

1847

K3W

C10

10nF

100V

LF01

R03

47K

10R

08 2

2

13R

11 1

K

12

C05

100p

F

11

R10

0.22

C04

47µ

F

89

1416

R06

27

R12

330

K

R13

47K

R9

24K

24 16

C07

1µF

R5

12K

6800

pF

1 3 87

D06

1N41

48

57

C09

8.2

nFR

21 1

00

C08

3.3n

F

6

Q01

ST

P6

NA

60F

I

4N35

18 15 13141617

C56

470µ

F 2

5V

C57

470µ

F 2

5V1112 10

D04

1N

4148

R07

47

D05

1N49

37

C52

100µ

F25

0V

C54

220µ

F 1

00V

R52 47

C58

47µF

25V

D55

BY

W10

0-10

0

D56

BY

W10

0-10

0

R53

4.7K

R54 1K

C61

0.05

6µF

R58

4.7K

Q51

TL4

31

VR

5110

0K R55

300K

R56

4.3K

C59

0.01

µF

180V

65W

80V

10W

GN

D

6.3V 5W +

15V

5W -15V

5W

D97

IN73

0A

C62

100µ

F 1

00V

C55

1000

µF16

V

D54

BY

W10

0-10

0

D53

BY

T11

-600

D52

BY

T13

-800

C11

470

0pF

4K

V C

12

R19

4.7

MR

20 4

.7M

L599

1

R04

47K

R16

750K

R17

750K

C06

C11

2.2n

F

VA

C(V

)

Pin

(W)

Pou

t(W

)

88 2.95

110

3.10

220

3.90

270

4.40

2

Figure 33. Typical application circuit for computer monitors (90W).

L5991 - L5991A

15/23

4700

pF 4

KV

4700

pF 4

KV

4.7M

ST

P4N

A60

4N35

220

2 x

330µ

F35

V

1K

0.02

2 µF

2.7K

3.9K

28V

/ 0.

7A

GN

D

470µ

F

16V

BY

W10

0-50

BY

W98

-100

BY

W10

0-20

04.

7M

12V

/ 1.

5A

5V /

0.5A

C02

0.

1 µF

C01

0.

1µF

F01

AC

250

V T

1A

85 T

O26

5 V

ac

BD

01

2.2

LF01

10K

1.1M

BC

337

10 2

2

13 1

K

1247

0pF

11

0.47

1/2

W

33µF

/25V

89

1415

2233K

4.7K

47K

234 1

100n

F

22K

3.3

nF16 7

330n

F

470

470p

F

6

BA

T46

TL4

31

L599

1

22V

1.1M

ST

K2N

50

1N49

37

5

5.6K

N1

N2

N3

N4

Nau

x

5.6K

5.6K

2 x

470µ

F16

V

5.1K

270K

100µ

F40

0VB

ZW

06-1

54

D97

IN61

8

VA

C(V

)

Pin

(W)

Pou

t(W

)

85 0.90

110

0.93

220

1.14

265

1.57

0.55

Figure 34. Typical application circuit for inkjet printers (40W).

L5991 - L5991A

16/23

L599112

4 13

SGND

VREF ISEN

OPTIONALD97IN751A

10

RSENSERA

R

Figure 35. Standby thresholds adjustment.

D97IN761

L5991

PGND

ISEN

OUT

VC

SGND

VIN

ISOLATIONBOUNDARY

10

9

13

1112

Figure 36. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies.

L5991

VREF

T

VCC

VIN

20V

D97IN762B

2.2MΩ 33KΩ

SELF-SUPPLYWINDING

84

12 1147KΩ

STD1NB50-1

Figure 37. Low consumption start-up.

D97IN763

L5991PGND

ISEN

OUT

VC

VIN

9

10

13

11

8

VCC

Figure 38. Bipolar transistor driver.

L5991 - L5991A

17/23

D97IN507

+

-EA

Ri

+

1.3mA

RdR

2R

12

Cf Rf

6

5

From VO 2.5V

+

-EA

RP

+

1.3mA

RdR

2R

12

Cf Rf

6

5

From VO 2.5V

Error Amp compensation circuit for stabilizing any current-mode topology exceptfor boost and flyback converters operating with continuous inductor current.

CP

Ri

Error Amp compensation circuit for stabilizing current-mode boost and flybacktopologies operating with continuous inductor current.

VFB

VFB

COMP

COMP

SGND

SGND

Figure 39. Typical E/A compensation networks.

L5991

COMP

D97IN759

TL431

VOUT

VFB

6

5

Figure 40. Feedback with optocoupler.

L5991

OPTIONAL

D97IN760A

I

VREF

SGND

RA

CT

RCT

RSLOPE

RSENSE

ISEN

L5991

OPTIONAL

I

VREF

SGND

RA

CT

RCT

RSLOPE

RSENSE

ISEN

L5991

OPTIONAL

OUT

SGND

R

RSLOPE

RSENSE

ISEN

CSLOPE

4

2

1312

4

2

1312

1312

10

RB

16ST-BY 16

ST-BY

RB

Figure 41. Slope compensation techniques.

L5991 - L5991A

18/23

Figure 42. Protection against overvoltage/feedback disconnection (latched)

L5991

D97IN755A

DC

VCCVREF

RSTART

3

12

84

11

Figure 43 Protection against overvoltage/feed-back disconnection (not latched)

D97IN756A

PGND

L5991

OPTIONAL

VREF

SGND

DIS

ISEN

I

4

14

131211

RSENSE

R2

R1 Ipk

Ipk max ≅2.5

RSENSE

1-R2

R1

•

Figure 44. Device shutdown on overcurrent

D97IN757

PGND

L5991

OUT

SGND

ISEN

Lp

RFF

R

VIN

RFF = 6·106 R·Lp

RSENSE

RSENSE

13

10

1211

80 ÷ 400VDC

Figure 45. Constant power in pulse-by-pulse current limitation (flyback discontinuous)

L5991

DC

10K

COMP

3

612 13

SGND ISEN

D97IN758A

Figure 46. Voltage mode operation.

L5991

D98IN905

SGND

DIS

VCC

RSTART

PGND

8

14

12 11

VZ

2.2K

L5991

D97IN754

SGND

DIS

VCC

RSTART

PGND

8

14

12 11

L5991 - L5991A

19/23

L5991

4

312 11

VREF

SGND PGND10KΩR25.1

R1

4.7K

VIN

80÷400VDC

D97IN750B

Figure 47. Device shutdown on mains undervoltage.

L59911

12

SYNC

SGND

1KΩ5.1V

D97IN753A

Figure 48. Synchronization to flyback pulses (for monitors).

L5991 - L5991A

20/23

DIP16

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 0.050

OUTLINE ANDMECHANICAL DATA

L5991 - L5991A

21/23

SO16 Narrow

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.75 0.069

a1 0.1 0.25 0.004 0.009

a2 1.6 0.063

b 0.35 0.46 0.014 0.018

b1 0.19 0.25 0.007 0.010

C 0.5 0.020

c1 45 (typ.)

D (1) 9.8 10 0.386 0.394

E 5.8 6.2 0.228 0.244

e 1.27 0.050

e3 8.89 0.350

F (1) 3.8 4 0.150 0.157

G 4.6 5.3 0.181 0.209

L 0.4 1.27 0.016 0.050

M 0.62 0.024

S

(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).

OUTLINE ANDMECHANICAL DATA

8˚(max.)

L5991 - L5991A

22/23

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication aresubject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics productsare not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics© 2001 STMicroelectronics – Printed in Italy – All Rights Reserved

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L5991 - L5991A

23/23