PRESENTATIONON

Scaling Of MOS

Submitted by :Raviraj Kour

Contents Moore’s LawWhy Scaling?Types of ScalingShort channel EffectsNarrow Width EffectsQueries

Thapar University , PatialaTuesday, May 2, 2023 2

Thapar University , PatialaTuesday, May 2, 2023 3

Moore’s Law[1]

No. of transistors on a chip doubled every 18 to 24 months.Semiconductor technology will double its effectiveness every 18 months.

Fig. 1 : No. of transistors with years

Fig. 2 : End of Moore’s LawThapar University , PatialaTuesday, May 2, 2023 4

Fig. 3 : Technology Evolution (1997 data)

Thapar University , PatialaTuesday, May 2, 2023 5

Why Scaling?[2]

Thapar University , PatialaTuesday, May 2, 2023 6

Design of high density chips in MOS VLSI technology requires: High packing density of MOSFETS Small transistor size

This reduction of size is k/a Scaling.

S>1 has been introduced leading to reduction of area by a factor S².

Disadvantage : Electric fields within the Gate Oxide grow larger.

Statistics[3]

Thapar University , PatialaTuesday, May 2, 2023 7

Fig. 4 : Data showing no. of transistors on processors of Intel Corporation with Years

Let’s Start

Thapar University , PatialaTuesday, May 2, 2023 8

Fig. 5 : MOSFET Scaling by a factor S

Types of Scaling1. Constant field scaling or full scaling :

Magnitude of internal electric fields is kept constant. Only lateral dimensions are changed. Threshold voltage is also effected.

Thapar University , PatialaTuesday, May 2, 2023 9

Fig. 6: Full – Scaling of MOSFET

Consequences of Constant Field Scaling :

Thapar University , PatialaTuesday, May 2, 2023 10

Fig. 7 : Change in parameters due to full scaling

Most significant reduction : Power dissipation is reduced by a factor of S² as P´= P/S²

Power density remains unchanged.

Gate oxide capacitance is scaled down as Cg´ = Cg/S

Overall performance improvement.

Thapar University , PatialaTuesday, May 2, 2023 11

2. Constant Voltage Scaling : More preferred. All dimensions are scaled down except power supply and terminal voltages.

Fig. 8 : Parameters effected due to Constant Voltage ScalingThapar University , PatialaTuesday, May 2, 2023 12

Cons of Constant Voltage Scaling :

Increase in drain current density and power density by a factor of S³ adversely effecting device reliability.

Causes problems like : Electro Migration Hot Carrier Degradation Gate Oxide Breakdown Electrical Over-stress

Thapar University , PatialaTuesday, May 2, 2023 13

Thapar University , PatialaTuesday, May 2, 2023 14

When channel length Leff approx. equals source and junction depth xj.

Why Short Channel MOS , even if it has degraded performance ?

Threshold voltage is less. Why ?

Effects : Drain- Induced Barrier Lowering Surface Scattering Velocity Saturation Impact Ionization Hot Carrier Effect

Short Channel Effects[4]

Fig. 9: Simplified geometry of MOSFET channel region

Thapar University , PatialaTuesday, May 2, 2023 15

Potential barrier is controlled by both VGS and VDS.

If drain voltage increases , barrier in the channel decreases , leading to DIBL.

Allows electron flow between S and D even at VGS < VTO .

A. Drain- Induced Barrier Lowering (DIBL)[5]

Fig. 10 : As channel length decreases, the barrier φB to be surmounted by an electron, from the source on its way to the drain reduces.

Thapar University , PatialaTuesday, May 2, 2023 16

Thapar University , PatialaTuesday, May 2, 2023 17

B. Surface Scattering Due to SCE , electric field increases and mobility becomes field dependent. Surface scattering occurs. Average surface mobility decreases.

Fig. 11: Pictorial representation of Surface Scattering[6]

Thapar University , PatialaTuesday, May 2, 2023 18

C. Velocity Saturation

Velocity of charge carries Vs Electric Field.

Three regions.

Reduces current in Short Channel MOSFET.

Formula :

Fig. 14 : Drift Velocity Vs Electric Field

Thapar University , PatialaTuesday, May 2, 2023 19

Thapar University , PatialaTuesday, May 2, 2023 20

D. Impact Ionisation[7]

Due to high electric field which causes high velocity of electrons. Generates Electron - Hole pairs.

Fig. 15 : Impact Ionization

E. Hot Carrier Effects

When electrons or holes gain sufficiently large energies to overcome barrier and get trapped in oxide layer.

Permanently changes MOSFET switching characteristics. Adversely effects reliability.

Thapar University , PatialaTuesday, May 2, 2023 21

Fig. 16 : Hot Electron Currents

Narrow Channel Effects[8]

MOS having channel widths (W) approx. equals depletion region thickness (xdm) is known as Narrow – Channel MOS.

Here , Vto (narrow channel) = Vto + ΔVto (most significant)

Overlapping of Gate Oxide and FOX.

Thapar University , PatialaTuesday, May 2, 2023 22

Thapar University , PatialaTuesday, May 2, 2023 23

Fig. 17 : Cross – sectional view of a narrow channel MOSFET

Thapar University , PatialaTuesday, May 2, 2023 24

Tuesday, May 2, 2023 Thapar University , Patiala 25

References[1] lect15-scaling.ppt[2] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , pg. no. 115 , TATA MCGRAW – HILL EDITION[3] www.intel.com/research/silicon/mooreslaw.htm[4] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , pg. no. 119 , TATA MCGRAW – HILL EDITION[5] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , pg. no. 127 , TATA MCGRAW – HILL EDITION[6] EE327 Lec 30a - Surface scattering[7] Introduction to VLSI design (EECS 467) Project Short-Channel Effects in MOSFETs December 11th, 2000 Fabio D’Agostino Daniele Quercia pdf , pg. no. 3.[8] Cmos Digital Integrated Circuits - Sung-Mo Kang and Yusuf Leblebici.pdf , page no. 125 , TATA MCGRAW – HILL EDITION