power electronic packaging, co -design and reliability · power electronic packaging, co -design...

10
www.onsemi.com 2018 IEEE 68th Electronic Components and Technology Conference San Diego, California May 29 – June 1, 2018 Power Electronic Packaging, Co-Design and Reliability Yong Liu, Corporate R & D May 29, 2018

Upload: others

Post on 24-Oct-2020

3 views

Category:

Documents


0 download

TRANSCRIPT

  • www.onsemi.com

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

    Power Electronic Packaging, Co-Design and Reliability

    Yong Liu, Corporate R & DMay 29, 2018

  • 2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

    Outline

    I. Power Electronics Packaging II. Current State of Art Co-Design in Power

    Electronics Packaging III. Challenges in Co-Design and ReliabilityIV. What is the Next?V. Summary

  • I. Power Electronic Packaging: Driven Capability

    Central PV*

    String PV*

    pile

    GaN

    SiC

    SiliconRemains Mainstream Technology

    10M

    1M

    100k

    10k

    1k

    1k 10k 100k 1M 10M

    * PV = photovolta ic inverter; ** OB C = onboard charger

    fsw [Hz]

    Pout [W]

    SJ

    OBC**

    Silicon : 12V – 1700V-Best FOM, Packaging Options

    Superjunction: 650V – 900V-Optimized HV solution

    SiC: 900V – above 1700 V-High power density performance

    GaN: 650V- High frequency performance

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

  • 4

    I. Power Electronic Packaging: GaN & SiC Applications

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

  • I. Power Electronic Packaging: Evolution

    10

    1001k

    10k100k

    1M

    100

    1 k

    10k

    100k

    1M

    10M

    10M

    Operation Frequency (Hz)

    SCRModule

    Triac

    GTO

    TransistorModule

    IGBTModule

    MOSFETModule

    IGBTModule

    IPMMOSFET

    • Air Conditioner• Refrigerator• Washing Machine

    • UPS• Welder

    • Inverter• Motor Control

    • Automotive

    • TV (Display)

    Cap

    acity

    (VA

    )

    Pkg Transition (Discrete to Intelligent Package)

    Discrete Package Intelligent Power Module

    Courtesy ofFormer FairchildCTO Dan Kinzer

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

  • I. Power Electronic Packaging: Core Technology

    L

    Microchannel DBC

    S o u r c e :

    O R T H O D Y N E

    LF DBC/DBA/IMS Double DBC/spacer

    Al wire bonding Ribbon Bonding Clip /LF bondingEmbedded die bonding

    Soldering Ag/Cu sintering

    US welding

    Substrate less

    Vacuum soldering

    Gel EMC Potting Epoxy MUF

    Interconnect

    Substrate

    Die Attach

    Encapsulation

    Ag attach

    Infineon

    UC Irving

    M itsub ish i

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

  • II. Current State of Art Co-Design in Power Electronic Packaging• To Provide Differentiating & Cost Effective Co-design Infrastructure for Power Electronics

    • Current Co-Design Platform Includes:

    Explore/Design + Simulation + Design Verification + Methodology + Development/Share

    Simulation Tools DesignMethodology

    Design PlatformDesign

    VerificationDevelopment/Share

    Weakness: Case by CaseNot strong in design sensitivity, optimization and probabilityNot Yet Ready for virtual prototyping

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

  • III. Challenges in Co-Design and Reliability

    Multi-Scale and Multi-Physics in Co-Design/Reliability:Reliability from Die design to system

    Assembly Reliability:Multi-Step Process/Variation/Probability

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

  • 9

    IV. What is the next: Co-Design Ecosystem for a Efficient Virtual Prototype

    The system will target:

    • Multi-scale and Multi-physics in Design• Sensitivity/Optimization/Probabilistic Analysis

    in Design, Assembly Process and Reliability

    Co-design ecosystem

    Various design and simulation

    software for co-design

    Co-design vault and

    environment

    Mat Lab for various mat

    properties test

    Test Lab for e lectrical,

    therm al and m echanical

    perform ance

    Current Co-Design

    Platform

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018

  • V. Summary Virtual Prototyping• Current state of art Co-Design includes Explore/Design +

    Simulation + Design Verification + Methodology + Development/Sharing

    • Key Challenges in Co-Design/Reliability include Multi-Scale and Multi-Physics, Multi-Step Process/Variation Probability

    • Co-Design Ecosystem & Virtual Prototyping will happen soon in Power Electronics Industry

    2018 IEEE 68th Electronic Components and Technology Conference │ San Diego, California │ May 29 – June 1, 2018