power-driven flip-floppgg merging and relocationispd.cc/slides/2011/6.1_wang.pdf · related work...
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Power-Driven Flip-Flop Merging p p g gand Relocation
Shao-Huan WangYu-Yi Liang
Tien-Yu KuoWai-Kei Mak
@National Tsing Hua University
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OutlineOutline Introduction
P bl F l ti Problem Formulation Algorithms Experimental Results Experimental Results Conclusions
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OutlineOutline Introduction
P bl F l ti Problem Formulation Algorithms Experimental Results Experimental Results Conclusions
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Flip-Flop MergingFlip Flop Merging Merge several 1-bit Flip-Flops into a Multi-
bit Flip Flop (MBFF)bit Flip-Flop (MBFF) Eliminate some inverters and area Reduce the # clock sinks
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Flip-Flop MergingFlip Flop Merging
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Reduction of clock sinksReduction of clock sinks
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Related WorkRelated Work [15] Post-placement power optimization
with multi bit flip flops ICCAD’10with multi-bit flip-flops, ICCAD 10 The objective of [15] is to minimize the
total FF Power However, our objective function is to
minimize the # clock sinks and switching power of signal netspower of signal nets
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Wirelength of Signal NetsWirelength of Signal Nets Different merging solutions will affect the
wirelength and switching power of signal wirelength and switching power of signal nets differently
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Post-Placement RelocationPost Placement Relocation After merging, we need to relocate these
MBFFsMBFFs It will affect the total switching power of
signal nets
0.3 0.1 0.3 0.1
0.3 0.1 0.3 0.1
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OutlineOutline Introduction
P bl F l ti Problem Formulation Algorithms Experimental Results Experimental Results Conclusions
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Problem FormulationProblem Formulation Inputs
A l d d i d MBFF Lib A preplaced design and a MBFF Library Objectives
Minimize the # sinks in clock network Minimize the # sinks in clock network Minimize the switching power of signal nets
α is the switching rate of signal netsαi is the switching rate of signal nets
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ConstraintsConstraints Guarantee there is no timing violation
Feasible region of FFs Feasible region of FFs Control the placement density
Maintain the quality of legalization Maintain the quality of legalization Consider routing congestion
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Feasible Region of a FFFeasible Region of a FF
Slack = Maximum allowed delay - DABSlackA = SlackB = Slack / 2
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Feasible Region of a FF (cont )Feasible Region of a FF (cont.)
KP Q
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OutlineOutline Introduction
P bl F l ti Problem Formulation Algorithms Experimental Results Experimental Results Conclusions
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Intersection GraphIntersection Graph Get the feasible regions of all FFs
Th i t ti f f ibl i b The intersection of feasible regions can be represented by an intersection graph
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Design FlowDesign Flow
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Find all the Maximal CliquesFind all the Maximal Cliques Finding all the maximal cliques is NPC in
general graphgeneral graph However, it can be solved in polynomial
time in the rectangle intersection graph Solve by the sweep line algorithm
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MBFF ExtractionMBFF Extraction We want to extract the MBFFs by clique
partitioningpartitioning Clique partitioning is a NP-Hard problem
Different extraction strategies will affectg The number of clock sinks The wirelength of signal nets
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MBFF Extraction (cont.)MBFF Extraction (cont.) Cost of creating MBFF β
D(β ): the merging possibility of FFs in β D(β ): the merging possibility of FFs in β B(β ): the # bits of β Switching power of signal nets connected g p g
to β
αi is the switching rate of signal netsi g g
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Example of Extraction AlgorithmExample of Extraction Algorithm Assume we have 1/2/4-bit MBFF in library There are two maximal cliques
c1 = {1,2,3,6,7}, c2 = {4,5,6} Random sampling 1, 2 or 4 of FFs from c1, c2
β1 = {1,2,3,6}, β2 = {4,6} cost(β ) < cost(β ) => select β cost(β1) < cost(β2) => select β1
Re-sampling β1’ = {7} from c1 cost(β2) < cost(β1’)
FF6 already covered FF6 already covered Re-sampling β2’ = {4, 5} from c2
Final Extraction {β1, β2’, β1’}
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MBFF RelocationMBFF Relocation For a MBFF β, we want to minimize the
switching power of its signal netsswitching power of its signal nets
αi is the switching rate of signal nets We can formulate it as a weighted
di blmedian problem
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MBFF Relocation (cont.)MBFF Relocation (cont.)
The weight of P1~P5 are 2:1:1:3:1The weight of P1~P5 are 2:1:1:3:1
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MBFF Relocation (cont.)MBFF Relocation (cont.) Because of bin density constraints, some
MBFFs cannot be placed in preferred regionMBFFs cannot be placed in preferred region
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OutlineOutline Introduction
P bl F l ti Problem Formulation Algorithms Experimental Results Experimental Results Conclusions
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Experimental SetupExperimental Setup Implemented in C++
W k Li ith 2 13GH CPU Work on Linux with 2.13GHz CPU We have 9 test cases
r1~r5 from [22] Exact Zero-Skew r1 r5 from [22] Exact Zero Skew t0~t3 from 2010 CAD contest of Taiwan Random generate switching rates 5%~15%
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Experimental ResultsExperimental Results Reduction of clock sinks and wirelength of
clock treeclock tree
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Experimental Results (cont.)Experimental Results (cont.) Reduction of wirelength and estimated
switching power of nets connected to FFsswitching power of nets connected to FFs
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Comparison with [15]Comparison with [15] Our algorithm can be modified to target
the objectives of [15]the objectives of [15]
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ConclusionsConclusions We present a power-driven flip-flop
merging and relocation approach to merging and relocation approach to reduce the switching power consumption of the entire circuit
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Q&AQ&A Thanks for your attention