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TRANSCRIPT
Power Considerations inHigh PerformanceFPGAs
Abu Eghan,Principal EngineerXilinx Inc.
2Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Agenda
• Introduction– Trends and opportunities– The programmable factor
• 4 focus areas for power consideration– Silicon design & Fabrication– Programmability & flexibility in implementation with Software– The Package choices– The end-user contribution
• Thermal Management – Enabling tools
• Summary
3Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Trends & Opportunities in FPGA
• Process shrinks & Increased level of integration:– Allows:
• More traditional Programmable logic Arrays• Embedded Blocks – 450Mhz PowerPC, SERDES – Multigigabit
Transceivers• BRAMs, DCM, Xtreme DSP, Ethernet MAC
– Impact – general and may not be unique to FPGA• Increased leakage current and static power• Heat flux (watts/cm2) trend is up.
• Higher clock speeds capability– The increased frequency imply high performance & higher dynamic
power• Challenges Shared with Industry
– Reliability limitation & lower operating temperatures– Performance & Cost Trade-offs– Lower thermal budgets
4Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
• Programmability & Uniqueness Factor:– More programmable transistors to deal with– The challenge to Packaging
• Flexibility means power needs are largely unknown• There is no single tailored thermal solution – for all applications
– The upside• Die size is relatively large – power density is not at the edge• More “standby” or “passive” transistors – reduced power density• Menu of packages offered - with broad heat handling capability,• Closer OEM collaboration, to get real world feedback• Opportunity to deal with power beyond packages – into silicon, software etc.
FPGA Attributes
5Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Power Considerations
• Critical for equipment with high Tj andlittle or no cooling– Wired/wireless equipment - outdoor– Modular racks in storage/servers– Automotive – Telematics & entertainment– Mil/Aero – battle tanks, fighter planes, etc
• Ideal & common requirement– Bigger, faster, cheaper!– Reduce the need for heatsinks or at least
the cost of thermal solution– Lower power supply overhead &
complexitySmaller Power SuppliesSmaller Power SuppliesSmaller Power Supplies
Reduced Need for Heat SinksReduced Need for Heat SinksReduced Need for Heat Sinks
6Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
The 4 Prong Approach
• The 4 focus areas– Silicon design & Fabrication– Software implementation of design
–Programmability, flexibility & choices– The Packages – FCBGA consistent TIM– The end-user contribution
• Thermal Management – Enabling tools
7Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Considerations - 1
The Silicon:Design & Implementation contribution to Heat
generation
8Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
FPGA-101: FPGA Terms
• Logic Blocks – used toimplement a wide range ofarbitrary digital functions.
• Programmable I/O Blocks• Routing resources• Switch matrix and
interconnects/pass gates
• Key FPGA attribute – regardless of what heterogeneous functions and elements areincorporated - is the ability to implement arbitrary digital logic circuit.
9Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
The 3 common PowerComponents
1. Transient Inrush current2. Static3. Dynamic
Time
Power Static
Dynamic
Inrush
TOTAL
10Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Addressing The 1st PowerComponents
1. Transient Inrush current2. Static3. Dynamic
Time
Power Static
Dynamic
Inrush
TOTAL
11Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Transient - Inrush Current
• While Vcc rises from 0 V to nominal voltage– Internal circuits can go through states of confusion– Configuration storage latches can wake up at random states
• Without proper handling of this wake phase, this confusion maylead to internal contention– In older generation FPGAs the inrush current spike (multiple amps) were
sources of concern prior to the elimination by sequential “house-cleaning”• Inrush current is almost eliminated in Xilinx devices through
innovative configuration features & protocols• Impact on Power:
– This was more of a power supply issue than a sustained heat managementissue due to its transient nature and the associated large heat capacity of thelarge chips where this phenomena can be significant.
12Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
The 2nd Power Components
1. Transient Inrush current2. Static3. Dynamic
Time
Power Static
Dynamic
Inrush
TOTAL
13Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Static Power IncreasesDramatically with Temperature
ICCINTQ vs Junction Temperature
Junction Temp Junction Temp °°CC
Nor
mal
ized
Lea
kage
Nor
mal
ized
Lea
kage
Cur
rent
Cur
rent
0 20 40 60 80 100 120 140-20-40
25 °C25 25 °°CC
85 °C85 85 °°CC
100 °C100 100 °°CC
ICCINTQ
source drain
gate
IIGATEGATE
IISS→→DD
1
2
3
4
5
6
0
7
14Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Xilinx 90nm Triple-OxideTechnology
• Leakage current increases as channellength and gate oxide thicknessdecrease
• Same oxide thickness is not needed inall the transistors
• Two oxide thicknesses are commonlyused in the industry– Thin oxide in the fast core logic– Thick oxide in the versatile I/O
• 90nm implementation adds a thirdmedium thickness oxide to selectedstructures to reduce leakage currentwithout compromising performance
Channel
Gate
Source Drain
Source
Metal
Connection
Drain
Metal
Connection
Gate Oxide – varyingthicknesses on die
15Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Optimal transistor mix forminimizing leakage and maximizing performance
Optimal transistor mix forOptimal transistor mix forminimizing leakage and maximizing performanceminimizing leakage and maximizing performance
OptimizingPerformance and Leakage
ThresholdVoltage (VT)
OxideThickness
TransistorSize
• High speed and lowpower:– Low VT transistors
used only wherenecessary for speed
– Choose differentoxide thicknesses
– Select transistor sizefor performance andfunction
LUTs, I/O, Interconnect,Configuration Memory Cells
LUTs, I/O, Interconnect,LUTs, I/O, Interconnect,Configuration Memory CellsConfiguration Memory Cells
16Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Reducing Leakage Current
Medium/HighVery FastShortLowThinLogic & Interconnect
LowFastShortLow/MediumMediumInterconnect Pass Gates
LowSlowLongMediumMediumConfiguration Memory
LowestFastLongestHighThickI/O
LeakageSpeedChannel LengthThreshold Voltage (VT)Oxide ThicknessFunction
• Careful management of various process parameters– Enables low leakage current; hence, low static power without a negative impact
on performance• Triple-oxide technology, threshold voltage, channel lengths are tuned• Triple-oxide technology yields biggest gains
17Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Logic CellsLogic Cells25K 50K 75K 100K 125K 150K 175K 200K0
Rel
ativ
e St
atic
Pow
erR
elat
ive
Stat
ic P
ower
(Wor
st C
ase
proc
ess
& 8
5 (W
orst
Cas
e pr
oces
s &
85
ºº C)
C)
50 % Lower Power
90nm has 50% lower static power than equivalent 130nm90nm has 50% lower static power than equivalent 130nm90nm has 50% lower static power than equivalent 130nm
1
2
3
4
0
Multi-oxide Technology ReducesStatic Power
130nm Trend
90nm FPGA Trend
5
6
18Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Xilinx 90nm FPGA Power
• 1 to 5 Watts lower power per FPGA– 50% reduction in 90nm static and dynamic power vs
130nm devices at the 100K Gate• Enabled through multi-oxide technologies
– 90nm triple-oxide technology deployment– High-performance embedded IP
• Design choices made to meet power budgetwithout compromising FPGA performance
19Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Addressing The 3rd PowerComponents
1. Transient Inrush current2. Static3. Dynamic
Time
Power Static
Dynamic
Inrush
TOTAL
20Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Dynamic Power• Dynamic Power
– P = kCV2fwherek = Nodes switchingC = Capacitance per nodeV = Voltage switchingf = switching frequency or toggle rate
• Reduced Core dynamic power– Internal operating voltage is the dominant
factor– Secondary scaling by frequency
and node capacitance– Even at 50% higher operating frequency,
the 90nm implementation reducesdynamic power by 20%
• Constant I/O dynamic power– Similar capacitance, voltage and
frequency to support industry I/Ostandards
130nm130nm
FPGA Core Dynamic Power TrendFPGA Core Dynamic Power Trend
20
100
80
60
40
0
Relative Capacitance or VoltageRelative Capacitance or Voltage
Rel
ativ
e C
ore
Pow
er %
Rel
ativ
e C
ore
Pow
er % 90nm90nm
Voltage dropsVoltage drops
Node Capacitancedrops
Node Capacitancedrops
100 80 60 40 20 0
21Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Process Shrink ReducesDynamic Power
1.5+50%1.51.0fmax (rel.)
0.77-23%1.732.25Power @ Max f(k*CV2f)
0.510.51-49%1.152.25Power @ samefrequency
0.80-20%0.81.0Ctot (rel.)
0.64-20%1.21.5Vccint
PowerPowerRatioRatio% Change% Change90 nm90 nm130 nm130 nm
E.g., Virtex-4 (90nm) has 50% lower dynamic power thanVirtex-II Pro (130nm)
E.g., Virtex-4 (90nm) has 50% lower dynamic power thanE.g., Virtex-4 (90nm) has 50% lower dynamic power thanVirtex-II Pro (130nm)Virtex-II Pro (130nm)
22Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Low Power by Design – Hard IP500 MHz Logic Array
1 Gbps diff I/Owith ChipSync™
500 MHzDifferentialClocking
500 MHzBRAM and FIFO
500 MHzXtremeDSP
Slice
450 MHz PowerPC™with APU
10/100/1000Ethernet MAC
23Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Why Hard-IPs• Reduced Static Power
– No extra transistors as in programmable logic– No programmable interconnect transistors
• Reduced Dynamic Power– Metal Interconnects vs. Metal and programmable
interconnects– Reduced trace lengths– No extra node capacitance because of lack of pass
transistors– Minimized layers of logic
24Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Considerations - 2
ISE Contribution to Total Thermal managementPlacement Implementation
25Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Optimizations for Power• Designs may be placed with Optimizations
– Optimized For performance– Optimized for lower power
• Feature selection, including power conservation features,impacts power
• Dynamic Power varies linearly with frequency– Implement non-critical functions to run on a low speed clock
rather than an arbitrary high speed clock in the design• “Your actual mileage will depend on the course you take
and your driving habits”
26Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Power Reduction TechniquesThrough Switching Nodes and Capacitance Reduction
• Reducing number of nodes switching into a capacitive load– Minimize Logic Levels through better logic packing (ex. Use a
packed Relationally Placed Macro - RPM)– Increase design speed target for routing purpose to minimize
interconnect length and reduce interconnect capacitance– Use an RPM or other placement method to guide tighter
placement and help reduce routing length, especially onrepeated macros
– Bump up performance target for XST router• May be able to gain 5-10 % power improvement• lower capacitance by minimizing path length and interconnect hops
27Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Dynamic Power Reduction TechniquesThrough Embedded Functions
• Significant reduction when implementing embedded functions– OSERDES, ISERDES, FIFOs, DSP48, PPC, EMAC
• 5 – 12x Reduction on power over FPGA fabric and FPGA programmableinterconnects
– Interconnect length is reduced and interconnect transistors eliminated• Not dependent on programmable paths or non-optimized placement• Direct metal connection reduce lumped node capacitance
– Logic is reduced• Minimal logic layers are present and minimal logic size
– Significant fewer transistor being switched– Able to use a smaller Virtex-4 FPGA due to logic saving
• Reduce both static power and dynamic power with Embedded functions
28Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Considerations - 3
The Package implementationContribution to Thermal Management
29Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Xilinx Package Features thatEnhance Thermal Performance
• Built on the heat efficient Flipchip BGA (FCBGA)offerings
• Enhance thermal performance beyond standardFCBGA packages
– Enable very low θJC through the top• Void free, thin and low resistance thermal Interface
material (TIM) consistently applied to ensure lowerθJC from the back of the die
– Deliver a low resistance platform for heat sinkapplications
– Offer up to 20% lower θJB compared to pastgeneration product ( see next slide)
• Enhanced power and ground plane arrangementthrough Xilinx unique SparseChevron technology
• Improved electrical return path boosts copperdensity and overall thermal conductivity throughthe package
• Increase vertical thermal conductivity through adenser and distributed via field
Silicon
VCCINT
VCCAUX
GND
VCCO
GND
GND
SIO
VCCO
VCCINT
GND
CORE (600 um)
30Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Vcco
GND
VccintVccaux
I/O
FPGA SparseChevron™ Pinnout
•• New IO/Vcco/GNDNew IO/Vcco/GNDpatternpattern
–– Better IO toBetter IO toGND/Vcco pairGND/Vcco pairratioratio
–– Every SelectIOEvery SelectIOadjacentadjacentto Vcco & GNDto Vcco & GND
FF1513 Pin-out FF1513 Pin-out
•• Thermal PerformanceThermal PerformanceImpactImpact
•• Increased via densityIncreased via density•• 18-20% improvement18-20% improvement
in Theta-JBin Theta-JB
31Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Considerations - 4
The Programmability ChallengeSupporting the End-user in their system Thermal
management using FPGAs.
32Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Managing System Level Heat• FPGA dilemma:
– Application environment is unknown. Some guesses are possible– When thermal margins are low the – Ja, Jc (figure of merit) thermal data
is inadequate.• Addressing the unknown
– Efficient packages - inherently low Theta-JC & Theta-JB– Predetermine some known environments
• Natural Air• Heatsinks with Forced air – fans (1 rack, 2 rack unit H/S)• Box/Container design, Board as a heatsink, Conducting plates
– Application specific thermal design - OEM contribution– Thermal Implementation Enablers:
• Xpower – Power estimations• BCI-CTM library for these product
33Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Post-ImplementationPower Analysis
• XPower™ in ISE® software– Integration in Design Flow– Considers device data, along with the
user's design files– Report estimated device power
consumption at high level of accuracycustomized to specific design
• Enables FPGA designers to performdetailed power analysis
• Tool extracts utilization from ISE andtoggle rates from test vectors andsimulation
• Output– Use the GUI or detailed report to see
what is consuming the power– FPGA nets can be highlighted in
XPower and shown in FPGA Editor
34Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
CTM for Thermal Budget Planning• Accurate temperature prediction of IC components at the system level
has become critical due to the shrinking thermal budget• Xilinx provide Compact Thermal Models (CTMs) for system thermal
budget planning– These behavioral models predict package temperature at the selected nodes
(e.g., junction, case, and balls) – when integrated with other ICs.– CTM libraries are Downloadable (pdml and taz format) on Xilinx.com for usage in
conjunction with customers’ thermal simulation tools.
Two model types offered by Xilinx
35Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Summary• Process shrinks & Increased level of integration offer some
challenges for FPGA at leading edge CMOS technologies.• Improvements in system and device reliability through significant
power reduction and package enhancements are still possible.• The following are some of the specific activities making those
incremental improvements possible– Static power reduced by >40% through innovative choices in process and
circuit design– Dynamic power reduced by 50% at a given frequency – general voltage
reduction– Use of Embedded functions reduce power by a factor of 5x to 10x– Enhanced package thermal performance through Xilinx unique via field
arrangement - SparseChevron technology applied to FCBGA– Lowered θJC and θJB to further reduce thermal concerns– Comprehensive software tools for placement and power optimization.– Thermal model libraries support for system design, power estimation and
system thermal analysis
36Feb 2006 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc.
Thanks for your attention
Acknowledgements:
Matt Klein, Xilinx Inc. for his inputs & contribution