power architecture microcontroller

8/13/2019 Power Architecture Microcontroller

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MPC5604P Microcontroller Reference Manual, Rev. 3

Freescale Semiconductor 1

MPC5604P MicrocontrollerReference Manual

Devices Supported:MPC5602PMPC5603P

MPC5604P

MPC560XPRMRev. 3

12 Feb 2010


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2 Freescale Semiconductor


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Chapter 1Overview

1.1 Chipset overview .............................................................................................................................471.2 Target applications ..........................................................................................................................48

1.2.1 Application examples .......................................................................................................481.2.1.1 Electric power steering ...................................................................................48

1.2.1.2 Airbag .............................................................................................................491.3 Features ...........................................................................................................................................491.4 Block diagram .................................................................................................................................511.5 Critical performance parameters .....................................................................................................521.6 Chip-level features ..........................................................................................................................521.7 Module features ...............................................................................................................................54

1.7.1 High performance e200z0 core processor .........................................................................541.7.2 Crossbar switch (XBAR) ..................................................................................................541.7.3 Enhanced Direct Memory Access (eDMA) ......................................................................551.7.4 On-chip flash memory with ECC .....................................................................................551.7.5 On-chip SRAM with ECC ................................................................................................561.7.6 Interrupt Controller (INTC) ..............................................................................................561.7.7 System clocks and clock generation .................................................................................571.7.8 Frequency modulated PLL (FMPLL) ...............................................................................571.7.9 Main oscillator ..................................................................................................................581.7.10 Internal RC oscillator ........................................................................................................581.7.11 Periodic Interrupt Timer Module (PIT) ............................................................................581.7.12 System Timer Module .......................................................................................................581.7.13 Software Watchdog Timer ................................................................................................591.7.14 Fault Collection Unit ........................................................................................................591.7.15 System Integration Unit (SIU-Lite) ..................................................................................591.7.16 Boot and censorship ..........................................................................................................60

1.7.16.1 Boot Assist Module (BAM) ............................................................................601.7.17 Error Correction Status Module (ECSM) .........................................................................601.7.18 CAN (FlexCAN) ...............................................................................................................601.7.19 Safety port (FlexCAN) ......................................................................................................611.7.20 FlexRay .............................................................................................................................611.7.21 Serial communication interface module (LINFlex) ..........................................................621.7.22 Deserial serial peripheral interface (DSPI) module ..........................................................631.7.23 FlexPWM .........................................................................................................................631.7.24 eTimer ...............................................................................................................................641.7.25 Analog to digital converter module ..................................................................................64

1.7.26 Cross Triggering Unit (CTU) ............................................................................................661.7.27 Junction temperature sensor ..............................................................................................661.7.28 Nexus Development Interface (NDI) ................................................................................661.7.29 IEEE 1149.1 JTAG controller ...........................................................................................671.7.30 On-chip Voltage Regulator (VREG) .................................................................................67

1.8 Developer environment ...................................................................................................................681.9 Package ............................................................................................................................................68


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1.10 MPC5604P memory map ................................................................................................................69

Chapter 2Signal Description

2.1 144-pin LQFP pinout ......................................................................................................................732.2 100-pin LQFP pinout ......................................................................................................................74

2.3 External signals ...............................................................................................................................762.3.1 Power supply and reference voltage pins .........................................................................762.3.2 Pin multiplexing ................................................................................................................78

2.4 CTU / ADCs / FlexPWM / eTimers connections ............................................................................91

Chapter 3Clock Description

3.1 Clock architecture ...........................................................................................................................953.2 Clock Generation Module (CGM) ..................................................................................................99

3.2.1 Introduction .......................................................................................................................993.2.2 Features ...........................................................................................................................100

3.2.3 Modes of operation .........................................................................................................1003.2.3.1 Normal and Reset Modes of Operation ........................................................100

3.2.4 External signal description ..............................................................................................1003.2.5 Memory map and registers description ...........................................................................1003.2.6 Register descriptions .......................................................................................................104

3.2.6.1 Output Clock Enable register (CGM_OC_EN) ............................................1053.2.6.2 Output Clock Division Select register (CGM_OCDS_SC) ..........................1053.2.6.3 System Clock Select Status register (CGM_SC_SS) ....................................1063.2.6.4 Auxiliary Clock 0 Select Control register (CGM_AC0_SC) .......................1073.2.6.5 Auxiliary Clock 0 Divider Configuration register (CGM_AC0_DC0) ........1083.2.6.6 Auxiliary Clock 1 Select Control register (CGM_AC1_SC) .......................1083.2.6.7 Auxiliary Clock 1 Divider Configuration register (CGM_AC1_DC0) ........1093.2.6.8 Auxiliary Clock 2 Select Control register (CGM_AC2_SC) .......................1103.2.6.9 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) .......1103.2.6.10 Auxiliary Clock 3 Select Control register (CGM_AC3_SC) ....................... 1113.2.6.11 Auxiliary Clock 3 Divider Configuration register (CGM_AC3_DC0) ........112

3.3 Functional description ...................................................................................................................1133.3.1 System clock generation .................................................................................................113

3.3.1.1 System clock source selection ......................................................................1133.3.1.2 System clock disable .....................................................................................113

3.3.2 Auxiliary clock generation ..............................................................................................1143.3.2.1 Auxiliary clock source selection ...................................................................1163.3.2.2 Dividers functional description .....................................................................116

3.3.3 Output clock multiplexing ..............................................................................................1163.3.4 Output clock division selection .......................................................................................117

3.4 Available clock domains ...............................................................................................................1183.4.1 FMPLL_ninput reference clock .....................................................................................1183.4.2 Clock selectors ................................................................................................................118


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3.4.2.1 System clock selector 0 for SYS_CLK .........................................................1183.4.2.2 Auxiliary clock selector 0 for MC_PLL_CLK divider (Motor Control clock) ..1183.4.2.3 Auxiliary clock selector 1 for CMU_PLL divider (CMU_1 clock) .............1183.4.2.4 Auxiliary clock selector 2 for SP_PLL divider (Safety Port clock) .............1193.4.2.5 Auxiliary Clock Selector 3 for FR_PLL divider (FlexRAY clock) ..............119

3.4.3 Auxiliary clock dividers ..................................................................................................1193.4.4 External clock divider .....................................................................................................120

3.5 Alternate module clock domains ...................................................................................................1203.5.1 FlexCAN clock domains .................................................................................................1203.5.2 FlexRay clock domains ...................................................................................................1203.5.3 SWT clock domains ........................................................................................................1203.5.4 Nexus Message Clock (MCKO) .....................................................................................1213.5.5 Cross Triggering Unit (CTU) clock domains .................................................................1213.5.6 IPS bus clock sync bridge ...............................................................................................1213.5.7 Peripherals behind the IPS bus clock sync bridge ..........................................................121

3.5.7.1 FlexPWM clock domain ...............................................................................121

3.5.7.2 eTimer_0 clock domain ................................................................................1213.5.7.3 eTimer_1 clock domain ................................................................................1213.5.7.4 ADC_0 clock domain ...................................................................................1213.5.7.5 ADC_1 clock domain ...................................................................................1223.5.7.6 Safety Port clock domains ............................................................................122

3.6 Clock behavior in STOP and HALT mode ....................................................................................1223.7 Software controlled power management/clock gating ..................................................................1223.8 System clock functional safety ......................................................................................................1233.9 IRC 16 MHz internal RC oscillator (RC_CTL) ............................................................................1233.10 XOSC external crystal oscillator ...................................................................................................124

3.10.1 Functional description .....................................................................................................1243.10.2 Register description ........................................................................................................125

3.11 Frequency Modulated Phase Locked Loop (FMPLL) ..................................................................1263.11.1 Introduction .....................................................................................................................1263.11.2 Overview .........................................................................................................................1263.11.3 Features ...........................................................................................................................1273.11.4 Memory map ...................................................................................................................1273.11.5 Register description ........................................................................................................128

3.11.5.1 Control Register (CR) ...................................................................................1283.11.5.2 Modulation Register (MR) ............................................................................130

3.11.6 Functional description .....................................................................................................1313.11.6.1 Normal mode ................................................................................................1313.11.6.2 Progressive clock switching ..........................................................................1313.11.6.3 Normal Mode with frequency modulation ....................................................1323.11.6.4 Powerdown mode .........................................................................................134

3.11.7 Recommendations ...........................................................................................................1343.12 Clock Monitor Unit (CMU) ..........................................................................................................134

3.12.1 Overview .........................................................................................................................134


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3.12.2 Main features ..................................................................................................................1353.12.3 Functional description .....................................................................................................135

3.12.3.1 Crystal clock monitor ....................................................................................1363.12.3.2 PLL clock monitor ........................................................................................1363.12.3.3 Frequency meter ...........................................................................................136

3.12.4 Memory map and register description ............................................................................137

3.12.4.1 Control Status Register (CMU_0_CSR) .......................................................1383.12.4.2 Frequency Display Register (CMU_0_FDR) ...............................................1383.12.4.3 High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A) ....1393.12.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) .....1393.12.4.5 Interrupt Status Register (CMU_0_ISR) ......................................................1403.12.4.6 Measurement Duration Register (CMU_0_MDR) .......................................1413.12.4.7 Control Status Register (CMU_1_CSR) .......................................................1413.12.4.8 High Frequency Reference Register FMPLL_1 (CMU_1_HFREFR_A) ....1423.12.4.9 Low Frequency Reference Register FMPLL_1 (CMU_1_LFREFR_A) .....1423.12.4.10Interrupt Status Register (CMU_1_ISR) ......................................................143

Chapter 4Operating Modes

4.1 Mode Entry Module (ME) .............................................................................................................1454.1.1 Overview .........................................................................................................................1454.1.2 Features ...........................................................................................................................1454.1.3 Modes of Operation ........................................................................................................146

4.1.3.1 Modes Overview ...........................................................................................1464.2 External signal description ............................................................................................................1474.3 Memory map and registers description .........................................................................................147

4.3.1 Register summary ...........................................................................................................1474.3.2 Memory Map ..................................................................................................................1504.3.3 Registers description .......................................................................................................155

4.3.3.1 Global Status register (ME_GS) ...................................................................1554.3.3.2 Mode Control register (ME_MCTL) ............................................................1574.3.3.3 Mode Enable register (ME_ME) ..................................................................1584.3.3.4 Interrupt Status register (ME_IS) ..................................................................1594.3.3.5 Interrupt Mask register (ME_IM) .................................................................1604.3.3.6 Invalid Mode Transition Status register (ME_IMTS) ...................................1614.3.3.7 Debug Mode Transition Status register (ME_DMTS) ..................................1624.3.3.8 RESET Mode Configuration register (ME_RESET_MC) ...........................1654.3.3.9 TEST Mode Configuration register (ME_TEST_MC) .................................1654.3.3.10 SAFE Mode Configuration register (ME_SAFE_MC) ................................1664.3.3.11 DRUN Mode Configuration register (ME_DRUN_MC) .............................1664.3.3.12 RUN03 Mode Configuration registers (ME_RUN03_MC) .................1674.3.3.13 HALT0 Mode Configuration register (ME_HALT0_MC) ...........................1684.3.3.14 STOP0 Mode Configuration register (ME_STOP0_MC) ............................1684.3.3.15 Peripheral Status register 0 (ME_PS0) .........................................................1704.3.3.16 Peripheral Status register 1 (ME_PS1) .........................................................171


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4.3.3.17 Peripheral Status register 2 (ME_PS2) .........................................................1714.3.3.18 Run Peripheral Configuration registers (ME_RUN_PC07) .....................1724.3.3.19 Low-Power Peripheral Configuration registers (ME_LP_PC07) .............1734.3.3.20 Peripheral Control registers (ME_PCTL0143) .........................................173

4.4 Functional description ...................................................................................................................1744.4.1 Mode transition request ..................................................................................................174

4.4.2 Mode details ....................................................................................................................1764.4.2.1 RESET mode ................................................................................................1764.4.2.2 DRUN mode .................................................................................................1764.4.2.3 SAFE mode ...................................................................................................1764.4.2.4 TEST mode ...................................................................................................1774.4.2.5 RUN03 modes ...........................................................................................1774.4.2.6 HALT0 mode ................................................................................................1784.4.2.7 STOP0 mode .................................................................................................178

4.4.3 Mode transition process ..................................................................................................1794.4.3.1 Target mode request ......................................................................................1794.4.3.2 Target mode configuration loading ...............................................................179

4.4.3.3 Peripheral clocks disable ..............................................................................1804.4.3.4 Processor low-power mode entry .................................................................1804.4.3.5 Processor and system memory clock disable ................................................1814.4.3.6 Clock sources switch-on ...............................................................................1814.4.3.7 Flash modules switch-on ..............................................................................1814.4.3.8 PLL0 switch-on .............................................................................................1824.4.3.9 Pad outputs on ...............................................................................................1824.4.3.10 Peripheral clocks enable ...............................................................................1824.4.3.11 Processor and memory clock enable .............................................................1824.4.3.12 Processor low-power mode exit ....................................................................1824.4.3.13 System clock switching ................................................................................1824.4.3.14 Pad switch-off ...............................................................................................1834.4.3.15 PLL0 switch-off ............................................................................................1844.4.3.16 Clock sources switch-off ...............................................................................1844.4.3.17 Flash switch-off ............................................................................................1844.4.3.18 Current Mode Update ...................................................................................184

4.4.4 Protection of mode configuration registers .....................................................................1864.4.5 Mode transition interrupts ...............................................................................................186

4.4.5.1 Invalid mode configuration interrupt ............................................................1864.4.5.2 Invalid mode transition interrupt ..................................................................1864.4.5.3 SAFE mode transition interrupt ....................................................................1884.4.5.4 Mode transition complete interrupt ...............................................................188

4.4.6 Peripheral clock gating ...................................................................................................1884.4.7 Application example .......................................................................................................189

Chapter 5Power Control Unit (PCU)

5.1 Introduction ...................................................................................................................................191


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5.1.1 Features ...........................................................................................................................1925.1.2 Modes of operation .........................................................................................................192

5.2 External signal description ............................................................................................................1925.3 Memory map and register definition .............................................................................................192

5.3.1 Memory map ...................................................................................................................1925.3.2 Register descriptions .......................................................................................................194

5.3.2.1 Power Domain #0 Configuration register (PCU_PCONF0) .........................1945.3.2.2 Power Domain #1 Configuration register (PCU_PCONF1) .........................1965.3.2.3 Power Domain #215 Configuration register (PCU_PCONF215) .........1965.3.2.4 Power Domain Status register (PCU_PSTAT) ..............................................197

5.4 Functional description ...................................................................................................................1975.4.1 General ............................................................................................................................1975.4.2 Reset / Power-on reset ....................................................................................................1975.4.3 PCU configuration ..........................................................................................................1975.4.4 Mode transitions .............................................................................................................198

5.4.4.1 DRUN, SAFE, TEST, RUN03, HALT0, and STOP0 mode transition .....1985.4.5 Power domain control state machine ..............................................................................199

5.4.5.1 Idle phase ......................................................................................................2015.4.5.2 Power-down phase ........................................................................................2015.4.5.3 Power-up phase .............................................................................................205

5.5 Initialization information ...............................................................................................................208

Chapter 6Reset Generation Module (RGM)

6.1 Introduction ...................................................................................................................................2096.2 Features .........................................................................................................................................2106.3 Modes of operation ........................................................................................................................2106.4 External signal description ............................................................................................................2116.5 Memory map and registers description .........................................................................................211

6.5.1 Registers description .......................................................................................................2146.5.1.1 Functional Event Status register (RGM_FES) ..............................................2146.5.1.2 Destructive Event Status register (RGM_DES) ............................................2156.5.1.3 Functional Event Reset Disable register (RGM_FERD) ..............................2176.5.1.4 Destructive Event Reset Disable register (RGM_DERD) ............................2186.5.1.5 Functional Event Alternate Request register (RGM_FEAR) .......................2196.5.1.6 Destructive Event Alternate Request register (RGM_DEAR) .....................2216.5.1.7 Functional Event Short Sequence register (RGM_FESS) ............................2226.5.1.8 Functional Bidirectional Reset Enable register (RGM_FBRE) ....................224

6.6 Functional description ...................................................................................................................2256.6.1 Reset state machine .........................................................................................................225

6.6.1.1 PHASE0 ........................................................................................................2266.6.1.2 PHASE1 ........................................................................................................2276.6.1.3 PHASE2 ........................................................................................................2276.6.1.4 PHASE3 ........................................................................................................2276.6.1.5 IDLE .............................................................................................................227


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6.6.2 Destructive resets ............................................................................................................2286.6.3 External reset ..................................................................................................................2286.6.4 Functional resets .............................................................................................................2296.6.5 Alternate event generation ..............................................................................................2296.6.6 Boot mode capturing .......................................................................................................230

Chapter 7Interrupt Controller (INTC)

7.1 Introduction ...................................................................................................................................2317.2 Features .........................................................................................................................................2317.3 Block diagram ...............................................................................................................................2337.4 Modes of operation ........................................................................................................................233

7.4.1 Normal mode ..................................................................................................................2337.4.1.1 Software vector mode ...................................................................................2337.4.1.2 Hardware vector mode ..................................................................................2347.4.1.3 Debug mode ..................................................................................................2347.4.1.4 Stop mode .....................................................................................................234

7.5 Memory map and registers description .........................................................................................2357.5.1 Module memory map ......................................................................................................2357.5.2 Registers description .......................................................................................................235

7.5.2.1 INTC Module Configuration Register (INTC_MCR) ..................................2367.5.2.2 INTC Current Priority Register for Processor (INTC_CPR) ........................2377.5.2.3 INTC Interrupt Acknowledge Register (INTC_IACKR) .............................2387.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ...........................................2397.5.2.5 INTC Software Set/Clear Interrupt Registers(INTC_SSCIR0_3INTC_SSCIR4_7) 2397.5.2.6 INTC Priority Select Registers (INTC_PSR0_3INTC_PSR220_221) .......240

7.6 Functional description ...................................................................................................................2437.6.1 Interrupt request sources .................................................................................................251

7.6.1.1 Peripheral interrupt requests .........................................................................2517.6.1.2 Software configurable interrupt requests ......................................................2527.6.1.3 Unique vector for each interrupt request source ...........................................252

7.6.2 Priority management .......................................................................................................2527.6.2.1 Current priority and preemption ...................................................................2527.6.2.2 Last-in first-out (LIFO) .................................................................................253

7.6.3 Handshaking with processor ...........................................................................................2537.6.3.1 Software vector mode handshaking ..............................................................2537.6.3.2 Hardware vector mode handshaking .............................................................255

7.7 Initialization/application information ............................................................................................2567.7.1 Initialization flow ............................................................................................................2567.7.2 Interrupt exception handler .............................................................................................256

7.7.2.1 Software vector mode ...................................................................................2577.7.2.2 Hardware vector mode ..................................................................................257

7.7.3 ISR, RTOS, and task hierarchy .......................................................................................2587.7.4 Order of execution ..........................................................................................................259


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7.7.5 Priority ceiling protocol ..................................................................................................2607.7.5.1 Elevating priority ..........................................................................................2607.7.5.2 Ensuring coherency .......................................................................................260

7.7.6 Selecting priorities according to request rates and deadlines .........................................2607.7.7 Software configurable interrupt requests ........................................................................261

7.7.7.1 Scheduling a lower priority portion of an ISR ..............................................261

7.7.7.2 Scheduling an ISR on another processor ......................................................2627.7.8 Lowering priority within an ISR .....................................................................................2627.7.9 Negating an interrupt request outside of its ISR .............................................................262

7.7.9.1 Negating an interrupt request as a side effect of an ISR ...............................2627.7.9.2 Negating multiple interrupt requests in one ISR ..........................................2627.7.9.3 Proper setting of interrupt request priority ...................................................263

7.7.10 Examining LIFO contents ...............................................................................................263

Chapter 8System Status and Configuration Module (SSCM)

8.1 Introduction ...................................................................................................................................265

8.1.1 Overview .........................................................................................................................2658.1.2 Features ...........................................................................................................................2658.1.3 Modes of operation .........................................................................................................266

8.2 Memory map and register description ...........................................................................................2668.2.1 Memory map ...................................................................................................................2668.2.2 Register description ........................................................................................................266

8.2.2.1 System Status register (STATUS) .................................................................2678.2.2.2 System Memory Configuration register (MEMCONFIG) ...........................2688.2.2.3 Error Configuration (ERROR) register .........................................................2698.2.2.4 Debug Status Port (DEBUGPORT) register .................................................2698.2.2.5 Password comparison registers .....................................................................272

8.3 Functional description ...................................................................................................................2738.4 Initialization/application information ............................................................................................273

8.4.1 Reset ................................................................................................................................273

Chapter 9System Integration Unit Lite (SIUL)

9.1 Introduction ...................................................................................................................................2759.2 Overview .......................................................................................................................................2759.3 Features .........................................................................................................................................276

9.3.1 Register protection ..........................................................................................................2779.4 External signal description ............................................................................................................277

9.4.1 Detailed signal descriptions ............................................................................................2779.4.1.1 General-purpose I/O pins (GPIO[0:105]) .....................................................2779.4.1.2 External interrupt request input pins (EIRQ[0:31]) ......................................277

9.5 Memory map and register description ...........................................................................................2789.5.1 SIUL memory map .........................................................................................................2789.5.2 Register description ........................................................................................................279


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9.5.2.1 MCU ID Register #1 (MIDR1) .....................................................................2799.5.2.2 MCU ID Register #2 (MIDR2) .....................................................................2819.5.2.3 Interrupt Status Flag Register (ISR) .............................................................2829.5.2.4 Interrupt Request Enable Register (IRER) ...................................................2829.5.2.5 Interrupt Rising-Edge Event Enable Register (IREER) ...............................2839.5.2.6 Interrupt Falling-Edge Event Enable Register (IFEER) ...............................283

9.5.2.7 Interrupt Filter Enable Register (IFER) ........................................................2849.5.2.8 Pad Configuration Registers (PCR[0:107]) ..................................................2849.5.2.9 Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35]) ............2869.5.2.10 GPIO Pad Data Output registers 0_3104_107 (GPDO[0_3:104_107]) ......2919.5.2.11 GPIO Pad Data Input registers 0_3104_107 (GPDI[0_3:104_107]) ..........2919.5.2.12 Parallel GPIO Pad Data Out register 03 (PGPDO[0:3]) .............................2929.5.2.13 Parallel GPIO Pad Data In register 03 (PGPDI[0:3]) .................................2929.5.2.14 Masked Parallel GPIO Pad Data Out register 06 (MPGPDO[0:6]) ............2939.5.2.15 Interrupt Filter Maximum Counter registers 031 (IFMC[0:31]) ................2949.5.2.16 Interrupt Filter Clock Prescaler Register (IFCPR) .......................................294

9.6 Functional description ...................................................................................................................296

9.6.1 General ............................................................................................................................2969.6.2 Pad control ......................................................................................................................2969.6.3 General purpose input and output pads (GPIO) ..............................................................2969.6.4 External interrupts ...........................................................................................................297

9.6.4.1 External interrupt management .....................................................................2989.7 Pin muxing ....................................................................................................................................298

Chapter 10e200z0 and e200z0h Core

10.1 Overview .......................................................................................................................................29910.2 Features .........................................................................................................................................299

10.2.1 Microarchitecture summary ............................................................................................30010.2.1.1 Block diagram ...............................................................................................30110.2.1.2 Instruction unit features ................................................................................30210.2.1.3 Integer unit features ......................................................................................30310.2.1.4 Load/Store unit features ................................................................................30310.2.1.5 e200z0h system bus features .........................................................................30310.2.1.6 Nexus features ...............................................................................................303

10.3 Core registers and programmers model .......................................................................................30410.3.1 Unimplemented SPRs and read-only SPRs ....................................................................307

10.4 Instruction summary ......................................................................................................................307

Chapter 11Peripheral Bridge (PBRIDGE)

11.1 Introduction ...................................................................................................................................30911.1.1 Block diagram .................................................................................................................30911.1.2 Overview .........................................................................................................................30911.1.3 Modes of operation .........................................................................................................310


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11.2 Functional description ...................................................................................................................31011.2.1 Access support ................................................................................................................310

11.2.1.1 Peripheral Write Buffering ............................................................................31011.2.1.2 Read cycles ...................................................................................................31011.2.1.3 Write cycles ...................................................................................................310

11.2.2 General operation ............................................................................................................310

Chapter 12Crossbar Switch (XBAR)

12.1 Introduction ...................................................................................................................................31112.2 Block diagram ...............................................................................................................................31112.3 Overview .......................................................................................................................................31212.4 Features .........................................................................................................................................31212.5 Modes of operation ........................................................................................................................312

12.5.1 Normal mode ..................................................................................................................31212.5.2 Debug mode ....................................................................................................................313

12.6 Functional description ...................................................................................................................313

12.6.1 Overview .........................................................................................................................31312.6.2 General operation ............................................................................................................31312.6.3 Master ports ....................................................................................................................31412.6.4 Slave ports .......................................................................................................................31412.6.5 Priority assignment .........................................................................................................31412.6.6 Arbitration .......................................................................................................................314

12.6.6.1 Fixed priority operation ................................................................................315

Chapter 13Error Correction Status Module (ECSM)

13.1 Introduction ...................................................................................................................................31713.2 Overview .......................................................................................................................................31713.3 Features .........................................................................................................................................31713.4 Memory map and registers description .........................................................................................317

13.4.1 Memory map ...................................................................................................................31813.4.2 Registers description .......................................................................................................320

13.4.2.1 Processor core type (PCT) register ...............................................................32013.4.2.2 Revision (REV) register ................................................................................32113.4.2.3 IPS Module Configuration (IMC) register ....................................................32113.4.2.4 Miscellaneous Reset Status Register (MRSR) ..............................................32113.4.2.5 Miscellaneous Interrupt Register (MIR) .......................................................32213.4.2.6 Miscellaneous User-Defined Control Register (MUDCR) ...........................32313.4.2.7 ECC registers ................................................................................................32313.4.2.8 ECC Configuration Register (ECR) .............................................................32413.4.2.9 ECC Status Register (ESR) ...........................................................................32513.4.2.10ECC Error Generation Register (EEGR) ......................................................32713.4.2.11 Flash ECC Address Register (FEAR) ...........................................................32913.4.2.12Flash ECC Master Number Register (FEMR) ..............................................329


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13.4.2.13Flash ECC Attributes (FEAT) register ..........................................................33013.4.2.14Flash ECC Data Register (FEDR) ................................................................33113.4.2.15RAM ECC Address Register (REAR) ..........................................................33113.4.2.16RAM ECC Syndrome Register (RESR) .......................................................33213.4.2.17RAM ECC Master Number Register (REMR) .............................................33413.4.2.18RAM ECC Attributes (REAT) register .........................................................334

13.4.2.19RAM ECC Data Register (REDR) ...............................................................33513.4.3 ECSM_reg_protection ....................................................................................................336

Chapter 14Internal Static RAM (SRAM)

14.1 Introduction ...................................................................................................................................33914.2 SRAM operating mode ..................................................................................................................33914.3 Register memory map ...................................................................................................................33914.4 SRAM ECC mechanism ................................................................................................................339

14.4.1 Access timing ..................................................................................................................34014.4.2 Reset effects on SRAM accesses ....................................................................................341

14.5 Functional description ...................................................................................................................34114.6 Initialization and application information .....................................................................................341

Chapter 15Flash Memory

15.1 Introduction ...................................................................................................................................34315.2 Platform flash controller ................................................................................................................343

15.2.1 Introduction .....................................................................................................................34315.2.1.1 Overview .......................................................................................................34415.2.1.2 Features .........................................................................................................344

15.2.2 Modes of operation .........................................................................................................34515.2.3 External signal descriptions ............................................................................................34515.2.4 Memory map and registers description ...........................................................................345

15.2.4.1 Memory map .................................................................................................34515.2.4.2 Registers description .....................................................................................347

15.2.5 Functional description .....................................................................................................34715.2.6 Basic interface protocol ..................................................................................................34715.2.7 Access protections ..........................................................................................................34815.2.8 Read cycles buffer miss .............................................................................................34815.2.9 Read cycles buffer hit ................................................................................................34915.2.10Write cycles .....................................................................................................................34915.2.11Error termination .............................................................................................................34915.2.12Access pipelining ............................................................................................................35015.2.13Flash error response operation ........................................................................................35015.2.14Bank0 page read buffers and prefetch operation ............................................................350

15.2.14.1Instruction/data prefetch triggering ..............................................................35115.2.14.2Per-master prefetch triggering ......................................................................35215.2.14.3Buffer allocation ...........................................................................................352


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15.2.14.4Buffer invalidation ........................................................................................35215.2.15Bank1 temporary holding register ..................................................................................35215.2.16Read-While-Write functionality .....................................................................................35315.2.17Wait state emulation ........................................................................................................35515.2.18Timing diagrams .............................................................................................................356

15.3 Flash memory ................................................................................................................................362

15.3.1 Introduction .....................................................................................................................36215.3.2 Main features ..................................................................................................................36215.3.3 Block diagram .................................................................................................................36215.3.4 Functional description .....................................................................................................363

15.3.4.1 Macrocell structure .......................................................................................36315.3.4.2 Flash module sectorization ...........................................................................364

15.3.5 Operating modes .............................................................................................................36715.3.5.1 Reset ..............................................................................................................36715.3.5.2 User mode .....................................................................................................36815.3.5.3 Low-power mode ..........................................................................................36815.3.5.4 Power-down mode ........................................................................................369

15.3.6 Registers description .......................................................................................................37015.3.7 Register map ...................................................................................................................371

15.3.7.1 Module Configuration Register (MCR) ........................................................37315.3.7.2 Low/Mid Address Space Block Locking register (LML) .............................37815.3.7.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) .37915.3.7.4 Secondary Low/Mid Address Space Block Locking register (SLL) ............38015.3.7.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register(NVSLL) 38115.3.7.6 Low/Mid Address Space Block Select register (LMS) ................................38315.3.7.7 Address Register (ADR) ...............................................................................38415.3.7.8 User Test 0 register (UT0) ............................................................................39215.3.7.9 User Test 1 register (UT1) ............................................................................39415.3.7.10User Test 2 register (UT2) ............................................................................39515.3.7.11 User Multiple Input Signature Register 0 (UMISR0) ...................................39515.3.7.12User Multiple Input Signature Register 1 (UMISR1) ...................................39615.3.7.13User Multiple Input Signature Register 2 (UMISR2) ...................................39715.3.7.14User Multiple Input Signature Register 3 (UMISR3) ...................................39715.3.7.15User Multiple Input Signature Register 4 (UMISR4) ...................................39815.3.7.16Non-Volatile Private Censorship Password 0 register (NVPWD0) ..............39815.3.7.17Non-Volatile Private Censorship Password 1 register (NVPWD1) ..............39915.3.7.18Non-Volatile System Censoring Information 0 register (NVSCI0) ..............40015.3.7.19Non-Volatile System Censoring Information 1 register (NVSCI1) ..............40015.3.7.20Non-Volatile User Options register (NVUSRO) ...........................................401

15.3.8 Programming considerations ..........................................................................................40215.3.8.1 Modify operation ..........................................................................................40215.3.8.2 Error Correction Code (ECC) .......................................................................41115.3.8.3 EEPROM emulation .....................................................................................41115.3.8.4 Protection strategy ........................................................................................412


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Chapter 16Enhanced Direct Memory Access (eDMA)

16.1 Introduction ...................................................................................................................................41516.2 Overview .......................................................................................................................................41516.3 Features .........................................................................................................................................41616.4 Modes of operation ........................................................................................................................417

16.4.1 Normal mode ..................................................................................................................41716.4.2 Debug mode ....................................................................................................................417

16.5 Memory map and register definition .............................................................................................41816.5.1 Memory map ...................................................................................................................41816.5.2 Register descriptions .......................................................................................................420

16.5.2.1 eDMA Control Register (EDMA_CR) .........................................................42016.5.2.2 eDMA Error Status Register (EDMA_ESR) ................................................42116.5.2.3 eDMA Enable Request Register (EDMA_ERQRL) ....................................42316.5.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL) ............................42416.5.2.5 eDMA Set Enable Request Register (EDMA_SERQR) ...............................42516.5.2.6 eDMA Clear Enable Request Register (EDMA_CERQR) ...........................42616.5.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) ......................42616.5.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) ..................42716.5.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR) .........................42716.5.2.10eDMA Clear Error Register (EDMA_CERR) ..............................................42816.5.2.11 eDMA Set START Bit Register (EDMA_SSBR) .........................................42916.5.2.12eDMA Clear DONE Status Bit Register (EDMA_CDSBR) ........................42916.5.2.13eDMA Interrupt Request Register (EDMA_IRQRL) ...................................43016.5.2.14eDMA Error Register (EDMA_ERL) ...........................................................43116.5.2.15DMA Hardware Request Status (DMAHRSL) .............................................43116.5.2.16eDMA Channel n Priority Registers (EDMA_CPRn) ..................................43216.5.2.17Transfer Control Descriptor (TCD) ..............................................................433

16.6 Functional description ...................................................................................................................44016.6.1 eDMA microarchitecture ................................................................................................44016.6.2 eDMA basic data flow ....................................................................................................44216.6.3 eDMA performance ........................................................................................................444

16.7 Initialization / application information ..........................................................................................44716.7.1 eDMA initialization ........................................................................................................44716.7.2 DMA programming errors ..............................................................................................44916.7.3 DMA request assignments ..............................................................................................45016.7.4 DMA arbitration mode considerations ...........................................................................450

16.7.4.1 Fixed-channel arbitration ..............................................................................450

16.7.4.2 Fixed-group arbitration, round-robin channel arbitration .............................45016.7.5 DMA transfer ..................................................................................................................45116.7.5.1 Single request ................................................................................................45116.7.5.2 Multiple requests ...........................................................................................45216.7.5.3 Modulo feature ..............................................................................................453

16.7.6 TCD status ......................................................................................................................45416.7.6.1 Minor loop complete .....................................................................................454


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16.7.6.2 Active channel TCD reads ............................................................................45516.7.6.3 Preemption status ..........................................................................................455

16.7.7 Channel linking ...............................................................................................................45516.7.8 Dynamic programming ...................................................................................................456

16.7.8.1 Dynamic channel linking and dynamic scatter/gather ..................................456

Chapter 17DMA Channel Mux (DMA_MUX)

17.1 Introduction ...................................................................................................................................45917.1.1 Overview .........................................................................................................................45917.1.2 Features ...........................................................................................................................45917.1.3 Modes of operation .........................................................................................................460

17.2 External signal description ............................................................................................................46017.2.1 Overview .........................................................................................................................460

17.3 Memory map and register definition .............................................................................................46017.3.1 Memory map ...................................................................................................................46017.3.2 Register descriptions .......................................................................................................462

17.3.2.1 Channel Configuration Registers ..................................................................46217.4 DMA request mapping ..................................................................................................................46317.5 Functional description ...................................................................................................................464

17.5.1 DMA channels with periodic triggering capability ........................................................46417.5.2 DMA channels with no triggering capability .................................................................467

17.6 Initialization/application information ............................................................................................46717.6.1 Reset ................................................................................................................................46717.6.2 Enabling and configuring sources ...................................................................................467

Chapter 18FlexRay Communication Controller (FlexRay)

18.1 Introduction ...................................................................................................................................47118.1.1 Reference ........................................................................................................................47118.1.2 Glossary ..........................................................................................................................47118.1.3 Color coding ...................................................................................................................47218.1.4 Overview .........................................................................................................................47218.1.5 Features ...........................................................................................................................47418.1.6 Modes of operation .........................................................................................................475

18.1.6.1 Disabled mode ..............................................................................................47518.1.6.2 Normal mode ................................................................................................475

18.2 External signal description ............................................................................................................47618.2.1 Detailed signal descriptions ............................................................................................476

18.2.1.1 FR_A_RX receive data channel A ...........................................................47618.2.1.2 FR_A_TX transmit data channel A .........................................................47618.2.1.3 FR_A_TX_EN transmit enable channel A ..............................................47718.2.1.4 FR_B_RX receive data channel B ...........................................................47718.2.1.5 FR_B_TX transmit data channel B ..........................................................47718.2.1.6 FR_B_TX_EN transmit enable channel B ...............................................477


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18.2.1.7 FR_DBG[3], FR_DBG[2], FR_DBG[1], FR_DBG[0] strobe signals .....47718.3 Controller host interface clocking .................................................................................................47718.4 Protocol engine clocking ...............................................................................................................477

18.4.1 PLL Clocking ..................................................................................................................47718.5 Memory map and register description ...........................................................................................478

18.5.1 Memory map ...................................................................................................................478

18.5.2 Register descriptions .......................................................................................................48118.5.2.1 Register reset .................................................................................................48118.5.2.2 Register write access .....................................................................................48118.5.2.3 Module Version Register (MVR) ..................................................................48318.5.2.4 Module Configuration Register (MCR) ........................................................48318.5.2.5 System Memory Base Address High Register (SYMBADHR) andSystem Memory Base Address Low Register (SYMBADLR) 48518.5.2.6 Strobe Signal Control Register (STBSCR) ...................................................48618.5.2.7 Message Buffer Data Size Register (MBDSR) .............................................48918.5.2.8 Message Buffer Segment Size and Utilization Register (MBSSUTR) .........48918.5.2.9 Protocol Operation Control Register (POCR) ..............................................490

18.5.2.10Global Interrupt Flag and Enable Register (GIFER) ....................................49218.5.2.11 Protocol Interrupt Flag Register 0 (PIFR0) ..................................................49418.5.2.12Protocol Interrupt Flag Register 1 (PIFR1) ..................................................49618.5.2.13Protocol Interrupt Enable Register 0 (PIER0) ..............................................49718.5.2.14Protocol Interrupt Enable Register 1 (PIER1) ..............................................49918.5.2.15CHI Error Flag Register (CHIERFR) ...........................................................50018.5.2.16Message Buffer Interrupt Vector Register (MBIVEC) .................................50218.5.2.17Channel A Status Error Counter Register (CASERCR) ...............................50218.5.2.18Channel B Status Error Counter Register (CBSERCR) ...............................50318.5.2.19Protocol Status Register 0 (PSR0) ................................................................50318.5.2.20Protocol Status Register 1 (PSR1) ................................................................50518.5.2.21Protocol Status Register 2 (PSR2) ................................................................50618.5.2.22Protocol Status Register 3 (PSR3) ................................................................50818.5.2.23Macrotick Counter Register (MTCTR) ........................................................50918.5.2.24Cycle Counter Register (CYCTR) ................................................................51018.5.2.25Slot Counter Channel A Register (SLTCTAR) .............................................51018.5.2.26Slot Counter Channel B Register (SLTCTBR) .............................................51018.5.2.27Rate Correction Value Register (RTCORVR) ...............................................51118.5.2.28Offset Correction Value Register (OFCORVR) ............................................51118.5.2.29Combined Interrupt Flag Register (CIFRR) .................................................51218.5.2.30System Memory Access Time-Out Register (SYMATOR) ..........................51318.5.2.31Sync Frame Counter Register (SFCNTR) ....................................................51318.5.2.32Sync Frame Table Offset Register (SFTOR) ................................................51418.5.2.33Sync Frame Table Configuration, Control, Status Register (SFTCCSR) .....51518.5.2.34Sync Frame ID Rejection Filter Register (SFIDRFR) ..................................51618.5.2.35Sync Frame ID Acceptance Filter Value Register (SFIDAFVR) .................51718.5.2.36Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR) .................51718.5.2.37Network Management Vector Registers (NMVR0NMVR5) ......................517


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18.5.2.38Network Management Vector Length Register (NMVLR) ..........................51818.5.2.39Timer Configuration and Control Register (TICCR) ....................................51918.5.2.40Timer 1 Cycle Set Register (TI1CYSR) .......................................................52018.5.2.41Timer 1 Macrotick Offset Register (TI1MTOR) ..........................................52018.5.2.42Timer 2 Configuration Register 0 (TI2CR0) ................................................52118.5.2.43Timer 2 Configuration Register 1 (TI2CR1) ................................................521

18.5.2.44Slot Status Selection Register (SSSR) ..........................................................52218.5.2.45Slot Status Counter Condition Register (SSCCR) ........................................52318.5.2.46Slot Status Registers (SSR0SSR7) ..............................................................52518.5.2.47Slot Status Counter Registers (SSCR0SSCR3) ..........................................52618.5.2.48MTS A Configuration Register (MTSACFR) ..............................................52718.5.2.49MTS B Configuration Register (MTSBCFR) ...............................................52818.5.2.50Receive Shadow Buffer Index Register (RSBIR) .........................................52818.5.2.51Receive FIFO Selection Register (RFSR) ....................................................52918.5.2.52Receive FIFO Start Index Register (RFSIR) ................................................53018.5.2.53Receive FIFO Depth and Size Register (RFDSR) ........................................53018.5.2.54Receive FIFO A Read Index Register (RFARIR) .........................................530

18.5.2.55Receive FIFO B Read Index Register (RFBRIR) .........................................53118.5.2.56Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) .53218.5.2.57Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) ...53218.5.2.58Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) ....53218.5.2.59Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) ...53318.5.2.60Receive FIFO Range Filter Configuration Register (RFRFCFR) ................53318.5.2.61Receive FIFO Range Filter Control Register (RFRFCTR) ..........................53418.5.2.62Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) ................53518.5.2.63Last Dynamic Transmit Slot Channel B Register (LDTXSLBR) ................53518.5.2.64Protocol configuration registers ....................................................................53518.5.2.65Message Buffer Configuration, Control, Status Registers (MBCCSRn) ......54418.5.2.66Message Buffer Cycle Counter Filter Registers (MBCCFRn) .....................54618.5.2.67Message Buffer Frame ID Registers (MBFIDRn) ........................................54718.5.2.68Message Buffer Index Registers (MBIDXRn) .............................................548

18.6 Functional description ...................................................................................................................54918.6.1 Message buffer concept ..................................................................................................54918.6.2 Physical message buffer ..................................................................................................549

18.6.2.1 Message buffer header field ..........................................................................54918.6.2.2 Message buffer data field ..............................................................................550

18.6.3 Message buffer types ......................................................................................................55018.6.3.1 Individual message buffers ...........................................................................55018.6.3.2 Receive shadow buffers ................................................................................55218.6.3.3 Receive FIFO ................................................................................................55218.6.3.4 Message buffer configuration and control data ............................................55418.6.3.5 Individual message buffer control data .........................................................55518.6.3.6 Receive shadow buffer configuration data ...................................................555


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18.6.3.7 Receive FIFO control and configuration data ...............................................55518.6.4 FlexRay memory layout ..................................................................................................556

18.6.4.1 Message buffer header area ..........................................................................55718.6.4.2 Message buffer data area ..............................................................................55718.6.4.3 Sync frame table area ....................................................................................558

18.6.5 Physical message buffer description ...............................................................................558

18.6.5.1 Message buffer protection and data consistency ..........................................55818.6.5.2 Message buffer header field description .......................................................55818.6.5.3 Message buffer data field description ...........................................................565

18.6.6 Individual message buffer functional description ...........................................................56718.6.6.1 Individual message buffer configuration ......................................................56718.6.6.2 Single transmit message buffers ...................................................................56818.6.6.3 Receive message buffers ...............................................................................57718.6.6.4 Double transmit message buffer ...................................................................583

18.6.7 Individual message buffer search ....................................................................................59218.6.7.1 Message buffer cycle counter filtering .........................................................59418.6.7.2 Message buffer channel assignment consistency ..........................................594

18.6.7.3 Node related slot multiplexing ......................................................................59418.6.7.4 Message buffer search error ..........................................................................595

18.6.8 Individual message buffer reconfiguration .....................................................................59518.6.8.1 Reconfiguration schemes ..............................................................................595

18.6.9 Receive FIFO ..................................................................................................................59618.6.9.1 Overview .......................................................................................................59618.6.9.2 Receive FIFO configuration .........................................................................59618.6.9.3 Receive FIFO reception ................................................................................59718.6.9.4 Receive FIFO message access ......................................................................59718.6.9.5 Receive FIFO filtering ..................................................................................597

18.6.10Channel device modes ....................................................................................................60018.6.10.1Dual channel device mode ............................................................................60018.6.10.2Single channel device mode .........................................................................601

18.6.11External clock synchronization .......................................................................................60218.6.12Sync frame ID and sync frame deviation tables .............................................................603

18.6.12.1Sync frame ID table content .........................................................................60418.6.12.2Sync frame deviation table content ...............................................................60418.6.12.3Sync frame ID and sync frame deviation table setup ...................................60418.6.12.4Sync frame ID and sync frame deviation table generation ...........................60518.6.12.5Sync Frame Table Access .............................................................................606

18.6.13MTS generation ..............................................................................................................60618.6.14Key slot transmission ......................................................................................................607

18.6.14.1Key slot assignment ......................................................................................60718.6.14.2Key slot transmission in POC:startup ...........................................................60718.6.14.3Key slot transmission in POC:normal active ................................................607

18.6.15Sync frame filtering ........................................................................................................60718.6.15.1Sync frame acceptance filtering ....................................................................60818.6.15.2Sync frame rejection filtering .......................................................................608


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18.6.16Strobe signal support .......................................................................................................60818.6.16.1Strobe signal assignment ...............................................................................60818.6.16.2Strobe signal timing ......................................................................................609

18.6.17Timer support ..................................................................................................................60918.6.17.1Absolute timer T1 .........................................................................................60918.6.17.2Absolute / relative timer T2 ..........................................................................610

18.6.18Slot status

power architecture microcontroller

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