post simulation debug tutorial

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Post Simulation Debug Tutorial

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Table Of Contents

Table Of Contents Post Simulation Debug Tutorial ....................................................................................................... 1

Introduction .................................................................................................................................. 1 Creating a project......................................................................................................................... 1 Simulation .................................................................................................................................... 2 Changing top-level during simulation in the PSD mode .............................................................. 8

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Introduction

Post Simulation Debug is a very useful feature that allows you to simulate a project in the "off-line" mode (without a connection to the simulator). This tutorial shows how to prepare data for Post Simulation Debug and conduct simulation in this mode.

Creating a project

In the normal course of action, the first thing you have to do is to create a new project. Next, you modify your project by adding or creating new modules (source code files, state diagrams, block diagrams, etc.). Since all steps needed to go through to create a design are described in other tutorials, we will omit this part and assume that we have a complete design that is ready for simulation.

NOTE: Creating a new project, adding new modules to the design and other topics related to the Design Entry are described in the following tutorials: VHDL Entry and Simulation Tutorial, Verilog Entry and Simulation Tutorial, Mixed VHDL-Verilog Tutorial.

In this tutorial we will use the freq_meter sample design that is shipped with the Active-HDL software.

1. In the first step, run Active-HDL and open the Workspace/Design Explorer (File | Open Workspace/Design Explorer) to load the freq_meter workspace. The figure below shows its default location:

Default location of the freq_meter sample design.

2. The design you have just opened has to be compiled, before you advance to the simulation phase. First, exclude from compilation two files:

CNT_BCD2.bde testbench_cnt_bcd_conf.vhd

3. Compile the design, by using the menu command Design | Compile All.

After successful compilation (the Console window should display a line similar to the following:

# Compile success 0 Errors 0 Warnings Analysis time : 1.0 [s])

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you will be prompted to set up the top-level. Use the same settings as shown in the picture and click the OK button:

Setting up the top-level unit of the design.

The next step allows you to simulate the project.

Simulation

Preparing the design for simulation

1. The first step you need to make is to initialize simulation by choosing the Simulation | Initialize Simulation menu command.

Note how the Simulation/Time Status field looks (upper left corner of the Active-HDL window). By examining this field you can easily determine whether you are dealing with a regular simulation or a simulation in the Post Simulation Debug mode.

The Simulation/Time field after the initialization of a regular simulation.

2. Create a new waveform file (click New Waveform button or choose File | New | Waveform).

3. Switch to the Structure tab of the Design Browser window and select the testbench (stimulusfromfile) item.

4. Select all signals with ACTUAL, EXPECTED, and STIM prefixes and drag them to the waveform window. You should see the following result:

Waveform window after dragging in the selected signals.

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Simulating the design

5. Set the simulation time step to 5us (microseconds) and perform a few steps (use the Run For

button) - see how far you can go. Note that the Move backward and Go to current

simulation time buttons are disabled.

NOTE: You may see a message box announcing the end of simulation: "Simulation has finished. There are no more vectors to simulate."

Enabling a signal history

The Move backward and Go to current simulation time buttons are disabled because there is no history of signal events that would allow you to browse back and forth. During this simulation, you can only watch the current values of selected signals. To be able to watch events that happened before the current simulation time, you need to modify the design settings.

6. Open the Design Settings dialog box (choose the Design | Settings menu command) and switch to the Trace/Debug category.

7. Select the Save full signal history checkbox. Note that the checkbox below (Preserve file with signal history for Post Simulation Debug) is now disabled. You will use this option later on to produce data for the PSD mode. Click the OK button to approve changes.

The Save full signal history option in the Trace/Debug category of the Design Settings dialog box.

This change will not be visible until you reinitialize simulation:

8. End the current simulation (Simulation | End Simulation) and initialize it again (Simulation | Initialize Simulation).

NOTE: Active-HDL allows you to observe values of signals in different views. In the next few steps, we will watch values in three windows (Hierarchy Viewer, Standard Waveform Viewer/Editor, Watch). In your further work with Active-HDL, you can choose the view that is most suitable for you.

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9. First open the Watch window (View | Watch), then select all signals in the waveform window and drag them to the Watch window.

The Watch window after dragging in signals from the waveform window.

10. In the Hierarchy Viewer window (Structure tab) highlight the testbench (stimulusfromfile) unit.

11. Click the Run Until button to advance simulation to 18us.

Advancing simulation to 18us.

NOTE: The Move backward and Go to current simulation time buttons are enabled.

Take a look at the current values of signals in the three windows mentioned before:

The Watch window in 18th us of the simulation.

The waveform window in 18th us of the simulation.

The Hierarchy Viewer window in 18th us of the simulation.

12. Set simulation time step to 4us and then navigate one step backward using the Move backward button. Note that values of some signals have changed.

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The Watch window in 14th us of the simulation

The waveform window in 14th us of the simulation.

The Hierarchy Viewer window in 14th us of the simulation

As you can see, the simulator remembers the history of signals during simulation. However, when you end simulation, the history is no longer available. In other words, the current design settings force you to use the simulator each time you want to access the signal(s) history. The solution to this problem is the Post Simulation Debug mode, which uses simulation data stored in an external file. Before you use this feature, however, you have to collect data for Post Simulation Debug.

Collecting data for PSD mode

13. Open the Design Settings dialog box one more time, switch to the Trace/Debug category and select the Preserve file with signal history for Post Simulation Debug option. Leave the default file name (freq_meter.psd) and approve the new settings by clicking the OK button.

The Preserve file with signal history for Post Simulation Debug option in the Trace/Debug category of the Design Settings dialog box

14. End simulation (Simulation | End Simulation) and start it again (Simulation | Initialize Simulation).

15. Use the Run Until button to advance simulation to 20 us.

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16. End the current simulation (Simulation | End Simulation).

The signal history has been written to the freq_meter.psd file and now you are ready to simulate the project in the Post Simulation Debug mode.

Simulation in the PSD mode

1. Use the Waveform | Clear All Waveforms menu command to clear all patterns from the waveform.

2. To initialize simulation in the Post Simulation Debug mode, select the Simulation | Initialize Post Simulation Debug menu command. The Open dialog box will be invoked. Choose the freq_meter.psd file (the one you have created during the last normal simulation) and click the Open button.

The simulation data will be loaded from the file you have chosen and the operation will be indicated by the folder icon in the Simulation Time/Status field.

The Simulation/Time field after initialization of the PSD mode.

Now you should see the waveform filled with signal patterns in the range from 0 to 20us (Zoom out on the waveform if you do not see the whole range).

3. Advance simulation to 15us and then perform a few steps, each for 1 us long (try to step forward and backward). Watch the values in the Value column of the waveform window. See what will happen when you exceed the 20 us range (moving forward).

The waveform window after 20us of simulation in the PSD mode.

When you exceed the 20us, all values in the Value column disappear. There is no data in the freq_top.psd file for signals after that time and there is no simulator engine to generate it.

So far you were simulating only signals from the top-level. But what will happen if you try to simulate signals that come from another hierarchy?

4. Go to the Design Browser window, switch to the Structure tab, expand the testbench (stimulusfromfile) unit, and highlight the UUT freq_top (freq_top) item.

As you can see, signals of this module are unavailable. If you go deeper in the hierarchy tree, you will note that all signals except those from the top-level unit are unavailable. By default, only signals from the top-level are "watched" and stored in the *.psd file during simulation. To watch other signals, you have to choose them by yourself in the Select Signals for PSD window.

Design Browser, list of UUT freq_top module signals.

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Selecting signals for PSD

5. Open the Design Settings dialog box and switch to the Trace/Debug category.

6. Click the Select Signals button to invoke the Select Signals for PSD window.

NOTE: If you highlight the root item in the Select Signals for PSD window (testbench (stimulusfromfile)), you will see that all signals are selected by default.

7. Expand the root item and highlight the UUT: freq_top (freq_top) unit.

8. Select the following signals: F_INPUT, F_PATTERN, RESET, START, LED_A, LED_B, LED_C, and LED_D. Approve the changes with the OK button and close the Design Settings window.

Selecting signals for PSD.

You need to simulate the design one more time to collect data for recently selected signals.

9. End the current PSD session and initialize the standard simulation session (Simulation | Initialize Simulation). Before the initialization, you will be asked if you want to confirm overwriting the existing file with PSD data. To proceed, answer Yes.

PSD file overwriting confirmation dialog box.

10. Run simulation (Simulation | Run command or press Alt+F5).

11. Close the dialog box indicating the end of simulation and then finish simulation.

12. Once more, initialize simulation in the PSD mode by using the same file (freq_meter.psd).

13. Go to the Design Browser window, switch to the Structure tab, expand the testbench (stimulusfromfile) unit, and highlight the UUT freq_top (freq_top) unit.

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List of the freq_top module signals.

The signals you have selected in the Select Signals for PSD window are now available (you can see the full history of their values). Select them and drag to the waveform window (you may also drag some of the unavailable signals for the comparison).

NOTE: Even if you add an unavailable signal to the waveform in the PSD mode, you will not see its history.

14. Advance simulation to 15us and then perform a few steps, each 2us long to see that values of selected signals are changing.

Changing top-level during simulation in the PSD mode

So far you were simulating the design using testbench (stimulusfromfile) set as the top-level unit. What will happen if you change it during simulation in the PSD mode?

Setting up freq_top as the top level unit.

To find out, change the top-level unit from testbench (stimulusfromfile) into freq_top (freq_top).

Note that all signals of the new top-level unit (freq_top) are unavailable, even though most of them were available before you have changed the top-level unit. The hierarchy paths of signals in the PSD mode come from a *.psd file. By changing the top-level from testbench (stimulusfromfile) into freq_top (freq_top) you introduce inequality between the hierarchy paths of the currently set simulation top-level unit and the paths in the freq_meter.psd file. As a result, Active-HDL does not display any signal values. Simulation in the PSD mode is meaningful only if the top-level set in the PSD mode is the same as the one set during regular simulation.

NOTE: The Simulator Resolution option in the Simulation category of the Design Settings dialog box allows you to set the simulator's resolution. However, this option is useful only during regular simulation. The PSD mode uses the same resolution that was set when you were collecting data for the PSD.

Conclusion The PSD mode provides a useful diagnosis tool. It allows you to browse values of signals read from an external file and does not need a connection to the simulator. You can watch values of signals in the following windows: Watch, Waveform Viewer, Hierarchy Viewer, Block Diagram Editor, and HDL Editor. You perform only one regular simulation to collect the PSD data and then

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analyze the design as many times as you need in the PSD mode. Moreover, you can share results of your simulation with others as well as use PSD files prepared by someone else on a different computer.

Thank you for using Active-HDL

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Post Simulation Debug Tutorial Introduction Creating a project Simulation Changing top-level during simulation in the PSD mode

post simulation debug tutorial

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