INTEGRATION, the VLSI journal 46 (2013) 69–79

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INTEGRATION, the VLSI journal

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Post-silicon power mapping techniques for integrated circuits$

Sherief Reda n, Abdullah N. Nowroz, Ryan Cochran, Stefan Angelevski

School of Engineering, Brown University, 184 Hope St, Providence RI 02912, United States

a r t i c l e i n f o

Available online 18 January 2012

Keywords:

Power mapping

Infrared imaging

Power analysis

Post-silicon validation

60/$ - see front matter & 2011 Elsevier B.V. A

016/j.vlsi.2011.12.001

earlier version of this paper appeared at the

wer Electronics and Design (ISLPED) 2010

s numerous novel material, including (1) det

the challenges of thermal to power inversio

ular value filtering in the proposed thermal to

a description of our thermal calibration met

f the test chip; (5) new test maps and exper

vious results; (6) new experiments to anal

ements, and (7) results from spatial power

ies.

esponding author.

ail addresses: Sherief_Reda@brown.edu (S. Re

h_nowroz@brown.edu (A.N. Nowroz),

chran@brown.edu (R. Cochran),

ngelevski@brown.edu (S. Angelevski).

a b s t r a c t

We propose a new methodology for post-silicon power validation using the captured thermal infrared

emissions from the back-side of operational integrated circuits. We first identify the challenges

associated with thermal to power inversion, and then we address these challenges by devising a

quadratic optimization formulation that incorporates Tikhonov filtering techniques to find the most

accurate power maps. To validate our methodology, a programmable circuit of micro-heaters is

implemented to create a number of reference power maps. The thermal emissions from the circuit are

captured using an infrared camera and then inverted to yield highly accurate post-silicon power maps.

& 2011 Elsevier B.V. All rights reserved.

1. Introduction

It is possible to sort modern chips into two main categories:power limited and hot spot limited [2]. Power-limited chips areused in battery-operated mobile devices where it is necessary tominimize the total power consumption to maximize the device’sbattery life. The wide range of applications (e.g., 3D games, webbrowsing, video decoding) that execute on mobile devices com-plicates the problem of power estimation. On the other hand,designers of hot-spot limited chips seek to minimize the peakjunction temperatures which arise from the spatial and temporaldistribution of power densities. Excessive chip temperaturesimpact reliability and constrain performance.

Design of power-limited and hot-spot limited chips require thecomputation of accurate, fine grained power estimates for thedifferent circuit blocks. Design-time estimates are typically inac-curate in comparison to the true post-silicon power consumptionfor the following reasons: modeling inaccuracies during designtime [3], unpredictability of runtime workloads [3,4], and manu-facturing process variations [4–7]. Our objective is to provide

ll rights reserved.

International Symposium on

[1]. This expanded article

ailed mathematical elabora-

n; (2) automatic techniques

power inversion methodol-

hod; (4) the implementation

imental results that outclass

yze the source of errors in

maps with varying power

da),

accurate post-silicon spatial power estimates for the variouscircuit blocks using the runtime thermal infrared emissionsemitted from the back side of semiconductor chips. Spatial powermapping from thermal emissions has emerged in the past fewyears through the research work of two groups [2,8]. In oneapproach, the spatial steady-state power consumption is esti-mated from temperature by minimizing total squared error [2]. Asecond approach uses a combinatorial optimization formulationbased on genetic algorithms to find dynamic and leakage powermaps that lead to the measured emissions [8]. The novel con-tributions of this paper are as follows.

�

We elucidate the technical challenges in thermal to powerinversion. Spatial discretization and measurement errors inthermal imaging limit the ability to resolve power spatially. Inaddition, heat conduction has a low-pass filtering effect thatattenuates the thermal impact of high-frequency spatial powervariations. We investigate these phenomena theoretically andempirically and demonstrate their impact on power estima-tion accuracy. � To address the outlined challenges we propose techniques

from regularization theory. We propose quadratic formula-tions that are augmented with Tikhonov regularization meth-ods to improve the accuracy of spatial power estimation. Ourtechniques limit the impact of measurement errors andimprove power estimation compared to previous techniques.

� A major challenge in thermal to power inversion is to be able

to validate the power estimations. Accordingly we design andimplement a circuit with programmable micro-heaters thatcan generate power maps with various intensities and spatialconstructions. We exercise the circuit with a number ofdifferent spatial power maps and then capture the thermalemissions in the mid-wave infrared range from the back-sideof the chip using a cryogenic-cooled InSb-based infrared

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–7970

camera. Our work is the first to validate its post-silicon powercharacterization estimates. We also trace the source of errorsusing statistical and frequency-domain analyses techniques.

� To address the difficulties encountered in realistic experimen-

tal setups, we provide novel techniques (1) to model therelationship between power and temperature, and (2) tocalibrate thermal imaging equipment to compensate for thedifferent material emissivities of semiconductor chips.

The organization of this paper is as follows. Section 2 discussesthe motivation for this work. In Section 3 we elucidate thechallenges associated with thermal to power inversion, and inSection 4 we describe our proposed methodology for thermal topower inversion that handles the outlined challenges. In Section 5we describe our proposed test chip design and modeling techni-ques. In Section 6 we provide our experimental and validationresults. Finally, Section 7 summarizes the main conclusions ofthis work.

2. Motivation

The design flow of a modern integrated circuit is highlycomplex. In a state-of-the-art custom chip, it is expected to spendabout half of the time to market in the design phase, starting witharchitecture and culminating with placement, routing, timingclosure, and meeting the power specifications. The initial designcould take more than a year, depending on complexity and IP re-use [9]. Once completed, the initial design is shipped for fabrica-tion and first silicon is received about three months later. At thispoint, the silicon still has to be debugged, nearly always requiringat least one major re-spin of the design [10]. The debug phase,including working out yield problems as volume is ramped up,can easily take as long as the initial design where in many casesthe mismatch between pre-silicon and post-silicon requires majorchanges in the design and implementation of the chip. In a widestudy from 2005, it was shown that 70% of new designs go at leastone design re-spin to fix post-silicon problems and that 20% ofthese re-spins are due to power-related issues [10]. It is likely thatthese figures are much higher now as chips are more complex asthey accommodate larger number of transistors. Popular exam-ples of large mismatches between pre- and post-silicon estimatesinclude IBM’s Cell processor, where the post-silicon power andthermal measurements led to large changes in its specificationsand implementation [11].

By performing post-silicon power validation on real chips, it ispossible to improve the final integrated circuit. The results ofpost-silicon power characterization can improve the design pro-cess during re-spins or for future designs in the following ways.

�

High-level power modeling tools rely on the use of parametersthat are estimated from empirical data [3,4]. The powercharacterization results can be used to calibrate and tunehigh-level power modeling tools. � The power characterization results can drive heat sink design.

Passive heat sinks remove heat indiscriminately from the die,and thus, their design is mainly driven by total powerconsumption. Active heat removal systems, such as thermo-electric Peltier coolers [12], can make use of the true post-silicon power characterization results to maximize their heatremoval capabilities.

� To evaluate ‘‘what if?’’ design re-spin questions, the power

characterization results can substitute the power simulatorestimates and directly feed thermal simulators. For example, ifthe thermal characterization results are unacceptable, then thelayout can be changed to reduce the spatial power densities

and hot spot temperatures. The power characterization resultsare fed together with the new layouts to a thermal simulatorto evaluate the impact of the changes.

� The post-silicon power characterization results can also force a

re-evaluation of an integrated circuit specifications (e.g., oper-ating frequencies).

The focus of this paper is to devise algorithmic and experi-mental techniques for post-silicon power mapping by usinginfrared imaging techniques, where the captured thermal emis-sions from the backside of the die are inverted to yield theunderlying spatial power maps.

3. Identified challenges in thermal to power inversion

The physical relationship between power and temperature isdescribed by the physics of heat transfer. Mainly, heat conductionby diffusion governs the relationship between power and tem-perature in the die and the heat spreader. The steady-state DCheat diffusion equation is given by

X � ðkðx,y,zÞXtðx,y,zÞÞ ¼�pðx,y,zÞ, ð1Þ

where tðx,y,zÞ, pðx,y,zÞ , and kðx,y,zÞ are the temperature, powerdensity, and the thermal conductivity at location ðx,y,zÞ respec-tively [7]. The heat transferred at the boundary between the die/heat spreader and the surrounding fluid is described by Fourier’slaw for heat transfer, and it is proportional to the temperaturedifference between the boundary of the die/heat spreader and thetemperature of the surrounding fluid (air or liquid). The constantof proportionality is the heat transfer coefficient which dependson the geometry of the heat sink, the fluid used for heat removaland its convection characteristics (e.g., speed and laminarity/turbulence) [13].

In any practical implementation, the heat equation must bediscretized. This discretization comes from the finite memory sizeof any computer and more importantly from the use of thermalimaging equipment with limited spatial resolution. In a discre-tized form, the continuous temperature signal is represented by avector t that gives the true temperatures at a discrete set of back-side die locations. The length of the vector t is determined by thespatial resolution of the infrared camera and the dimensions ofthe die. The continuous power signal is represented by a vector pthat gives the power consumption of each of the circuit’s units. Insuch case, Eq. (1) is approximated by the following linear matrixformulation:

Rp¼ t, ð2Þ

where the matrix R is a linear operator that captures the impactof all modes of heat transfer. The objective of the thermal to power

inversion problem is to find the vector p that leads to thetemperatures t. An inversion problem well-posed if it satisfiesthree conditions (first outlined by Hadamard [14]): existence,uniqueness, and stability. In the context of thermal to powerinversion, existence means that for every measured temperaturemap, there exists a power map that leads to the temperaturemap; uniqueness means that exists one and only power map thatleads to the temperature map; and stability means that smallperturbations in the temperature measurements lead to smallperturbations in the estimated power maps.

In the next two subsections, we identify and describe twomain challenges that can lead to ill-posed thermal to powerinversion problems. The first challenge arises from the physicsof heat diffusion and the second challenge arises from the physicsof noise and the technology used to perform thermal imaging.

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–79 71

3.1. First challenge: spatial filtering

The first limit in thermal to power inversion is inherent to thephysics of heat transfer. It is well-established in the literature thata chip’s temperature map is a low-pass filtered form of its powerdensity map [15,16]. While the power density can spatially varyabruptly according to the chip’s layout and application behavior,the temperature will always vary smoothly in space. This low-pass filtering effect is governed by Eq. (1). In this subsection wewill consider a 2-D die with homogenous material, i.e.,kðx,y,zÞ ¼ k, to simplify the discussions and to focus on the keyconcepts. In this case, Eq. (1) simplifies to

k@2tðx,yÞ

@x2þ@2tðx,yÞ

@y2

� �¼�pðx,yÞ: ð3Þ

The 2D Fourier transform of some function tðx,yÞ is defined by

Ftðu,vÞ ¼

Z 1�1

Z 1�1

tðx,yÞe�j2pðuxþvyÞ dx dy, ð4Þ

where u and v are variables that represent the spatial frequenciesin the x and y directions respectively. Applying the 2-D Fouriertransform to both sides of Eq. (3) gives

kð�u2Ftðu,vÞ�v2Ftðu,vÞÞ ¼�Fpðu,vÞ: ð5Þ

Thus, the power-temperature transfer function, Gðu,vÞ, is equal to

Gðu,vÞ ¼Ftðu,vÞ

Fpðu,vÞ¼

1

kðu2þv2Þð6Þ

It is clear from Eq. (6) that the higher frequency components ofspatial power maps will be subjected to greater attenuation. Thisspatial filtering phenomenon is illustrated in Fig. 1, where wecreate checkerboard power maps with increasing spatial fre-quency in a test chip and measure their emissions. The maps inFig. 1a have the same amount of total power but they differ intheir spatial frequencies. Fig. 1b gives the resultant emissionsdemonstrating that the variations are attenuated as the spatialfrequency increases. For example, the standard deviation dropsfrom 184 mK to 111 mK and 64 mK as the spatial frequency isincreased. In a simulation-based environment with double

Fig. 1. Illustrating the impact of spatial low pass filtering on the intensity and

variations of thermal emissions. (a) Power maps and (b) thermal emissions.

precision floating point numbers, attenuation is not an issue,but in real systems with physical and technological limits on theirdetectors and analog to digital converters, attenuation is a majorproblem as it degrades the signal to noise ratio. This degradationcan attenuate the signal to a level below the detection sensitivityof the infrared imaging equipment, leading to irreversible loss ofinformation. In the discrete form of the heat diffusionequation (Eq. (2)), the low-pass filtering effect implies that thereexists at least one power vector pg that belongs to the null spaceof R. If vector p satisfies Eq. (2), then pþpg also satisfies theequation. In practical terms, pg is in the null space of R, if Rpg isbelow the detection sensitivity of the imaging system. Thus, thelow-pass filtering effect could render the temperature to powerinversion problem ill-posed as the uniqueness condition isviolated.

3.2. Second challenge: noise in measurements

The second limit arises from discretization and measurementnoise introduced during infrared imaging. A number of noisephenomena could lead to errors in the measurements [17].Sources of noise include (i) dark noise caused by random genera-tion of electron-hole pairs in quantum detectors; (ii) thermalnoise caused by the agitation of charge carrier in the electronicreadout circuitry; (iii) flicker noise which is inversely proportionalto the emission frequency; and (iv) discretization errors intro-duced by the analog to digital converters of the imaging system.Mathematically, the impact of these errors can be expressed as

Rpþe¼ tþe¼ tm, ð7Þ

where the vector e denotes the errors in measurements intro-duced during imaging, and the vector tm denotes the measuredtemperatures. To understand the impact of measurement errorson the inversion problem, we will use the Singular Value Decom-position (SVD). SVD decomposes a matrix into a weighted sum ofordered matrices. That is

R¼X

i

siuivTi and R�1

¼X

i

1

siviu

Ti , ð8Þ

where the si’s are the singular values, the ui’s form a set oforthonormal vectors, and the vi’s form a set of orthonormalvectors such that Rui ¼ sivi. The operator T denotes the transposeoperation. Using the non-zero singular values of the SVD of R andEq. (7), we find that

estimated p¼R�1tm ¼R�1ðtþeÞ ¼ pþ

Xi

1

siðuT

i eÞvi: ð9Þ

Thus, small singular values amplify the impact of noise duringinversion [14]. Using Eq. (9), we can bound the error in powerestimation, dp, as follows. Since dp¼R�1e, JdpJ2rJR�1J2JeJ2,where J � J2 is the L2 norm. Thus,

JdpJ2

JpJ2r

JR�1J2JeJ2

JpJ2¼

JR�1J2JRJ2JeJ2

JpJ2JRJ2

rJR�1J2JRJ2JeJ2

JtJ2r

smax

smin

JeJ2

JtJ2, ð10Þ

where we used the fact that JRJ2 ¼ smax and JR�1J2 ¼ 1=smin [18].The ratio smax=smin is the condition number of R and it controls thepropagation of errors from the measurements to the estimatedpower. For example, if the condition number of our chip’s Rmatrix is in the order of 103 then the inversion algorithm couldtransform a tiny milli-Kelvin error – a typical number in cryo-genic thermal quantum detectors – in temperature measurementinto a significant error in power estimation. This amplificationof noise leads to ill-posed inversion as the stability condition

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–7972

is violated, where slight changes in the measured temperatureslead to the large changes in the estimated power.

Fig. 2. Tradeoff between JRp�tJ and JpJ as a function of the regularization

parameter a.

Fig. 3. Attenuation of the singular values as a function of s. The regularization

parameter a¼ 0:5.

4. Proposed methodology for thermal to power inversion

The objective of thermal to power inversion is to find the bestpower map p that minimizes the total squared error between thetrue temperatures t as computed using Eq. (2) and the measuredtemperatures; that is, minJRp�tJ2

2. As mentioned in Section 3,this objective is challenging to achieve because (1) spatial filteringcould lead to ill-posed inversion with a singular or ill-conditionedmatrix R and (2) measurement noise can deviate tm from the truetemperature t. To address these two challenges, we propose twotechniques. We introduce regularization theory techniques toimprove the numerical stability of R and to reduce the impactof measurement noise, and we introduce constraints on thesolution space to reduce the possibility of getting a wrongsolution due to the existence of a null space for R. We explainthe details of these two techniques in the rest of this section.

To reduce the impact of measurement noise and the potentialill-posed nature of the problem, we propose techniques fromregularization theory [14]. Regularization techniques consider afamily of approximate solutions using a positive parameter calledthe regularization parameter. When the measured thermal data isnoise-free, the solution converges to the true power solution asthe regularization parameter goes to zero. Tikhonov regularization

finds the power solution that gives the least total squared errorwhile simultaneously minimizing the L2 norm; that is,

pa ¼ argp

minJRp�tmJ22þaJpJ2

2, ð11Þ

where a40 is the regularization parameter that controls theminimization emphasis between the two terms of the objectivefunction [19]. The first term JRp�tmJ2

2, which gives the totalsquared error, controls how well the power estimates, p, lead totemperatures that match the measurements (which could benoisy). If the value of this term is large then the solution is farfrom the true power, but a small value for this term could lead toa fitting that is driven by noise. The second term JpJ2

2 controls theregularity of the solution. Large values for this term could lead tosolutions that are dominated by high-frequency measurementnoise. Using one of our captured thermal traces, the trade-offbetween the two terms as a function of a is illustrated in Fig. 2.Increasing the value of a traces the curve from the top-left cornerto the lower-right corner, and thus the trade-off curve is typicallyreferred to as the L-curve [19]. Small values for a can lead tosolutions dominated by noise, while large values for a leads tomore regularized solutions.

To develop further insight into the role of the regularizationparameter a, we utilize the SVD, but it is first necessary to re-castthe objective of Eq. (11) as a least squares problem as follows:

pa ¼ argp

minRffiffiffiap

I

!p�

tm

0

� �����������

2

2

: ð12Þ

Thus, the solution to the least square estimation problem is

Rffiffiffiap

I

!TRffiffiffiap

I

!pa ¼

Rffiffiffiap

I

!Ttm

0

� �,

pa ¼ ðRT RþaIÞ�1RT tm: ð13Þ

The SVD expansion of Eq. (8) can be written as R¼USVT ,where U and V are unitary matrices formed from the ui and vi

vectors respectively, and S is a diagonal matrix with the diagonalelements are the non-zero singular values si. Using the SVD,

Eq. (13) can be further analyzed as follows:

pa ¼ ðVST UT USVTþaVIVT

Þ�1VST UT tm ¼VðST SþaIÞ�1ST UT tm

¼ V diags2

i

s2i þa

�1

si

!UT tm ¼

Xi

1

si

s2i

s2i þa

viuTi tm: ð14Þ

Comparing Eq. (14) against Eq. (9), we find that each singularvalue in the SVD decomposition of Eq. (9) is multiplied by a factors2

i =ðs2i þaÞ known as Tikhonov attenuation factor [20,19]. Fig. 3

gives the value of the Tikhonov attenuation factor s2i =ðs

2i þaÞ as a

function of the singular value si for a¼ 0:5. The figure shows thatthe attenuation factor essentially functions as a filter function thatfilters out singular components that are small relative to a andpasses singular components that are large relative to a [20].Singular values of zero value are totally eliminated. The attenua-tion of the small singular components makes the inverse problemmore well conditioned and controls the error propagation asgoverned by Eq. (10). Good values for a can be found byinspecting the L-curve. One possibility is to the use the corner ofthe curve [19]. The corner is the point on the L-curve with themaximum curvature. In Fig. 2 the corner occurs at a is equalto 1.6.

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–79 73

To reduce the possibility of getting a wrong solution due to theexistence of a null space for R, we introduce additional con-straints on the solution space. One possible constraint is that thesum of the elements of the power map must be equal to the totalpower consumption of the chip ptotal and that these elements arenonnegative; i.e.,

JpJ1 ¼X

i

pi ¼ ptotal and pZ0, ð15Þ

where J � J1 is the L1 norm and ptotal is the total power consump-tion of the chip which could be measured externally using adigital multimeter. Thus, if multiple solutions exist, then thesolution with least total power error is chosen. Note that becausethe total (and average) power is constrained by Eq. (15), theregularization term in Eq. (11) controls the variance in spatialpower estimates. In practice, any digital multimeter has a toler-ance, tol, in its measurements (the tolerance is typically listed inthe multimeter’s data sheet), and thus it is better to replace theconstraint of Eq. (15) by the following constraints:

JpJ1rptotalþtol, ð16Þ

JpJ1Zptotal�tol, ð17Þ

and

pZ0: ð18Þ

Our overall inversion methodology is summarized in thealgorithm given in Fig. 4.

Comparison to previous approaches: Previous numericalapproaches in thermal to power inversion mainly focused onminimizing the total squared error between the temperaturescomputed from the power estimates and the thermal measure-ments [21,2,8]. These approaches can produce suboptimal resultsas they ignore the ill-posed nature of the problem wheremeasurement noise and spatial diffusion reduce the accuracy ofpower estimation. Compared to previous approaches, our

Fig. 4. Proposed thermal to power inversion methodology.

6

10

10

Two Levels 0mW

25mW

Fig. 5. Grid of microprogrammable heaters. (a) Grid of bi-leve

proposed numerical techniques handle many of the challengesassociated with inversion. We introduce regularization theory toreduce the impact of noise and improve the numerical instabilityin the model matrix R by eliminating zero singular values andfilter small singular values. We also introduce constraints onthe solution space to eliminate the possibility of gettingmultiple solutions. Our constraints are customizable accordingto the tolerance associated with electrical current measurementequipment.

5. Test chip design and modeling

One of our main research goals is to assess the accuracy ofthermal to power inversion. Previous studies [2,8] presented spatialpower estimates for the different processor blocks ‘‘as is’’ [2,8]. Noneof the previous studies provided a thorough validation for theaccuracy of their spatial power estimations. This lack of validationis the result of the experimental setup that previous studies chose.Earlier experimental setups used general-purpose processors (a dualcore PowerPC 970MP [2] and an AMD Athlon 64 processor [8]) inwhich it is impossible to fully control the underlying spatial powerconsumption, and there exists no alternative means to verify thespatial power maps. To address this issue, we designed our experi-mental test chip with special emphasis on the ability to estimate thespatial power consumption through two different means, and hencewe are able to provide estimations for the accuracy of our proposedpower characterization methodology.

5.1. Test chip design and implementation

The basic unit of our circuit is a programmable micro-heater,which consists of a number of ring oscillators (ROs) that arecontrolled by flip-flops that determine the operational status ofthe micro-heater. We create two kinds of micro-heater designs:

1.

l mi

Bi-level micro-heaters: A bi-level micro-heater consists of nine15-stage ROs together with one flip-flop that controls theiroperational status. If the D Flip-flop (DFF) holds a binary valueof 1 then the heater is turned on; otherwise, it is turned off.When enabled, each micro-heater consumes 25 mW. Using theprogrammable heater, a grid that consists of 10�10 micro-heaters is created as shown in Fig. 5a. In the grid structure, theoutput of each DFF is connected to the input of the DFF of theconsecutive heater forming a scan chain.

2.

Multi-level micro-heaters: A multi-level micro-heater consists ofROs that can be programmed to one of the following configura-tions: 9 51-stage ROs with a power consumption of 25 mW; 1825-stage ROs with a power consumption of 60 mW; 27 19-stageROs with a power consumption of 102 mW; and 36 13-stage ROswith a power consumption of 142 mW. Thus, each micro-heater

6

Five Levels 0mW

25mW60mW

102mW142mW

cro-heaters and (b) grid of multi-level micro-heaters.

9.8 mm

8.8 mm

7.9 mm

7.2 mm

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–7974

block offers five different power levels: 0, 25, 60, 102, and142 mW. The DFFs associated with each micro-heater determineits status. Using the programmable micro-heater blocks, a gridthat consists of 6�6 blocks is created as shown in Fig. 5b. In thegrid structure, the output of each DFF is connected to the input ofthe DFF of the consecutive heater forming a scan chain.

In both designs, the advancements of the programming bits inthe chain is controlled by the clock signal. To create any desiredpower pattern, we inject control bits into the flip-flops of themicro-heaters to selectively turn on the micro-heaters thatcorrespond to the required power pattern. Our experimentalnovelty of using a chip of programmable micro-heaters enablesus to achieve the following two experimental goals which havenot been attained in previous works:

Fig. 6. Implementation areas in Altera Stratix II EP2S180 device. (a) Die section for

10�10 grid and (b) die section for 6�6 grid.

1. The grid structure of the micro-heaters, where every micro-

heater can be selectively controlled, enables us to create anydesired spatial power map on a real chip. Previous works usedprocessors in which independent control of various processorblocks is infeasible. The programmable nature of the gridenables the generation of a large number of different mapsthat can be used to test the accuracy of the thermal to powerinversion methodology.

2.

Fig. 7. Measuring the power to thermal inversion matrix R using a sliding window

of power pulses. (a) Sliding window of power pulses and (b) temperature maps

after emissivity calibration.

The regular and homogenous structure of the micro-heatergrid enables us to estimate the power consumption of eachmicro-heater by simply measuring the total power consump-tion of the grid and dividing it by the number of enabledmicro-heaters. The locations of the enabled heaters are knownby construction. Hence, we are able to construct the spatialpower map through an alternative path to infrared emissions.Previous works lacked this ability to validate their spatialpower estimations through different means.

For implementation, we choose a 90 nm Altera Stratix II(EP2S180) field programmable gate array (FPGA) with 180,000logic elements with total die dimensions of 23 mm�24 mm. Theregular fabric of the FPGA ideally fits our design. For our experi-ments, we use a relatively homogenous section of the die thatspans 7.2 mm�7.9 mm for the bi-level 10�10 grid as shown inFig. 6a, and a section that spans 8.8 mm�8.9 mm for the multi-level 6�6 grid. The micro-heater blocks are mapped to the logicarray blocks at the precise grid locations using Altera’s Quartus IIplacement assignment editor. In order to capture the chip’sthermal emissions it was necessary to remove the heat spreader.While removing the heat spreader is going to change the spatialthermal behavior, the change in spatial thermal emissions doesnot change the underlying dynamic power consumption (fCV2)[22], which is weakly dependent on temperature. The spatialpower consumption remains relatively intact, and the new inter-actions between temperature and power are captured in thelearned R matrix as described in the next paragraph.

5.2. Measuring operator matrix (R) of the test chip

Given the test chip, it is necessary to measure the operatormatrix R. The matrix R can be measured in a column-by-columnbasis as follows. Enabling only one micro-heater at a time ismathematically equivalent to setting the vector p to be equal to½0 � � � pk � � � 0�T , where pk is the power consumption of the kthenabled block. For each micro-heater location, we enable theselected micro-heater as shown in Fig. 7a and record the emittedtemperatures across the field as shown in Fig. 7b. If tk denote thethermal emissions captured from enabling the kth micro-heater,then column k of matrix R is equal to tk=pk. We automate the

whole process in order to measure the columns of R with fastturn-around time.

We utilized the programmability of FPGAs to estimate themodel matrix R. In custom chips with generic designs, the matrixR can be estimated in the same conceptual way but through adifferent implementation approach [2,8]. One approach is to turnoff the chip, and scan a laser beam with known power density todeliver the power from the outside to the regions of interest. Thescanning of the laser system can be automated by using a pair ofgalvo-directing mirrors [2]. Our method uses the programmablenature of our design to get the same results of the expensive laserscanning system but in a much cheaper way. Another approach isto use the actual design and layout of the chip to conduct a fluiddynamic simulation coupled with a heat diffusion simulation toestimate the matrix R [2,8].

There is always a possibility that errors might occur during theestimation of R. If R is estimated from direct measurement, thenmeasurement noise can introduce errors, and if R is estimatedfrom simulations, then unrealistic simulation assumptions canlead to errors. Our experimental results in the next section showthat the overall power estimation error arising from our inversionprocedure is relatively small.

6. Validation and experimental results

To test our post-silicon power characterization methodology,we put together the following experimental setup which is shownin Fig. 8.

�

To capture the thermal emissions from the back-side of ourdie, we use a FLIR SC5600 infrared camera with a mid-wave

infrared camera

thermocoupleFPGAfan

multimeter data acquisition workstation

Fig. 8. Experimental setup showing the different equipment that make up our

measurement system.

Fig. 9. Relationship between camera’s digital levels and temperatures for two

pixels.

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–79 75

spectral range of 2:525:1 mm. The camera is capable ofoperating at 100 Hz with a spatial resolution of 30 mm with a0.5� microscopy kit. Silicon is transparent to infrared emis-sions in the 1:525:1 mm range with a 55% transmittance. Thus,the infrared camera can measure the temperature through thechip under test [8]. The camera’s cyrogenic cooled InSbdetectors have a sensitivity of about 15 mK noise equivalenttemperature difference (NETD).

�

Fig. 10. Thermal images before and after emissivity calibration. (a) Digital levels

without emissivity calibration and (b) temperature after emissivity calibration.

1 For high-power chips, thermally controlled infrared transparent oil can be

used to force the isothermal status. Interested readers are referred to our earlier

publication for oil-based setup [24].

We use an Agilent E3634A power supply to supply andmeasure the total power consumption of FPGA chip.

6.1. Thermal calibration

Measuring the temperature is slightly complicated because aninfrared camera is really a photon detector that measures theinfrared radiation intensity at different parts of the chip. Thus, it isnecessary to convert photon measurements recorded by thecamera to temperatures. One problem is that radiation intensityis not constant among different materials even if they are at thesame temperature. Perfect radiation emitters are black bodies withan emissivity of 1. The emissions of real materials are a fraction ofthe black-body level, and each material is characterized with anemissivity value, which is defined as the ratio of that material’sthermal emission to that of a perfect black-body at the sametemperature [17]. As integrated circuits are comprised of amixture of different materials (e.g., copper, silicon and dielectrics)with varying spatial material densities, the radiation intensities ofdifferent parts of the chip could be different even if the chip isheld at isothermal temperature by external means.

To handle the emissivity problem, previous approaches coatedthe backside of the die with a material of constant emissivity [2].The downside of this approach is that it obstructs the silicontransparency and only measures the heat emissions resultingfrom the projections of the internal emissions on the backside ofthe die. Previous approaches were thus forced to thin the backsidesilicon to reduce the amount of internal projections. To get a moreaccurate thermal imagery, we avoid coating the backside of thesilicon and instead devise a pixel-by-pixel calibration process thattranslates the captured emissions (as measured by the digitallevels of the camera’s A/D converters) to temperatures.

The relationship between the digital level Di and temperatureti of a pixel i can be modeled by an exponential function

Di ¼ aiebiti , ð19Þ

where ai and bi are per-pixel coefficients that are function ofmany factors including emissivity, path to length, and integrationtime [23]. The exponential relationship arises from the physics ofphoton detectors in which the current of an infrared-sensitivediode depends exponentially on the incident radiation. If therewere no emissivity differences between the different pixels thenai and bi would be chip-wide constants, but instead they must becomputed for each pixel. For example, Fig. 9 shows two curvesrelating the temperatures to the measured digital levels for twodifferent pixels on the test chip. Our pixel-by-pixel calibrationprocedure is simple. We first turn the test chip off and then forceit to an isothermal status through external means,1 and thenmeasure the temperature of the chip through a thermocouple asshown in Fig. 8. Two thermocouples placed at opposite ends ofthe die could be used to verify chip-wide steady-state attainment.Once steady-steady is reached, the digital levels of all pixels arecaptured using the camera. This process is repeated for a fewtemperatures and then the calibration curves (as the ones given inFig. 9) are constructed, and the ai and bi for every pixel i are foundthrough curve fitting. Fig. 10 contrasts the raw digital thermallevels before calibration and the thermal images after calibration.The images show that the calibration process successfullyremoves imaging artifacts introduced by emissivity variation.

We conduct and report the results of four experiments:

1.

The first experiment compares the estimation accuracy of ourproposed method against previous techniques using the bi-

0.0% / 0 0.0% / 0 0.0% / 012.8% / 6

0.0% / 0 4.9% / 2 0.0% / 014.9% / 7

Fig. 11. Accuracy of estimating arbitrary power maps using thermal emissions. (a) Injected power patterns, (b) resultant temperature measurements, (c) estimated power

maps using previous methods, and (d) estimated power maps using proposed method.

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–7976

level micro-heater block grid. We analyze the sources of errorsusing statistical and frequency-domain techniques.

2.

The second experiment assesses the effectiveness of ourmethod using random spatial maps constructed using the bi-level micro-heater grid.

3.

The third experiment evaluates the accuracy of our powerestimation method as a function of the spatial frequency of thepower maps.

4.

The fourth experiment assesses our power mapping methodusing the multi-level micro-heater block grid. We demonstratethat our method is capable of handing underlying power mapswith various intensities and spatial constructions.

Experiment 1. In the first experiment we assess the accuracy ofour thermal to power inversion methodology by evaluating itspower estimates for a number of reference spatial power mapsgenerated using the bi-level micro-heater grid. The locations ofthe activated micro-heaters of these maps are illustrated inFig. 11a, and the measured temperature maps after emissivitycalibration are illustrated in Fig. 11b. Given our low-power micro-heater designs, the temperature range, i.e., the difference betweenthe maximum temperature and the minimum temperature ineach map, is about 1.5–2 1C. The power maps estimated by justminimizing total squared error as proposed by previousapproaches [2] are given in Fig. 11c; and the estimated powermaps from our methodology are given in Fig. 11d. The powermapping results in Fig. 11c and d are rounded to the nearestpower level. We report the estimation error in percentage which isequal to the sum of the absolute differences between the powerestimates and their true values divided by the total power. The

average error from using previous approaches is 4.95%, while theaverage error from using our proposed approach is 1.5%. We alsoreport the number of block heaters that were not estimatedcorrectly (either turned on and estimated to be off or vice versa).Previous techniques give a total of nine incorrectly estimatedblocks, whereas our technique give six incorrectly estimatedblocks for reduction of 30%. By visually comparing the injectedpower maps and the estimated maps, we notice that our techni-que recovers the injected maps to a very good extent.

To understand the source of errors, we conduct the following

two analyses. First, we simulate the resultant temperatures if the

true power maps are used as inputs; the simulation is basically

the result of multiplying the injected power maps by the matrix

R. We plot in Fig. 12a the residual error between the measured

temperatures and the simulated measurements. We verify that

the errors form a normal distribution using the Kolmogorov–

Smirnov test, and we compute the standard deviation for each

residual distribution. The standard deviations are given as labels

(s) in Fig. 12a. For instance, the first pattern, which has an error of

2.0% in its power map estimates, has a residual standard deviation

of 9 mK which means that the large majority of errors (97%) are

between 718 mK. The residual errors fall within the sensitivity

limitation (15 mK) of our camera detectors. The first pattern has

the highest standard deviation in residuals which implies that it

had the highest amount of noise. Our second analysis technique

computes Discrete Cosine Transform (DCT) of the true power

maps and report them in Fig. 12b (the top-left corner is the lowest

frequency). The DCT quantifies the spatial frequencies of an input

power map. For each power map, we compute the percentage of

σ = 9 mK σ = 8 mK σ = 8 mK σ = 7 mK

energy = 25% energy = 30% energy = 35% energy = 30%

Fig. 12. Analysis of errors of maps in Fig. 11. (a) Residual error and (b) DCT transform of power maps.

2.1% / 1

0.0% / 0

15.7% / 8

11.8% / 6

Fig. 13. Accuracy of estimating spatial power estimates from thermal emissions of

random power maps. (a) Injected power patterns, (b) resultant temperature

measurements, (c) estimated power maps using previous methods, and

(d) estimated power maps using proposed method.

energy = 24%

σ = 8 mK σ = 18 mK

energy = 38%

Fig. 14. Analysis of errors of maps in Fig. 13. (a) Residual error and (b) DCT

transform of power maps.

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–79 77

the power signal energy that is present in higher frequencies of

the DCT.2 The third pattern, which has 12.8% error in its power

map estimates, has the largest amount of energy, 35%, in the high-

2 The energy of a signal is the sum of squares of its frequency-domain

coefficients. We compute the energy in coefficients with frequencies Z7 and

divide the result by the total energy.

frequency range. Thus, we attribute the power estimation error to

such high-frequency energy content.

Experiment 2. In the second experiment we use random spatialpower maps for testing our methodology. In addition to the mapsof Experiment 1. The use of random maps provides a morecomplete assessment of our proposed method. In Fig. 13a weprovide the random maps tested, and the resultant thermalimages are provided in Fig. 13b. Fig. 13c gives the resultantpower maps from previous techniques, while Fig. 13d gives theresults from using our inversion methodology. The results showestimation errors of 0% and 11.8% from our techniques versus2.1% and 15.7% from previous techniques. We also report thenumber of block heaters that were not estimated correctly.Previous techniques give a total of 9 incorrectly estimated blocks,whereas our technique give six incorrectly estimated blocks forreduction of 30%. Overall, the results of experiments 1 and 2 showan average error of about 4.4% from our techniques versus 6.6%from previous techniques, where our technique gives a total of 13incorrectly estimated blocks and previous techniques give 19incorrectly estimated blocks. Thus, our technique gives 31%improvement in power mapping.

To further understand the reason for the errors in some of themaps, we conduct analyses similar to the ones of Experiment 1.First, we compute the residual error between the simulated

error = 0.00%error = 4.76% e

Fig. 17. Results from multi-level power estimation. (a) Constructe

Increased horizontal spatial frequenc

Incr

ease

d ve

rtica

lsp

atia

l fre

quen

cy

Fig. 16. DCT of chec

Error = 0.0 % Error = 0.0 % Error = 11.5 %

Fig. 15. Impact of increasing spatial frequencies of power maps on the accuracy

of thermal to power inversion. (a) Power patterns with increasing spatial

frequencies, (b) Resultant temperature measurements, and (c) estimated power

patterns.

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–7978

temperatures and the measured temperatures and plot the resultsin Fig. 14a. We verify that the errors form a normal distribution,and we compute the standard deviations for the distributionswhich are given as labels (s) in Fig. 14a. For instance, the secondpattern, which has a large error of 11.8% in its power mapestimates, has a residual standard deviation of 18 mK. Second,we compute the Discrete Cosine Transform (DCT) of the truepower maps and give them in Fig. 14b (the top-left corner is thelowest frequency). Again, the second pattern shows the largestamount of energy, 38%, in its higher-frequency components. Thus,we attribute both the noise and high-spatial frequencies to thelarge error in power estimation.

Experiment 3. To further gain insight into the behavior ofthermal to power inversion, we assess the accuracy of ourmethodology as a function of the spatial frequency of powermaps. As discussed earlier in Section 3, the nature of heatconduction on chips leads to a low-pass filtering effect. Hence,we create checker-board maps of increasing spatial frequencies asillustrated in Fig. 15a, which lead to the thermal emissionsillustrated in Fig. 15b. The estimated spatial power maps aregiven in Fig. 15c. The average errors are: 0.0%, 0.0%, and 11.5%. Toprovide further analysis into the source of error, we plot the 2-DDCT of the power maps in Fig. 16. The figures clearly show thetrend of increased frequencies in the power pattern, where thethird pattern has the highest frequency and error. The resultsagree with our earlier discussions in Section 3 that concluded that

mW

mW

rror = 1.81% error = 3.10%

d circuits, (b) thermal images, and (c) estimated power maps.

y

kerboard maps.

S. Reda et al. / INTEGRATION, the VLSI journal 46 (2013) 69–79 79

increasing the spatial frequencies of power maps can lead to adeterioration in the accuracy of thermal to power inversion due tothe impact of low pass filtering.

Experiment 4. In this experiment, we provide results using themulti-level micro-heater grid design. In contrast to the first threeexperiments where the power of each micro-heater was onlyrestricted to two levels (0 and 25 mW), the micro-heaters in theconstructed spatial power maps of this experiment have powerlevels of multiple intensities (0, 25, 60, 102, and 142 mW). Ourinversion procedure can naturally handle any number of levels,and the results of this experiment confirm this capability. Fig. 17agives the constructed multi-level power maps. The resultantthermal maps are given in Fig. 17b, and the estimated powermaps from our inversion procedure are given in Fig. 17c. Thepower mapping results are rounded to the nearest power level.The power estimation errors of the four maps are 4.76%, 0.00%,1.81% and 3.10%, with an average of 2.41%. The magnitudes of thepower estimation errors from the multi-level power mappingexperiment are comparable to the magnitude of the errors in thefirst three experiments using bi-level micro-heaters. The results ofthis experiment confirm that our technique is capable of handling alarge range of power intensities and spatial power maps.

7. Conclusions and future work

In this paper we have presented a new methodology for spatialpost-silicon power characterization using the infrared emissionsfrom the back of the silicon die. We have elucidated the variouschallenges that underlie thermal to power inversion. We havedemonstrated mathematically and experimentally how low-passfiltering, discretization, and measurement errors could all compro-mise the accuracy of power estimation. We have proposed newtechniques from regularization theory to improve the accuracy oftemperature to power inversion. Furthermore, we have providedexperimental techniques to compensate for the varying emissivity ofdifferent chip materials and to measure the thermal resistancemodel matrix. We designed a highly modular, programmable testchip to create sets of known power maps. Our test chip and realisticinfrastructure enabled us to validate our methodology by comparingits power estimates against the known injected spatial power maps.Compared to previous approaches, our experiments demonstrateconsistent improvement in power estimation accuracy where weimprove the power mapping accuracy by 30%. We have alsoanalyzed the residual errors between the simulated temperaturesand the measured temperatures to understand the error sources.Our statistical and frequency-domain analyses quantify the roles ofnoise and spatial filtering on the accuracy of power estimates.

For future work, we will extend our approach to handle transientanalysis. The relationship between temperature and power intransient analysis can be described using state space models. Inparticular, the temperature vector t½kþ1� at time kþ1 is linked tothe temperature vector t[k] at time k and the power consumptionp[k] at time k by t½kþ1� ¼At½k�þBp½k�. Transient analysis can followa similar approach to the one described in this paper, where t½kþ1�and t[k] are measured using the camera, and A and B are learned ina similar way to the approach used to learn R.

Acknowledgments

This work is partially supported by a DoD ARO grant numberW911NF-09-1-0320, NSF grants number 1115424 and 0952866,

and an equipment grant from Altera corporation. We would liketo thank J. Renau from UCSC for the insights on the setup ofinfrared imaging systems, J. Mundy from Brown University for thehelpful discussions on inversion problems, P. Temple from BrownUniversity for constructing an acquisition system to automatedata collection, and the anonymous reviewers who helpedimprove the contents of this paper.

References

[1] R. Cochran, A. Nowroz, S. Reda, Post-silicon power characterization usingthermal infrared emissions, in: International Symposium on Low PowerElectronics and Design, 2010, pp. 331–336.

[2] H. Hamann, A. Weger, J. Lacey, Z. Hu, P. Bose, Hotspot-limited microproces-sors: direct temperature and power distribution measurements, IEEE Journalof Solid 42 (2007) 56–65.

[3] D. Brooks, V. Tiwari, M. Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, in: International Symposium onComputer Architecture, 2000, pp. 83–94.

[4] M. Powell, A. Biswas, J. Emer, S. Mukherjee, CAMP: a technique to estimateper-structure power at run-time using a few simple parameters, Interna-tional Symposium on High Performance Computer Architecture 44 (2009)289–300.

[5] A. Srivastava, R. Bai, D. Blaauw, D. Sylvester, Modeling and analysis of leakagepower considering within-die process variations, in: International Sympo-sium on Low Power Electronics and Design, 2002, pp. 64–67.

[6] C. Isci, G. Contreras, M. Martonosi, Live, runtime phase monitoring andprediction on real systems with application to dynamic power management,in: International Symposium on Microarchitecture, 2006, pp. 359–370.

[7] M. Pedram, S. Nazarin, Thermal modeling, analysis, and management in VLSIcircuits: principles and methods, Proceedings of the IEEE 94 (8) (2006)1487–1501.

[8] F.J. Mesa-Martinez, M. Brown, J. Nayfach-Battilana, J. Renau, Measuringperformance, power, and temperature from real processors, in: InternationalSymposium on Computer Architecture, 2007, pp. 1–10.

[9] B.P. Colwell, The Pentium Chronicles: The People, Passion, and Politics BehindIntel’s Landmark Chips, Wiley-IEEE Computer Society, 2005.

[10] G. Spirakis, Designing for 65 nm and Beyond: Where is the Revolution? in:Electronic Design Process (EDP) Symposium, 2005.

[11] H. Hamann, Personal communication, 2010.[12] A. Shakouri, Nanoscale thermal transport and microrefrigerators on a chip,

Proceedings of the IEEE 94 (2006) 1613–1638.[13] W. Huang, K. Skadron, S. Gurumurthi, R.J. Ribando, M.R. Stan, Differentiating

the roles of IR measurement and simulation for power and temperature-aware design, in: International Symposium on Performance Analysis ofSystems and Software, 2009, pp. 1–10.

[14] M. Bertero, P. Boccacci, Introduction to Inverse Problems in Imaging, Institute

of Physics Publishing, 1998.[15] K. Etessam-Yazdani, M. Asheghi, H. Hamann, Investigation of the impact of

power granularity on chip thermal modeling using white noise analysis, IEEE

Transactions on Components and Packaging Technologies 31 (2008)211–215.

[16] W. Huan, M.R. Stan, K. Sankaranarayanan, R.J. Ribando, K. Skadron, Many-core design from a thermal perspective, in: Design Automation Conference,

2008, pp. 746–749.[17] A. Rogalski, K. Chrzanowski, Infrared devices and techniques, Opto-Electro-

nics Review 10 (2002) 111–136.[18] G. Strang, Computational Science and Engineering, 1st ed., Wellesley-

Cambridge Press, 2007.[19] P.C. Hansen, Discrete Inverse Problems: Insight and Algorithms, Society for

Industrial and Applied Math, 2010.[20] C.R. Vogel, Computational Methods for Inverse Problems, Society for Indus-

trial and Applied Math, 2002.[21] H. Hamann, A. Weger, J. Lacey, E. Cohen, C. Atherton, Power distribution

measurements of the dual core PowerPC 970MP Microprocessor, in: IEEE

International Solid-State Circuits Conference, 2006, pp. 2172–2179.[22] J. Renau, personal communication, 2009.[23] C. Hsieh, C. Wu, F. Jih, T. Sun, Focal-plane-arrays and CMOS readout

techniques of infrared imaging systems, IEEE Transactions on Circuits andSystems for Video Technology 7 (1997) 594–605.

[24] R. Cochran, S. Reda, Consistent runtime thermal prediction and controlthrough workload phase detection, in: Design Automation Conference,2010, pp. 62–67.