pmic homework
DESCRIPTION
PMICTRANSCRIPT
HOMEWORK #1
Design library/tutorial will be provided separately
1. Simulate (cadence or PSpice) the I-V curves of a 60000um/0.6um PMOS used in an LDO. Extract the following answers from the simulation or analytical calculation:
a. For a given output voltage of 3V, what is the relationship between dropout
voltage and load current? b. For a given output voltage of 1.5V, what is the relationship between dropout
voltage and load current? c. What is the maximum load current if Vin=4V, Vout=3V?
2. For the above pass transistor, construct and add an error amplifier similar to that shown in slide #18 of LDO-AC Performance. Assume, Co=4.7uF, Cb=0.47uF, Vin=4V, Vout=3V, Vref=1V. Load=50mA. Study the range of Resr that provides the best phase margin. Plot a number of loop gain (for each Resr) bode plots to prove your work. Indicate on the final bode plot where is P1, P2, P3 and Z1.
3. Simulate a load transient response to LDO’s output. Assume a load current waveform as follow. Plot the output voltage waveform.
10ns 1ms 10ns
10μA
30mA
Iload10μA
I vs Vds Plots for Vgs= 1V, 2V, 3V & 4 V.
Name
M5: 5.93237A 1.025502V
M4: 5.834393A 2.984392VM3: 680.7692mA 2.999647V
M2: 1.104A 1.000442V
/Vout ...")-v("/Vout" ?result "dc")
1
4
0
3V
(V
) 2
dc (A)0.0 5.02.5 7.5 10.0
DC Response
Name
M7: 9.724A 2.513606V
M8: 9.7A 1.488667V
M6: 357.1429mA 2.499828V
M10: 385.7143mA 1.500172V
/Vout ...")-v("/Vout" ?result "dc")
V (
V)
3
1
-1
4
0
2
0.0 2.5 5.0 12.5dc (A)
7.5 15.010.0
DC Response
Phase margin is shifted by 180 degs duw to the Iprobe used
Phase margin is shifted by 180 degs duw to the Iprobe used
100.0LO
OPG
AIN
(dB
)
-100.0
-50.0
0.0
-150.0
-200.0
-250.0
50.0
107
10-2
105
100
101
109
10-3
1010
106
103
102
10-1
104
freq (Hz)10
8
Loop...dB20
Name
M4: 376.4936m 49.08149Deg
Phase Margin 50.0
-10.0
30.0
40.0
10.0
20.0
0.0
Deg
(D
eg)
1.00.0Resr
.8.2 .4 .6
Phase Margin
Phase margin is shifted by 180 degs duw to the Iprobe used
Name
M3: 367.53904m 49.114859Deg
Phase Margin
49
45
46
50
Deg
(D
eg)
48
44
47
400.0250.0 350.0300.0 500.0Resr (m)
450.0
Stability Response
M12: 588.8437kHz 33.11013deg
M9: 82.1686Hz 152.2898degM11: 128.1422kHz 45.86536deg
M10: 7.720959kHz 44.36189deg
Loop Gain Phase
-400.0
LOO
PGA
IN (
deg)
0.0
-500.0
100.0
-300.0
-100.0
-200.0
200.0
M8: 504.5929kHz -6.551269dB
M1: 91.52473Hz 86.56511dB
M7: 124.1989kHz 8.537669dB
M6: 7.696643kHz 50.24965dB Loop Gain dB20
-50.0
LOO
PGA
IN (
dB)
-250.0
-150.0
100.0
0.0
-100.0
50.0
-200.0
Name
10-2
10-1
101
106
100
102
105
freq (Hz)10
810
1010
-310
410
910
310
7
Stability Response
Pole 2
Zero 1
Pole 3
Pole 1
Phase margin is shifted by 180 degs duw to the Iprobe used
M4: 2.9806017ms 3.0032031VM5: 153.4956us 3.0031704V
M3: 505.70162us 2.968434V
M1: 510.2444us 3.0062121V
M2: 1.5002884ms 3.0111647V
/Vout /I1/PLUS
35.0
25.0
30.0
-5.0
10.0
15.0
20.0
5.0
I (m
A)
0.0
2.98
2.97
V (
V)
3.01
2.96
3.0
2.99
3.02Name Vis
1 2 4time (ms)
0 3 5
Transient Response