pld
TRANSCRIPT
![Page 1: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/1.jpg)
Programmable Logic Devices
![Page 2: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/2.jpg)
What is Programmable Logic?Circa 1970 -- TTL Design
Y A BC
Design a logic circuit that implements the function
74HC08
74HC32
74HC04
Design is done “by hand” using TTL DataBook. Verification is performed using a “breadboard.”
![Page 3: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/3.jpg)
TTL DesignA
Y
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
74HC04
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
74HC08
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
+5V
74HC32
BC
We need three separate Dual Inline Package (DIP) TTL packages to implement this design in hardware. Note, because of the multiple components this design consumes power, board space is costly, hard to debug and manufacture.
![Page 4: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/4.jpg)
PLD DesignIn programmable logic device (PLD) design, we use a computer aided design (CAD) software tool to perform “design entry.” We can also use the same package for “design verification” and also to “download” the “design program” into hardware (i.e. the PLD). Our designnow becomes:
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
EPM7032
ABCY
+5V
This single chip design requiresLess power, less board space, should cost less on a per gatebasis, is easier to debug (in software),and be easier to manufacture. Also,Intellectual Property (IP) can be protected and exploited using a FPLD.
![Page 5: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/5.jpg)
Benefits of PLD Design1. Increased system performance (Speed)
This is due to the reduced interconnect distances between gates. In a TTL design we have large RC delays as we propagate signals from one chipto another. In PLD designs, this distances are in the um range.
A
Y
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
74HC04
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
74HC08
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
+5V
74HC32
BC
Large Delay on this net
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc1
0
a11
a22
3a3
4a4
b1
b2
b3
b4
5
6
7
8GND
0
EPM7032
ABCY
+5VFPLD Design
The same netis now internalto the FPLD
![Page 6: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/6.jpg)
Benefits of PLD Design2. Increased Gate Density
More logic gates on each PLD implies that you can have more functionality per unit area of board space. A single PLDs/FPGAs can hold the equivalent of over 1 million TTL logic gates.
3.Reduced Development Time CAD tools significantly reduce the development time
for new designs. This not only cuts down the “time to market,” but also allows reduces the size of the team needed to complete a design.
![Page 7: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/7.jpg)
Benefits of PLD Design4.Rapid Hardware Prototyping Hardware prototyping is greatly simplified using PLDs
because it is relatively easy to change the design. One major concern however is I/O pin assignments.
5.Reduced “Time to Market” Since PLDs are already “complete,” there is no need to
wait for fabrication.
![Page 8: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/8.jpg)
Benefits of PLD Design6. Future Modifications Since PLDs can be “reconfigured” in the field. It
is possible to have the end user perform system “upgrades.”
7. Reduced Development Costs The development costs for FPLDs tend to be
lower than Application Specific Integrated Circuits (ASICs); however, the per unit cost of a FPLD is higher than an ASIC for large volumes.
![Page 9: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/9.jpg)
Why not a Microprocessor?1. Unlike a Microprocessor, a PLD implements real
logic gates
2. PLDs can operate very fast
3. PLDs can do more than one thing at a time – a single micro can only pretend to do more than one thing at a time
![Page 10: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/10.jpg)
Classifying Three Basic PLDs
Fixed AND planeFixed AND plane(decoder)(decoder)
Programmable Programmable OR planeOR plane
ProgrammableConnections
(Programmable) Read-Only Memory (ROM)(Programmable) Read-Only Memory (ROM)
INPUT OUTPUT
Programmable Programmable OR planeOR plane
ProgrammableConnections
Programmable Logic Array (PLA)Programmable Logic Array (PLA)
ProgrammableProgrammableAND planeAND planeINPUT OUTPUT
ProgrammableProgrammableAND planeAND plane
Fixed Fixed OR planeOR plane
Programmable Array Logic (PAL) DevicesProgrammable Array Logic (PAL) Devices
INPUTOUTPUT
F/F
![Page 11: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/11.jpg)
Read Only Memory (ROM)“Permanent” binary information is storedNon-volatile memory Power off does not erase information stored
2k wordsN-bit per work
ROMROM N-bit Data OutputK-bit address lines NK
![Page 12: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/12.jpg)
32x8 ROM32x8 ROM 85
0123
28293031
D7 D6 D5 D4 D3 D2 D1 D0
A4A3A2A1A0
5-to-32
Decoder
Each represents 32 wires
Fuse can beimplemented as a diode or a pass transistor
![Page 13: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/13.jpg)
Programming the 32x8 ROM
A4 A3 A2 A1 A0 D7
D6 D5
D4 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 1 0 10 0 0 0 1 1 0 0 0 1 0 1 10 0 0 1 0 1 0 1 1 0 0 0 0… … … … … … … … … … … … …1 1 1 0 1 0 0 0 1 0 0 0 01 1 1 1 0 0 1 0 1 0 1 1 01 1 1 1 1 1 1 1 0 0 0 0 1
012
293031
D7 D6 D5 D4 D3 D2 D1 D0
A4A3A2A1A0
5-to-32
Decoder
![Page 14: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/14.jpg)
Example: Lookup TableDesign a square lookup table for F(X) = XF(X) = X22 using ROM
X F(X)=X2
0 01 12 43 94 165 256 367 49
X F(X)=X2
000 000000001 000001010 000100011 001001100 010000101 011001110 100100111 110001
![Page 15: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/15.jpg)
Square Lookup Table using ROM
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0123
F5 F4 F3 F2 F1 F0
X2X1X0
3-to-8
Decoder 4567
![Page 16: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/16.jpg)
Square Lookup Table using ROM
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
= X0= X0Not UsedNot Used
0123
F5 F4 F3 F2 F1 F0
X2X1X0
3-to-8
Decoder 4567
![Page 17: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/17.jpg)
Square Lookup Table using ROM
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0123
F5 F4 F3 F2 F0
X2X1X0
3-to-8
Decoder 4567
F1
![Page 18: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/18.jpg)
Programmable Logic Array (PLA)
C
B
A
C C B B A A
F2
Programmable AND Plane
Programmable OR Plane
![Page 19: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/19.jpg)
Example using PLAPLA
m(0,5,6,7)C)B,F2(A,m(0,1,2,4) C)B,F1(A,
CBAACABF2
BCACABF1
CBCABAF1
![Page 20: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/20.jpg)
Example using PLAPLA
C
BA
C C B B A A
CBAACABF2
BCACABF1
AB
AC
BC
A B C
F2F1
![Page 21: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/21.jpg)
PAL Device
A
B
IO1
IO2
IO1 IO1B BA A IO1 IO2
Programmable AND Plane
Fixed OR Plane
![Page 22: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/22.jpg)
PAL Device Design Example
A
B
IO1
IO2
IO1 IO1B BA A
DCBADCADCBACABIO2
DCBACABIO1
D DC C
Not programmed
![Page 23: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/23.jpg)
CPLD and FPGA [Brown&Rose 96]Complex Programmable Logic Device (CPLDCPLD) Multiple PLDs (e.g. PALs, PLAs) with
programmable interconnection structure Pioneered by Altera
Field-Programmable Gate Array (FPGAFPGA) High logic capacity with large distributed
interconnection structure Logic capacity number of 2-input NAND gates
Offers more narrow logic resources CPLD offers logic resources w/ a wide number of inputs
(AND planes) Offer a higher ratio of Flip-flops to logic resources
than CPLDHCPLDHCPLD (High Capacity PLD) is often used to refer to both CPLD and FPGA
![Page 24: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/24.jpg)
CPLD structure
PLD PLD PLD PLD
PLD PLD PLD PLD
Logic block
Interconnects
I/O block
![Page 25: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/25.jpg)
FPGA StructureLogic block
I/O block
Interconnects
![Page 26: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/26.jpg)
Programming Elements - PEPEs are used to physically “program” the interconnects.
Vgate
A
B
Field Effect Transistor (FET)
FET acts like a “switch”If Vgate is ONE, switch is closed, connecting A and B otherwise A and B are isolated.
![Page 27: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/27.jpg)
Programming Elements - PE
ONE
A
B
Closed
A
B
OpenCkt
Open
Vgate=OneSwitch Closed
Vgate=ZeroSwitch Open
Example
![Page 28: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/28.jpg)
Programming Elements - PE
So, we’ll have one FET at every programmable Interconnect, but we need a method or techniqueto “program” VGATE to be ONE or ZERO.
Before, we look at our options, some definitions
![Page 29: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/29.jpg)
Programming Elements - PETwo Types:
1. Volatile“Program” is lost when power is removed
2. Non-volatile “Program” is retained with power is removed.
Two Classes: 1. Re-programmable
PE can be “erased” and “re-programmed” 2. One-time-programmable (OTP)
PE can only be programmed “one” time.(not really used anymore)
![Page 30: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/30.jpg)
Programming TechnologiesEPROM – Erasable Programmable Read Only Memory
Reprogrammable and non-volatile It is possible to physically program an EPROM cell to
always be ONE when power is applied. Also, we can use ultraviolet (UV) light to reset or “erase” the EPROM cell back to ZERO.
![Page 31: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/31.jpg)
Programming TechnologiesEPROM
We can, therefore, erase all the cells of the EPROM and then program the PEs that we want to be ONEs.
A
B
EPROMCell
UVTo erase
![Page 32: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/32.jpg)
Programming TechnologiesEEPROM – (E2PROM) Electrically Erasable Programmable Read Only Memory
Reprogrammable and non-volatile Similar to an EPROM except cell can be “erased”
electrically.
![Page 33: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/33.jpg)
Programming TechnologiesSRAMStatic Random Access Memory
Volatile and Reprogrammable (electrically)
Store the value of VGATE within a SRAM cell. We losethe program whenever the power is removed. Therefore,we’ll need the ability to “reload” the design upon power-up.
SRAMCell
To Vgate
![Page 34: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/34.jpg)
SRAM CELLWrite
ToVGATE
WL
BL
Write 0
1
1
1 0 0 ToVGATE
WL
BL
Write 1
1
0
0 1 1
WL=1, turns “ON” FET, connecting BL to the cell
![Page 35: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/35.jpg)
SRAM CELLRead
ToVGATE
WL
BL
Read
0
X
data datadata
WL=0, turns “OFF” FET, isolating data from the cell.However, Due to “positive” feedback, data is retained in the memory cell until power is removed
![Page 36: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/36.jpg)
Programming TechnologiesSRAM
Use a SRAM cell to store VGATE. Lose “program” whenpower is removed.
A
B
SRAMCell
![Page 37: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/37.jpg)
Programming TechnologiesAnti-Fuse
.
Non-volatile and OTP
Normally, anti-fuse behaves like an “open” circuit, however you can “destroy” the fuse electrically so that it behaves like a short circuit.
A
B
Anti-fuseThe antifuse is very small compared to theother PEs.
![Page 38: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/38.jpg)
Summary FPLD Benefits
1. Increased Performance2. Increased Gate Density3. Reduced Development Time4. Rapid Hardware Prototyping5. Reduced “Time to Market”6. Future Modifications7. Reduced Inventory Risks8. Reduced Development Costs
![Page 39: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/39.jpg)
Summary FPLD Types
1.PALS2.Simple PLDs3.Complex PLDs (FPLDs)4.FPGAs
![Page 40: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/40.jpg)
Summary Programming Elements
1. EPROM (Obsolete)2. EEPROM3. Anti-Fuse 4. SRAM
Technologies:
Types:1.Volatile2.Non-Volatile
Classes:1.Reprogrammable2.OTP
![Page 41: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/41.jpg)
Summary Programming Elements
Technology Volatile ReprogrammableRelative Size
Relative Cost
Relative Importance
SRAM yes yes-In Circuit Very Large Low StrongEEPROM no yes-In Circuit Large High StrongEPROM no yes-Out circuit Small Very High WeakAntifuse no no Very Small High Moderate
![Page 42: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/42.jpg)
Generic CPLD/FPGA DesignAt a minimum, every CPLD/FPGA needs
1. Programmable Logic (L) 2. Programmable Interconnects (I) 3. Input/Output Logic (I/O)
L I I/O
![Page 43: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/43.jpg)
Generic CPLD/FPGA Design1/3 Logic, 1/3 Interconnects, 1/3 Input/Output
L I I/O
Do I have enough logic?
![Page 44: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/44.jpg)
Generic CPLD/FPGA Design1/2 Logic, 1/4 Interconnects, 1/4 Input/Output
L I I/O
Logic is good, but now do I have enoughinterconnects for my logic?
![Page 45: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/45.jpg)
Generic CPLD/FPGA Design1/4 Logic, 1/2 Interconnects, 1/4 Input/Output
L I I/O
Ok, I have enough interconnects for mylogic. Do I have enough I/O?
![Page 46: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/46.jpg)
Generic FPLD DesignDifferent vendors use different approaches
L I I/O
![Page 47: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/47.jpg)
Basic Design FlowDescribe your desired circuit using a software toolCompile your circuitSimulate the circuit on the PC to see if behavior is correctProgram chip using special printer port cable
![Page 48: PLD](https://reader033.vdocuments.us/reader033/viewer/2022061106/54475988b1af9f10358b48c7/html5/thumbnails/48.jpg)
Circuit DescriptionUsually at least four ways to describe your circuit Schematic drawing (vendor specific) VHDL language (standard) Verilog language (standard) State machine or waveform (vendor
specific)Some vendors supply proprietary languages also