Pipelining

Overview

Pipelining is widely used in modern processors.

Pipelining improves system performance in terms of throughput.

Pipelined organization requires sophisticated compilation techniques.

Basic Concepts

Making the Execution of Programs Faster

Use faster circuit technology to build the processor and the main memory.

Arrange the hardware so that more than one operation can be performed at the same time.

In the latter way, the number of operations performed per second is increased even though the elapsed time needed to perform any one operation is not changed.

Use the Idea of Pipelining in a Computer

F1

E1

F2

E2

F3

E3

I1 I2 I3

(a) Sequential execution

Instructionfetchunit

Executionunit

Interstage bufferB1

(b) Hardware organization

T ime

F1 E1

F2 E2

F3 E3

I1

I2

I3

Instruction

(c) Pipelined execution

Figure 8.1. Basic idea of instruction pipelining.

Clock cycle 1 2 3 4Time

Fetch + Execution

Use the Idea of Pipelining in a Computer

F4I4

F1

F2

F3

I1

I2

I3

D1

D2

D3

D4

E1

E2

E3

E4

W1

W2

W3

W4

Instruction

Figure 8.2. A 4-stage pipeline.

Clock cycle 1 2 3 4 5 6 7

(a) Instruction execution divided into four steps

F : Fetchinstruction

D : Decodeinstructionand fetchoperands

E: Executeoperation

W : Writeresults

Interstage buffers

(b) Hardware organization

B1 B2 B3

Time

Fetch + Decode+ Execution + Write

Textbook page: 457

Role of Cache Memory

Each pipeline stage is expected to complete in one clock cycle.

The clock period should be long enough to let the slowest pipeline stage to complete.

Faster stages can only wait for the slowest one to complete.

Since main memory is very slow compared to the execution, if each instruction needs to be fetched from main memory, pipeline is almost useless.

Fortunately, we have cache.

Pipeline Performance

The potential increase in performance resulting from pipelining is proportional to the number of pipeline stages.

However, this increase would be achieved only if all pipeline stages require the same time to complete, and there is no interruption throughout program execution.

Unfortunately, this is not true.

Pipeline Performance

F1

F2

F3

I1

I2

I3

E1

E2

E3

D1

D2

D3

W1

W2

W3

Instruction

F4 D4I4

Clock cycle 1 2 3 4 5 6 7 8 9

Figure 8.3. Effect of an execution operation taking more than one clock cycle.

E4

F5I5 D5

Time

E5

W4

Pipeline Performance The previous pipeline is said to have been stalled for two clock

cycles. Any condition that causes a pipeline to stall is called a hazard. Data hazard – any condition in which either the source or the

destination operands of an instruction are not available at the time expected in the pipeline. So some operation has to be delayed, and the pipeline stalls.

Instruction (control) hazard – a delay in the availability of an instruction causes the pipeline to stall.

Structural hazard – the situation when two instructions require the use of a given hardware resource at the same time.

Pipeline Performance

F1

F2

F3

I1

I2

I3

D1

D2

D3

E1

E2

E3

W1

W2

W3

Instruction

Figure 8.4. Pipeline stall caused by a cache miss in F2.

1 2 3 4 5 6 7 8 9Clock cycle

(a) Instruction execution steps in successive clock cycles

1 2 3 4 5 6 7 8Clock cycle

Stage

F: Fetch

D: Decode

E: Execute

W: Write

F1 F2 F3

D1 D2 D3idle idle idle

E1 E2 E3idle idle idle

W1 W2idle idle idle

(b) Function performed by each processor stage in successive clock cycles

9

W3

F2 F2 F2

Time

Time

Idle periods – stalls (bubbles)

Instruction hazard

Pipeline Performance

F1

F2

F3

I1

I2 (Load)

I3

E1

M2

D1

D2

D3

W1

W2

Instruction

F4I4

Clock cycle 1 2 3 4 5 6 7

Figure 8.5. Effect of a Load instruction on pipeline timing.

F5I5 D5

Time

E2

E3 W3

E4D4

Load X(R1), R2Structural hazard

Pipeline Performance

Again, pipelining does not result in individual instructions being executed faster; rather, it is the throughput that increases.

Throughput is measured by the rate at which instruction execution is completed.

Pipeline stall causes degradation in pipeline performance.

We need to identify all hazards that may cause the pipeline to stall and to find ways to minimize their impact.

Quiz

Four instructions, the I2 takes two clock cycles for execution. Pls draw the figure for 4-stage pipeline, and figure out the total cycles needed for the four instructions to complete.

Data Hazards

Data Hazards We must ensure that the results obtained when instructions are

executed in a pipelined processor are identical to those obtained when the same instructions are executed sequentially.

Hazard occursA ← 3 + AB ← 4 × A

No hazardA ← 5 × CB ← 20 + C

When two operations depend on each other, they must be executed sequentially in the correct order.

Another example:Mul R2, R3, R4Add R5, R4, R6

Data Hazards

F1

F2

F3

I1 (Mul)

I2 (Add)

I3

D1

D3

E1

E3

E2

W3

Instruction

Figure 8.6. Pipeline stalled by data dependency between D2 and W1.

1 2 3 4 5 6 7 8 9Clock cycle

W1

D2A W2

F4 D4 E4 W4I4

D2

Time

Figure 8.6. Pipeline stalled by data dependency between D2 and W1.

Operand Forwarding

Instead of from the register file, the second instruction can get data directly from the output of ALU after the previous instruction is completed.

A special arrangement needs to be made to “forward” the output of ALU to the input of ALU.

Registerfile

SRC1 SRC2

RSLT

Destination

Source 1

Source 2

(a) Datapath

ALU

E: Execute(ALU)

W: Write(Register file)

SRC1,SRC2 RSLT

(b) Position of the source and result registers in the processor pipeline

Figure 8.7. Operand forw arding in a pipelined processor.

Forwarding path

Handling Data Hazards in Software

Let the compiler detect and handle the hazard:

I1: Mul R2, R3, R4 NOP NOPI2: Add R5, R4, R6

The compiler can reorder the instructions to perform some useful work during the NOP slots.

Side Effects The previous example is explicit and easily detected. Sometimes an instruction changes the contents of a register

other than the one named as the destination. When a location other than one explicitly named in an instruction

as a destination operand is affected, the instruction is said to have a side effect. (Example?)

Example: conditional code flags:Add R1, R3AddWithCarry R2, R4

Instructions designed for execution on pipelined hardware should have few side effects.

Instruction Hazards

Time lost as a result of branch instruction is referred as branch penalty

Branch penalty is one clock cycle For longer pipeline, branch penalty may be

higher Reducing branch penalty requires branch

instruction to be computed earlier in pipeline

Instruction fetch unit should have dedicated hardware to identify branch instruction

Compute branch target address as quickly as possible after instruction is fetched

So above task in performed in decode stage Explaination of fig-8.8,8.9-a,8.9-b

Unconditional Branches

F2I2 (Branch)

I3

Ik

E2

F3

Fk Ek

Fk+1 Ek+1Ik+1

Instruction

Figure 8.8. An idle cycle caused by a branch instruction.

Execution unit idle

1 2 3 4 5Clock cycleTime

F1I1 E1

6

X

Branch TimingX

Figure 8.9. Branch timing.

F1 D1 E1 W1

I2 (Branch)

I1

1 2 3 4 5 6 7Clock cycle

F2 D2

F3 X

Fk Dk Ek

Fk+1 Dk+1

I3

Ik

Ik+1

Wk

Ek+1

(b) Branch address computed in Decode stage

F1 D1 E1 W1

I2 (Branch)

I1

1 2 3 4 5 6 7Clock cycle

F2 D2

F3

Fk Dk Ek

Fk+1 Dk+1

I3

Ik

Ik+1

Wk

Ek+1

(a) Branch address computed in Execute stage

E2

D3

F4 XI4

8Time

Time

- Branch penalty

- Reducing the penalty

Instruction Queue and Prefetching

F : Fetchinstruction

E : Executeinstruction

W : Writeresults

D : Dispatch/Decode

Instruction queue

Instruction fetch unit

Figure 8.10. Use of an instruction queue in the hardware organization of Figure 8.2b.

unit

To reduce the effect of cache miss or stall,processor employ sophisticated fetch unit

Fetched instruction are placed in instruction queue before they are are needed

instruction queue can store several instructions

Dispatch unit takes instruction from front of the queue and send to execution unit

Explaination pg-468 2nd para (exam must)

Branch instruction is executed concurrently with other instruction. This technique is called branch folding

branch folding occurs only at the time a branch instruction is encountered,atleast one instruction is available in the queue other than branch instruction

Conditional Braches

A conditional branch instruction introduces the added hazard caused by the dependency of the branch condition on the result of a preceding instruction.

The decision to branch cannot be made until the execution of that instruction has been completed.

Branch instructions represent about 20% of the dynamic instruction count of most programs.

Branch instruction can be handled in several ways to reduce branch penalty

Delayed branch Branch prediction Dynamic branch prediction

DELAYED BRANCH

Location following a branch instruction is called branch delay slot

There may be more than one branch delay slot depending on the time to execute a branch instruction

A techcnique called delay branching can minimize the penalty incurred as a result of branch instruction

Arrange the instruction execution such that whether or not the branch is taken

Place useful instruction in delay slot But no useful instruction can be placed in

delay slot But slot can be filled with NOP instructions Effectiveness of delay branch approach

depends on how often it is possible to reorder instructions

BRANCH PREDICTION

In branch prediction, assume that branch will not take place and continue to fetch instruction in sequential address order

Speculative execution means that instruction are executed before the processor is certain that they are in correct execution sequence

Hence care must be taken no processor or register are updated until it is confirmed that these instruction should indeed be executed

Branch prediction is classified into 2 types

1.Static branch prediction Prediction is always the same every time a given

instruction takes place

2.Dynamic branch prediction Prediction decision may change based depending

on execution history

2 state algorithm

4 state algorithm