Pipelined Parallel AC-based Approach for Multi-String

Matching

Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

Authors: Wei Lin, Bin Liu

Publisher: 2008 14th IEEE International Conference on Parallel and Distributed Systems.IEEE Computer Society

Present: Chia-Ming ,Chang Date: 2, 3, 2009

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Outline

1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion

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Introduction (1/3) A string Y of length n is a sequence of characters c1c2……cn. Let Σ = {Y1, Y2, ...YN} be a finite set of strings c

alled keywords or signatures proposed hardware solutions are based on the

well-known Aho-Corasick (AC) algorithm , where the system is modeled as a deterministic finite automaton(DFA)

we present a pipelined processing approach to the implementation of AC algorithm, called P2-AC.

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Introduction (2/3)

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Introduction (3/3)

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Outline

1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion

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Pipelined Architecture (1/7)

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Pipelined Architecture (2/7)

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pattern set is{apple, applause, ampliation, past, pat, parable}

appl e appl ause ampl iati on past pat para ble

Pipelined Architecture (3/7)

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Pipelined Architecture (4/7)

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Pipelined Architecture (5/7)

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Pipelined Architecture (6/7)

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1

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64

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Pipelined Architecture (7/7)

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<current state, input segment, next state>

<root, appl, appl>,

<appl, e, apple> T1

<ampliati, on, ampliation> T2

<para, ble, parable>T3

<appl, ause, applause>T4

4*n+1 4*n+2 4*n+3 4*n

Outline

1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion

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Conclusion (1/4) In all, the Snort pattern set costs 305 M 5

12 SRAM blocks and 228 M 4K SRAM blocks, which are about 133KB and 13.68 bits per character for the utilized Snort pattern set.

which are 4132 LUTs in FPGA and about 0.05 LUTs per character. We use Altera’s StratixII EP2S60 FPGA to implement the pattern matching system using P2-AC method.

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Performance evaluation (2/4)

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Performance evaluation (3/4)

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Performance evaluation (4/4)

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Outline

1. Introduction 2. P2-AC algorithm and architecture 3. Performance evaluation 4. Conclusion

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Conclusion (1/1) The memory cost of P2-AC is as low as 1

3.68 bits/char for a signature set with 5.7K strings which is less than 47% of the best known AC-based methods.

Speed 2(char/cycle) Using the Xilinx Virtex-5 FPGA that opera

tes at 550 MHz, the throughput of P-AC is up to 8.8 Gbps.

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