picoblaze & microblaze ernest jamro dep. of electronics agh – university of science and...
TRANSCRIPT
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PicoBlaze & MicroBlaze
Ernest Jamro
Dep. Of Electronics
AGH – University of
Science and Technology
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MicroBlaze•32 bit soft-processor
•32 bit instructions
•32 registers
•Independent data and instruction buses
•Different bus standards:
- PLB (Processor Local Bus)
- AXI (Advanced eXtensible Interface)
- LMB (Local Memory Bus)
- FSL (Fast Simplex Link)
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MicroBlaze Block Diagram
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Different Bus Configurations
LMB: AXI / PLB
Complexity simply complex
Local/glonal local global
# Master 1 >=1
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MB bus configurations: only LMB This configuration cannot communicat with external
modules, thus should not be employed
MB
Lmb_bram _if_ctrl
Lmb_bram _if_ctrl
BRAM (dwu-portowy)
Instr LMB
Dane LMB
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LMB: Instructions, PLB:Data
MB
LMB_bram _if_ctrl
plb_bram _if_ctrl
BRAM (dula-port)
Instr LMB
Dane PLB
Peripheral modules e.g.. UART, GPIO, SRAM
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EDK Print Screen
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Instructions:LMB; Data: PLB + LMB
MB employs LMB for instructions and memory accessand PLB/AXI for peripheral module access
MB
LMB_bram _if_ctr
LMB_bram _if_ctr
BRAM (dual port)
Instr LMB
Dane PLB LMB
Peripheral modules e.g. UART, GPIO, SDRAM
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Only one PLB/AXI bus
MB
(external memory) e.g. plb_ddr
Pheripheral modules e.g. UART, GPIO
cache I
cache D
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Two PLB/AXI buses
MB
(Exter. Memory) e.g. plb_ddr
Instr PLB
Dane PLB
Peripheral Modules e.g. UART, GPIO
cache I
cache D
(Exter. Memory) e.g. plb_ddr
Warning: plb_ddr memory cannot be written (how to initialise instruction memory)
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Two PLBs, single memory
FPGA
MB
External Memory
Instr PLB
Data PLB
Pheripheral modules e.g. UART, GPIO
cache I
cache D
Multi-channel Memory controller
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Without Data Cache
MB
External Memory
Instr PLB
Dane PLB
Peripheral Modules e.g. UART, GPIO
cache I
Multi-channel Memory controller lmb_bram_
if_ctrl
BRAM
Manual (in C program) handling of data memory transfer
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Example (6)The MB is booted from BRAM
MB
plb_sdram LMB_bram _if_ctr
BRAM (dual-port)
Instr. PLB
Data PLB LMB
Peripheral Modules e.g. UART, GPIO
LMB_bram _if_ctr
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Fast Simplex Link (FSL)
32-bit single direction bus – one master one slave
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Registers•R0-R31 32x32-bit –general purpose registers R0- always equal to 0
•PC – Program counter – initial value = 0
•MSR (Machine State Register)
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MSR
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Instruction Format
Typu A Instruction
Typu B instruction
Example: instruction ADD
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Example of Instructions
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Pipeline Architecture
Delay Slot Instructions
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(Hard)Procesor (e.g. PowerPC in Virtex 2Pro)
• Implemented directly in silicon (ASIC technology)
• Employs ASIC technology (not FPGA technology) so this silicon area cannot be reused for other purposes
•Parameters are defined (ASIC) and cannot be changed
•Is relatively fast and consumes relatively small silicon area and power
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Soft-procesor (e.g. MicroBlaze)•Employs standard FPGA logic resources
•thus the logic resources can be freed when not required
•Parameters can be freely defined by a user
•In comparison to the hard-processor is slower, consumes more silicon area and power
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MicroBlaze parameters•Different types of buses (PLB/AXI, LMB)
•(Implement or not) cache memory, define its size
•Barrel-Shifter
•fast multiplier: define the bit-width of the multiplier: 32-bit, 64-bit
•divider
•debugger (and its parameters)
•Floating-point unit (and its parameters)
•MMU – Memory Management Unit
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EDK - Ports
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EDK Addresses
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Adding IP-Cores
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IP-Core Options
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Microprocessor Hardware Specification
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8-bit soft-processor PicoBlaze • Optimized for Xilinx Spartan-3 architecture—just 96 slices (0.3% of an
XC3S5000 device) and 0.5 to 1 block RAM
•16 byte-wide general-purpose data registers
• 1K instructions of programmable on-chip program store, automatically loaded during
FPGA configuration
• Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags
• 64-byte internal scratchpad RAM
• 256 input and 256 output ports for easy expansion and enhancement
• Automatic 31-location CALL/RETURN stack
• Predictable performance, always two clock cycles per instruction, up to 200 MHz or
100 MIPS in a Virtex-II Pro FPGA
• Fast interrupt response; worst-case 5 clock cycles
• Support in Spartan-6, and Virtex-6 FPGA architectures
• Assembler, instruction-set simulator support
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Block diagram
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Example, external multiplier
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PicoBlaze, in VHDLprocessor: kcpsm
port map( address => address_signal,
instruction => instruction_signal,
port_id => port_id_signal,
write_strobe => write_strobe_signal,
out_port => out_port_signal,
read_strobe => read_strobe_signal,
in_port => in_port_signal,
interrupt => interrupt_signal,
reset => reset_signal,
clk => clk_signal);
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PB, assembler
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PB, data moving
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MicroBlaze – cache memory• Small cache memory is much quicker than external memory
•For the MB it is better to use internal BRAM memory (in the case when data moving is easily determined) than cache as BRAM as quick as cache memory but consumes less recourses
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cache block structureThis structure is for tutorial-pupose only (not used in
real applications)
Data 0 Address 0
Valid-bit
Data 1 Address 1 Valid-bit
Data N Address N Valid-bit
=
=
=
Address
Data
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Real Application
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The End
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Uproszczony przykład działania
Pamięć Tag
CacheL. DanaTag Cache adr
0 0x00 0x0000
1 0x00 0x0004
2 0x00 0x0008
3 0x03 0x030C
4 0x03 0x0310
5 0x05 0x0514
6 0x06 0x0618
7 0x07 0x071C
...
Linie adresowe:
a30-a31 – ignorowane – dane są 4 bajtowe
a24-a29 – linie adresowe pamięci tag i danych (instrukcji)
a0-a23 – linie adresowe zapisywane w pamięci tag i wykorzystywane podczas porównywania
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LMB (Local Memory Bus) Sygnały
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LMB (odczyt i zapis)
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LMB szybki odczyt