picoblaze cpld microcontroller
DESCRIPTION
PicoBlaze CPLD Microcontroller. Agenda. What is PicoBlaze PicoBlaze operation PicoBlaze software flow Customize PicoBlaze Memory integration Why PicoBlaze. What is PicoBlaze?. A fully customizable 8-bit soft microcontroller macros that provides 49 16-bit instructions - PowerPoint PPT PresentationTRANSCRIPT
PicoBlaze CPLD Microcontroller
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Agenda
• What is PicoBlaze• PicoBlaze operation• PicoBlaze software flow• Customize PicoBlaze• Memory integration• Why PicoBlaze
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What is PicoBlaze?
• A fully customizable 8-bit soft microcontroller macros that provides – 49 16-bit instructions– 8 general-purpose 8-bit registers– 256 directly and indirectly addressable ports– Reset and a maskable interrupt
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PicoBlaze Block Diagram
Interrupt Control
8OUT_PORT8 Registers 8-bit
Program Flow
Control
ZERO & CARRY Flags
ALU
Interrupt Flag Store
Program Counter
Program Counter
Stack
8
8
8
8
Operational Control & Instruction Decoding
8PORT_IDPort
Address Control
READ_STROBEWRITE_STROBE
INTERRUPT
8 8ADDRESS
8
RESET
CLK
16INSTRUCTION
8
8
8
8IN_PORT
CONSTANT DATA
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PicoBlaze Operation
INSTRUCTION[15:0]
ADDRESS[7:0]
CLK
IN_PORT[7:0]
INTERRUPT
RESET
INSTRUCTIOIN[15:0]ADDRESS[7:0]
OUT_PORT[7:0]PORT_ID[7:0]
READ_STROBE
WRITE_STROBE
CLK
PicoBlaze
Program ROM
CLK
ADDRESS(7:0) 00 00 01 02 03 04
INSTRUCTION(15:0) 0700 0700 0801 F632 DC5A
RESET
2 clock cycle operation
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PicoBlaze Instruction Set• Program Control
Group– JUMP– CALL– RETURN
• Logical Group– LOAD– AND– OR– XOR
• Arithmetic Group– ADD– ADDCY– SUB– SUBCY
• Shift & Rotate Group– SR0– SR1– SRX– SRA– RR– SL0– SL1– SLX– SLA– RL
• Input/Output Group– INPUT– OUTPUT
• Interrupt Group– RETURNI ENABLE– RETURNI DISABLE– INTERRUPT ENABLE– INTERRUPT DISABLE
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Assembler
• A simple DOS executable file• Written in C• Use Microsoft Visual Studio 6.0• Easy to change
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Assembler FilesFilename.asm
ASM.EXE
Filename.mcs Filename.vhd
Filename.bin
Filename.fmt
Filename.log
<User input file>
<VHDL for simulation>
<Binary code in hex format>
<Formatted assembly file>
<Assembler report>
<Binary code for ROM>
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A Simple Shifter
Constant shifter_port, 04 ;declare port
Namereg s7, shifter_reg ;declare register
Loop1: Load shifter_reg, 01 ;init shifter reg
Loop2: Output shifter_reg, shifter_port
SL0 shifter_reg ;shift left with 0
Jump NZ, loop2 ;goto loop2 when s7<>0
Jump loop1 ;goto loop1
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Shifter Program
Address Hex Binary
00 0701 0000011100000001
01 8F04 1000111100000100
02 A706 1010011100000110
03 D501 1101010100000001
04 D000 1101000000000000
Load s7, 01
Output s7, 04
SL0 s7
Jump NZ, 01
Jump 00
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PicoBlaze Software Flow
• Compile PicoBlaze source– Use WebPACK 5.2i or later– Use FISE 5.2i or later
• Assemble the program code– asm filename.asm
• Download to the CPLD– iMPACT 5.2i or later
• Download assembled object code to EEPROM
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Making a Processor Change• Add an instruction
– Modify picoblaze.vhd– Add a constant with instruction code:
constant new_instruction_id : std_logic_vector(4 downto 0) := “10101";– Add instruction decoding signal
i_new_instruction <= '1' when instruction(15 downto 11) = new_instruction_id else '0';
– Define VHDL component with functionality of new instruction – Add new component to picoblaze.vhd
• Tweak the assembler– Add new instruction to asm.cpp
char *new_instruction_id = “10101“;– Add case to write_program_word function of asm.cpp– Recompile asm.cpp to create asm.exe
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Making a Processor Change
• A DSP example - bit reversal (“Flip”) operation
• 12 to 18 instructions needed in regular microcontroller programming
• A newly created FLIP function in PicoBlaze can be used to complete the operation in just one instruction cycle
A B C D E F G H
H G F E D C B A
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Macrocell Usage
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Program Memory Integration
• Binary code and processor can be integrated into a single CPLD
• Eliminates external PROM• SOC solution• Reduces size• Increases performance
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Integration Design Flow• Assemble the design
– Use PicoBlaze Assembler– asm design.asm– Generates design.vhd
• Write top level VHDL– Wrap picoblaze.vhd and design.vhd (output from assembler)
• Compile top level VHDL source– Use WebPACK 5.2i or later– Use FISE 5.2i or later
• Download to CPLD– Use iMPACT 5.2i or later
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1 + 1 < 2
Macrocells Product Terms Registers FB Inputs Fmax
212/256 ( 83%) 642 /896 ( 72%) 155/256 ( 61%) 451/640 ( 70%) 30 MHz
Macrocells Product Terms Registers FB Inputs Fmax
107/256 ( 42%) 341 /896 ( 38%) 82 /256 ( 32%) 208/640 ( 32%) 87 MHz
PicoBlaze
PicoBlaze + Shifter
- Fitter removes redundant circuits
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PicoBlaze Demonstration
• Demonstrate simple shifter• Add FLIP instruction
– Exchanges bits in specified register• MSB to LSB• LSB to MSB
– Modify picoblaze.vhd– Create FLIP component– Modify asm.cpp
• Demonstrate FLIP instruction with new program
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Why Use PicoBlaze?
• Emulate out of production processors• Lower power consumption than older small processors• Customizable for performance
– PicoBlaze runs faster than most 8-bit and16-bit uCs (PICs, 8051, 6811, 80188, 6816, etc.)
• Customizable for specific applications– uCs have fixed features– uCs have fixed instructions sets– PicoBlaze can run functions quickly in parallel logic
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Why Use PicoBlaze?
• PicoBlaze is parameterized– uCs have fixed size– uCs have limited I/Os
• Can be reconfigured “On the Fly (OTF)”• Cryptography/security
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Conclusion
• PicoBlaze is a soft microcontroller module• Use PicoBlaze for custom microcontroller
applications• Create custom instruction sets• Program memory integration• Use PicoBlaze Assembler• Compile with current Xilinx software
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CoolRunner-II Reference DesignsApplication Reference Design
Reference Number
Lanaguage MacrocellTarget Device
% Utilizated
XPATH Module Design XAPP356 VHDL 225 XC2C384 588 Channel DVM Springboard XAPP146 Pocket C, VHDL 184 XC2C256 71Springboard Module Design XAPP147 Pocket C, VHDL 67 XC2C128 52
8051 Microcontroller Interface XAPP349 VHDL 57 XC2C64 89SPI XAPP348 VHDL 135 XC2C256 52
IrDA and UART XAPP345 VHDL or Verilog 87 XC2C128 67UARTS XAPP341 VHDL or Verilog 61 XC2C128 47
I2C Bus Controller XAPP333 VHDL or Verilog 131 XC2C256 51
N x N Crosspoint Switch XAPP380 VHDL 193 XC2C256 75SMBus Controller XAPP353 VHDL 158 XC2C256 61
Encoder Manchester Encoder/Decoder XAPP339 VHDL or Verilog 55 XC2C64 85Decoder 16b/20b Encoder/Decoder XAPP336 VHDL 76 XC2C128 59
Error Detection & Correction XAPP383 VHDL 66 XC2C128 52NAND Interface XAPP354 VHDL or Verilog 9 XC2C32 28
Wirless Wireless Transciever XAPP358 VHDL 156 XC2C256 60Consumer MP3 Player XAPP328 VHDL 225 XC2C256 88
PDA
Memory
Datacom
Free HDL CoolRunner-II design code download:http://www.xilinx.com/products/xaw/coolvhdlq.htm
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Appendix A
• Instruction set descriptions– Syntax– Bit description
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Program Syntax• No blank lines – Use a semicolon for blank lines
• Comments – Any item on a line following a semicolon (;)
• Constant – Must be specified in the form of a 2 digit hexadecimal value(00 – FF)
• Line Labels – To identify a program line for JUMP or CALL instruction should be followed by a colon (:)
• CONSTANT Directive – Assigns an 8-bit constant value to a label
• NAMEREG Directive – Assigns a new name to any of the 8 registers
• ADDRESS Directive – Forces the following instructions commencing at a new address value
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Program Control
I I I I I C C C A A A A A A A A
1 1 0 1 01 1 0 1 11 0 0 1 0
JUMP
CALL
RETURN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01
Unconditional
Conditional
Address
0 00 11 01 1
if Zero
if NOT Zero
if Carry
if NOT Carry
JUMP aa
JUMP Z, aa
JUMP NZ, aa
JUMP C, aa
JUMP NC, aa
CALL aa
CALL Z, aa
CALL NZ, aa
CALL C, aa
CALL NC, aa
RETURN
RETURN Z
RETURN NZ
RETURN C
RETURN NC
Instruction syntax
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Interrupt Control
I I I I I 0 0 0 0 0 0 0 0 0 0 C
INTERRUPT
RETURNI
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01
Enable
Disable
1 1 1 1 0
1 0 1 1 0Don’t Care
INTERRUPT ENABLE
INTERRUPT DISABLE
ENABLE INTERRUPT
DISABLE INTERRUPT
Instruction syntax
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Logical Operation
I I I I I X X X Y Y Y K K K K K15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Constant
sX sY
0 C 0 0 00 C 0 0 10 C 0 1 00 C 0 1 1
LOAD sX, C
AND sX, C
OR sX, C
XOR sX, C
01
K
sY
LOAD sX, KK
AND sX, KK
OR sX, KK
XOR sX, KK
LOAD sX, sY
AND sX, sY
OR sX, sY
XOR sX, sY
Instruction syntax
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Arithmetic Operation
I I I I I X X X Y Y Y K K K K K15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Constant
sX sY
0 C 1 0 00 C 1 0 10 C 1 1 00 C 1 1 1
ADD sX, C
ADDCY sX, C
SUB sX, C
SUBCY sX, C
01
K
sY
ADD sX, KK
ADDCY sX, KK
SUB sX, KK
SUBCY sX, KK
ADD sX, sY
ADDCY sX, sY
SUB sX, sY
SUBCY sX, sY
Instruction syntax
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SHIFT/ROTATE
1 0 1 0 0 X X X 0 0 0 0 C D D D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sX 01
L - Left
R - Right
Instruction
1 1 01 1 10 1 00 0 01 0 0
SR0/SL0
SR1/SL1
SRX/SLX
SRA/SLA
RR/RL
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
Carry
SR0 sX
SR1 sX
SRX sX
SRA sX
RR sX
SL0 sX
SL1 sX
SLX sX
SLA sX
RL sX
Instruction syntax
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Input/Output Control
I I I I I X X X Y Y Y P P P P P15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Constant PORT_ID
sX sY01
P
sY
Input
Output
1 C 0 0 0
1 C 0 0 1
INPUT sX, PP
INPUT sX, sY
OUTPUT sX, PP
OUTPUT sX, sY
Instruction syntax