pic24fjxxxga2/gb2 families flash programming...
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PIC24FJXXXGA2/GB2 FAMILIESPIC24FJXXXGA2/GB2 Families Flash
Programming Specification
1.0 DEVICE OVERVIEWThis document defines the programming specificationfor the PIC24FJXXXGA2/GB2 families of microcontrollerdevices. This programming specification is required onlyfor those developing programming support for thePIC24FJXXXGA2/GB2 devices. Customers using onlyone of these devices should use development tools thatalready provide support for device programming.
This programming specification is specific to thefollowing devices:
2.0 PROGRAMMING OVERVIEW OF PIC24FJXXXGA2/GB2 DEVICES
There are two methods of programming thePIC24FJXXXGA2/GB2 devices discussed in thisprogramming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The ICSP programming method is the most directmethod to program the device; however, it is also theslower of the two methods. It provides native, low-levelprogramming capability to erase, program and verifythe chip.
The Enhanced In-Circuit Serial Programming (EnhancedICSP) protocol uses a faster method that takesadvantage of the Programming Executive (PE), asillustrated in Figure 2-1. The Programming Executiveprovides all the necessary functionality to erase, programand verify the chip through a small command set. Thecommand set allows the programmer to program thePIC24FJXXXGA2/GB2 MCUs without having to dealwith the low-level programming protocols of the chip.
This specification is divided into major sections thatdescribe the programming methods independently.Section 3.0 “Device Programming – ICSP” describesthe In-Circuit Serial Programming method. Section 4.0“Device Programming – Enhanced ICSP” describesthe Enhanced In-Circuit Serial Programming method.
• PIC24FJ128GA204 • PIC24FJ64GA204• PIC24FJ128GA202 • PIC24FJ64GA202• PIC24FJ128GB204 • PIC24FJ64GB204• PIC24FJ128GB202 • PIC24FJ64GB202
Note: The address of the Special FunctionRegister, TBLPAG, has moved from 32h to54h in the devices covered in thisspecification.
In those cases where legacy program-ming specification code from other devicefamilies is used as a basis to implementthe programming specification for thePIC24FJXXXGA2/GB2 devices, specialcare must be taken to ensure all refer-ences to TBLPAG and NVMCON, in anyexisting code, are updated with the correctopcode hex data for the mnemonic andoperands.
PIC24FJXXXGA2/GB2 Devices:
Previous PIC24F Families:
Command(Binary)
Data(Hex) Description
0000 8802A0 MOV W0, TBLPAG
Command(Binary)
Data(Hex) Description
0000 880190 MOV W0, TBLPAG
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PIC24FJXXXGA2/GB2 FAMILIES
FIGURE 2-1: PROGRAMMING SYSTEMOVERVIEW FOR ENHANCED ICSP™
2.1 Power RequirementsAll PIC24FJXXXGA2/GB2 devices power their coredigital logic at a nominal 1.8V. To simplify system design,all devices in the PIC24FJXXXGA2/GB2 families incor-porate an on-chip regulator that allows the device to runits core logic from VDD. The regulator provides power tothe core from the other VDD pins. A low-ESR capacitor(such as ceramic or tantalum) must be connected to theVCAP pin (see Table 2-1 and Figure 2-2). This helps tomaintain the stability of the regulator. The specificationsfor core voltage and capacitance are listed inSection 7.0 “AC/DC Characteristics and TimingRequirements”.
Devices in the PIC24FJ128GA204/GB204 familiesalso incorporate a secondary voltage source pin (VBAT)that allows the device to resume operation after VDDhas been removed. It is recommended that the VBATpin always be supplied with voltage from either VDD ora backup battery source during programming.
FIGURE 2-2: CONNECTIONS FOR THE VCAP AND VBAT PINS
2.2 Program Memory Write/Erase Requirements
The Flash program memory on PIC24FJXXXGA2/GB2devices has a specific write/erase requirement thatmust be adhered to for proper device operation. Therule is that any given word in memory must not be writ-ten more than twice before erasing the page in which itis located. Thus, the easiest way to conform to this ruleis to write all of the data in a programming block, withinone write cycle. The programming methods specified inthis specification comply with this requirement.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
PIC24F Devices
Programmer ProgrammingExecutive
On-Chip Memory
Note: Writing to a location multiple times withouterasing is not recommended.
VDD
VBAT
VCAP
VSS
PIC24FJXXXGA2/GB2
CEFC
3.3V
PIC24FJ128GA20X/GB20X Devices
(10 F typ.)
(VBAT tied to VDD):
Pin NameDuring Programming
Pin Name Pin Type Pin Description
MCLR MCLR P Programming EnableVDD, AVDD(1) VDD P Power SupplyVSS, AVSS(1) VSS P GroundVBAT(2) VBAT P VBAT Mode Power SupplyVCAP VCAP P On-Chip Voltage Regulator Output to the CorePGECx PGECx I Programming Pin Pairs 1, 2 and 3: Serial ClockPGEDx PGEDX I/O Programming Pin Pairs 1, 2 and 3: Serial DataVUSB3V3(3) VUSB3V3 P USB Transceiver Power Input Voltage (3.3V nominal)Legend: I = Input, O = Output, P = Power
1: All power supply and ground pins must be connected, including analog supplies and ground (AVDD/AVSS are implemented).
2: It is recommended to connect the VBAT pin to the battery or VDD during programming.3: This pin is available only in the PIC24FJXXXGB2XX family devices.
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PIC24FJXXXGA2/GB2 FAMILIES
2.3 Pin DiagramsFigure 2-3 through Figure 2-6 provide the pin diagramsfor the PIC24FJXXXGA2/GB2 devices. The pins that arerequired for programming are listed in Table 2-1 and areshown in bold type in the figures. Refer to the specificdevice data sheet for complete pin descriptions.2.3.1 PGECx AND PGEDx PIN PAIRSAll of the PIC24FJXXXGA2/GB2 devices have threeseparate pairs of programming pins, labeled asPGEC1/PGED1, PGEC2/PGED2 and PGEC3/PGED3.Any one of these pin pairs may be used for device pro-gramming by either the ICSP or Enhanced ICSPmethod. Unlike voltage supply and ground pins, it is notnecessary to connect all three pin pairs to program thedevice. However, the programming method must useboth pins of the same pair.
FIGURE 2-3: PIN DIAGRAMS (28-PIN PDIP/SSOP/SOIC)
PIC
24FJ
XXXG
A20
2
1234567891011121314
2827262524232221201918171615
MCLR
VSS
VDD
RA0RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
RA4RB4RA3RA2
RB3RB2
PGEC1/AN3/C2IN+/RP1/CN5/RB1
PGED3/RP5/ASDA1/CN27/RB5
VDDVSS
PGEC3/RP6/ASCL1/CN24/RB6
VCAP
RB7
RB9RB8
RB15RB14RB13RB12
PGED2/TDI/RP10/CN16/RB10PGEC2/TMS/RP11/CN15/RB11
VBAT
1234567891011121314
2827262524232221201918171615
MCLR
VSS
VDD
PGED3/RA0PGEC3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
RA4RB4RA3RA2
RB3RB2
PGEC1/AN3/C2IN+/RP1/CN5/RB1
RB5
VDDVSS
VBUS/RB6
VCAP
RB7
RB9RB8
RB15RB14RB13VUSB3V3
PGED2/RP10/D+/CTED11/CN16/RB10PGEC2/REFI/RP11/D-/CTED9/CN15/RB11
VBAT
PIC
24FJ
XXXG
B20
2
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FIGURE 2-4: PIN DIAGRAMS (28-PIN QFN)(1)10 11
23
6
1
18192021
22
12 13 1415
87
1617
232425262728
9
PIC24FJXXXGB20254
VSS
PGED1/AN2/CTCMP/HLVDIN/C2INB/RP0/CN4/RB0
RA3RA2
RB3RB2
PGEC1/AN3/C2INA/RP1/CTED12/CN5/RB1
VCAP
RB9
RB13VUSB3V3
PGED2/RP10/D+/CTED11/CN16/RB10PGEC2/REFI/RP11/D-/CTED9/CN15/RB11
VDD
VB
US/R
B6
RA
4R
B4
RB
7R
B8
RB
5M
CLR
VDD
VSS
RB1
5R
B14
Note 1: The bottom pad of QFN packages should be connected to VSS.
VBAT
10 11
23
6
1
18192021
22
12 131415
87
1617
232425262728
9
54
VSS
PGED1/AN2/C2IN-/RP0/CN4/RB0
RA3RA2
RB3RB2
PGEC1/AN3/C2IN+/RP1/CN5/RB1
VCAP
RB9
RB13RB12
PGED2/TDI/RP10/CN16/RB10PGEC2/TMS/RP11/CN15/RB11
VDD
PGEC
3/C
N24
/RB6
RA4
RB4
RB7
RB8
PGED
3/C
N27
/RB5
MC
LRR
A0R
A1
VDD
VSS
RB1
5R
B14
VBAT
PIC24FJXXXGA202
PGEC
3/C
VRE
F-/V
RE
F-/A
N1/
C3I
ND
/RP6
/AS
CL1
/CTE
D2/
CN
3/R
A1
PGED
3/C
V RE
F+/V
RE
F+/A
N0/
C3I
NC
/RP
5/A
SD
A1/
CTE
D1/
CN
2/R
A0
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PIC24FJXXXGA2/GB2 FAMILIES
FIGURE 2-5: PIN DIAGRAMS (44-PIN QFN)(1)1011
23456
1
18 19 20 21 2212 13 14 15
38
87
44 43 42 41 40 3916 17
2930313233
232425262728
36 3435
9
PIC24FJXXXGA204
37
RB
8R
B7
PGEC
3/R
B6
PGED
3/R
B5
VDD
RA
9R
A4
VSS
RC
5R
C4
RC
3
RB12PGEC2/RP11/CN15/PMD1/RB11PGED2/RP10/CN16/PMD2/RB10
VCAP
RC9RC8RC7RC6RB9
RB13 RB2RB3RC0RC1RC2
RB4
VDDVSSRA2RA3RA8
PGEC
1/A
N3/
C2I
N+/
RP
1/C
N5/
RB
1PG
ED1/
AN
2/C
2IN
-/RP
0/C
N4/
RB
0 R
A1
RA
0M
CLR
RA1
0
AVD
DAV
SSR
B15
RB1
4R
A7
Note 1: The bottom pad of QFN packages should be connected to VSS.
VBAT
1011
23456
1
18 19 20 21 2212 13 14 15
38
87
44 43 42 41 40 3916 17
2930313233
232425262728
36 3435
9
PIC24FJXXXGB204
37
RB
8R
B7
VB
US/R
B6
RB
5VD
D
RA
9R
A4
VSS
RC
5R
C4
RC
3
VUSB3V3PGEC2/RP11/CN15/D-/RB11
PGED2/RP10/CN16/D+/RB10VCAP
RC9RC8RC7RC6RB9
RB13 RB2RB3RC0RC1RC2
RB4
VDDVSSRA2RA3RA8
PGEC
1/A
N3/
C2I
N+/
RP1
/CN
5/R
B1
PGED
1/A
N2/
C2I
N-/R
P0/C
N4/
RB
0PG
EC3/
CV R
EF-
/AN
1/C
3IN
D/C
N3/
RA
1PG
ED3/
CV R
EF+
/AN
0/C
3IN
C/C
N2/
RA
0M
CLR
RA1
0
AVD
DAV
SSR
B15
RB1
4R
A7
VBAT
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FIGURE 2-6: PIN DIAGRAMS (44-PIN TQFP)RB
8R
B7
PGEC
3/R
B6
PGED
3/R
B5
VDD
RA
9R
A4
VSS
RC
5R
C4
RC
3
RB12PGEC2/RP11/CN15/PMD1/RB11PGED2/RP10/CN16/PMD2/RB10
VCAP
RC9RC8RC7RC6RB9
RB13 RB2RB3RC0RC1RC2
RB4
VDDVSSRA2RA3RA8
PGEC
1/A
N3/
C2I
N+/
RP1
/CN
5/R
B1PG
ED1/
AN
2/C
2IN
-/RP0
/CN
4/R
B0 R
A1R
A0M
CLR
RA
10
AVD
DAV
SSR
B15
RB
14R
A7
VBAT
RB
8R
B7
VB
US/R
B6R
B5
V DD
RA
9R
A4
VSS
RC
5R
C4
RC
3
VUSB3V3PGEC2/RP11/CN15/D-/RB11
PGED2/RP10/CN16/D+/RB10VCAP
RC9RC8RC7RC6RB9
RB13 RB2RB3RC0RC1RC2
RB4
VDDVSSRA2RA3RA8
PGEC
1/A
N3/
C2I
N+/
RP1
/CN
5/R
B1
PGED
1/A
N2/
C2I
N-/R
P0/C
N4/
RB
0PG
EC3/
CVR
EF-
/AN
1/C
3IN
D/C
N3/
RA
1PG
ED3/
CVR
EF+
/AN
0/C
3IN
C/C
N2/
RA
0M
CLR
RA1
0
AVD
DAV
SSR
B15
RB1
4R
A7
VBAT
1011
23456
1
18 19 20 21 2212 13 14 15
38
87
44 43 42 41 40 3916 17
2930313233
232425262728
36 3435
9
37
PIC24FJXXXGA204
1011
23456
1
18 19 20 21 2212 13 14 15
38
87
44 43 42 41 40 3916 17
2930313233
232425262728
36 3435
9
37
PIC24FJXXXGB204
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PIC24FJXXXGA2/GB2 FAMILIES
2.4 Memory MapThe program memory map extends from 000000h toFFFFFEh. Code storage is located at the base of thememory map and supports up to 87K instruction words(about 256 Kbytes). Table 2-2 shows the programmemory sizes, and the number of erase and programblocks present in each device variant. Each eraseblock or page contains 512 instructions and eachprogram block or row contains 64 instructions.Locations, 800000h through 8007FEh, are reserved forexecutive code memory. This region stores theProgramming Executive and the Debugging Executive.The Programming Executive is used for deviceprogramming and the Debugging Executive is used forin-circuit debugging. This region of memory cannot beused to store user code.
The last four implemented program memory locationsare reserved for the Flash Configuration Words. Thereserved addresses are provided in Table 2-2.
Locations, FF0000h and FF0002h, are reserved for theDevice ID registers. These bits can be used by theprogrammer to identify what device type is being pro-grammed. They are described in Section 6.1 “DeviceID”. The Device ID registers read out normally, evenafter code protection is applied.
Figure 2-7 displays the memory map for thePIC24FJXXXGA2/GB2 devices.
TABLE 2-2: CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJXXXGA2/GB2 DEVICES
DeviceUser MemoryAddress Limit
(Instruction Words)
Write Blocks
Erase Blocks
Configuration Word Addresses
1 2 3 4
PIC24FJ64GA2XX00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh 00ABF8h
PIC24FJ64GB2XXPIC24FJ128GA2XX
0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAh 0157F8hPIC24FJ128GB2XX
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FIGURE 2-7: PROGRAM MEMORY MAPUse
r Mem
ory
Spac
e
000000h
Flash Configuration Words
Code Memory(1)
0XXX00h(1)0XXXFEh(1)
Con
figur
atio
n M
emor
ySp
ace
800000h
Device IDFEFFFEhFF0000h
FFFFFEh
Reserved
Reserved
8007FEh
800880h
Executive Code Memory
7FFFFEh
FF0002hFF0004hReserved
(2 x 16-bit)
Note 1: The size and address boundaries for user Flash code memory are device dependent. See Table 2-2 for details.
User Flash
(1024 x 24-bit)
0XXXF8h(1)0XXXF7h(1)
800800h
8008FEh
80088Eh
Diagnostic andCalibration Words
(8 x 24-bit)
Reserved Memory
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3.0 DEVICE PROGRAMMING – ICSPICSP mode is a special programming protocol thatallows you to read and write to the memory ofPIC24FJXXXGA2/GB2 devices. The ICSP mode is themost direct method used to program the device; notehowever, that Enhanced ICSP is faster. ICSP modealso has the ability to read the contents of executivememory to determine if the Programming Executive ispresent. This capability is accomplished by applyingcontrol codes and instructions, serially to the device,using pins, PGECx and PGEDx.
In ICSP mode, the system clock is taken from thePGECx pin, regardless of the device’s Oscillator Con-figuration bits. All instructions are shifted serially into aninternal buffer, then loaded into the Instruction Register(IR) and executed. No program fetching occurs frominternal memory. Instructions are fed in, 24 bits at atime. PGEDx is used to shift data in, and PGECx isused as both the serial shift clock and the CPUexecution clock.
3.1 Overview of the Programming Process
Figure 3-1 shows the high-level overview of the pro-gramming process. After entering ICSP mode, the firstaction is to Chip Erase the device. Next, the codememory is programmed, followed by the deviceConfiguration registers. Code memory (including theConfiguration registers) is then verified to ensure thatprogramming was successful. Then, the code-protectConfiguration bits are programmed, if required.
FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW
3.2 ICSP OperationUpon entry into ICSP mode, the CPU is Idle. Executionof the CPU is governed by an internal state machine. A4-bit control code is clocked in using PGECx andPGEDx, and this control code is used to command theCPU (see Table 3-1).
The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device via the VISI register.
TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE
Note: During ICSP operation, the operatingfrequency of PGECx must not exceed10 MHz.
4-Bit Control Code Mnemonic Description
0000 SIX Shift in 24-bit instruction and execute.
0001 REGOUT Shift out the VISI (0784h) register.
0010-1111 N/A Reserved.
Start
Perform ChipErase
Program Memory
Verify Program
End
Enter ICSP™
Program Configuration Bits
Verify Configuration Bits
Exit ICSP
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3.2.1 SIX SERIAL INSTRUCTIONEXECUTIONThe SIX control code allows execution of PIC24Fassembly instructions. When the SIX code is received,the CPU is suspended for 24 clock cycles, as theinstruction is then clocked into the internal buffer. Oncethe instruction is shifted in, the state machine allows itto be executed over the next four PGECx clock cycles.While the received instruction is executed, the statemachine simultaneously shifts in the next 4-bitcommand (see Figure 3-2).
Coming out of Reset, the first 4-bit control code isalways forced to SIX and a forced NOP instruction isexecuted by the CPU. Five additional PGECx clocksare needed on start-up, resulting in a 9-bit SIXcommand instead of the normal 4-bit SIX command.
After the forced SIX is clocked in, ICSP operationresumes as normal. That is, the next 24 clock cyclesload the first instruction word to the CPU.
FIGURE 3-2: SIX SERIAL EXECUTION
3.2.1.1 Differences Between Execution of SIX and Normal Instructions
There are some differences between executing instruc-tions normally and using the SIX ICSP command. As aresult, the code examples in this specification may notmatch those for performing the same functions duringnormal device operation.
During SIX ICSP operation:
• Two-word instructions require two SIX operationsto clock in all of the necessary data.Examples of two-word instructions are GOTO andCALL.
• Two-cycle instructions require two SIX operations.The first SIX operation shifts in the instruction andbegins to execute it. The second SIX operation,which should shift in a NOP to avoid losing data,provides the CPU clocks required to finishexecuting the instruction.Examples of two-cycle instructions are Table Readand Table Write instructions.
• The CPU does not automatically stall to accountfor pipeline changes.A CPU Stall occurs when an instruction modifies aregister that is used for Indirect Addressing by thefollowing instruction.
During normal device operation:
• The CPU will automatically force a NOP while the newdata is read. When using ICSP, there is no automaticstall, so any indirect references to a recently modifiedregister should be preceded by a NOP.
For example, the instructions, MOV #0x0,W0 andMOV [W0],W1, must have a NOP insertedbetween them.If a two-cycle instruction modifies a register that isused indirectly, it will require two NOPs: one toexecute the second half of the instruction and theother to stall the CPU to correct the pipeline.Instructions, such as TBLWTL [W0++], [W1],should be followed by two NOPs.
• The device Program Counter (PC) continues toautomatically increment during ICSP instructionexecution, even though the Flash memory is notbeing used.As a result, the PC may be incremented to point toinvalid memory locations. Invalid memory spacesinclude unimplemented Flash addresses and thevector space (locations: 0x0 to 0x1FF).If the PC points to these locations, the device willreset, possibly interrupting the ICSP operation. Toprevent this, instructions should be periodicallyexecuted to reset the PC to a safe space. Theoptimal method to accomplish this is to perform aGOTO 0x200.
Note: To account for this forced NOP, all examplecode in this specification begins with aNOP to ensure that no data is lost.
P4
2 3 1 2 3 23 24 1 2 3 4P1
PGECx P4A
PGEDx
24-Bit Instruction FetchExecute PC – 1,
1 6
0 0 0 0
Fetch SIX
4 5 6 7 8 18 19 20 21 2217
LSB X X X X X X X X X X X X X X MSB
PGEDx = Input
P2
P3P1B
P1A
7 8 9
0 0 0 00 0 0
Only forProgram
Memory EntryControl Code
4 5
0 0
Execute 24-BitInstruction, Fetch
Next Control Code
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3.2.2 REGOUT SERIAL INSTRUCTIONEXECUTIONThe REGOUT control code allows for data to beextracted from the device in ICSP mode. It is used toclock the contents of the VISI register, out of the device,over the PGEDx pin. After the REGOUT control code isreceived, the CPU is held Idle for 8 cycles. After these8 cycles, an additional 16 cycles are required to clockthe data out (see Figure 3-3).
The REGOUT code is unique because the PGEDx pin isan input when the control code is transmitted to thedevice. However, after the control code is processed,the PGEDx pin becomes an output as the VISI registeris shifted out.
FIGURE 3-3: REGOUT SERIAL EXECUTION
Note 1: After the contents of VISI are shifted out,PIC24FJXXXGA2/GB2 devices maintainPGEDx as an output until the first risingedge of the next clock is received.
2: Data changes on the falling edge andlatches on the rising edge of PGECx.For all data transmissions, the LeastSignificant bit (LSb) is transmitted first.
1 2 3 4 1 2 7 8
PGECxP4
PGEDx
PGEDx = Input
Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register<15:0>
P5
PGEDx = Output
1 2 3 1 2 3 4
P4A
11 13 15 161412
No Execution Takes Place,Fetch Next Control Code
0 0 0 0 0
PGEDx = Input
MSb1 2 3 41
4 5 6
LSb 141312... 11100
Fetch REGOUT Control Code
0
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3.3 Entering ICSP ModeAs shown in Figure 3-4, entering ICSP Program/Verifymode requires three steps:1. MCLR is briefly driven high, then low.2. A 32-bit key sequence is clocked into PGEDx.3. MCLR is then driven high within a specified
period and held.
The programming voltage applied to MCLR is VIH, whichis essentially VDD in the case of PIC24FJXXXGA2/GB2devices. There is no minimum time requirement for hold-ing at VIH. After VIH is removed, an interval of at leastP18 must elapse before presenting the key sequence onPGEDx.
The key sequence is a specific 32-bit pattern:‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 4D434851h in hexadeci-mal). The device will enter Program/Verify mode only ifthe sequence is valid. The Most Significant bit (MSb) ofthe most significant nibble must be shifted in first.
Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time, P19 and P7, must elapse before present-ing data on PGEDx. Signals appearing on PGECxbefore P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can beaccessed and programmed in serial fashion. While inICSP mode, all unused I/Os are placed in thehigh-impedance state.
FIGURE 3-4: ENTERING ICSP™ MODE
MCLR
PGEDx
PGECx
VDD
P6P14
b31 b30 b29 b28 b27 b2 b1 b0b3...
Program/Verify Entry Code = 4D434851h
P1AP1B
P18
P19
0 1 0 0 0 0
P7VIH VIH
101
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3.4 Flash Memory Programming inICSP Mode
3.4.1 PROGRAMMING OPERATIONSFlash memory write and erase operations are controlledby the NVMCON register. Programming is performed bysetting NVMCON to select the type of erase operation(see Table 3-2) or write operation (see Table 3-3) andinitiating the programming by setting the WR control bit(NVMCON<15>).
In ICSP mode, all programming operations areself-timed. There is an internal delay between the usersetting the WR control bit and the automatic clearing ofthe WR control bit when the programming operation iscomplete. For information about the delays associatedwith various programming operations, refer toSection 7.0 “AC/DC Characteristics and TimingRequirements”.
TABLE 3-2: NVMCON ERASE OPERATIONS
TABLE 3-3: NVMCON WRITE OPERATIONS
3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE
The WR bit (NVMCON<15>) is used to start an eraseor write cycle. Setting the WR bit initiates theprogramming cycle.
All erase and write cycles are self-timed. The WR bitshould be polled to determine if the erase or write cyclehas been completed. Starting a programming cycle isperformed as follows:
3.5 Erasing Program MemoryThe procedure for erasing program memory (all of thecode memory, data memory, executive memory andcode-protect bits) consists of setting NVMCON to404Fh and executing the programming cycle.
A Chip Erase can erase all of the user memory or boththe user and configuration memory. A Table Writeinstruction should be executed, prior to performing theChip Erase, to select which sections are erased.
The Table Write instruction is executed:
• If the TBLPAG register points to user space (isless than 80h), the Chip Erase will erase only usermemory and Flash Configuration Words.
• If the TBLPAG register points to configurationspace (is greater than or equal to 80h), the ChipErase is not allowed. The configuration space canbe erased, one page at a time.
Figure 3-5 displays the ICSP programming process forperforming a Chip Erase. This process includes theICSP command code, which must be transmitted (foreach instruction), LSb first, using the PGECx andPGEDx pins (see Figure 3-2).
FIGURE 3-5: CHIP ERASE FLOW
NVMCONValue Erase Operation
404Fh Erase all code memory, executive memory and Configuration registers (does not erase Device ID registers).
4042h Erase a page of code memory or executive memory.
NVMCONValue Write Operation
4003h Write a single code memory word, Configuration Word or executive memory word.
4001h Program 1 row (64 instruction words) of code memory or executive memory.
BSET NVMCON, #WR
Note: The Chip Erase is not allowed when theTBLPAG points to the configuration spaceto avoid the diagnostic and calibrationwords from getting erased.
Note: Program memory must be erased beforewriting any data to program memory.
Start
End
Set the WR bit to Initiate Erase
Write 404Fh to NVMCON SFR
Is WR bit
Yes
Nocleared (‘0’)?
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TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASECommand(Binary)
Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Set the NVMCON register to erase all program memory.00000000
2404FA883B0A
MOV #0x404F, W10MOV W10, NVMCON
Step 3: Set the TBLPAG register and perform a dummy Table Write to select what portions of memory are erased.000000000000000000000000
2xxxx08802A0200000BB0800000000000000
MOV #<PAGEVAL>, W0MOV W0, TBLPAGMOV #0x0000, W0TBLWTL W0,[W0]NOPNOP
Step 4: Initiate the erase cycle.000000000000
A8E761000000000000
BSET NVMCON, #WRNOPNOP
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000
040200000000803B02883C22000000<VISI>000000
GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI registerNOP
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3.6 Writing Code MemoryThe procedure for writing code memory is the same asthe procedure for writing the Configuration registers,except that 64 instruction words are programmed at atime. To facilitate this operation, Working registers,W0:W5, are used as temporary holding registers for thedata to be programmed.Table 3-5 provides the ICSP programming details,including the serial pattern with the ICSP commandcode which must be transmitted, LSb first, using thePGECx and PGEDx pins (see Figure 3-2).
In Step 1, the Reset vector is exited. In Step 2, theNVMCON register is initialized for programming a fullrow of code memory. In Step 3, the 24-bit starting des-tination address for programming is loaded into theTBLPAG register and W7 register. (The upper byte ofthe starting destination address is stored in TBLPAGand the lower 16 bits of the destination address arestored in W7.)
To minimize the programming time, a packedinstruction format is used (see Figure 3-6).
In Step 4, four packed instruction words are stored inWorking registers, W0:W5, using the MOV instruction.The Read Pointer, W6, is initialized. The contents ofW0:W5 (holding the packed instruction word data) areshown in Figure 3-6.
In Step 5, eight TBLWT instructions are used to copy thedata from W0:W5 to the write latches of code memory.Since code memory is programmed, 64 instructionwords at a time, Steps 4 and 5 are repeated, 16 times,to load all the write latches (Step 6).
After the write latches are loaded, programming isinitiated by writing to the NVMCON register in Steps 7and 8. In Step 9, the internal PC is reset to 200h. Thisis a precautionary measure to prevent the PC fromincrementing into unimplemented memory when largedevices are being programmed. Lastly, in Step 10,Steps 3-9 are repeated until all of the code memory isprogrammed.
FIGURE 3-6: PACKED INSTRUCTION WORDS IN W0:W5
15 8 7 0W0 LSW0W1 MSB1 MSB0W2 LSW1W3 LSW2W4 MSB3 MSB2W5 LSW3
TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORYCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Set the NVMCON register to program 64 instruction words.00000000
24001A883B0A
MOV #0x4001, W10MOV W10, NVMCON
Step 3: Initialize the Write Pointer (W7) for the TBLWT instruction.000000000000
200xx08802A02xxxx7
MOV #<DestinationAddress23:16>, W0MOV W0, TBLPAGMOV #<DestinationAddress15:0>, W7
Step 4: Load W0:W5 with the next 4 instruction words to program.000000000000000000000000
2xxxx02xxxx12xxxx22xxxx32xxxx42xxxx5
MOV #<LSW0>, W0MOV #<MSB1:MSB0>, W1MOV #<LSW1>, W2MOV #<LSW2>, W3MOV #<MSB3:MSB2>, W4MOV #<LSW3>, W5
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Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
EB0300000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000
CLR W6NOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOP
Step 6: Repeat Steps 4 and 5, 16 times, to load the write latches for 64 instructions. Step 7: Initiate the write cycle.
000000000000
A8E761000000000000
BSET NVMCON, #WRNOPNOP
Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000
040200000000803B02883C22000000<VISI>000000
GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP
Step 9: Reset the device’s internal PC.00000000
040200000000
GOTO 0x200NOP
Step 10: Repeat Steps 3 through 9 until all code memory is programmed.
TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)Command
(Binary)Data(Hex) Description
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FIGURE 3-7: PROGRAM CODE MEMORY FLOWStart Write Sequence
Alllocations
done?
No
End
Start
Yes
Load 1 Instruction WordWrite Buffer at <Addr>
Allinstruction words
written?
No
Yes
and Poll for WR bitto be Cleared
N = 1LoopCount = 0
ConfigureDevice for
Writes
N = 1LoopCount =
LoopCount + 1
N = N + 1
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3.7 Writing Configuration WordsDevice configuration for PIC24FJXXXGA2/GB2 devicesis stored in the Flash Configuration Words at the end ofthe user space program memory and in multiple Config-uration Word registers located in the test space. Theseregisters reflect values read at any Reset from programmemory locations. The values for the ConfigurationWords for the default device configurations are listed inTable 3-6.TABLE 3-6: DEFAULT CONFIGURATION REGISTER VALUES
The values can be changed only by programming thecontent of the corresponding Flash Configuration Wordand resetting the device. The Reset forces an auto-matic reload of the Flash stored configuration values bysequencing through the dedicated Flash ConfigurationWords and transferring the data into the Configurationregisters.
For the PIC24FJXXXGA2/GB2 devices, certainreserved Configuration bits have default states thatmust always be maintained to ensure device function-ality, regardless of the settings of other Configurationbits. These bits and their values are listed in Table 3-7.
To change the values of the Flash Configuration Wordonce it has been programmed, the device must be ChipErased, as described in Section 3.5 “Erasing Pro-gram Memory”, and reprogrammed to the desiredvalue. It is not possible to program a ‘0’ to a ‘1’; a ‘1’ toa ‘0’ may be programmed to enable code protection.
Table 3-8 provides the ICSP programming details forprogramming the Configuration Word locations. Thisincludes the serial pattern with the ICSP commandcode which must be transmitted, LSb first, using thePGECx and PGEDx pins (see Figure 3-2).
In Step 1, the Reset vector is exited. In Step 2, the lower16 bits of the source address are stored in W7. InStep 3, the NVMCON register is initialized for program-ming of code memory. In Step 4, the upper byte of the24-bit starting source address for writing is loaded intothe TBLPAG register.
The TBLPAG register must be loaded with 00h for64 Kbytes, and 01h for 128-Kbyte and 256-Kbytedevices.
To verify the data by reading the Configuration Wordsafter performing the write in order, the code protectionbits should initially be programmed to a ‘1’ to ensurethat the verification can be performed properly. Afterverification is finished, the code protection bit can beprogrammed to a ‘0’ by using a word write to theappropriate Configuration Word.
TABLE 3-7: RESERVED CONFIGURATION BIT LOCATIONS
Address Name Default Value
Last Word CW1 7FFFhLast Word – 2 CW2 BFFFh(1)
Last Word – 4 CW3 FFFFhLast Word – 6 CW4 FFFFhNote 1: For the PIC24FJXXXGB2 family, the
default value is BFFFh. For the PIC24FJXXXGA2 family, the default value is B7FFh.
Family Register/Bits Value Comments
All Devices CW1<15> 0 Always program as ‘0’; required to maintain device functionality.CW2<2> 1 Always program as ‘1’.
CW2<14> 0 Always program as ‘0’.CW3<7> 1 Always program as ‘1’.CW4<9> 1 Always program as ‘1’.
PIC24FJXXGA2XX CW2<11> 0 Always program as ‘0’.
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TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERSCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction.0000 2xxxx7 MOV #<CW1Address15:0>, W7
Step 3: Set the NVMCON register to program CW1.00000000
24003A883B0A
MOV #0x4003, W10MOV W10, NVMCON
Step 4: Initialize the TBLPAG register.00000000
200xx08802A0
MOV #<CW1Address23:16>, W0MOV W0, TBLPAG
Step 5: Load the Configuration register data to W6.0000 2xxxx6 MOV #<CW1_VALUE>, W6
Step 6: Write the Configuration register data to the write latch and decrement the Write Pointer.00000000000000000000000000000000
200008000000BBCB88000000000000BB1386000000000000
MOV #0x0000, W8NOPTBLWTH.B W8, [W7]NOPNOPTBLWTL.W W6, [W7--]NOPNOP
Step 7: Initiate the write cycle.000000000000
A8E761000000000000
BSET NVMCON, #WRNOPNOP
Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000
040200000000803B02883C22000000<VISI>000000
GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP
Step 9: Reset the device’s internal PC.00000000
040200000000
GOTO 0x200NOP
Step 10: Repeat Steps 5 through 9 to write Configuration Word 2 to Configuration Word 4.
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3.8 Reading Code MemoryReading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.Table 3-9 provides the ICSP programming details forreading code memory. In Step 1, the Reset vector isexited. In Step 2, the Write Pointer, W7, is initialized. InStep 3, the 24-bit starting source address for reading isloaded into the TBLPAG and W6 registers. The upperbyte of the starting source address is stored in TBLPAGand the lower 16 bits of the source address are storedin W6.
To minimize the reading time, the packed instructionword format that was utilized for writing is also used forreading (see Figure 3-6). In Step 4, two instructionwords are read from code memory and clocked out ofthe device, through the VISI register, using the REGOUTcommand. Step 4 is repeated until the desired amountof code memory is read.
TABLE 3-9: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORYCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the Write Pointer (W7) to point to the VISI register.00000000
207847000000
MOV #VISI, W7 NOP
Step 3: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.000000000000
200xx08802A02xxxx6
MOV #<SourceAddress23:16>, W0MOV W0, TBLPAGMOV #<SourceAddress15:0>, W6
Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using the REGOUT command.
000000000000000100000000000000000000000000000001000000000000000000010000
BA0B96000000000000<VISI>000000BADBB6000000000000BAD3D6000000000000<VISI>000000BA0BB6000000000000<VISI>000000
TBLRDL [W6], [W7]NOPNOPClock out contents of the VISI registerNOPTBLRDH.B [W6++], [W7++]NOPNOPTBLRDH.B [++W6], [W7--]NOPNOPClock out contents of the VISI registerNOPTBLRDL [W6++], [W7]NOPNOPClock out contents of the VISI registerNOP
Step 5: Reset the device’s internal PC.00000000
040200000000
GOTO 0x200NOP
Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset the device’s internal PC” will be Step 5).
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3.9 Reading Configuration WordsThe procedure for reading configuration memory issimilar to the procedure for reading code memory,except that 16-bit data words are read instead of 24-bitwords. Configuration Words are read, one register at atime.Table 3-10 provides the ICSP programming details forreading the Configuration Words. Note that theTBLPAG register must be loaded with 00h for64 Kbytes, and 01h for 128-Kbyte and 256-Kbytedevices. W6 is initialized to the lower 16 bits of theConfiguration Word location.
TABLE 3-10: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORYCommand(Binary)
Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the TBLPAG register, the Read Pointer (W6) and the Write Pointer (W7) for the TBLRD instruction.00000000000000000000
200xx08802A02xxxx6207847000000
MOV #<CW1Address23:16>, W0MOV W0, TBLPAGMOV #<CW1Address15:0>, W6MOV #VISI, W7NOP
Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command.
00000000000000010000
BA0BA6000000000000<VISI>000000
TBLRDL [W6--], [W7]NOP NOPClock out contents of the VISI registerNOP
Step 4: Repeat Step 3 to read Configuration Word 2 to Configuration Word 4. Step 5: Reset the device’s internal PC.
00000000
040200000000
GOTO 0x200NOP
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3.10 Verify Code Memory andConfiguration WordThe verify step involves reading back the code memoryspace and comparing it with the copy held in theprogrammer’s buffer. The Configuration registers areverified with the rest of the code.
The verify process is shown in the flowchart inFigure 3-8. Memory reads occur, a single byte at atime, so two bytes must be read to compare against theword in the programmer’s buffer. Refer to Section 3.8“Reading Code Memory” for implementation detailsof reading code memory.
FIGURE 3-8: VERIFY CODE MEMORY FLOW
3.11 Reading the Application ID WordThe Application ID Word is stored at address,8007F0h, in executive code memory. To read thismemory location, you must use the SIX control code tomove this program memory location to the VISI regis-ter. Then, the REGOUT control code must be used toclock the contents of the VISI register out of the device.Table 3-11 provides the corresponding control andinstruction codes that must be serially transmitted tothe device to perform this operation.
After the programmer has clocked out the ApplicationID Word, it must be inspected. If the Application ID hasthe value, CEh, the Programming Executive is residentin memory and the device can be programmed usingthe mechanism described in Section 4.0 “Device Pro-gramming – Enhanced ICSP”. However, if theApplication ID has any other value, the ProgrammingExecutive is not resident in memory; it must be loadedto memory before the device can be programmed. Theprocedure for loading the Programming Executive tomemory is described in Section 5.4 “Programmingthe Programming Executive to Memory”.
3.12 Exiting ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as shown in Figure 3-9. The only require-ment for exit is that an interval, P16, should elapsebetween the last clock, and program signals on PGECxand PGEDx, before removing VIH.
FIGURE 3-9: EXITING ICSP™ MODE
Note: Because the Configuration registersinclude the device code protection bit,code memory should be verified immedi-ately after writing if code protection isenabled. This is because the device willnot be readable or verifiable if a deviceReset occurs after the code-protect bit inCW1 has been cleared.
Read Low Byte
Read High Byte
DoesWord = Expect
Data?
Failure,ReportError
Allcode memory
verified?
No
Yes
No
Set TBLPTR = 0
Start
Yes
End
with Post-Increment
with Post-Increment
MCLR
P16
PGEDx
PGEDx = Input
PGECx
VDD
VIH
VIH
P17
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TABLE 3-11: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORDCommand(Binary)
Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the TBLPAG register and the Read Pointer (W0) for the TBLRD instruction.00000000000000000000000000000000
2008008802A0207F00207841000000BA0890000000000000
MOV #0x80, W0MOV W0, TBLPAGMOV #0x07F0, W0MOV #VISI, W1NOPTBLRDL [W0], [W1]NOPNOP
Step 3: Output the VISI register using the REGOUT command.00010000
<VISI>000000
Clock out contents of the VISI registerNOP
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4.0 DEVICE PROGRAMMING – ENHANCED ICSP
This section discusses programming the devicethrough Enhanced ICSP and the Programming Execu-tive. The Programming Executive resides in executivememory (separate from code memory) and is executedwhen Enhanced ICSP Programming mode is entered.The Programming Executive provides the mechanismfor the programmer (host device) to program and verifythe PIC24FJXXXGA2/GB2 devices, using a simplecommand set and communication protocol. There areseveral basic functions provided by the ProgrammingExecutive:
• Read Memory• Erase Memory• Program Memory• Blank Check• Read Executive Firmware Revision
The Programming Executive performs the low-leveltasks required for erasing, programming and verifying adevice. This allows the programmer to program thedevice by issuing the appropriate commands and data.Table 4-1 summarizes the commands. A detaileddescription for each command is provided in Section 5.2“Programming Executive Commands”.
TABLE 4-1: COMMAND SET SUMMARY
The Programming Executive uses the device’s dataRAM for variable storage and program execution. Afterthe Programming Executive has run, no assumptionsshould be made about the contents of data RAM.
4.1 Overview of the Programming Process
Figure 4-1 shows the high-level overview of theprogramming process. After entering Enhanced ICSPmode, the Programming Executive is verified. Next, thedevice is erased. Then, the code memory is pro-grammed, followed by the configuration locations. Codememory (including the Configuration registers) is thenverified to ensure that programming was successful.
After the Programming Executive has been verifiedin memory (or loaded if not present), thePIC24FJXXXGA2/GB2 devices can be programmedusing the command set provided in Table 4-1.
FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW
4.2 Confirming the Presence of the Programming Executive
Before programming can begin, the programmer mustconfirm that the Programming Executive is stored inexecutive memory. The procedure for this task isshown in Figure 4-2.
First, ICSP mode is entered. Then, the unique Applica-tion ID Word stored in executive memory is read. If theProgramming Executive is resident, the Application IDWord is CEh, which means programming can resumeas normal. However, if the Application ID Word is notCEh, the Programming Executive must be programmedto executive code memory using the method describedin Section 5.4 “Programming the ProgrammingExecutive to Memory”.
Section 3.0 “Device Programming – ICSP” describesthe ICSP programming method. Section 3.11 “Readingthe Application ID Word” describes the procedure forreading the Application ID Word in ICSP mode.
Command Description
SCHECK Sanity CheckREADC Read Device ID RegistersREADP Read Code Memory PROGP Program One Row of Code Memory
and VerifyPROGW Program One Word of Code Memory
and VerifyQBLANK Query if the Code Memory is BlankQVER Query the Software Version
Start
End
Perform ChipErase
Program Memory
Verify Program
Enter Enhanced ICSP™
Program Configuration Bits
Verify Configuration Bits
Exit Enhanced ICSP
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FIGURE 4-2: CONFIRMING PRESENCEOF PROGRAMMING EXECUTIVE
4.3 Entering Enhanced ICSP ModeAs shown in Figure 4-3, entering Enhanced ICSPProgram/Verify mode requires three steps:
1. The MCLR pin is briefly driven high, then low.2. A 32-bit key sequence is clocked into PGEDx.3. MCLR is then driven high within a specified
period and held.
The programming voltage applied to MCLR is VIH, whichis essentially VDD in the case of PIC24FJXXXGA2/GB2devices. There is no minimum time requirement for hold-ing at VIH. After VIH is removed, an interval of at leastP18 must elapse before presenting the key sequence onPGEDx.
The key sequence is a specific 32-bit pattern:‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 4D434850h in hexadeci-mal format). The device will enter Program/Verify modeonly if the key sequence is valid. The MSb of the mostsignificant nibble must be shifted in first.
Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time, P19 and P7, must elapse before present-ing data on PGEDx. Signals appearing on PGEDx,before P7 has elapsed, will not be interpreted as valid.
On successful entry, the program memory can beaccessed and programmed in serial fashion. While inthe Program/Verify mode, all unused I/Os are placed inthe high-impedance state.
FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE
Is
Start
Enter ICSP™ Mode
Application IDCEh?
Resident in Memory
Yes
No
Prog. Executive is
Application IDRead the
be ProgrammedProg. Executive must
from Address8007F0h
End
MCLR
PGEDx
PGECx
VDD
P6P14
b31 b30 b29 b28 b27 b2 b1 b0b3...
Program/Verify Entry Code = 4D434850h
P1AP1B
P18
P19
0 1 0 0 1 0 0 0 0
P7VIH VIH
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4.4 Blank CheckThe term, “Blank Check”, implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as ‘1’.The Device ID registers (FF0002h:FF0000h) can beignored by the Blank Check since this region storesdevice information that cannot be erased. The deviceConfiguration registers are also ignored by the BlankCheck. Additionally, all unimplemented memory spaceshould be ignored by the Blank Check.
The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.
4.5 Code Memory Programming
4.5.1 PROGRAMMING METHODOLOGYCode memory is programmed with the PROGPcommand. PROGP programs one row of code memory,starting from the memory address specified in thecommand. The number of PROGP commands requiredto program a device depends on the number of writeblocks that must be programmed in the device.
A flowchart for programming the code memory of thePIC24FJXXXGA2/GB2 devices is shown in Figure 4-4.In this example, all 87K instruction words of a256-Kbyte device are programmed. First, the numberof commands to send (called ‘RemainingCmds’ in theflowchart) is set to 1368 and the destination address(called ‘BaseAddress’) is set to ‘0’. Next, one writeblock in the device is programmed with a PROGP com-mand. Each PROGP command contains data for onerow of code memory of the device. After the firstcommand is processed successfully, ‘RemainingCmds’is decremented by 1 and compared with 0. Since thereare more PROGP commands to send, ‘BaseAddress’ isincremented by 80h to point to the next row of memory.
On the second PROGP command, the second row isprogrammed. This process is repeated until the entiredevice is programmed. No special handling must beperformed when a panel boundary is crossed.
FIGURE 4-4: FLOWCHART FOR PROGRAMMING CODE MEMORY
4.5.2 PROGRAMMING VERIFICATIONAfter code memory is programmed, the contents ofmemory can be verified to ensure that programmingwas successful. Verification requires code memory tobe read back and compared with the copy held in theprogrammer’s buffer.
The READP command can be used to read back all ofthe programmed code memory.
Alternatively, you can have the programmer performthe verification, after the entire device is programmed,using a checksum computation.
IsPROGP Response
PASS?
AreRemainingCmds 0?
BaseAddress = 00hRemainingCmds = 1368
RemainingCmds =RemainingCmds – 1
BaseAddress =BaseAddress + 80h
No
No
Yes
Yes
Start
FailureReport Error
Send PROGPCommand to Program
BaseAddress
Finish
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4.6 Configuration Bits Programming4.6.1 OVERVIEWThe PIC24FJXXXGA2/GB2 devices have Configura-tion bits stored in the last four locations of implementedprogram memory (see Table 2-2 for locations). Thesebits can be set or cleared to select various deviceconfigurations.
There are two types of Configuration bits: system oper-ation bits and code-protect bits. The system operationbits determine the power-on settings for system-levelcomponents, such as the oscillator and WatchdogTimer. The code-protect bits prevent program memoryfrom being read and written.
The descriptions for the Configuration bits for thePIC24FJXXXGA2/GB2 device families are shown inTable 4-2.
Note: Although not implemented with a specificfunction, some Configuration bit positionshave default states that must always bemaintained to ensure device functionality,regardless of the settings of other Config-uration bits. Refer to Table 3-7 for a list ofthese bit positions and their default states.
TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONSBit Field Register(1) Description
ALTCMPI CW2<12> Alternate Comparator Input bit1 = C1INC is on RB13, C2INC is on RB9 and C3INC is on RA00 = C1INC, C2INC and C3INC are on RB9
ALTRB6(2,3) CW2<11> Alternate RB6 Pin Functions Location Enable bit1 = Appends the RP6/ASCL1/PMD6 functions of RB6 to RA1 pin functions0 = Retains the RP6/ASCL1/PMD6 functions to RB6
BOREN CW3<12> Brown-out Reset Enable bit1 = BOR is enabled in hardware (outside of Deep Sleep)0 = BOR is disabled
DEBUG CW1<11> Background Debugger Enable bit1 = Device resets into Operational mode0 = Device resets into Debug mode
DSSWEN CW4<8> Deep Sleep Software Control bit1 = Deep Sleep operation is enabled and controlled by the DSEN bit0 = Deep Sleep operation is always disabled
DSWDTEN CW4<7> Deep Sleep Watchdog Timer (DSWDT) Enable bit1 = DSWDT is enabled in Deep Sleep0 = DSWDT is disabled
DSBOREN CW4<6> Deep Sleep BOR Enable bit1 = BOR is enabled in Deep Sleep0 = BOR is disabled in Deep Sleep (does not affect Sleep mode)
DSWDTOSC CW4<5> DSWDT Reference Clock Select bit1 = DSWDT uses LPRC as the reference clock0 = DSWDT uses SOSC as the reference clock
Note 1: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.
2: This bit must be ‘1’ whenever VBUS functionality is used.3: This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’.4: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).5: Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the
Configuration Words page, the Configuration Words page will be protected.6: Reserved; do not use for the PIC24FJXXXGA20X family.
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DSWDTPS<4:0> CW4<4:0> Deep Sleep Watchdog Timer Postscale Select bitsThe DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.11111 = 1:68,719,476736 (25.7 days)11110 = 1:34,359,738368(12.8 days)11101 = 1:17,179,869184 (6.4 days)11100 = 1:8,589,934592 (77.0 hours)11011 = 1:4,294,967296 (38.5 hours)11010 = 1:2,147,483648 (19.2 hours)11001 = 1:1,073,741824 (9.6 hours)11000 = 1:536,870912 (4.8 hours)10111 = 1:268,435456 (2.4 hours)10110 = 1:134,217728 (72.2 minutes)10101 = 1:67,108864 (36.1 minutes)10100 = 1:33,554432 (18.0 minutes)10011 = 1:16,777216 (9.0 minutes)10010 = 1:8,388608 (4.5 minutes)10001 = 1:4,194304 (135.3s)10000 = 1:2,097152 (67.7s)01111 = 1:1,048576 (33.825s)01110 = 1:524288 (16.912s)01101 = 1:262114 (8.456s)01100 = 1:131072 (4.228s)01011 = 1:65536 (2.114s)01010 = 1:32768 (1.057s)01001 = 1:16384 (528.5 ms)01000 = 1:8192 (264.3 ms)00111 = 1:4096 (132.1 ms)00110 = 1:2048 (66.1 ms)00101 = 1:1024 (33 ms)00100 = 1:512 (16.5 ms)00011 = 1:256 (8.3 ms)00010 = 1:128 (4.1 ms)00001 = 1:64 (2.1 ms)00000 = 1:32 (1 ms)
FCKSM<1:0> CW2<7:6> Clock Switching and Fail-Safe Clock Monitor Selection Configuration bits1x = Clock switching and Fail-Safe Clock Monitor are disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)Bit Field Register(1) Description
Note 1: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.
2: This bit must be ‘1’ whenever VBUS functionality is used.3: This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’.4: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).5: Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the
Configuration Words page, the Configuration Words page will be protected.6: Reserved; do not use for the PIC24FJXXXGA20X family.
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FNOSC<2:0> CW2<10:8> Initial Oscillator Source Selection bits111 = Fast RC Oscillator with Postscaler module (FRCDIV)110 = Reserved101 = Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC)001 = Fast RC Oscillator with Postscaler and PLL modules (FRCPLL)000 = Fast RC (FRC) Oscillator
FWDTEN<1:0> CW1<7:6> Watchdog Timer Configuration bits11 = Watchdog Timer is enabled in hardware10 = Watchdog Timer is controlled with the SWDTEN bit setting01 = Watchdog Timer is enabled only while device is active and disabled
in Sleep; SWDTEN bit is disabled00 = Watchdog Timer is disabled in hardware; SWDTEN bit is disabled
FWPSA CW1<4> Watchdog Timer Prescaler Ratio Select bit1 = Watchdog Timer prescaler ratio of 1:1280 = Watchdog Timer prescaler ratio of 1:32
GCP CW1<13> General Segment Program Memory Code Protection bit1 = Code protection is disabled0 = Code protection is enabled for the entire program memory space
GWRP CW1<12> General Segment Code Flash Write Protection bit1 = Writes to program memory are allowed0 = Writes to program memory are disabled
I2C1SEL CW4<14> Alternate I2C1 Location Select bit1 = I2C1 is multiplexed to SDA1 and SCL1 (default)0 = I2C1 is multiplexed to ASDA1 and ASCL1
ICS<1:0> CW1<9:8> ICD Emulator Pin Placement Select bits11 = Emulator functions are shared with PGEC1/PGED110 = Emulator functions are shared with PGEC2/PGED201 = Emulator functions are shared with PGEC3/PGED300 = Reserved; do not use
IESO CW2<15> Internal External Switchover bit1 = Two-Speed Start-up is enabled0 = Two-Speed Start-up is disabled
IOL1WAY CW4<15> IOLOCK Bit One-Way Set Enable bit1 = The IOLOCK bit (OSCCON<6>) can be set once, provided an unlock
sequence has been completed. Once set, the Peripheral Pin Select(PPS) registers cannot be written to a second time.
0 = The IOLOCK is cleared as needed (provided an unlocking sequenceis executed)
TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)Bit Field Register(1) Description
Note 1: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.
2: This bit must be ‘1’ whenever VBUS functionality is used.3: This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’.4: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).5: Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the
Configuration Words page, the Configuration Words page will be protected.6: Reserved; do not use for the PIC24FJXXXGA20X family.
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JTAGEN(4) CW1<14> JTAG Enable bit1 = JTAG port is enabled0 = JTAG port is disabled
LPCFG CW1<10> Low-Power (Low-Voltage) Regulator Control Enable bit1 = Low-voltage regulator is disabled, regardless of the RETEN bit0 = Low-voltage regulator feature is available and controlled by the
RETEN bit during SleepOSCIOFCN CW2<5> OSC2 Pin Function bit (except in XT and HS modes)
If POSCMD<1:0> = 11 or 00:1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2)0 = OSCO/CLKO/RA3 functions as port I/O (RA3)If POSCMD<1:0> = 10 or 01:OSCIOFCN has no effect on OSCO/CLKO/RA3.
PLLDIV<3:0> CW4<13:10> PLL Input Prescaler Select bits1111 = PLL is disabled1110 = 8 x PLL is selected1101 = 6 x PLL is selected1100 = 4 x PLL is selected1011 = }
• }• } Reserved; do not use• }
1001 = }0111 = Oscillator divided by 12 (48 MHz input)(6)
0110 = Oscillator divided by 8 (32 MHz input)(6)
0101 = Oscillator divided by 6 (24 MHz input)(6)
0100 = Oscillator divided by 5 (20 MHz input)(6)
0011 = Oscillator divided by 4 (16 MHz input)(6)
0010 = Oscillator divided by 3 (12 MHz input)(6)
0001 = Oscillator divided by 2 (8 MHz input)(6)
0000 = Oscillator used directly (4 MHz input)(6)
PLLSS CW3<11> PLL Secondary Source Select bit1 = Primary Oscillator0 = FRC Oscillator (8 MHz source)
POSCMD<1:0> CW2<1:0> Primary Oscillator Mode Select bits11 = Primary Oscillator mode is disabled10 = HS Oscillator mode is selected01 = XT Oscillator mode is selected00 = EC Oscillator mode is selected
SOSCSEL CW3<8> SOSC Selection Configuration bit1 = Secondary Crystal Oscillator (SOSC) mode0 = Digital External Clock (SCLKI) mode
TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)Bit Field Register(1) Description
Note 1: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.
2: This bit must be ‘1’ whenever VBUS functionality is used.3: This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’.4: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).5: Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the
Configuration Words page, the Configuration Words page will be protected.6: Reserved; do not use for the PIC24FJXXXGA20X family.
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WDTCLK<1:0> CW2<4:3> WDT Clock Source Select bitsWhen WDTCMX = 1:11 = WDT uses LPRC10 = WDT uses 31 kHz source from FRC when active in Windowed WDT
mode and when not using LPRC as the system clock; uses LPRCduring Sleep mode and for all other settings
01 = WDT uses SOSC input00 = WDT uses system clock when active, LPRC while in Sleep modeWhen WDTCMX = 0:WDTCLKx bits are ignored, LPRC is the WDT clock source.
WDTCMX CW2<13> Watchdog Timer Clock Multiplex Select bit1 = WDT clock source is determined by the WDTCLKx Configuration bits0 = WDT always uses LPRC as its clock source
WDTPS<3:0> CW1<3:0> Watchdog Timer Postscaler bits1111 = 1:32,7681110 = 1:16,384
•••
0001 = 1:20000 = 1:1
WDTWIN<1:0> CW3<10:9> Watchdog Timer Window Width bits00 = 75%01 = 50%10 = 37.5%11 = 25%
WINDIS CW1<5> Windowed WDT bit1 = Standard Watchdog Timer is enabled0 = Windowed Watchdog Timer is enabled; FWDTEN<1:0> must not
be ‘00’WPCFG CW3<14> Configuration Word Code Page Write Protection Select bit
1 = Last page (at the top of program memory) and Flash ConfigurationWords are not write-protected(5)
0 = Last page and Flash Configuration Words are write-protectedprovided WPDIS = 0
WPDIS CW3<13> Segment Write Protection Disable bit1 = Segmented code protection is disabled0 = Segmented code protection is enabled; protected segment is defined
by the WPEND, WPCFG and WPFPx Configuration bits
TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)Bit Field Register(1) Description
Note 1: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.
2: This bit must be ‘1’ whenever VBUS functionality is used.3: This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’.4: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).5: Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the
Configuration Words page, the Configuration Words page will be protected.6: Reserved; do not use for the PIC24FJXXXGA20X family.
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WPEND CW3<15> Segment Write Protection End Page Select bit1 = Protected code segment upper boundary is at the last page of
program memory; lower boundary is the code page specified byWPFP<6:0>(5)
0 = Protected code segment lower boundary is at the bottom of programmemory (000000h); upper boundary is the code page specified byWPFP<6:0>
WPFP<6:0> CW3<6:0> Write-Protect Program Flash Pages bits (valid when WPDIS = 0)(5)
When WPEND = 0:Erase/write-protect Flash memory pages, starting at Page 0 and endingwith Page WPFP<6:0>.When WPEND = 1:Erase/write-protect Flash memory pages, starting at Page WPFP<6:0>and ending with the last page in user Flash memory.
TABLE 4-2: PIC24FJXXXGA2/GB2 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)Bit Field Register(1) Description
Note 1: Bits<23:16> should be programmed to a value of 00h to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.
2: This bit must be ‘1’ whenever VBUS functionality is used.3: This bit is reserved in PIC24FJXXXGA20X devices; the default value is ‘0’.4: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).5: Irrespective of the WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the
Configuration Words page, the Configuration Words page will be protected.6: Reserved; do not use for the PIC24FJXXXGA20X family.
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4.6.2 PROGRAMMING METHODOLOGYConfiguration bits may be programmed, a single wordat a time, using the PROGW command. This commandspecifies the configuration data and Configurationregister address. When Configuration bits are pro-grammed, any unimplemented or reserved bits must beprogrammed with a ‘1’.Four PROGW commands are required to program theConfiguration bits. A flowchart for Configuration bitprogramming is shown in Figure 4-5.
4.6.3 PROGRAMMING VERIFICATIONAfter the Configuration bits are programmed, thecontents of memory should be verified to ensure thatthe programming was successful. Verification requiresthe Configuration bits to be read back and comparedwith the copy held in the programmer’s buffer. TheREADP command reads back the programmedConfiguration bits and verifies that the programmingwas successful.
FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW
Note: If the General Segment Code-Protect bit(GCP) is programmed to ‘0’, codememory is code-protected and cannot beread. Code memory must be verifiedbefore enabling read protection. SeeSection 4.6.4 “Code-Protect Configu-ration Bits” for more information aboutcode-protected Configuration bits.
Send PROGWCommand
ConfigAddress = 0XXXF8h(1)
IsPROGP response
PASS?
No
Yes
No
FailureReport Error
Start
End
Yes
IsConfigAddress0XXXFEh?(1)
ConfigAddress =ConfigAddress + 2
Note 1: Refer to Table 2-2 for Flash Configuration Word addresses.
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4.6.4 CODE-PROTECT CONFIGURATIONBITSPIC24FJXXXGA2/GB2 devices provide two compli-mentary methods to protect application code fromoverwrites and erasures. These methods also help toprotect the device from inadvertent configurationchanges during run time. Additional information isavailable in the product data sheet.
4.6.4.1 GENERAL SEGMENT PROTECTION
For the PIC24FJXXXGA2/GB2 devices, the on-chipprogram memory space is treated as a single block,known as the General Segment (GS). Code protectionfor this block is controlled by one Configuration bit, GCP.This bit inhibits external reads and writes to the programmemory space; it has no direct effect in normalexecution mode.
Write protection is controlled by the GWRP bit in theConfiguration Word. When GWRP is programmed to‘0’, internal write and erase operations to the programmemory are blocked.
4.6.4.2 CODE SEGMENT PROTECTIONIn addition to global General Segment protection, aseparate subrange of the program memory space canbe individually protected against writes and erases.This area can be used for many purposes, where aseparate block of write and erase-protected code isneeded, such as bootloader applications. Unlikecommon boot block implementations, the specially pro-tected segment in PIC24FJXXXGA2/GB2 devices canbe located by the user anywhere in the program spaceand configured in a wide range of sizes.
Code segment protection provides an added level ofprotection to a designated area of program memory bydisabling the NVM safety interlock whenever a write orerase address falls within a specified range. It does notoverride General Segment protection controlled by theGCP or GWRP bits. For example, if GCP and GWRPare enabled, enabling segmented code protection forthe bottom half of program memory does not undoGeneral Segment protection for the top half.
4.7 Exiting Enhanced ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as shown in Figure 4-6. The only require-ment for exit is that an interval, P16, should elapsebetween the last clock, and program signals on PGECxand PGEDx, before removing VIH.
FIGURE 4-6: EXITING ENHANCED ICSP™ MODE
Note: Chip Erasing in ICSP mode is the onlyway to reprogram code-protect bits froman ON state (‘0’) to an OFF state (‘1’).
MCLR
P16
PGEDx
PGEDx = Input
PGECx
VDD
VIH
VIH
P17
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5.0 THE PROGRAMMING EXECUTIVE
5.1 Programming Executive Communication
The programmer and Programming Executive have amaster-slave relationship, where the programmer isthe master programming device and the ProgrammingExecutive is the slave.
All communication is initiated by the programmer in theform of a command. Only one command at a time canbe sent to the Programming Executive. In turn, theProgramming Executive only sends one response tothe programmer after receiving and processing acommand. The Programming Executive command setis described in Section 5.2 “Programming ExecutiveCommands”. The response set is described inSection 5.3 “Programming Executive Responses”.
5.1.1 COMMUNICATION INTERFACE AND PROTOCOL
The Enhanced ICSP interface is a 2-wire SPI, imple-mented using the PGECx and PGEDx pins. ThePGECx pin is used as a clock input pin and the clocksource must be provided by the programmer. ThePGEDx pin is used for sending command data to, andreceiving response data from, the ProgrammingExecutive.
Data transmits to the device must change on the risingedge and hold on the falling edge. Data receives fromthe device must change on the falling edge and hold onthe rising edge.
All data transmissions are sent, MSb first, using 16-bitmode (see Figure 5-1).
FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE
FIGURE 5-2: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE
Since a 2-wire SPI is used, and data transmissions arehalf-duplex, a simple protocol is used to control thedirection of PGEDx. When the programmer completesa command transmission, it releases the PGEDx lineand allows the Programming Executive to drive this linehigh. The Programming Executive keeps the PGEDxline high to indicate that it is processing the command.
After the Programming Executive has processed thecommand, it brings PGEDx low for 15 s to indicate tothe programmer that the response is available to beclocked out. The programmer can begin to clock outthe response, 23 s after PGEDx is brought low, and itmust provide the necessary amount of clock pulses toreceive the entire response from the ProgrammingExecutive.
After the entire response is clocked out, the program-mer should terminate the clock on PGECx until it is timeto send another command to the ProgrammingExecutive. This protocol is shown in Figure 5-3.
5.1.2 SPI RATEIn Enhanced ICSP mode, the PIC24FJXXXGA2/GB2devices operate from the Internal Fast RC Oscillator(FRCDIV), which has a nominal frequency of 8 MHz.This oscillator frequency yields an effective systemclock frequency of 4 MHz. To ensure that the program-mer does not clock too fast, it is recommended that a4 MHz clock be provided by the programmer.
Note: The Programming Executive (PE) can beobtained from each device page on theMicrochip web site, www.microchip.com.
PGECx
PGEDx
1 2 3 11 13 15 161412
LSb14 13 12 11
4 5 6
MSb 123... 45
P2
P3
P1
P1BP1A
PGECx
PGEDx
1 2 3 11 13 15 161412
LSb14 13 12 11
4 5 6
MSb 123... 45
P2
P3
P1
P1BP1A
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5.1.3 TIME-OUTSThe Programming Executive uses no Watchdog Timer ortime-out for transmitting responses to the programmer. Ifthe programmer does not follow the flow control mecha-nism using PGECx, as described in Section 5.1.1“Communication Interface and Protocol”, it ispossible that the Programming Executive will behaveunexpectedly while trying to send a response to theprogrammer. Since the Programming Executive has notime-out, it is imperative that the programmer correctlyfollow the described communication protocol.
As a safety measure, the programmer should usethe command time-outs identified and provided inTable 5-1. If the command time-out expires, theprogrammer should reset the Programming Executiveand start programming the device again.
FIGURE 5-3: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
5.2 Programming Executive Commands
The Programming Executive command set is shown inTable 5-1. This table contains the opcode, mnemonic,length, time-out and description for each command.Functional details on each command are provided inSection 5.2.4 “Command Descriptions”.
5.2.1 COMMAND FORMATAll Programming Executive commands have a generalformat, consisting of a 16-bit header and any requireddata for the command (see Figure 5-4). The 16-bitheader consists of a 4-bit opcode field, which is used toidentify the command, followed by a 12-bit commandlength field.
FIGURE 5-4: COMMAND FORMAT
The command opcode must match one of those in thecommand set. Any command that is received, whichdoes not match the list in Table 5-1, will return a“NACK” response (see Section 5.3.1.1 “OpcodeField”).
The command length is represented in 16-bit wordssince the SPI operates in 16-bit mode. The Program-ming Executive uses the command length field todetermine the number of words to read from the SPIport. If the value of this field is incorrect, the commandwill not be properly received by the ProgrammingExecutive.
1 2 15 16 1 2 15 16
PGECx
PGEDx
PGECx = Input PGECx = Input (Idle)
Host TransmitsLast Command Word
PGEDx = Input PGEDx = Output
P8
1 2 15 16
MSB X X X LSB MSB X X X LSB MSB X X X LSB1 0
P20
PGECx = InputPGEDx = Output
P9
Programming ExecutiveProcesses Command Host Clocks Out Response
P21
15 12 11 0Opcode Length
Command Data First Word (if required)••
Command Data Last Word (if required)
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5.2.2 PACKED DATA FORMATWhen 24-bit instruction words are transferred acrossthe 16-bit SPI interface, they are packed to conservespace using the format shown in Figure 5-5. Thisformat minimizes traffic over the SPI and provides theProgramming Executive with data that is properlyaligned for performing Table Write operations.FIGURE 5-5: PACKED INSTRUCTION WORD FORMAT
5.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING
The Programming Executive will “NACK” allunsupported commands. Additionally, due to thememory constraints of the Programming Executive, nochecking is performed on the data contained in theprogrammer command. It is the responsibility of theprogrammer to command the Programming Executivewith valid command arguments or the programmingoperation may fail. Additional information on errorhandling is provided in Section 5.3.1.3 “QE_CodeField”.
15 8 7 0LSW1
MSB2 MSB1LSW2
LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Bytes of instruction word
Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 cannot be transmitted.
TABLE 5-1: PROGRAMMING EXECUTIVE COMMAND SET
Opcode Mnemonic Length(16-bit words) Time-out Description
0h SCHECK 1 1 ms Sanity check.1h READC 3 1 ms Read an 8-bit word from the specified Device ID register.2h READP 4 1 ms/row Read N 24-bit instruction words of code memory, starting
from the specified address.3h RESERVED N/A N/A This command is reserved; it will return a NACK.4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers.5h PROGP 99 5 ms Program one row of code memory at the specified
address, then verify.(1)
6h RESERVED 5 5 ms This command is reserved; it will return a NACK.7h RESERVED N/A N/A This command is reserved; it will return a NACK.8h RESERVED N/A N/A This command is reserved; it will return a NACK.9h RESERVED N/A N/A This command is reserved; it will return a NACK.Ah RESERVED N/A N/A This command is reserved.Bh QVER 1 1 ms Query the Programming Executive software version.Ch RESERVED N/A N/A This command is reserved; it will return a NACK.Dh PROGW 4 5 ms Program one instruction word of code memory at the
specified address and then verify.Eh QBLANK 3 30 ms/Kbyte Query if the code memory is blank.
Note 1: One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information.
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5.2.4 COMMAND DESCRIPTIONSAll commands supported by the Programming Executiveare described in Section 5.2.5 “SCHECK Command”through Section 5.2.12 “QVER Command”.5.2.5 SCHECK COMMAND
The SCHECK command instructs the ProgrammingExecutive to do nothing but generate a response. Thiscommand is used as a “Sanity Check” to verify that theProgramming Executive is operational.
Expected Response (2 Words):1000h0002h
5.2.6 READC COMMAND
The READC command instructs the Programming Exec-utive to read N or Device ID registers, starting from the24-bit address specified by Addr_MSB and Addr_LS.This command can only be used to read 8-bit or 16-bitdata.
When this command is used to read Device IDregisters, the upper byte in every data word returned bythe Programming Executive is 00h and the lower bytecontains the Device ID register value.
Expected Response (4 + 3 * (N – 1)/2 Words for N Odd):
1100h2 + NDevice ID Register 1... Device ID Register N
15 12 11 0Opcode Length
Field Description
Opcode 0hLength 1h
Note: This instruction is not required for pro-gramming; it is provided for developmentpurposes only.
15 12 11 8 7 0Opcode Length
N Addr_MSBAddr_LS
Field Description
Opcode 1hLength 3hN Number of 8-bit Device ID registers to
read (max. of 256)Addr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit
source address
Note: Reading unimplemented memory willcause the Programming Executive to reset.Ensure that only memory locations presenton a particular device are accessed.
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5.2.7 READP COMMANDThe READP command instructs the ProgrammingExecutive to read N 24-bit words of code memory,including Configuration Words, starting from the 24-bitaddress specified by Addr_MSB and Addr_LS. Thiscommand can only be used to read 24-bit data. All datareturned in response to this command uses the packeddata format described in Section 5.2.2 “Packed DataFormat”.
Expected Response (2 + 3 * N/2 Words for N Even):1200h2 + 3 * N/2Least Significant Program Memory Word 1... Least Significant Data Word N
Expected Response (4 + 3 * (N – 1)/2 Words for N Odd):1200h
4 + 3 * (N – 1)/2
Least Significant Program Memory Word 1
...
MSB of Program Memory Word N (zero-padded)
5.2.8 PROGC COMMAND
The PROGC command instructs the ProgrammingExecutive to program a single Device ID registerlocated at the specified memory address.
After the specified data word has been programmed tocode memory, the Programming Executive verifies theprogrammed data against the data in the command.
Expected Response (2 Words):1400h0002h
15 12 11 8 7 0Opcode Length
NReserved Addr_MSB
Addr_LS
Field Description
Opcode 2hLength 4hN Number of 24-bit instructions to read
(max. of 32768)Reserved 0hAddr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit
source address
Note: Reading unimplemented memory willcause the Programming Executive toreset. Ensure that only memory locationspresent on a particular device areaccessed.
15 12 11 8 7 0Opcode Length
Reserved Addr_MSBAddr_LS
Data
Field Description
Opcode 4hLength 4hReserved 0hAddr_MSB MSB of the 24-bit destination addressAddr_LS Least Significant 16 bits of the 24-bit
destination addressData 8-bit data word
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5.2.9 PROGP COMMANDThe PROGP command instructs the ProgrammingExecutive to program one row of code memory, includ-ing Configuration Words (64 instruction words), to thespecified memory address. Programming begins withthe row address specified in the command. Thedestination address should be a multiple of 80h.
The data to program to memory, located in commandwords, D_1 through D_96, must be arranged using thepacked instruction word format shown in Figure 5-5.
After all data has been programmed to code memory,the Programming Executive verifies the programmeddata against the data in the command.
Expected Response (2 Words):1500h0002h
5.2.10 PROGW COMMAND
The PROGW command instructs the ProgrammingExecutive to program one word of code memory(3 bytes) to the specific memory address.
After the word has been programmed to code memory,the Programming Executive verifies the programmeddata against the data in the command.
Expected Response (2 Words):1600h0002h
15 12 11 8 7 0Opcode Length
Reserved Addr_MSBAddr_LS
D_1D_2...
D_96
Field Description
Opcode 5hLength 63hReserved 0hAddr_MSB MSB of the 24-bit destination addressAddr_LS Least Significant 16 bits of the 24-bit
destination addressD_1 16-bit Data Word 1D_2 16-bit Data Word 2... 16-bit Data Word 3 through 95D_96 16-bit Data Word 96
Note: Refer to Table 2-2 for code memory sizeinformation.
15 12 11 8 7 0Opcode Length
Data_MSB Addr_MSBAddr_LSData_LS
Field Description
Opcode DhLength 4hReserved 0hAddr_MSB MSB of the 24-bit destination addressAddr_LS Least Significant 16 bits of the 24-bit
destination addressData_MSB MSB of 24-bit dataData_LS Least Significant 16 bits of the 24-bit
data
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5.2.11 QBLANK COMMANDThe QBLANK command queries the ProgrammingExecutive to determine if the contents of code memoryand code-protect Configuration bits (GCP and GWRP)are blank (contain all ‘1’s). The size of code memory tocheck must be specified in the command.
The Blank Check for code memory begins at 0h andadvances toward larger addresses for the specifiednumber of instruction words.
QBLANK returns a QE_Code of F0h if the specifiedcode memory and code-protect bits are blank;otherwise, QBLANK returns a QE_Code of 0Fh.
Expected Response (2 Words for Blank Device):1AF0h
0002h
Expected Response (2 Words for Non-Blank Device):1A0Fh
0002h
5.2.12 QVER COMMAND
The QVER command queries the version of theProgramming Executive software stored in testmemory. The “version.revision” information is returnedin the response’s QE_Code, using a single byte withthe following format: main version in upper nibble andrevision in the lower nibble (i.e., 23h means Version 2.3of Programming Executive software).
Expected Response (2 Words):1BMNh (where “MN” stands for Version M.N)0002h
15 12 11 0Opcode Length
PSize_MSWPSize_LSW
Field Description
Opcode AhLength 3hPSize Length of program memory to check
in 24-bit words plus one (max. of 49152)
Note: QBLANK does not check the systemoperation Configuration bits, since thesebits are not set to ‘1’ when a Chip Erase isperformed.
15 12 11 0Opcode Length
Field Description
Opcode BhLength 1h
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5.3 Programming ExecutiveResponsesThe Programming Executive sends a response to theprogrammer for each command that it receives. Theresponse indicates if the command was processedcorrectly. It includes any required response data orerror data.
The Programming Executive response set is shown inTable 5-2. This table contains the opcode, mnemonicand description for each response. The response formatis described in Section 5.3.1 “Response Format”.
TABLE 5-2: PROGRAMMING EXECUTIVE RESPONSE OPCODES
5.3.1 RESPONSE FORMATAll Programming Executive responses have a generalformat, consisting of a two-word header and anyrequired data for the command.
5.3.1.1 Opcode FieldThe opcode is a 4-bit field in the first word of theresponse. The opcode indicates how the commandwas processed (see Table 5-2). If the command wasprocessed successfully, the response opcode is PASS.If there was an error in processing the command, theresponse opcode is FAIL and the QE_Code indicatesthe reason for the failure. If the command sent tothe Programming Executive is not identified, theProgramming Executive returns a NACK response.
5.3.1.2 Last_Cmd FieldThe Last_Cmd is a 4-bit field in the first word ofthe response and indicates the command that theProgramming Executive processed. Since the Pro-gramming Executive can only process one commandat a time, this field is technically not required. However,it can be used to verify that the Programming Executivecorrectly received the command that the programmertransmitted.
Opcode Mnemonic Description
1h PASS Command is successfully processed
2h FAIL Command is unsuccessfully processed
3h NACK Command is not known
Field Description
Opcode Response opcodeLast_Cmd Programmer command that generated
the responseQE_Code Query code or error codeLength Response length in 16-bit words
(includes 2 header words)D_1 First 16-bit data word (if applicable)D_N Last 16-bit data word (if applicable)
15 12 11 8 7 0
Opcode Last_Cmd QE_Code
Length
D_1 (if applicable)
...
D_N (if applicable)
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5.3.1.3 QE_Code FieldThe QE_Code is a byte in the first word of theresponse. This byte is used to return data for querycommands and error codes for all other commands.When the Programming Executive processes one ofthe two query commands (QBLANK or QVER), thereturned opcode is always PASS and the QE_Codeholds the query response data. The format of theQE_Code for both queries is provided in Table 5-3.
TABLE 5-3: QE_Code FOR QUERIES
When the Programming Executive processes anycommand other than a query, the QE_Code representsan error code. Supported error codes are shown inTable 5-4. If a command is successfully processed, thereturned QE_Code is set to 0h, which indicates thatthere was no error in the command processing. If theverification of the programming for the PROGP or PROGCcommand fails, the QE_Code is set to 1h. For all otherProgramming Executive errors, the QE_Code is 2h.
TABLE 5-4: QE_Code FOR NON-QUERY COMMANDS
5.3.1.4 Response LengthThe response length indicates the length of theProgramming Executive’s response in 16-bit words.This field includes the 2 words of the response header.
With the exception of the response for the READPcommand, the length of each response is only 2 words.
The response to the READP command uses thepacked instruction word format, described inSection 5.2.2 “Packed Data Format”. When readingan odd number of program memory words (N odd), theresponse to the READP command is (3 * (N + 1)/2 + 2)words. When reading an even number of programmemory words (N even), the response to the READPcommand is (3 * N/2 + 2) words.
Query QE_Code
QBLANK 0Fh = Code memory is NOT blankF0h = Code memory is blank
QVER 0xMN, where Programming Executive Software Version = M.N (i.e., 32h means Software Version 3.2)
QE_Code Description
0h No error1h Verify failed2h Other error
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5.4 Programming the ProgrammingExecutive to Memory
5.4.1 OVERVIEWIf it is determined that the Programming Executive isnot present in executive memory (as described inSection 4.2 “Confirming the Presence of the Pro-gramming Executive”), it must be programmed intoexecutive memory using ICSP, as described inSection 3.0 “Device Programming – ICSP”.
Storing the Programming Executive to executivememory is similar to normal programming of codememory. Namely, the executive memory must beerased and then the Programming Executive must beprogrammed, 64 words at a time. Table 5-5 providesthis control flow.
Note: The Programming Executive must alwaysbe erased before it is programmed, asdescribed in Table 5-5.
TABLE 5-5: PROGRAMMING THE EXECUTIVECommand(Binary)
Data(Hex) Description
Step 1: Exit the Reset vector and erase the executive memory.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the NVMCON register to erase the executive memory.00000000
240420883B00
MOV #0x4042, W0MOV W0, NVMCON
Step 3: Initialize the Erase Pointers to the first page of the executive and then initiate the erase cycle.0000000000000000000000000000000000000000
2008008802A0200001000000BB0881000000000000A8E761000000000000
MOV #0x80, W0MOV W0, TBLPAGMOV #0x0, W1NOPTBLWTL W1, [W1]NOPNOPBSET NVMCON, #15NOPNOP
Step 4: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.00000000000000000001
0000
040200000000803B02883C22000000<VISI>000000
GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP
Step 5: Repeat Steps 3 and 4 to erase the second page of executive memory. The W1 Pointer should be incremented by 400h to point to the second page.
Step 6: Initialize the NVMCON register to program 64 instruction words.00000000
240010883B00
MOV #0x4001, W0MOV W0, NVMCON
Step 7: Initialize the TBLPAG register and the Write Pointer (W7).0000000000000000
2008008802A0EB0380000000
MOV #0x80, W0MOV W0, TBLPAGCLR W7NOP
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Step 8: Load W0:W5 with the next four words of packed Programming Executive code and initialize W6 for programming. Programming starts from the base of executive memory (800000h) using W6 as a Read Pointer and W7 as a Write Pointer.
000000000000000000000000
2<LSW0>02<MSB1:MSB0>12<LSW1>22<LSW2>32<MSB3:MSB2>42<LSW3>5
MOV #<LSW0>, W0MOV #<MSB1:MSB0>, W1MOV #<LSW1>, W2MOV #<LSW2>, W3MOV #<MSB3:MSB2>, W4MOV #<LSW3>, W5
Step 9: Set the Read Pointer (W6) and load the (next four write) latches.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
EB0300000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000
CLR W6NOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOP
Step 10: Repeat Steps 8 and 9, 16 times, to load the write latches for the 64 instructions. Step 11: Initiate the programming cycle.
000000000000
A8E761000000000000
BSET NVMCON, #15NOPNOP
Step 12: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000
040200000000803B02883C22000000<VISI>000000
GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP
Step 13: Reset the device’s internal PC. 00000000
040200000000
GOTO 0x200NOP
Step 14: Repeat Steps 8 through 13 until all 16 rows of executive memory have been programmed.
TABLE 5-5: PROGRAMMING THE EXECUTIVE (CONTINUED)Command(Binary)
Data(Hex) Description
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5.4.2 PROGRAMMING VERIFICATION After the Programming Executive has beenprogrammed to executive memory using ICSP, it mustbe verified. Verification is performed by reading out thecontents of executive memory and comparing it withthe image of the Programming Executive stored in theprogrammer.Reading the contents of executive memory can beperformed using the same technique described inSection 3.8 “Reading Code Memory”. A procedurefor reading executive memory is provided in Table 5-6.Note that in Step 2, the TBLPAG register is set to 80h,such that executive memory may be read. The lasteight words of executive memory should be verifiedwith stored values of the diagnostic and calibrationwords to ensure accuracy.
TABLE 5-6: READING EXECUTIVE MEMORYCommand
(Binary)Data(Hex) Description
Step 1: Exit the Reset vector.000000000000
000000040200000000
NOPGOTO 0x200NOP
Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.000000000000
2008008802A0EB0300
MOV #0x80, W0 MOV W0, TBLPAGCLR W6
Step 3: Initialize the Write Pointer (W7) to point to the VISI register. 00000000
207847000000
MOV #VISI, W7NOP
Step 4: Read and clock out the contents of the next two locations of executive memory, through the VISI register, using the REGOUT command.
000000000000000100000000000000000000000000000001000000000000000000010000
BA0B96000000000000<VISI>000000BADBB6000000000000BAD3D6000000000000<VISI>000000BA0BB6000000000000<VISI>000000
TBLRDL [W6], [W7] NOPNOPClock out contents of the VISI registerNOPTBLRDH.B [W6++], [W7++]NOPNOPTBLRDH.B [++W6], [W7--]NOPNOPClock out contents of the VISI registerNOPTBLRDL [W6++], [W7]NOPNOPClock out contents of the VISI registerNOP
Step 5: Reset the device’s internal PC.00000000
040200000000
GOTO 0x200 NOP
Step 6: Repeat Steps 4 and 5 until all 1024 instruction words of executive memory are read.
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6.0 DEVICE DETAILS
6.1 Device IDThe Device ID region of memory can be used to deter-mine mask, variant and manufacturing informationabout the chip. The Device ID region is 2 x 16 bits andit can be read using the READC command. This regionof memory is read-only and can also be read whencode protection is enabled.
Table 6-1 shows the Device ID for each device,Table 6-2 shows the Device ID registers and Table 6-3describes the bit field of each register.
TABLE 6-2: PIC24FJXXXGA2/GB2 DEVICE ID REGISTERS
TABLE 6-3: DEVICE ID BIT DESCRIPTIONS
TABLE 6-1: DEVICE IDs Device DEVID
PIC24FJ128GB204 4C5BPIC24FJ128GB202 4C5APIC24FJ64GB204 4C59PIC24FJ64GB202 4C58PIC24FJ128GA204 4C53PIC24FJ128GA202 4C52PIC24FJ64GA204 4C51PIC24FJ64GA202 4C50
Address NameBit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FF0000h DEVID FAMID<7:0> DEV<7:0>FF0002h DEVREV — REV<3:0>
Bit Field Register Description
FAMID<7:0> DEVID Encodes the ID of the device familyDEV<7:0> DEVID Encodes the individual ID of the deviceREV<3:0> DEVREV Encodes the sequential (numerical) revision identifier of the device
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6.2 Checksum ComputationChecksums for the PIC24FJXXXGA2/GB2 devices are16 bits in size. The checksum is calculated by summingthe following:• Contents of code memory locations• Contents of Configuration registers
Table 6-4 describes how to calculate the checksum foreach device. All memory locations are summed, onebyte at a time, using only their native data size. Morespecifically, Configuration registers are summed byadding the lower two bytes of these locations (theupper byte is ignored), while code memory is summedby adding all three bytes of code memory.
TABLE 6-4: CHECKSUM COMPUTATION
Device Read Code Protection Checksum Computation
ErasedChecksum
Value
Checksum with 0xAAAAAA at 0x0
and Last Code Address
PIC24FJ128GA204 Disabled CFGB + SUM(0:157F7) F73C F53EEnabled 0 0000h 0000h
PIC24FJ128GA202 Disabled CFGB + SUM(0:157F7) F73C F53EEnabled 0 0000h 0000h
PIC24FJ128GB204 Disabled CFGB + SUM(0:157F7) F744h F546hEnabled 0 0000h 0000h
PIC24FJ128GB202 Disabled CFGB + SUM(0:157F7) F744h F546hEnabled 0 0000h 0000h
PIC24FJ64GA204 Disabled CFGB + SUM(0:0ABF7) F93C F73EEnabled 0 0000h 0000h
PIC24FJ64GA202 Disabled CFGB + SUM(0:0ABF7) F93C F73EEnabled 043 0000h 0000h
PIC24FJ64GB204 Disabled CFGB + SUM(0:0ABF7) F944h F746hEnabled 0 0000h 0000h
PIC24FJ64GB202 Disabled CFGB + SUM(0:0ABF7) F944h F746hEnabled 0 0000h 0000h
Legend: Item DescriptionSUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)CFGB = Configuration Block (masked) byte sum of ((CW1 & 0x7FFF) + (CW2 & 0xFFFF) +
(CW3 & 0xFFFF) + (CW4 & 0xFFFF))Note: CW1 address is the last location of implemented program memory; CW2 is (last location – 2); CW3 is (last
location – 4); CW4 is (last location – 6).
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7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating ConditionsOperating Temperature: 0C to +70C. Programming at +25C is recommended.
Param No. Symbol Characteristic Min Max Units Conditions
D111 VDD Supply Voltage During Programming 2.20 3.60 V Normal programming(1)
D112 IPP Programming Current on MCLR — 5 AD113 IDDP Supply Current During Programming — 16 mAD031 VIL Input Low Voltage VSS 0.2 VDD VD041 VIH Input High Voltage 0.8 VDD VDD VD080 VOL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6VD090 VOH Output High Voltage 3.0 — V IOH = -3.0 mA @ 3.6VD012 CIO Capacitive Loading on I/O Pin (PGEDx) — 50 pF To meet AC specificationsD013 CF Filter Capacitor Value on VCAP 4.7 10 F Required for controller coreP1 TPGEC Serial Clock (PGECx) Period 100 — ns ICSP™ mode
250 — ns Enhanced ICSP modeP1A TPGECL Serial Clock (PGECx) Low Time 40 — ns ICSP mode
100 — ns Enhanced ICSP modeP1B TPGECH Serial Clock (PGECx) High Time 40 — ns ICSP mode
100 — ns Enhanced ICSP modeP2 TSET1 Input Data Setup Time to Serial Clock 15 — nsP3 THLD1 Input Data Hold Time from PGECx 15 — nsP4 TDLY1 Delay Between 4-Bit Command and
Command Operand40 — ns
P4A TDLY1A Delay Between 4-Bit Command Operand and Next 4-Bit Command
40 — ns
P5 TDLY2 Delay Between Last PGECx of Command Byte to First PGECx of Read of Data Word
20 — ns
P6 TSET2 VDD Setup Time to MCLR 100 — ns
P7 THLD2 Input Data Hold Time from MCLR 25 — msP8 TDLY3 Delay Between Last PGECx of Command
Byte to PGEDx by Programming Executive12 — s
P9 TDLY4 Programming Executive Command Processing Time
40 — s
P10 TDLY6 PGECx Low Time After Programming 400 — nsP11 TDLY7 Chip Erase Time 20 40 msP12 TDLY8 Page Erase Time 20 40 msP13 TDLY9 Row Programming Time 1.5 — ms
P14 TR MCLR Rise Time to Enter ICSP mode — 1.0 sP15 TVALID Data Out Valid from PGECx 10 — ns
P16 TDLY10 Delay Between Last PGECx and MCLR 0 — s
P17 THLD3 MCLR to VDD 100 — ns
P18 TKEY1 Delay from First MCLR to First PGECx for Key Sequence on PGEDx
10 — ms
Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. When the internal voltage regulator is enabled (i.e., ENVREG = VDD), the nominal VCAP is 1.8V.
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P19 TKEY2 Delay from Last PGECx for Key Sequence on PGEDx to Second MCLR
1 — ms
P20 TDLY11 Delay Between PGEDx by Programming Executive to PGEDx Driven by Host
23 — µs
P21 TDLY12 Delay Between Programming Executive Command Response Words
8 — ns
7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)
Standard Operating ConditionsOperating Temperature: 0C to +70C. Programming at +25C is recommended.
Param No. Symbol Characteristic Min Max Units Conditions
Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. When the internal voltage regulator is enabled (i.e., ENVREG = VDD), the nominal VCAP is 1.8V.
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APPENDIX A: REVISION HISTORYRevision A (March 2012)
Initial revision of this document, released forPIC24FJ128GB204 family devices.
Revision B (August 2012)
Adds the PIC24FJ128GA204 device family to thespecification:
Changes opcode in Table 3-4, Table 3-5, Table 3-8,Table 5-5 and Section 2.0 “Programming Overview ofPIC24FJXXXGA2/GB2 Devices”.
Revision C (January 2013)
Redistributes pin diagrams for clarity and addsFigure 2-6.
Updates Table 2-2 to include new devices.
Updates Table 6-1 to update all Device IDs.
Corrects notes on specification, P18 (TKEY1), andremoves alternate value; key specification value of10 ms is unchanged.
Updates the history description for Revision B (previouslydid not mention the addition of the PIC24FJ128GA204device family).
Revision D (February 2014)
This revision incorporates the following updates:
• Figures:- Updated Figure 2-3, Figure 2-4, Figure 2-5,
Figure 2-6• Tables:
- Updated Table 3-7, Table 4-2, Table 5-5
Revision E (May 2014)
This revision incorporates the following updates:
• Tables:- Updates Table 3-6, Table 3-7, Table 4-2,
Table 6-4
Revision F (May 2015)
This revision incorporates the following updates:
• Tables:- Updates Table 3-6, Table 3-7, Table 4-2 and
Table 6-4
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NOTES:DS30000510F-page 52 2012-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.
2012-2015 Microchip Technology Inc.
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV
== ISO/TS 16949 ==
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2012-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-412-5
Microchip received ISO/TS-16949:2009 certification for its worldwide
DS30000510F-page 53
headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS30000510F-page 54 2012-2015 Microchip Technology Inc.
AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.comAtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455Austin, TXTel: 512-257-3370 BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075ClevelandIndependence, OH Tel: 216-447-0464 Fax: 216-447-0643DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924DetroitNovi, MI Tel: 248-848-4000Houston, TX Tel: 281-894-5983IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453Los AngelesMission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608New York, NY Tel: 631-435-6000San Jose, CA Tel: 408-735-9110Canada - TorontoTel: 905-673-0699 Fax: 905-673-6509
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01/27/15