PIC24FJXXXDA1/DA2/GB2/GA3

PIC24FJXXXDA1/DA2/GB2/GA3 Families Flash Programming Specification

1.0 DEVICE OVERVIEWThis document defines the programming specificationfor the PIC24FJXXXDA1/DA2/GB2/GA3 families of16-bit microcontrollers (MCUs). This programmingspecification is required only for those developing pro-gramming support for the PIC24FJXXXDA1/DA2/GB2/GA3 families. Customers using only one of thesedevices should use development tools that alreadyprovide support for device programming.

This specification includes programming specificationsfor the following devices:

Topics covered include:1.0 Device Overview ................................................. 12.0 Programming Overview of the PIC24FJXXXDA1/

DA2/GB2/GA3 Families ..................................... 13.0 Device Programming – ICSP ............................ 144.0 Device Programming – Enhanced ICSP ........... 295.0 The Programming Executive ............................. 426.0 Device Details ................................................... 547.0 AC/DC Characteristics and Timing

Requirements .................................................. 56

2.0 PROGRAMMING OVERVIEW OF THE PIC24FJXXXDA1/DA2/GB2/GA3 FAMILIES

There are two methods of programming thePIC24FJXXXDA1/DA2/GB2/GA3 families of devicesdiscussed in this programming specification. They are:

• In-Circuit Serial Programming™ (ICSP™)• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

The ICSP programming method is the most directmethod to program the device; however, it is also theslower of the two methods. It provides native, low-levelprogramming capability to erase, program and verifythe chip.

• PIC24FJ128DA106 • PIC24FJ256DA106• PIC24FJ128DA110 • PIC24FJ256DA110• PIC24FJ128DA206 • PIC24FJ256DA206• PIC24FJ128DA210 • PIC24FJ256DA210• PIC24FJ128GB206 • PIC24FJ256GB206• PIC24FJ128GB210 • PIC24FJ256GB210• PIC24FJ64GA310 • PIC24FJ128GA310 • PIC24FJ64GA308 • PIC24FJ128GA308 • PIC24FJ64GA306 • PIC24FJ128GA306

Note 1: The address of Special Function Regis-ter, ‘TBLPAG’, has changed from 0x32 to0x54 in the PIC24FJXXXDA1/DA2/GB2/GA3 family.

2: In the cases where legacy programmingspecification code from other devicefamilies is used as a basis to implementthe PIC24FJXXXDA1/DA2/GB2/GA3 fam-ily programming specification, special caremust be taken to ensure all references to‘TBLPAG’ in any existing code are updatedwith the correct opcode hex data for themnemonic and operands (as shownbelow).

PIC24FJXXXDA1/DA2/GB2/GA3 Family

Non PIC24FJXXXDA1/DA2/GB2/GA3 Family

Command(Binary)

Data(Hex) Description

0000 8802A0 MOV W0, TBLPAG

Command(Binary)

Data(Hex) Description

0000 880190 MOV W0, TBLPAG

2010 Microchip Technology Inc. DS39970B-page 1

PIC24FJXXXDA1/DA2/GB2/GA3

The Enhanced In-Circuit Serial Programming(Enhanced ICSP) protocol uses a faster method thattakes advantage of the programming executive, asillustrated in Figure 2-1. The programming executiveprovides all the necessary functionality to erase, pro-gram and verify the chip through a small command set.The command set allows the programmer to programthe PIC24FJXXXDA1/DA2/GB2/GA3 MCUs withouthaving to deal with the low-level programmingprotocols of the chip.

FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™

This specification is divided into major sections thatdescribe the programming methods independently.Section 3.0 “Device Programming – ICSP” describesthe In-Circuit Serial Programming method. Section 4.0“Device Programming – Enhanced ICSP” describesthe Run-Time Self-Programming (RTSP) method.

2.1 Power RequirementsAll PIC24FJXXXDA1/DA2/GB2/GA3 devices powertheir core digital logic at a nominal 1.8V. To simplify sys-tem design, all devices in the PIC24FJXXXDA1/DA2/GB2/GA3 families incorporate an on-chip regulator thatallows the device to run its core logic from VDD. For thePIC24F128GA310 family, the regulator is alwaysenabled, so there is no ENVREG pin on the device.

The regulator provides power to the core from the otherVDD pins. A low-ESR capacitor (such as ceramic or tan-talum) must be connected to the VCAP pin (see Table 2-1and Figure 2-2). This helps to maintain the stability of theregulator. The specifications for core voltage and capac-itance are listed in Section 7.0 “AC/DC Characteristicsand Timing Requirements”.

2.2 Program Memory Write/Erase Requirements

The Flash program memory on PIC24FJXXXDA1/DA2/GB2/GA3 devices has a specific write/erase require-ment that must be adhered to for proper deviceoperation. Any given word in memory must not bewritten more than twice before erasing the page where itis located. Thus, the easiest way to conform to this ruleis to write all of the data in a programming block withinone write cycle. The programming methods specified inthis specification comply with this requirement.

2.3 Pin DiagramsFigure 2-4 through Figure 2-10 provide the pin diagramsfor the PIC24FJXXXDA1/DA2/GB2/GA3 families. Thepins that are required for programming are listed inTable 2-1 and are indicated in bold text in the figures.Refer to the appropriate device data sheet for completepin descriptions.

2.3.1 PGECx AND PGEDx PIN PAIRSAll of the devices in the PIC24FJXXXDA1/DA2/GB2/GA3 families have three separate pairs of program-ming pins, labelled as PGEC1/PGED1, PGEC2/PGED2and PGEC3/PGED3. Any one of these pin pairs may beused for device programming by either ICSP orEnhanced ICSP. Unlike voltage supply and groundpins, it is not necessary to connect all three pin pairs toprogram the device. However, the programmingmethod must use both pins of the same pair.

FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR

FIGURE 2-3: CONNECTIONS FOR THE VBAT PIN

PIC24FJXXXDA1/DA2/GB2/GA3

Programmer ProgrammingExecutive

On-Chip Memory

Note: Writing to a location multiple times withouterasing is not recommended.

VDDENVREG

VCAP

VSS

PIC24FJXXXDA1/DA2/GB2

CEFC

3.3VRegulator Enabled (ENVREG tied to VDD):

(10 F typ)

VDDVBAT

VCAP

VSS

PIC24FJXXXGA3

CEFC

3.3V

Regulator Enabled (VBAT tied to VDD or a Battery):

(10 F typ)

DS39970B-page 2 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)

FIGURE 2-4: PIN DIAGRAM (64-PIN TQFP)

Pin NameDuring Programming

Pin Name Pin Type Pin Description

MCLR MCLR P Programming EnableENVREG(2) ENVREG(2) I Enable for On-Chip Voltage Regulator

VDD and AVDD(1) VDD P Power SupplyVSS and AVSS(1) VSS P Ground

VCAP VCAP P On-Chip Voltage Regulator Output to the CorePGECx PGECx I Programming Pin Pairs 1, 2 and 3: Serial ClockPGEDx PGEDX I/O Programming Pin Pairs 1, 2 and 3: Serial Data

Legend: I = Input, O = Output, P = PowerNote 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground

(AVSS).2: There is no ENVREG pin in the GA310 family. The regulator is always enabled and the ENVREG pin is

replaced by the VBAT pin. It is recommended to connect the VBAT pin to the battery or VDD during programming.

2345678910111213141516

4847

22

44

24 25 26 27 28 29 30 31 32

PIC24FJXXXDAX06

1

4645

23

4342414039

RD

6R

D5

RD

4R

D3

RD

2R

D1

RE

4R

E3

RE

2R

E1

RF0

VCA

P

RC13RD0

RD9RD8

RC15RC12VDDRG2

RF6RF2RF3

RG3

AVD

D

RB

8R

B9

RB

10R

B11

V DD

PGEC

2/A

N6/

RP6

/CN

24/R

B6

PGED

2/A

N7/

RP7

/RC

V/C

N25

/RB

7

RF5

RF4

RE5RE6RE7RG6

VDDPGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5

PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4RB3RB2

RG7RG8

PGEC1/AN1/RP1/VREF-/CN3/RB1PGED1/AN0/VREF+/RP0/

RG9MCLR

RB

12R

B13

RB

14R

B15

RE

0R

F1

RD

7

VSS

VSS

VSS

ENVR

EG

63 62 61 5960 58 57 56 5455 53 52 51 4950

3837

34

3635

33

17 19 20 2118

AVSS

64

RC14

CN2/RB0

RD10RD11

2010 Microchip Technology Inc. DS39970B-page 3

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-5: PIN DIAGRAM (64-PIN)

2345678910111213141516

4847

22

44

24 25 26 27 28 29 30 31 32

PIC24FJXXXGA306

1

4645

23

4342414039

RD

6R

D5

RD

4R

D3

RD

2R

D1

RE

4R

E3

RE

2R

E1

RF0

VCA

P

RC13RD0

RD10RD9RD8

RD11

RC15RC12VDDRG2

RF6RF2RF3

RG3

RC14

AVD

D

RB8

RB9

RB

10R

B11

V DD

PGEC

2/A

N6/

RP6

/LC

DB

IAS3

/CN

24/R

B6

PGED

2/A

N7/

RP7

/CN

25/R

B7

RF5

RF4

RE5RE6RE7RG6

VDDPGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4

RB3RB2

RG7RG8

PGEC1/CVREF-/AN1/RP1/SEG6//CN3/RB1PGED1/CVREF+/AN0/RP0/SEG7/PMA6/CN2/RB0

RG9MCLR

RB

12R

B13

RB

14R

B15

RE

0R

F1

RD

7

VSS

VSS

VSS

VBA

T

63 62 61 5960 58 57 56 5455 53 52 51 4950

3837

34

3635

33

17 19 20 2118

AVSS

64

DS39970B-page 4 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-6: PIN DIAGRAM (64-PIN TQFP)

2345678910111213141516

4847

22

44

24 25 26 27 28 29 30 31 32

PIC24FJXXXGB206

1

4645

23

4342414039

RD

6R

D5

RD

4R

D3

RD

2R

D1

RE

4R

E3

RE

2R

E1

RF0

VCA

P

RC13RD0

RD9RD8

RC15RC12VDDD+/RG2

VUSBVBUSRF3

D-/RG3

AVD

D

RB

8R

B9

RB

10R

B11

V DD

PGEC

2/A

N6/

RP6

/CN

24/R

B6

PGED

2/A

N7/

RP7

/RC

V/C

N25

/RB

7

RF5

RF4

RE5RE6RE7RG6

VDDPGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5

PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4RB3RB2

RG7RG8

PGEC1/AN1/RP1/VREF-/CN3/RB1PGED1/AN0/RP0/VREF+/

RG9MCLR

RB

12R

B13

RB

14R

B15

RE

0R

F1

RD

7

VSS

VSS

VSS

ENVR

EG

63 62 61 5960 58 57 56 5455 53 52 51 4950

3837

34

3635

33

17 19 20 2118

AVSS

64

RC14

CN2/RB0

RD10RD11

2010 Microchip Technology Inc. DS39970B-page 5

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-7: PIN DIAGRAM (80-PIN TQFP)

80 79 78

20

2345678910111213141516

6059

26

56

403928 29 30 31 32 33 34 35 36 37 38

PIC24FJXXXGA308

171819

1

7677

5857

27

5554535251

RD

5R

D4

RD

13R

D12

RD

3R

D2

RD

1

RE

2R

E1

RE

0R

G0

RE

4R

E3

RF0

V CA

P

RC13RD0

RD10RD9RD8

RD11

RA15RA14

RC15RC12VDDRG2

RF6RF7RP15

RG3

RF2RF3

RC14

RA1

0R

A9

AVD

D

RB

8R

B9

RB1

0R

B11

V DD

RD

14R

D15

PGEC

2/A

N6/

RP6

/LC

DB

IAS3

/CN

24/R

B6

PGED

2/A

N7/

RP7

/CN

25/R

B7

RF5

RF4

RE5RE6RE7RC1RC3RG6

VDDRE8RE9

RB3RB2

RG7RG8

PGEC1/CVREF-/AN1/RP1/SEG6PGED1/CVREF+/AN0/RP0/SEG7

RG9MCLR

RB1

2R

B13

RB1

4R

B15

RG

1R

F1

RD

7R

D6

VSS

VSS

VSS

VBA

T

75 74 73 7172 70 69 68 6667 65 64 63 6162

5049

46

4847

4544434241

21 23 24 2522

AVSS

PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4

DS39970B-page 6 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-8: PIN DIAGRAM (100-PIN TQFP)

9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78

20

2345678910111213141516

65646362616059

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

PIC24XJXXXDAX10

171819

2122

95

1

7677

72717069686766

757473

5857

2423

25

9698 979927 46 47 48 49 50

5554535251

100

RD

5R

D4

RD

13R

D12

RD

3R

D2

RD

1

RA

7R

A6

RE

2R

G13

RG

12R

G14

RE

1R

E0

RG

0

RE

4R

E3

RF0 VC

AP

RC13RD0

RD9RD8RA15RA14

RC15RC12VDD

RG2

RF6RF7RF8

RG3

RF2RF3

VSS

RA

10R

A9

AVD

DAV

SSR

B8

RB

9R

B10

RB1

1

V DD

RF1

2R

F13

VSS

VDD

RD

15R

D14

PGEC

2/A

N6/

RP6

/CN

24/R

B6

PGED

2/A

N7/

RP7

/RC

V/G

PWR

/CN

25/R

B7

RF5

RF4

RE5RE6RE7RC1RC2RC3RC4RG6

VDDRA0RE8RE9

RB3RB2

RG7RG8

PGEC1/AN1/RP1/CN3/RB1PGED1/AN0/RP0CN2/RB0

RG15VDD

RG9MCLR

RB

12R

B13

RB

14R

B15

RG

1R

F1

RD

7R

D6

RA5

RA3RA2

VSSVS

S

VSS

ENVR

EG

RA4R

A1

RC14

RD10RD11

PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5PGED3/AN4/C1INB/USBOEN//RP28/GD4/CN6/RB4

2010 Microchip Technology Inc. DS39970B-page 7

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-9: PIN DIAGRAM (100-PIN TQFP)

9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78

20

2345678910111213141516

65646362616059

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

PIC24FJXXXGA310

171819

2122

95

1

7677

72717069686766

757473

5857

2423

25

9698 979927 46 47 48 49 50

5554535251

100

RD

5R

D4

RD

13R

D12

RD

3R

D2

RD

1

RA

7R

A6

RE

2R

G13

RG

12R

G14

RE

1R

E0

RG

0

RE

4R

E3

RF0

VCA

P

RC13RD0

RD10RD9RD8

RD11

RA15RA14

RC15RC12VDD

RG2

RF6RF7RF8

RG3

RF2RF3

VSSRC14

RA

10R

A9

AVD

DAV

SS

RB

8R

B9

RB

10R

B11

VDD

RF1

2R

F13

VS

SV

DD

RD

15R

D14

PGEC

2/A

N6/

RP6

/LC

DB

IAS3

/CN

24/R

B6

PGED

2/A

N7/

RP7

/CN

25/R

B7

RF5

RF4

RE5RE6RE7RC1RC2RC3RC4RG6

VDDRA0RE8RE9

PGC3/AN5/C1INA/RP18/SEG2/CN7/RB5

RB3RB2

RG7RG8

PGEC1/CVREF-/AN1/RB1/SEG6PGED1/CVREF+/AN0/RB0/SEG7

RG15VDD

RG9MCLR

RB

12R

B13

RB

14R

B15

RG

1R

F1

RD

7R

D6

RA5

RA3RA2

VSSVS

S

VSS

VBA

T

RA4R

A1

PGD3/AN4/C1INB/RP28/SEG3/CN6/RB4

DS39970B-page 8 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-10: PIN DIAGRAM (100-PIN TQFP)

9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78

20

2345678910111213141516

65646362616059

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

PIC24XJXXXGB210

171819

2122

95

1

7677

72717069686766

757473

5857

2423

25

9698 979927 46 47 48 49 50

5554535251

100

RD

5R

D4

RD

13R

D12

RD

3R

D2

RD

1

RA7

RA6

RE2

RG

13R

G12

RG

14R

E1R

E0

RG

0

RE4

RE3

RF0 VC

AP

RC13RD0

RD9RD8RA15RA14

RC15RC12VDD

D+/RG2

VUSBVBUSRF8

D-/RG3

RF2RF3

VSS

RA

10R

A9

AVD

DAV

SSR

B8

RB

9R

B10

RB

11

V DD

RF1

2R

F13

VSS

VDD

RD

15R

D14

PGEC

2/A

N6/

RP6

/CN

24/R

B6

PGED

2/A

N7/

RP7

/RC

V/C

N25

/RB

7

RF5

RF4

RE5RE6RE7RC1RC2RC3RC4RG6

VDDRA0RE8RE9

RB3RB2

RG7RG8

PGEC1/CVREF-/AVREF-/AN1/RP1/CN3/RB1PGED1/CVREF-/AVREF-/AN0/RP0/CN2/RB0

RG15VDD

RG9MCLR

RB

12R

B13

RB

14R

B15

RG

1R

F1

RD

7R

D6

RA5

RA3RA2

VSSVS

S

VSS

ENVR

EG

RA4R

A1

RC14

RD10RD11

PGEC3/AN5/RP18/VBUSON/ C1INA/CN7/RB5PGED3/AN4/RP28/USBOEN/ C1INB/CN6/RB4

2010 Microchip Technology Inc. DS39970B-page 9

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-11: PIC24FJXXXDAX10 121-PIN BGA PINOUT DIAGRAM

FIGURE 2-12: PIC24FJXXXGBX10 121-PIN BGA PINOUT DIAGRAM

RE4 RE3 RG13 RE0 RG0 RF1 ENVREG N/C RD12 RD2 RD1

N/C RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14

RE6 VDD RG12 RG14 RA6 N/C RD7 RD4 VDD RC13 RD11

RC1 RE7 RE5 VSS VSS N/C RD6 RD13 RD0 N/C RD10

RC4 RC3 RG6 RC2 VDD RG1 N/C RA15 RD8 RD9 RA14

MCLR RG8 RG9 RG7 VSS N/C N/C VDD RC12 VSS RC15

RE8 RE9 RA0 N/C VDD VSS VSS N/C RA5 RA3 RA4

PGEC3/ PGED3/ VSS VDD N/C VDD N/C RF7 VUSB D+/RG2 RA2

RB3 RB2

PGED2/

AVDD RB11 RA1 RB12 N/C N/C RF8 D-/RG3

PGEC1/ PGED1/ RA10 RB8 N/C RF12 RB14 VDD RD15 RF3 RF2

PGEC2/ RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5

GD4/RB4

RB1 RB0

RB6

RB7GPWR/

A

B

C

D

E

F

G

H

J

K

1 3 5 10 112 4 6 987

L

RB5

RE4 RE3 RG13 RE0 RG0 RF1 ENVREG N/C RD12 RD2 GD1

N/C RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14

RE6 VDD RG12 RG14 RA6 N/C RD7 RD4 VDD RC13 RD11

RC1 RE7 RE5 VSS VSS N/C RD6 RD13 RD0 N/C RD10

RC4 RC3 RG6 RC2 VDD RG1 N/C RA15 RD8 RD10 RA14

MCLR RG8 RG9 RG7 VSS N/C N/C VDD RC12 VSS RC15

RE8 RE9 RA0 N/C VDD VSS VSS N/C RA5 RA3 RA4

PGEC3/ PGED3/ VSS VDD N/C VDD N/C RF7 VUSB D+/RG2 RA2

RB3 RB2 PGED2/ AVDD RB11 RA1 RB12 N/C N/C RF8 D-/RG3

PGEC1/ PGED1/ RA10 RB8 N/C RF12 RB14 VDD RD15 RF3 RF2

PGEC2/ RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5

RB5 RB4

RB1 RB0

RB6

RB7

A

B

C

D

E

F

G

H

J

K

1 3 5 10 112 4 6 987

L

DS39970B-page 10 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 2-13: PIC24FJXXXGA310 121-PIN BGA PINOUT DIAGRAM

1 3 5 7 8 9 10 11

ARE4 RE3 RE0 RG0 RF1 VBAT N/C RD12 RD1

BN/C RE2 RE1 RA7 RF0 VCAP/ RD5 RD3 VSS RC14

CRE6 VDD RG14 N/C RD7 RD4 VSS RC13 RD11

DRE7 RE5 VSS N/C N/C RD6 RD13 RD0 N/C RD10

ERC4 RG6 N/C RG1 N/C RA15 RD8 RA14

FMCLR RG8 RG9 RG7 VSS N/C N/C VDD OSCI/ VSS OSCO/

GRE8 RE9 RA0 N/C VDD VSS VSS N/C RA5 RA3 RA4

HVSS VSS N/C VDD N/C RF6 RG2 RA2

JAVDD RB11 RA1 RB12 N/C N/C RF8 RG3

KRA10 N/C RF12 RB14 VDD

LRA9 AVSS RB10 RB13 RB15 RF4 RF5

2 4 6

RF7

RG13 RD2

RG15

RG12 RA6

RC1

RC3 RC2 RD9

RC12 RC15

RB4/

RB3 RB2

RB8 RD15 RF3 RF2

RB9 RF13 RD14

RB5/

RB1/ RB0/

RB6/

RB7/

VDDCORE

PGED1PGEC1

PGEC2

PGED2

PGEC3 PGED3

2010 Microchip Technology Inc. DS39970B-page 11

PIC24FJXXXDA1/DA2/GB2/GA3

2.4 Memory MapThe program memory map extends from 000000h toFFFFFEh. Code storage is located at the base of thememory map and supports up to 87K instruction words(about 256 Kbytes). Table 2-2 provides the programmemory size, and number of erase and program blockspresent in each device variant. Each erase block, orpage, contains 512 instructions, and each programblock, or row, contains 64 instructions.

Locations, 800000h through 8007FEh, are reserved forexecutive code memory. This region stores theprogramming executive and the debugging executive.The programming executive is used for deviceprogramming and the debugging executive is used forin-circuit debugging. This region of memory cannot beused to store user code.

The last four implemented program memory locationsare reserved for the Flash Configuration Words. Thereserved addresses are provided in Table 2-2.

Locations, FF0000h and FF0002h, are reserved for theDevice ID registers. These bits can be used by theprogrammer to identify what device type is beingprogrammed. They are described in Section 6.1“Device ID”. The Device ID registers read outnormally, even after code protection is applied.

Figure 2-14 displays the memory map for thePIC24FJXXXDA1/DA2/GB2/GA3 family variants.

TABLE 2-2: CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJXXXDA1/DA2/GB2/GA3 DEVICES

DeviceUser MemoryAddress Limit

(Instruction Words)

Write Blocks

Erase Blocks

Configuration Word Addresses

1 2 3 4

PIC24FJ64GA3XX 00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh 00ABF8h

PIC24FJ128DA1XXPIC24FJ128DA2XX 0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAh 0157F8hPIC24FJ128GB2XXPIC24FJ128GA3XXPIC24FJ256DA1XXPIC24FJ256DA2XX 02ABFEh (87K) 1368 171 02ABFEh 02ABFCh 02ABFAh 02ABF8hPIC24FJ256GB2XX

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FIGURE 2-14: PROGRAM MEMORY MAP

Use

r Mem

ory

Spac

e

000000h

Flash Configuration Words

Code Memory(1)

0XXX00h(1)0XXXFEh(1)

Con

figur

atio

n M

emor

ySp

ace

800000h

Device IDFEFFFEhFF0000h

FFFFFEh

Reserved

Reserved

8007FEh

800880h

Executive Code Memory

7FFFFEh

FF0002hFF0004hReserved

(2 x 16-bit)

Note 1: The size and address boundaries for user Flash code memory are device dependent. See Table 2-2 for details.

User Flash

(1024 x 24-bit)

Diagnostic and Calibration Words

(8 x 24-bit)

0XXXF8h(1)0XXXF7h(1)

Reserved Memory

800800h

8008FEh

80088Eh

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PIC24FJXXXDA1/DA2/GB2/GA3

3.0 DEVICE PROGRAMMING – ICSPICSP mode is a special programming protocol thatallows you to read and write to the memory ofPIC24FJXXXDA1/DA2/GB2/GA3 devices. The ICSPmode is the most direct method used to program thedevice; however, Enhanced ICSP is faster. ICSP modealso has the ability to read the contents of executivememory to determine if the programming executive ispresent. This capability is accomplished by applyingcontrol codes and instructions, serially to the device,using pins, PGECx and PGEDx.

In ICSP mode, the system clock is taken from thePGECx pin, regardless of the device’s oscillator Con-figuration bits. All instructions are shifted serially into aninternal buffer, then loaded into the Instruction Register(IR) and executed. No program fetching occurs frominternal memory. Instructions are fed in 24 bits at atime. PGEDx is used to shift data in and PGECx is usedas both the serial shift clock and the CPU executionclock.

3.1 Overview of the Programming Process

See Figure 3-1 for high-level overview of theprogramming process. After entering ICSP mode, thefirst action is to Chip Erase the device. Next, the codememory is programmed, followed by the deviceConfiguration registers. Code memory (including theConfiguration registers) is then verified to ensure thatprogramming was successful. Then, the code-protectConfiguration bits are programmed, if required.

3.2 ICSP OperationUpon entry into ICSP mode, the CPU is Idle. Executionof the CPU is governed by an internal state machine. A4-bit control code is clocked in using PGECx andPGEDx and this control code is used to command theCPU (see Table 3-1).

The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device via the VISI register.

TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE

FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW

Note: During ICSP operation, the operatingfrequency of PGECx must not exceed10 MHz.

4-Bit Control Code Mnemonic Description

0000 SIX Shift in 24-bit instruction and execute.

0001 REGOUT Shift out the VISI (0784h) register.

0010-1111 N/A Reserved.

Start

Perform ChipErase

Program Memory

Verify Program

End

Enter ICSP™

Program Configuration Bits

Verify Configuration Bits

Exit ICSP

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3.2.1 SIX SERIAL INSTRUCTION

EXECUTIONThe SIX control code allows execution of PIC24F familyassembly instructions. When the SIX code is received,the CPU is suspended for 24 clock cycles, as the instruc-tion is then clocked into the internal buffer. Once theinstruction is shifted in, the state machine allows it to beexecuted over the next four PGECx clock cycles. Whilethe received instruction is executed, the state machinesimultaneously shifts in the next 4-bit command (seeFigure 3-2).

Coming out of Reset, the first 4-bit control code isalways forced to SIX and a forced NOP instruction isexecuted by the CPU. Five additional PGECx clocksare needed on start-up, resulting in a 9-bit SIXcommand instead of the normal 4-bit SIX command.

After the forced SIX is clocked in, ICSP operationresumes as normal. That is, the next 24 clock cyclesload the first instruction word to the CPU.

FIGURE 3-2: SIX SERIAL EXECUTION

3.2.1.1 Differences Between the Execution of SIX and Normal Instructions

There are some important differences betweenexecuting instructions normally and using the SIX ICSPcommand. Therefore, the code examples in this speci-fication may not match those for performing the samefunctions during normal device operation.

During SIX ICSP operation:

• Two-word instructions require two SIX operations to clock in all the necessary data.

Examples of two-word instructions are GOTO andCALL.

• Two-cycle instructions require two SIX operations.

The first SIX operation shifts in the instruction andbegins to execute it. The second SIX operation,which should shift in a NOP to avoid losing data,provides the CPU clocks required to finishexecuting the instruction.

Examples of two-cycle instructions are Table Readand Table Write instructions.

• The CPU does not automatically stall to account for pipeline changes.

A CPU stall occurs when an instruction modifies aregister that is used for indirect addressing by thefollowing instruction.

During normal device operation:

• The CPU automatically will force a NOP while the new data is read. When using ICSP, there is no automatic stall, so any indirect references to a recently modified register should be preceded by a NOP.For example, the instructions, MOV #0x0,W0 andMOV [W0],W1, must have a NOP inserted amongthem.

If a two-cycle instruction modifies a register that isused indirectly, it will require two NOPs: one toexecute the second half of the instruction and theother to stall the CPU to correct the pipeline.

Instructions, such as TBLWTL [W0++],[W1],should be followed by two NOPs.

• The device Program Counter (PC) continues to automatically increment during ICSP instruction execution, even though the Flash memory is not being used.

As a result, the PC may be incremented to point toinvalid memory locations. Invalid memory spacesinclude unimplemented Flash addresses and thevector space (locations: 0x0 to 0x1FF).

If the PC points to these locations, the device willreset, possibly interrupting the ICSP operation. Toprevent this, instructions should be periodicallyexecuted to reset the PC to a safe space. Theoptimal method to accomplish this is to perform aGOTO 0x200.

Note: To account for this forced NOP, all examplecode in this specification begins with aNOP to ensure that no data is lost.

P4

2 3 1 2 3 23 24 1 2 3 4P1

PGECx P4A

PGEDx

24-Bit Instruction FetchExecute PC – 1,

1 6

0 0 0 0

Fetch SIX

4 5 6 7 8 18 19 20 21 2217

LSB X X X X X X X X X X X X X X MSB

PGEDx = Input

P2

P3P1B

P1A

7 8 9

0 0 0 00 0 0

Only forProgram

Memory Entry

Control Code

4 5

Execute 24-BitInstruction, FetchNext Control Code

0 0

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3.2.2 REGOUT SERIAL INSTRUCTION

EXECUTIONThe REGOUT control code allows for data to beextracted from the device in ICSP mode. It is used toclock the contents of the VISI register, out of the device,over the PGEDx pin. After the REGOUT control code isreceived, the CPU is held Idle for 8 cycles. After these8 cycles, an additional 16 cycles are required to clock thedata out (see Figure 3-3).

The REGOUT code is unique because the PGEDx pinis an input when the control code is transmitted to thedevice. However, after the control code is processed,the PGEDx pin becomes an output as the VISI registeris shifted out.

FIGURE 3-3: REGOUT SERIAL EXECUTION

Note 1: After the contents of VISI are shifted out,the PIC24FJXXXDA1/DA2/GB2/GA3devices maintain PGEDx as an outputuntil the first rising edge of the next clockis received.

2: Data changes on the falling edge andlatches on the rising edge of PGECx. Forall data transmissions, the LeastSignificant bit (LSb) is transmitted first.

1 2 3 4 1 2 7 8PGECx

P4

PGEDx

PGEDx = Input

Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register

P5

PGEDx = Output

1 2 3 1 2 3 4

P4A

11 13 15 161412

No Execution Takes Place,Fetch Next Control Code

0 0 0 0 0

PGEDx = Input

MSb1 2 3 41

4 5 6

LSb 141312... 11100

Fetch REGOUT Control Code

0

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3.3 Entering ICSP ModeAs displayed in Figure 3-4, entering ICSP Program/Verifymode requires three steps:

1. MCLR is briefly driven high, then low.2. A 32-bit key sequence is clocked into PGEDx.3. MCLR is then driven high within a specified

period and held.

The programming voltage applied to MCLR is VIH,which is essentially VDD in the case ofPIC24FJXXXDA1/DA2/GB2/GA3 devices. There is nominimum time requirement for holding at VIH. After VIHis removed, an interval of at least P18 must elapsebefore presenting the key sequence on PGEDx.

The key sequence is a specific 32-bit pattern:‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 4D434851h in hexa-decimal). The device will enter Program/Verify mode onlyif the sequence is valid. The Most Significant bit (MSb) ofthe most significant nibble must be shifted in first.

Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time, P19 and P7, must elapse before present-ing data on PGEDx. Signals appearing on PGECxbefore P7 has elapsed will not be interpreted as valid.

On successful entry, the program memory can beaccessed and programmed in serial fashion. While inICSP mode, all unused I/Os are placed in thehigh-impedance state.

FIGURE 3-4: ENTERING ICSP™ MODE

MCLR

PGEDx

PGECx

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 4D434851h

P1AP1B

P18

P19

0 1 0 0 0 0

P7VIH VIH

101

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3.4 Flash Memory Programming in

ICSP Mode

3.4.1 PROGRAMMING OPERATIONSFlash memory write and erase operations arecontrolled by the NVMCON register. Programming isperformed by setting NVMCON to select the type oferase operation (see Table 3-2) or write operation (seeTable 3-3) and initiating the programming by setting theWR control bit (NVMCON).

In ICSP mode, all programming operations areself-timed. There is an internal delay between the usersetting the WR control bit and the automatic clearing ofthe WR control bit when the programming operation iscomplete. Refer to Section 7.0 “AC/DC Characteris-tics and Timing Requirements” for information aboutthe delays associated with various programmingoperations.

TABLE 3-2: NVMCON ERASE OPERATIONS

TABLE 3-3: NVMCON WRITE OPERATIONS

3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE

The WR bit (NVMCON) is used to start an erase orwrite cycle. Setting the WR bit initiates the programmingcycle.

All erase and write cycles are self-timed. The WR bitshould be polled to determine if the erase or write cyclehas been completed. Starting a programming cycle isperformed as follows:

3.5 Erasing Program MemoryThe procedure for erasing program memory (all of thecode memory, data memory, executive memory andcode-protect bits) consists of setting NVMCON to404Fh and executing the programming cycle.

A Chip Erase can erase all of the user memory or all ofboth the user and configuration memory. A Table Writeinstruction should be executed prior to performing theChip Erase to select which sections are erased.

The Table Write instruction is executed:

• If the TBLPAG register points to user space (is less than 0x80), the Chip Erase will erase only user memory and Flash Configuration Words.

• If the TBLPAG register points to configuration space (is greater than or equal to 0x80), the Chip Erase is not allowed. The configuration space can be erased one page at a time.

Figure 3-5 displays the ICSP programming process forperforming a Chip Erase. This process includes theICSP command code, which must be transmitted (foreach instruction), LSb first, using the PGECx andPGEDx pins (see Figure 3-2).

FIGURE 3-5: CHIP ERASE FLOW

NVMCONValue Erase Operation

404Fh Erase all code memory, executive memory and Configuration registers (does not erase Device ID registers).

4042h Erase a page of code memory or executive memory.

NVMCONValue Write Operation

4003h Write a single code memory word, Configuration Word or Executive Memory Word.

4001h Program 1 row (64 instruction words) of code memory or executive memory.

BSET NVMCON, #WR

Note: The Chip Erase is not allowed when theTBLPAG points to the configuration spaceto avoid the Diagnostic and CalibrationWords from getting erased.

Note: Program memory must be erased beforewriting any data to program memory.

Start

End

Set the WR bit to Initiate Erase

Write 404Fh to NVMCON SFR

Is WR bit

Yes

Nocleared (‘0’)?

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TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.000000000000

000000040200000000

NOPGOTO 0x200NOP

Step 2: Set the NVMCON to erase all program memory.00000000

2404FA883B0A

MOV #0x404F, W10MOV W10, NVMCON

Step 3: Set TBLPAG and perform dummy Table Write to select what portions of memory are erased.000000000000000000000000

2xxxx08802A0200000BB0800000000000000

MOV #, W0MOV W0, TBLPAGMOV #0x0000, W0TBLWTL W0,[W0]NOPNOP

Step 4: Initiate the erase cycle.000000000000

A8E761000000000000

BSET NVMCON, #WRNOPNOP

Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000

040200000000803B02883C22000000

000000

GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI registerNOP

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3.6 Writing Code MemoryThe procedure for writing code memory is the same asthat of writing the Configuration registers, except that64 instruction words are programmed at a time. Tofacilitate this operation, working registers, W0:W5, areused as temporary holding registers for the data to beprogrammed.

Table 3-5 provides the ICSP programming details,including the serial pattern with the ICSP commandcode, which must be transmitted, LSb first, using thePGECx and PGEDx pins (see Figure 3-2).

In Step 1, the Reset vector is exited. In Step 2, theNVMCON register is initialized for programming a fullrow of code memory. In Step 3, the 24-bit startingdestination address for programming is loaded into theTBLPAG register and W7 register. (The upper byte ofthe starting destination address is stored in TBLPAGand the lower 16 bits of the destination address arestored in W7.)

To minimize the programming time, a packed instructionformat is used (see Figure 3-6).

In Step 4, four packed instruction words are stored inworking registers, W0:W5, using the MOV instructionand the Read Pointer, W6, is initialized. The contents ofW0:W5 (holding the packed instruction word data) aredisplayed in Figure 3-6.

In Step 5, eight TBLWT instructions are used to copy thedata from W0:W5 to the write latches of code memory.Since code memory is programmed 64 instructionwords at a time, Steps 4 and 5 are repeated 16 times toload all the write latches (Step 6).

After the write latches are loaded, programming isinitiated by writing to the NVMCON register in Steps 7and 8. In Step 9, the internal PC is reset to 200h. Thisis a precautionary measure to prevent the PC fromincrementing into unimplemented memory when largedevices are being programmed. Lastly, in Step 10,Steps 3-9 are repeated until all of the code memory isprogrammed.

FIGURE 3-6: PACKED INSTRUCTION WORDS IN W0:W5

15 8 7 0W0 LSW0W1 MSB1 MSB0W2 LSW1W3 LSW2W4 MSB3 MSB2W5 LSW3

TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORYCommand(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.000000000000

000000040200000000

NOPGOTO 0x200NOP

Step 2: Set the NVMCON to program 64 instruction words.00000000

24001A883B0A

MOV #0x4001, W10MOV W10, NVMCON

Step 3: Initialize the Write Pointer (W7) for TBLWT instruction.000000000000

200xx08802A02xxxx7

MOV #, W0MOV W0, TBLPAGMOV #, W7

Step 4: Load W0:W5 with the next 4 instruction words to program.000000000000000000000000

2xxxx02xxxx12xxxx22xxxx32xxxx42xxxx5

MOV #, W0MOV #, W1MOV #, W2MOV #, W3MOV #, W4MOV #, W5

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Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0300000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000

CLR W6NOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOP

Step 6: Repeat Steps 4 and 5, 16 times, to load the write latches for 64 instructions. Step 7: Initiate the write cycle.

000000000000

A8E761000000000000

BSET NVMCON, #WRNOPNOP

Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000

040200000000803B02883C22000000

000000

GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP

Step 9: Reset device internal PC.00000000

040200000000

GOTO 0x200NOP

Step 10: Repeat Steps 3 through 9 until all code memory is programmed.

TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)Command(Binary)

Data(Hex) Description

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PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 3-7: PROGRAM CODE MEMORY FLOW

Start Write Sequence

Alllocations

done?

No

End

Start

Yes

Load 1 Instruction WordWrite Buffer at

Allinstruction words

written?

No

Yes

and Poll for WR bitto be Cleared

N = 1LoopCount = 0

ConfigureDevice for

Writes

N = 1LoopCount =

LoopCount + 1

N = N + 1

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3.7 Writing Configuration WordsDevice configuration for PIC24FJXXXDA1/DA2/GB2/GA3 devices is stored in Flash Configuration Words atthe end of the user space program memory and inmultiple register Configuration Words, located in the testspace. These registers reflect values read at any Resetfrom program memory locations. The values for the Con-figuration Words for the default device configurations arelisted in Table 3-6.

The values can be changed only by programming thecontent of the corresponding Flash Configuration Wordand resetting the device. The Reset forces an auto-matic reload of the Flash stored configuration values bysequencing through the dedicated Flash ConfigurationWords and transferring the data into the Configurationregisters.

For the PIC24FJXXXDA1/DA2/GB2/GA3 families, cer-tain Configuration bits have default states that mustalways be maintained to ensure device functionality,regardless of the settings of other Configuration bits.

To change the values of the Flash Configuration Wordonce it has been programmed, the device must be ChipErased, as described in Section 3.5 “Erasing ProgramMemory” and reprogrammed to the desired value. It isnot possible to program a ‘0’ to ‘1’; they may beprogrammed from a ‘1’ to ‘0’ to enable code protection.

TABLE 3-6: DEFAULT CONFIGURATION REGISTER VALUES

Table 3-7 provides the ICSP programming details forprogramming the Configuration Word locations, includ-ing the serial pattern with the ICSP command code,which must be transmitted, LSb first, using the PGECxand PGEDx pins (see Figure 3-2).

In Step 1, the Reset vector is exited. In Step 2, the lower16 bits of the source address are stored in W7. InStep 3, the NVMCON register is initialized for program-ming of code memory. In Step 4, the upper byte of the24-bit starting source address for writing is loaded intothe TBLPAG register.

The TBLPAG register must be loaded with 00h for64 Kbytes, and 01h for 128 and 256 Kbytes devices.

To verify the data by reading the Configuration Wordsafter performing the write in order, the code protectionbits initially should be programmed to a ‘1’ to ensurethat the verification can be performed properly. Afterverification is finished, the code protection bit can beprogrammed to a ‘0’ by using a word write to theappropriate Configuration Word.

Address Name Default Value

Last Word CW1 7FFFhLast Word – 2 CW2 FFFFhLast Word – 4 CW3 FFFFhLast Word – 6 CW4 FFFFh

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TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERSCommand

(Binary)Data(Hex) Description

Step 1: Exit the Reset vector.000000000000

000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction.0000 2xxxx7 MOV #, W7

Step 3: Set the NVMCON register to program CW1.00000000

24003A883B0A

MOV #0x4003, W10MOV W10, NVMCON

Step 4: Initialize the TBLPAG register.00000000

200xx08802A0

MOV #, W0MOV W0, TBLPAG

Step 5: Load the Configuration register data to W6.0000 2xxxx6 MOV #, W6

Step 6: Write the Configuration register data to the write latch and decrement the Write Pointer.00000000000000000000000000000000

200008000000BBCB88000000000000BB1386000000000000

MOV #0x0000, W8NOPTBLWTH.B W8, [W7]NOPNOPTBLWTL.W W6, [W7--]NOPNOP

Step 7: Initiate the write cycle.000000000000

A8E761000000000000

BSET NVMCON, #WRNOPNOP

Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.0000000000000000000000010000

040200000000803B02883C22000000

000000

GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOPClock out contents of the VISI register.NOP

Step 9: Reset device internal PC.00000000

040200000000

GOTO 0x200NOP

Step 10: Repeat Steps 5 through 9 to write Configuration Word 2 to Configuration Word 4.

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3.8 Reading Code MemoryReading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.

Table 3-8 provides the ICSP programming details forreading code memory. In Step 1, the Reset vector isexited. In Step 2, the Write Pointer, W7, is initialized. InStep 3, the 24-bit starting source address for reading isloaded into the TBLPAG register and W6 register. Theupper byte of the starting source address is stored inTBLPAG and the lower 16 bits of the source addressare stored in W6.

To minimize the reading time, the packed instructionword format that was utilized for writing is also used forreading (see Figure 3-6). In Step 4, two instructionwords are read from code memory and clocked out ofthe device, through the VISI register, using theREGOUT command. Step 4 is repeated until thedesired amount of code memory is read.

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORYCommand

(Binary)Data(Hex) Description

Step 1: Exit Reset vector.000000000000

000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize the Write Pointer (W7) to point to the VISI register.00000000

207847000000

MOV #VISI, W7 NOP

Step 3: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction.000000000000

200xx08802A02xxxx6

MOV #, W0MOV W0, TBLPAGMOV #, W6

Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using the REGOUT command.

000000000000000100000000000000000000000000000001000000000000000000010000

BA0B96000000000000

000000BADBB6000000000000BAD3D6000000000000

000000BA0BB6000000000000

000000

TBLRDL [W6], [W7]NOPNOPClock out contents of VISI registerNOPTBLRDH.B [W6++], [W7++]NOPNOPTBLRDH.B [++W6], [W7--]NOPNOPClock out contents of VISI registerNOPTBLRDL [W6++], [W7]NOPNOPClock out contents of VISI registerNOP

Step 5: Reset device internal PC.00000000

040200000000

GOTO 0x200NOP

Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset device internal PC” will be Step 5).

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3.9 Reading Configuration WordsThe procedure for reading configuration memory issimilar to the procedure for reading code memory,except that 16-bit data words are read instead of 24-bitwords. Configuration Words are read one register at atime.

Table 3-9 provides the ICSP programming details forreading the Configuration Words. Note that theTBLPAG register must be loaded with 00h for64 Kbytes, and 01h for 128 and 256 Kbytes devices.W6 is initialized to the lower 16 bits of the ConfigurationWord location.

TABLE 3-9: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORYCommand

(Binary)Data(Hex) Description

Step 1: Exit Reset vector.000000000000

000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction.00000000000000000000

200xx08802A02xxxx6207847000000

MOV #, W0MOV W0, TBLPAGMOV #, W6MOV #VISI, W7NOP

Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command.

00000000000000010000

BA0BA6000000000000

000000

TBLRDL [W6--], [W7]NOP NOPClock out contents of VISI registerNOP

Step 4: Repeat Step 3 to read Configuration Word 2 to Configuration Word 4. Step 5: Reset device internal PC.

00000000

040200000000

GOTO 0x200NOP

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3.10 Verify Code Memory and

Configuration WordThe verify step involves reading back the code memoryspace, and comparing it with the copy held in theprogrammer’s buffer. The Configuration registers areverified with the rest of the code.

The flowchart in Figure 3-8 illustrates the verify pro-cess. Memory reads occur a single byte at a time, sotwo bytes must be read to compare with the word in theprogrammer’s buffer. Refer to Section 3.8 “ReadingCode Memory” for implementation details of readingcode memory.

FIGURE 3-8: VERIFY CODE MEMORY FLOW

3.11 Reading the Application ID WordThe Application ID Word is stored at address,8007F0h, in executive code memory. To read thismemory location, you must use the SIX control code tomove this program memory location to the VISIregister. Then, the REGOUT control code must beused to clock the contents of the VISI register out of thedevice. Table 3-10 provides the corresponding controland instruction codes that must be serially transmittedto the device to perform this operation.

After the programmer has clocked out the ApplicationID Word, it must be inspected. If the Application ID hasthe value, CCh, the programming executive is residentin memory and the device can be programmed usingthe mechanism described in Section 4.0 “DeviceProgramming – Enhanced ICSP”. However, if theApplication ID has any other value, the programmingexecutive is not resident in memory; it must be loadedto memory before the device can be programmed. Theprocedure for loading the programming executive tomemory is described in Section 5.4 “Programmingthe Programming Executive to Memory”.

3.12 Exiting ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as displayed in Figure 3-9. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock and program signals onPGECx and PGEDx before removing VIH.

FIGURE 3-9: EXITING ICSP™ MODE

Note: Because the Configuration registersinclude the device code protection bit,code memory should be verified immedi-ately after writing if code protection isenabled. This is because the device willnot be readable or verifiable if a deviceReset occurs after the code-protect bit inCW1 has been cleared.

Read Low Byte

Read High Byte

DoesWord = Expect

Data?

Failure,ReportError

Allcode memory

verified?

No

Yes

No

Set TBLPTR = 0

Start

Yes

End

with Post-Increment

with Post-Increment

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VIH

VIH

P17

2010 Microchip Technology Inc. DS39970B-page 27

PIC24FJXXXDA1/DA2/GB2/GA3

TABLE 3-10: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD

Command(Binary)

Data(Hex) Description

Step 1: Exit Reset vector.000000000000

000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize TBLPAG and the Read Pointer (W0) for TBLRD instruction.00000000000000000000000000000000

2008008802A0207F00207841000000BA0890000000000000

MOV #0x80, W0MOV W0, TBLPAGMOV #0x07F0, W0MOV #VISI, W1NOPTBLRDL [W0], [W1]NOPNOP

Step 3: Output the VISI register using the REGOUT command.00010000

000000

Clock out contents of the VISI registerNOP

DS39970B-page 28 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

4.0 DEVICE PROGRAMMING – ENHANCED ICSP

This section discusses programming the devicethrough Enhanced ICSP and the programming execu-tive. The programming executive resides in executivememory (separate from code memory) and is executedwhen Enhanced ICSP Programming mode is entered.The programming executive provides the mechanismfor the programmer (host device) to program and verifythe PIC24FJXXXDA1/DA2/GB2/GA3 devices, using asimple command set and communication protocol.There are several basic functions provided by theprogramming executive:

• Read Memory• Erase Memory• Program Memory• Blank Check• Read Executive Firmware Revision

The programming executive performs the low-leveltasks required for erasing, programming and verifyinga device. This allows the programmer to program thedevice by issuing the appropriate commands and data.Table 4-1 provides the commands. A detailed descrip-tion for each command is provided in Section 5.2“Programming Executive Commands”.

TABLE 4-1: COMMAND SET SUMMARY

The programming executive uses the device’s dataRAM for variable storage and program execution. Afterthe programming executive has run, no assumptionsshould be made about the contents of data RAM.

4.1 Overview of the Programming Process

Figure 4-1 displays the high-level overview of theprogramming process. After entering Enhanced ICSPmode, the programming executive is verified. Next, thedevice is erased. Then, the code memory isprogrammed, followed by the configuration locations.Code memory (including the Configuration registers) isthen verified to ensure that programming was successful.

After the programming executive has been verifiedin memory (or loaded if not present), thePIC24FJXXXDA1/DA2/GB2/GA3 families can beprogrammed using the command set provided inTable 4-1.

FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW

4.2 Confirming the Presence of the Programming Executive

Before programming can begin, the programmer mustconfirm that the programming executive is stored inexecutive memory. The procedure for this task isdisplayed in Figure 4-2.

First, ICSP mode is entered. Then, the uniqueApplication ID Word stored in executive memory isread. If the programming executive is resident, theApplication ID Word is CCh, which means programmingcan resume as normal. However, if the Application IDWord is not CCh, the programming executive must beprogrammed to executive code memory using themethod described in Section 5.4 “Programming theProgramming Executive to Memory”. Section 3.0 “Device Programming – ICSP” describesthe ICSP programming method. Section 3.11 “Readingthe Application ID Word” describes the procedure forreading the Application ID Word in ICSP mode.

Command Description

SCHECK Sanity CheckREADC Read Device ID RegistersREADP Read Code Memory PROGP Program One Row of Code Memory

and VerifyPROGW Program One Word of Code Memory

and VerifyQBLANK Query if the Code Memory is BlankQVER Query the Software Version

Start

End

Perform ChipErase

Program Memory

Verify Program

Enter Enhanced ICSP™

Program Configuration Bits

Verify Configuration Bits

Exit Enhanced ICSP

2010 Microchip Technology Inc. DS39970B-page 29

PIC24FJXXXDA1/DA2/GB2/GA3

FIGURE 4-2: CONFIRMING PRESENCE

OF PROGRAMMING EXECUTIVE

4.3 Entering Enhanced ICSP ModeAs displayed in Figure 4-3, entering Enhanced ICSPProgram/Verify mode requires three steps:

1. The MCLR pin is briefly driven high, then low.2. A 32-bit key sequence is clocked into PGEDx.3. MCLR is then driven high within a specified

period and held.

The programming voltage applied to MCLR is VIH,which is essentially VDD in the case ofPIC24FJXXXDA1/DA2/GB2/GA3 devices. There is nominimum time requirement for holding at VIH. After VIHis removed, an interval of at least P18 must elapsebefore presenting the key sequence on PGEDx.

The key sequence is a specific 32-bit pattern:‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 4D434850h in hexa-decimal format). The device will enter Program/Verifymode only if the key sequence is valid. The MSb of themost significant nibble must be shifted in first.

Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time, P19 and P7, must elapse before present-ing data on PGEDx. Signals appearing on PGEDx,before P7 has elapsed, will not be interpreted as valid.

On successful entry, the program memory can beaccessed and programmed in serial fashion. While inthe Program/Verify mode, all unused I/Os are placed inthe high-impedance state.

FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE

Is

Start

Enter ICSP™ Mode

Application IDCCh?

Resident in Memory

Yes

No

Prog. Executive is

Application IDRead the

be ProgrammedProg. Executive must

from Address8007F0h

End

MCLR

PGEDx

PGECx

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 4D434850h

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 0

P7VIH VIH

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PIC24FJXXXDA1/DA2/GB2/GA3

4.4 Blank CheckThe term “Blank Check” implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as ‘1’.The Device ID registers (FF0002h:FF0000h) can beignored by the Blank Check since this region storesdevice information that cannot be erased. The deviceConfiguration registers are also ignored by the BlankCheck. Additionally, all unimplemented memory spaceshould be ignored by the Blank Check.

The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.

4.5 Code Memory Programming

4.5.1 PROGRAMMING METHODOLOGYCode memory is programmed with the PROGPcommand. PROGP programs one row of code memorystarting from the memory address specified in thecommand. The number of PROGP commandsrequired to program a device depends on the numberof write blocks that must be programmed in the device.

A flowchart for programming the code memory of thePIC24FJXXXDA1/DA2/GB2/GA3 families is displayedin Figure 4-4. In this example, all 87K instruction wordsof a 256-Kbyte device are programmed. First, the num-ber of commands to send (called ‘RemainingCmds’ inthe flowchart) is set to 1368 and the destinationaddress (called ‘BaseAddress’) is set to ‘0’. Next, onewrite block in the device is programmed with a PROGPcommand. Each PROGP command contains data forone row of code memory of the device. After the firstcommand is processed successfully, ‘RemainingCmds’is decremented by 1 and compared with 0. Since thereare more PROGP commands to send, ‘BaseAddress’is incremented by 80h to point to the next row ofmemory.

On the second PROGP command, the second row isprogrammed. This process is repeated until the entiredevice is programmed. No special handling must beperformed when a panel boundary is crossed.

FIGURE 4-4: FLOWCHART FOR PROGRAMMING CODE MEMORY

4.5.2 PROGRAMMING VERIFICATIONAfter code memory is programmed, the contents ofmemory can be verified to ensure that programmingwas successful. Verification requires code memory tobe read back and compared with the copy held in theprogrammer’s buffer.

The READP command can be used to read back all ofthe programmed code memory.

Alternatively, you can have the programmer performthe verification, after the entire device is programmed,using a checksum computation.

IsPROGP response

PASS?

AreRemainingCmds

0?

BaseAddress = 00hRemainingCmds = 1368

RemainingCmds =RemainingCmds – 1

BaseAddress =BaseAddress + 80h

No

No

Yes

Yes

Start

FailureReport Error

Send PROGPCommand to Program

BaseAddress

Finish

2010 Microchip Technology Inc. DS39970B-page 31

PIC24FJXXXDA1/DA2/GB2/GA3

4.6 Configuration Bits Programming

4.6.1 OVERVIEWThe PIC24FJXXXDA1/DA2/GB2/GA3 families haveConfiguration bits stored in the last four locations ofimplemented program memory (see Table 2-2 for loca-tions). These bits can be set or cleared to select variousdevice configurations. There are two types of Configura-tion bits: system operation bits and code-protect bits. Thesystem operation bits determine the power-on settingsfor system level components, such as the oscillator andWatchdog Timer. The code-protect bits prevent programmemory from being read and written to.

Table 4-2 provides the descriptions for thePIC24FJXXXDA1/DA2/GB2 Configuration bits in theFlash Configuration Words.

Note: Although not implemented with a specificfunction, the bit at CW1 must alwaysbe maintained as ‘0’ to ensure devicefunctionality, regardless of the settings ofother Configuration bits.

TABLE 4-2: PIC24FJXXXDA1/DA2/GB2 CONFIGURATION BITS DESCRIPTIONBit Field Register(1) Description

ALTPMP CW3 Alternate PMP Pin Mapping bit1 = EPMP is in Default Location mode0 = EPMP is in Alternate Location mode

ALTVREF CW1 Alternate VREF Location Enable bit1 = VREF is on a default pin (VREF+ on RA9 and VREF- on RA10)0 = VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1)

DEBUG CW1 Background Debugger Enable bit1 = Device resets into Operational mode0 = Device resets into Debug mode

FCKSM CW2 Clock Switching and Fail-Safe Clock Monitor (FSCM) Configuration bits1x = Clock switching and Fail-Safe Clock Monitor are disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

FNOSC CW2 Initial Oscillator Source Selection bits111 = Fast RC Oscillator with Postscaler module (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary (XT, HS, EC) Oscillator001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)000 = Fast RC (FRC) Oscillator

FWDTEN CW1 Watchdog Timer Enable bit1 = Watchdog Timer is enabled0 = Watchdog Timer is disabled

FWPSA CW1 Watchdog Timer Prescaler bit1 = WDT prescaler ratio of 1:1280 = WDT prescaler ratio of 1:32

GCP CW1 General Segment Program Memory Code Protection bit1 = Code protection is disabled0 = Code protection is enabled for the entire program memory space

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified using only In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

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PIC24FJXXXDA1/DA2/GB2/GA3

GWRP CW1 General Segment Code Flash Write Protection bit1 = Writes to program memory are allowed0 = Writes to program memory are disabled

ICS CW1 ICD Emulator Pin Placement Select bits11 = Emulator functions are shared with PGEC1/PGED110 = Emulator functions are shared with PGEC2/PGED201 = Emulator functions are shared with PGEC3/PGED300 = Reserved; do not use

IESO CW2 Internal External Switchover bit1 = Two-Speed Start-up is enabled0 = Two-Speed Start-up is disabled

IOL1WAY CW2 IOLOCK Bit One-Way Set Enable bit1 = The IOLOCK bit (OSCCON) can be set once, provided

the unlock sequence has been completed. Once set, the Peripheral Pin Select (PPS) registers cannot be written to a second time.

0 = The IOLOCK is cleared as needed (provided an unlocking sequence is executed)

JTAGEN(2) CW1 JTAG Enable bit1 = JTAG port is enabled0 = JTAG port is disabled

OSCIOFCN CW2 OSC2 Pin Function bit (except in XT and HS modes)If POSCMD = 11 or 00:1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2)0 = OSCO/CLKO/RC15 functions as port I/O (RC15)If POSCMD = 10 or 01:OSCIOFCN has no effect on OSCO/CLKO/RC15

PLLDIV CW2 USB 96 MHz PLL Prescaler Select bits111 = Oscillator input divided by 12 (48 MHz input)110 = Oscillator input divided by 8 (32 MHz input)101 = Oscillator input divided by 6 (24 MHz input)100 = Oscillator input divided by 5 (20 MHz input)011 = Oscillator input divided by 4 (16 MHz input)010 = Oscillator input divided by 3 (12 MHz input)001 = Oscillator input divided by 2 (8 MHz input)000 = Oscillator input used directly (4 MHz input)

POSCMD CW2 Primary Oscillator Mode Select bits11 = Primary Oscillator is disabled10 = HS Oscillator mode is selected01 = XT Oscillator mode is selected00 = EC Oscillator mode is selected

PLL96MHz CW2 USB 96 MHz PLL Start-up Enable bit1 = 96 MHz PLL is enabled automatically on start-up0 = 96 MHz PLL is enabled by user in software (controlled with

the PLLEN bit in CLKDIV)

TABLE 4-2: PIC24FJXXXDA1/DA2/GB2 CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register(1) Description

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified using only In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

2010 Microchip Technology Inc. DS39970B-page 33

PIC24FJXXXDA1/DA2/GB2/GA3

SOSCSEL CW3 SOSC Selection Configuration bits11 = Secondary oscillator in Default (high drive strength) Oscillator mode10 = Reserved; do not use01 = Secondary oscillator in Low-Power (low drive strength) Oscillator

mode00 = External clock (SCLKI) or Digital I/O mode

WDTPS CW1 Watchdog Timer Postscaler bits1111 = 1:32,7681110 = 1:16,384

.

.

.0001 = 1:20000 = 1:1

WINDIS CW1 Windowed WDT bit1 = Standard Watchdog Timer is enabled0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’

WPCFG CW3 Configuration Word Code Page Write Protection Select bit1 = Last page (at the top of program memory) and Flash Configuration

Words are not write-protected(3)0 = Last page and Flash Configuration Words are write-protected

provided, WPDIS = 0WPDIS CW3 Segment Write Protection Disable bit

1 = Segmented code protection is disabled0 = Segmented code protection is enabled; protected segment defined

by the WPEND, WPCFG and WPFPx Configuration bitsWPEND CW3 Segment Write Protection End Page Select bit

1 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP

0 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP

WPFP CW3 Write-Protected Code Segment Boundary Page bitsDesignate the 512-instruction page that is the boundary of the protected code segment, starting with Page 0 at the bottom of program memory.If WPEND = 1:First address of designated code page is the lower boundary of the segment; the last implemented page will be the last write-protected page.If WPEND = 0:Last address of designated code page is the upper boundary of the segment.

WUTSEL CW3 Voltage Regulator Standby Mode Wake-up Time Select bits11 = Default regulator start-up time is used01 = Fast regulator start-up time is usedx0 = Reserved; do not use

TABLE 4-2: PIC24FJXXXDA1/DA2/GB2 CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register(1) Description

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified using only In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

DS39970B-page 34 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

Table 4-3 provides the descriptions for thePIC24FJXXXGA3 Configuration bits in the FlashConfiguration Words.

Note: Although not implemented with a specificfunction, the bit at CW1 must alwaysbe maintained as ‘0’ to ensure devicefunctionality, regardless of the settings ofother Configuration bits.

TABLE 4-3: PIC24FJXXXGA3 CONFIGURATION BITS DESCRIPTIONBit Field Register(1) Description

ALTVREF CW2 Alternate VREF/CVREF Location Enable bit00 = AVREF AND CVREF are in alternate locations01 = AVREF is in alternate location and CVREF is in default location10 = AVREF is in default location and CVREF is in alternate location11 = AVREF is in default location and CVREF is in default location

BBEN CW4 Back Bias Enable bit0 = Back bias is disabled1 = Back bias is enabled

BBDIS CW2 Back Bias Feature Disable bit0 = Back bias feature enabled in Deep Sleep1 = Back bias feature disabled

BOREN CW3 Brown-out Reset Enable bit0 = BORMV is disabled1 = BORMV is enabled outside of Deep Sleep (BORMV is always

disabled in Deep Sleep)BORV CW2 Brown-out Reset Voltage bit

0 = BORMV trip point is 1.8V min1 = BORMV trip point is 2.0V min

DEBUG CW1 Background Debugger Enable bit1 = Device resets into Operational mode0 = Device resets into Debug mode

DSBITEN CW4 Deep Sleep Control bit0 = Deep Sleep operation is always disabled1 = Deep Sleep is controlled by the register bit, DSEN

DSWDTEN CW4 Deep Sleep Watchdog Timer Enable bit1 = DSWDT is enabled0 = DSWDT is disabled

DSBOREN CW4 Deep Sleep BOR Enable bit1 = BOR is enabled in Deep Sleep0 = BOR is disabled in Deep Sleep (does not affect Sleep mode)

DSWDTOSC CW4 DSWDT Reference Clock Select bit1 = DSWDT uses LPRC as reference clock0 = DSWDT uses SOSC as reference clock

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

2010 Microchip Technology Inc. DS39970B-page 35

PIC24FJXXXDA1/DA2/GB2/GA3

DSWDTPS CW4 Deep Sleep Watchdog Timer Postscale Select bitsThe DS WDT prescaler is 32; this creates an approximate base time unit of 1 ms.11111 = 1:68,719,476736 (25.7 days)11110 = 1:34,359,738368(12.8 days)11101 = 1:17,179,869184 (6.4 days)11100 = 1:8,589,934592 (77.0 hours)11011 = 1:4,294,967296 (38.5 hours)11010 = 1:2,147,483648 (19.2 hours)11001 = 1:1,073,741824 (9.6 hours)11000 = 1:536,870912 (4.8 hours)10111 = 1:268,435456 (2.4 hours)10110 = 1:134,217728 (72.2 minutes)10101 = 1:67,108864 (36.1 minutes)10100 = 1:33,554432 (18.0 minutes)10011 = 1:16,777216 (9.0 minutes)10010 = 1:8,388608 (4.5 minutes)10001 = 1:4,194304 (135.3 s)10000 = 1:2,097152 (67.7 s)01111 = 1:1,048576 (33.825 s)01110 = 1:524288 (16.912 s)01101 = 1:262114 (8.456 s)01100 = 1:131072 (4.228 s)01011 = 1:65536 (2.114 s)01010 = 1:32768 (1.057 s)01001 = 1:16384 (528.5 ms)01000 = 1:8192 (264.3 ms)00111 = 1:4096 (132.1 ms)00110 = 1:2048 (66.1 ms)00101 = 1:1024 (33 ms)00100 = 1:512 (16.5 ms)00011 = 1:256 (8.3 ms)00010 = 1:128 (4.1 ms)00001 = 1:64 (2.1 ms)00000 = 1:32 (1 ms)

FCKSM CW2 Clock Switching and Fail-Safe Clock Monitor Selection Configuration bits1x = Clock switching and Fail-Safe Clock Monitor are disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

FNOSC CW2 Initial Oscillator Source Selection bits111 = Fast RC Oscillator with Postscaler module (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary (XT, HS, EC) Oscillator001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)000 = Fast RC (FRC) Oscillator

TABLE 4-3: PIC24FJXXXGA3 CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register(1) Description

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

DS39970B-page 36 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

FWDTEN CW1 11 = Watchdog Timer is enabled in hardware10 = Watchdog Timer is controlled with the SWDTEN bit setting01 = Watchdog Timer is enabled only while device is active and disabled

in Sleep; SWDTEN bit is disabled00 = Watchdog Timer is disabled in hardware; SWDTEN bit is disabled

FWPSA CW1 Watchdog Timer Prescaler Ratio Select bit1 = Watchdog Timer prescaler ratio of 1:1280 = Watchdog Timer prescaler ratio of 1:32

GCP CW1 General Segment Program Memory Code Protection bit1 = Code protection is disabled0 = Code protection is enabled for the entire program memory space

GWRP CW1 General Segment Code Flash Write Protection bit1 = Writes to program memory are allowed0 = Writes to program memory are disabled

ICS CW1 ICD Emulator Pin Placement Select bits11 = Emulator functions are shared with PGEC1/PGED110 = Emulator functions are shared with PGEC2/PGED201 = Emulator functions are shared with PGEC3/PGED300 = Reserved; do not use

IESO CW2 Internal External Switchover bit1 = Two-Speed Start-up is enabled0 = Two-Speed Start-up is disabled

IOL1WAY CW2 IOLOCK Bit One-Way Set Enable bit1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock

sequence has been completed. Once set, the Peripheral PinSelect (PPS) registers cannot be written to a second time.

0 = The IOLOCK is cleared as needed (provided an unlocking sequenceis executed)

JTAGEN(2) CW1 JTAG Enable bit1 = JTAG port is enabled0 = JTAG port is disabled

LPCFG CW1 Low-Power Regulator Control Enable bit0 = LP regulator feature is available and controlled by ULPEN during

Sleep1 = LP regulator feature is not available

OSCIOFCN CW2 OSC2 Pin Function bit (except in XT and HS modes)If POSCMD = 11 or 00:1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2)0 = OSCO/CLKO/RC15 functions as port I/O (RC15)If POSCMD = 10 or 01:OSCIOFCN has no effect on OSCO/CLKO/RC15

POSCMD CW2 Primary Oscillator Mode Select bits11 = Primary Oscillator is disabled10 = HS Oscillator mode is selected01 = XT Oscillator mode is selected00 = EC Oscillator mode is selected

TABLE 4-3: PIC24FJXXXGA3 CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register(1) Description

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

2010 Microchip Technology Inc. DS39970B-page 37

PIC24FJXXXDA1/DA2/GB2/GA3

RTCBATEN CW4 RTCC VBAT Battery Operation Enable bit0 = RTC operation is discontinued in VBAT1 = RTC operation is continued through VBAT

SOSCSEL CW3 SOSC Selection Configuration bits11 = Secondary oscillator in Default (high drive strength) Oscillator mode10 = Reserved; do not use01 = Secondary oscillator in Low-Power (low drive strength) Oscillator

mode00 = External clock (SCLKI) or Digital I/O mode

WDTPS CW1 Watchdog Timer Postscaler bits1111 = 1:32,7681110 = 1:16,384 . . .0001 = 1:20000 = 1:1

WDTWIN CW3 Watchdog Timer Window Width00 = 75%01 = 50%10 = 37.5%11 = 25%

WINDIS CW1 Windowed WDT bit1 = Standard Watchdog Timer is enabled0 = Windowed Watchdog Timer is enabled; FWDTEN must be '1'

WPCFG CW3 Configuration Word Code Page Write Protection Select bit1 = Last page (at the top of program memory) and Flash Configuration

Words are not write-protected(3)0 = Last page and Flash Configuration Words are write-protected

provided, WPDIS = 0WPDIS CW3 Segment Write Protection Disable bit

1 = Segmented code protection is disabled0 = Segmented code protection is enabled; protected segment defined

by the WPEND, WPCFG and WPFPx Configuration bitsWPEND CW3 Segment Write Protection End Page Select bit

1 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP

0 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP

TABLE 4-3: PIC24FJXXXGA3 CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register(1) Description

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

DS39970B-page 38 2010 Microchip Technology Inc.

PIC24FJXXXDA1/DA2/GB2/GA3

WPFP CW3 Write-Protect Program Flash Pages (valid when WPDIS = 0)(3)When WPEND = 0:Erase/write-protect Flash memory pages, starting at page 0 and ending with page WPFPWhen WPEND = 1:Erase/write-protect Flash memory pages, starting at page WPFP and ending with the last page in user Flash

RTCBATEN CW4 RTCC VBAT Battery Operation Enable bit0 = RTC operation is discontinued in VBAT1 = RTC operation is continued through VBAT

LPCFG CW1 Low-Power Regulator Control Enable bit0 = LP regulator feature is available and controlled by ULPEN

during Sleep1 = LP regulator feature is not available

TABLE 4-3: PIC24FJXXXGA3 CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register(1) Description

Note 1: Bits should be programmed to a value of 0x00 to ensure that accidental program execution of any of the Configuration Words would be interpreted as a NOP opcode.

2: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).3: Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words

page, the Configuration Words page will be protected

2010 Microchip Technology Inc. DS39970B-page 39

PIC24FJXXXDA1/DA2/GB2/GA3

4.6.2 PROGRAMMING METHODOLOGYConfiguration bits may be programmed a single word ata time using the PROGW command. This commandspecifies the configuration data and Configurationregister address. When Configuration bits areprogrammed, any unimplemented or reserved bitsmust be programmed with a ‘1’.Four PROGW commands are required to program theConfiguration bits. See Figure 4-5 for a flowchart forConfiguration bit programming.

4.6.3 PROGRAMMING VERIFICATIONAfter the Configuration bits are programmed, thecontents of memory should be verified to ensure thatthe programming was successful. Verification requiresthe Configuration bits to be read back and comparedwith the copy held in the programmer’s buffer. TheREADP command reads back the programmedConfiguration bits and verifies that the programmingwas successful.

FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW

Note: If the General Segment Code-Protect bit(GCP) is programmed to ‘0’, code memoryis code-protected and cannot be read. Codememory must be verified before enablingread protection. See Section 4.6.4“Code-Protect Configuration Bits” formore information about code-protectConfiguration bits.

Send PROGWCommand

ConfigAddress = 0XXXF8h(1)

IsPROGP response

PASS?

No

Yes

No

FailureReport Error

Start

End

Yes

IsConfigAddress0XXXFEh?(1)

ConfigAddress =ConfigAddress + 2

Note 1: Refer to Table 2-2 for Flash Configuration Word addresses.

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PIC24FJXXXDA1/DA2/GB2/GA3

4.6.4 CODE-PROTECT CONFIGURATION

BITSPIC24FJXXXDA1/DA2/GB2/GA3 family devices pro-vide two complimentary methods to protect applicationcode from overwrites and erasures. These also help toprotect the device from inadvertent configurationchanges during run time. Additional information isavailable in the product data sheet.

4.6.4.1 GENERAL SEGMENT PROTECTION

For all devices in the PIC24FJXXXDA1/DA2/GB2/GA3families, the on-chip program memory space is treatedas a single block, known as the General Segment (GS).Code protection for this block is controlled by one Con-figuration bit, GCP. This bit inhibits external reads andwrites to the program memory space. It has no directeffect in normal execution mode.

Write protection is controlled by the GWRP bit in theConfiguration Word. When GWRP is programmed to‘0’, internal write and erase operations to programmemory are blocked.

4.6.4.2 CODE SEGMENT PROTECTIONIn addition to global General Segment protection, aseparate subrange of the program memory space canbe individually protected against writes and erases.This area can be used for many purposes, where aseparate block of write and erase-protected code isneeded, such as bootloader applications. Unlikecommon boot block implementations, the specially pro-tected segment in PIC24FJXXXDA1/DA2/GB2/GA3devices can be located by the user anywhere in theprogram space, and configured in a wide range ofsizes.

Code segment protection provides an added level ofprotection to a designated area of program memory bydisabling the NVM safety interlock, whenever a write orerase address falls, within a specified range. It does notoverride General Segment protection controlled by theGCP or GWRP bits. For example, if GCP and GWRPare enabled, enabling segmented code protection forthe bottom half of program memory does not undoGeneral Segment protection for the top half.

4.7 Exiting Enhanced ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as displayed in Figure 4-6. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock, and program signals onPGECx and PGEDx, before removing VIH.

FIGURE 4-6: EXITING ENHANCED ICSP™ MODE

Note: Chip Erasing in ICSP mode is the only wayto reprogram code-protect bits from an ONstate (‘0’) to an OFF state (‘1’).

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VIH

VIH

P17

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5.0 THE PROGRAMMING EXECUTIVE

5.1 Programming Executive Communication

The programmer and programming executive have amaster-slave relationship, where the programmer isthe master programming device and the programmingexecutive is the slave.

All communication is initiated by the programmer in theform of a command. Only one command at a time canbe sent to the programming executive. In turn, theprogramming executive only sends one response tothe programmer after receiving and processing acommand. The programming executive command setis described in Section 5.2 “Programming ExecutiveCommands”. The response set is described inSection 5.3 “Programming Executive Responses”.

5.1.1 COMMUNICATION INTERFACE AND PROTOCOL

The Enhanced ICSP interface is a 2-wire SPI,implemented using the PGECx and PGEDx pins. ThePGECx pin is used as a clock input pin and the clocksource must be provided by the programmer. ThePGEDx pin is used for sending command data to, andreceiving response data from, the programmingexecutive.

Data transmits to the device must change on the risingedge and hold on the falling edge. Data receives fromthe device must change on the falling edge and hold onthe rising edge.

All data transmissions are sent MSb first using 16-bitmode (see Figure 5-1).

FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE

FIGURE 5-2: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE

Since a 2-wire SPI is used, and data transmissions arehalf-duplex, a simple protocol is used to control thedirection of PGEDx. When the programmer completesa command transmission, it releases the PGEDx lineand allows the programming executive to drive this linehigh. The programming executive keeps the PGEDxline high to indicate that it is processing the command.

After the programming executive has processed thecommand, it brings PGEDx low for 15 s to indicate tothe programmer that the response is available to beclocked out. The programmer can begin to clock out theresponse, 23 s after PGEDx is brought low, and it mustprovide the necessary amount of clock pulses to receivethe entire response from the programming executive.

After the entire response is clocked out, the program-mer should terminate the clock on PGECx until it is timeto send another command to the programmingexecutive. See Figure 5-3 for this protocol.

5.1.2 SPI RATEIn Enhanced ICSP mode, the PIC24FJXXXDA1/DA2/GB2/GA3 devices operate from the Internal Fast RCOscillator (FRCDIV), which has a nominal frequency of8 MHz. This oscillator frequency yields an effectivesystem clock frequency of 4 MHz. To ensure that theprogrammer does not clock too fast, it is recommendedthat a 4 MHz clock be provided by the programmer.

Note: The Programming Executive (PE) can belocated within the following folder withinyour installation of MPLAB® IDE:Microchip\MPLAB IDE\REAL ICE andthen select the Hex PE file:RIPE_01c_xxxxxx.hex.

PGECx

PGEDx

1 2 3 11 13 15 161412

LSb14 13 12 11

4 5 6

MSb 123... 45

P2

P3

P1

P1BP1A

PGECx

PGEDx

1 2 3 11 13 15 161412

LSb14 13 12 11

4 5 6

MSb 123... 45

P2

P3

P1

P1BP1A

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5.1.3 TIME-OUTSThe programming executive uses no Watchdog Timeror time-out for transmitting responses to theprogrammer. If the programmer does not follow the flowcontrol mechanism using PGECx, as described inSection 5.1.1 “Communication Interface and Proto-col”, it is possible that the programming executive willbehave unexpectedly while trying to send a