pic16lf1566/1567 data sheet - microchip...

PIC16LF1566/156728/40/44-Pin Flash, 8-Bit Microcontrollers with XLP Technology

DescriptionThe PIC16LF1566/1567 microcontrollers deliver unique on-chip features for the design of mTouch® solutions andgeneral purpose applications in 28/40/44-pin count packages. Two 10-bit high-speed ADCs with automated hardwareCVD modules connect up to 34 analog channels to achieve a total sampling rate of 600k samples per second. Thisfamily provides mutual capacitance output drivers on all analog channels, two PWMs, two MSSP modules with low inputvoltage options and one EUSART, which makes this family an excellent solution to implement low-power and noise-robust capacitive sensing and other front-end sampling applications with minimal software overhead.

Core Features• C Compiler Optimized RISC Architecture• Only 49 Instructions• Operating Speed:

- 0-32 MHz clock input- 125 ns minimum instruction cycle

• Interrupt Capability• 16-Level Deep Hardware Stack• Up to Three 8-bit Timers• One 16-bit Timer• Power-on Reset (POR)• Power-up Timer (PWRT)• Low-Power Brown-Out Reset (LPBOR)• Programmable Watchdog Timer (WDT) up to 256s• Programmable Code Protection

Memory• Up to 8k Words Flash Program Memory• 1024 Bytes Data SRAM Memory• Direct, Indirect and Relative Addressing modes

Operating Characteristics• Operating Voltage Range:

- 1.8V to 3.6V• Temperature Range:

- Industrial: -40°C to 85°C- Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features• Sleep mode: 50 nA @ 1.8V, typical• Watchdog Timer: 500 nA @ 1.8V, typical• Operating Current:

- 8 µA @ 32 kHz, 1.8V, typical- 32 µA/MHz @ 1.8V, typical

Digital Peripherals• PWM: Two 10-bit Pulse-Width Modulators

- Output on up to five pins per PWM at the same time

• Dual Master Synchronous Serial Port (MSSP) with SPI and I2C:- 7-bit address masking- SMBus/PMBus™ compatibility- Configurable low input voltage threshold for I2C

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART):

- RS-232, R-485, and LIN compatible- Auto-Baud Detect- Auto-wake-up on start

• Up to 35 I/O Pins and One Input Pin:- Individually programmable pull-ups- Interrupt-on-change with edge-select

Intelligent Analog Peripherals• Dual 10-Bit Analog-to-Digital Converter (ADC):

- Up to 35 external channels- Conversion available during Sleep- Temperature indicator- Simultaneous sampling on two ADCs- Connect multiple channels together for

sampling- External conversion trigger- Fixed Voltage Reference as a channel- External pin as positive ADC voltage reference- Combined 600k samples per second

• Hardware Capacitive Voltage Divider (CVD)- Double-sample conversions- Two sets of result registers- 7-bit precharge timer- 7-bit acquisition timer- Two guard ring output drives- Mutual capacitance Tx output on any analog

channel- 30 pF adjustable sample and hold capacitor

• Internal Voltage Reference ModuleClocking Structure• 16 MHz Internal Oscillator Block:

- ±1% at calibration- Selectable frequency range from 0 to 32 MHz

• 31 kHz Low-Power Internal Oscillator• External Oscillator Block with:

- Two external clock modes up to 32 MHz• Oscillator Start-up Timer (OST)Programming/Debug Features• In-Circuit Debug Integrated On-Chip• Emulation Header for Advanced Debug:

- Provides trace, background debug and up to 32 hardware break points

• In-Circuit Serial Programming™ (ICSP™) via Two Pin

2015-2018 Microchip Technology Inc. Preliminary DS40001817C-page 1

PIC16LF1566/1567

TABLE 1: PIC16LF1566/1567 FAMILY TYPES

Dev

ice

Dat

a Sh

eet I

ndex

Prog

ram

Mem

ory

Flas

h(w

ords

)

Dat

a EE

PRO

M (b

ytes

)

SRA

M (b

ytes

)

I/Os

(1)

10-b

it A

DC

s(4)

Ana

log

Cha

nnel

s(2)

(3)

CVD

RX

Cha

nnel

s

CVD

TX

Cha

nnel

s(5)

Tim

ers

8/16

-bit

EUSA

RT

MSS

P

PWM

Deb

ug

PIC12LF1552 (A) 2048 0 256 6 1 4 1 1 / 0 - 1 - -PIC16LF1554 (B) 4096 0 256 12 2 10 2 2 / 1 1 1 2 I

PIC16LF1559 (B) 8192 0 512 18 2 16 2 2 / 1 1 1 2 I

PIC16LF1566 (C) 8192 0 1024 25 2 23 23 3 / 1 1 2 2 I

PIC16LF1567 (C) 8192 0 1024 36 2 34 34 3 / 1 1 2 2 I

Note 1: The MCLR pin is input-only.2: Analog channels are split between the available ADCs.3: Maximum usable analog channels assuming one pin must be assigned to output.4: If VDD > 2.4V, ADC may be overclocked 4x (TAD = 0.25 µs).5: Includes functionality of ADxGRDA output pin.

Data Sheet Index (Unshaded devices are described in this document.)A: DS40001674 PIC12LF1552 Data Sheet, 8-Pin Flash, 8-Bit MicrocontrollersB: DS40001761 PIC16LF1554/1559 Data Sheet, 20-Pin Flash, 8-Bit Microcontrollers with XLP TechnologyC: DS40001817 PIC16LF1566/1567 Data Sheet 28/40/44-Pin Flash, 8-Bit Microcontrollers with XLP

Technology

Note: For other small form-factor package availability and marking information, please visithttp://www.microchip.com/packaging or contact your local sales office.

DS40001817C-page 2 Preliminary 2015-2018 Microchip Technology Inc.

http://ww1.microchip.com/downloads/en/DeviceDoc/40001674F.pdfhttp://ww1.microchip.com/downloads/en/DeviceDoc/40001761E.pdfhttp://ww1.microchip.com/downloads/en/DeviceDoc/40001761E.pdfhttp://ww1.microchip.com/downloads/en/DeviceDoc/40001674E.pdfhttp://ww1.microchip.com/downloads/en/DeviceDoc/40001761C.pdf

PIC16LF1566/1567

PIN DIAGRAMS

FIGURE 1: 28-PIN SPDIP, SOIC, SSOP DIAGRAM FOR PIC16LF1566

FIGURE 2: 28-PIN UQFN DIAGRAM FOR PIC16LF1566

Note: See Table 2 for the pin allocation tables.PI

C16

LF15

66

12345678910

VPP/MCLR/RE3RA0RA1RA2RA3RA4RA5

RB6/ICSPCLKRB5RB4RB3RB2RB1RB0VDDVSS

11121314 15

1617181920

2827262524232221VSS

RA7RA6RC0RC1RC2RC3

RC5RC4

RC7RC6

RB7/ICSPDAT

Note: See Table 2 or the pin allocation tables.

23

6

1

18192021

1571617

RC

0

54

RB

7/IC

SPD

ATR

B6/

ICSP

CLK

RB

5R

B4

RB0VDDVSSRC7

RC

6R

C5

RC

4

RE3

/MC

LR/V

PPR

A0

RA

1

RA2RA3RA4RA5VSSRA7RA6

RC

1R

C2

RC

3

9 10 138 141211

27 26 2328 222425

RB3RB2RB1

PIC16LF1566


PIC16LF1566/1567

FIGURE 3: 40-PIN PDIP DIAGRAM FOR PIC16LF1567

FIGURE 4: 40-PIN UQFN DIAGRAM FOR PIC16LF1567

Note: See Table 3 for the pin allocation tables.

PIC

16LF

1567

2

3

4

5

6

789

10

VPP/MCLR/RE3RA0RA1RA2RA3RA4RA5RE0RE1RE2

RB6/ICSPCLKRB5RB4

RB0VDDVSS

RD2

11

12

13

14

151617181920

40

39

38

37

36

35

3433323130

29

28

27

262524232221

VDDVSSRA7RA6RC0RC1RC2RC3RD0RD1

RC5RC4RD3

RD4RC7RC6

RD7RD6RD5

RB7/ICSPDAT1

RB3RB2RB1

Note: See Table 3 for the pin allocation tables.

10

11

2

3456

1

18 19 20

2122

12 13 14 1538

87

40 39

16 17

2930

313233

232425262728

36 3435

9

37

RA

1R

A0

VPP/

MC

LR/R

E3RB

3

ICSP

DAT

/RB

7IC

SPC

LK/R

B6

RB

5R

B4

RC

6R

C5

RC

4R

D3

RD

2R

D1

RD

0R

C3

RC

2R

C1

RC0RA6RA7VSSVDDRE2RE1RE0RA5RA4

RC7RD4RD5RD6RD7VSSVDDRB0RB1RB2

PIC16LF1567

RA

3R

A2


PIC16LF1566/1567

FIGURE 5: 44-PIN TQFP DIAGRAM FOR PIC16LF1567

Note: See Table 3 for the pin allocation table.

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

37

54

PIC16LF1567

RC

6R

C5

RC

4R

D3

RD

2R

D1

RD

0R

C3

RC

2R

C1

RC0

RA

1R

A0

VPP/

MC

LR/R

E3

RB3

ICSP

DAT

/RB

7IC

SPC

LK/R

B6

RB

5R

B4

NC

RA

3R

A2

RC7RD4RD5RD6RD7VSSVDDRB0RB1RB2

RA6RA7VSS

NC

VDDRE2RE1RE0RA5RA4

NC

NC


PIC16LF1566/1567

PIN ALLOCATION TABLES

TABLE 2: 28-PIN ALLOCATION TABLE (PIC16LF1566)

I/O

28-P

in S

PDIP

/SO

IC/S

SOP

28-P

in U

QFN

Ana

log

Cha

nnel

AD

C a

nd C

VD

Tim

ers

PWM

EUSA

RT

MSS

P

Inte

rrup

t

Pull-

up

Bas

ic

RA0 2 27 AN20 — — PWM10 — SS1(1) — — —

RA1 3 28 AN10 — — PWM11 — SS2 — — —

RA2 4 1 AN0 VREF- — PWM12 — — — — —

RA3 5 2 AN1 VREF+ — PWM13 — — — — —

RA4 6 3 AN2 — T0CKI — — — — — —

RA5 7 4 AN21 — — — — SS1(1) — — —

RA6 10 7 AN22 ADTRIG — — — — — — CLKOUT

RA7 9 6 AN11 — — — — — — — CLKIN

RB0 21 18 AN16 — — PWM20 — — INTIOC

Y —

RB1 22 19 AN27 — — PWM21 — — IOC Y —

RB2 23 20 AN17 — — PWM22 — — IOC Y —

RB3 24 21 AN28 — — PWM23 — — IOC Y —

RB4 25 22 AN18 AD1GRDA(1)AD2GRDA(1)

— — — — IOC Y —

RB5 26 23 AN29 AD1GRDA(1)AD2GRDA(1)

T1G — — — IOC Y —

RB6 27 24 AN19 AD1GRDB(1)AD2GRDB(1)

— — — — IOC Y ICSPCLKICDCLK

RB7 28 25 AN40 AD1GRDB(1)AD2GRDB(1)

— — — — IOC Y ICSPDATICDDAT

RC0 11 8 AN12 — T1CKI — — SDO2 — — —

RC1 12 9 AN23 — — PWM2 — SCL2SCK2

— — —

RC2 13 10 AN13 — — PWM1 — SDA2SDI2

— — —

RC3 14 11 AN24 — — — — SCL1SCK1

— — —

RC4 15 12 AN14 — — — — SDA1SDI1

— — —

RC5 16 13 AN25 — — — — SDO1I2CLVL

— — —


PIC16LF1566/1567

RC6 17 14 AN15 — — — TXCK

— — — —

RC7 18 15 AN26 — — — RXDT

— — — —

RE3 1 26 — — — — — — — Y MCLRVPP

VDD 20 17 — — — — — — — — VDD

VSS 8 5 — — — — — — — — VSS

VSS 19 16 — — — — — — — — VSS

Note 1: Pin functions can be assigned to one of two pin locations via software.

TABLE 2: 28-PIN ALLOCATION TABLE (PIC16LF1566) (CONTINUED)

I/O

28-P

in S

PDIP

/SO

IC/S

SOP

28-P

in U

QFN

Ana

log

Cha

nnel

AD

C a

nd C

VD

Tim

ers

PWM

EUSA

RT

MSS

P

Inte

rrup

t

Pull-

up

Bas

ic


PIC16LF1566/1567

TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16LF1567)I/O

40-P

in P

DIP

40-P

in U

QFN

44-P

in T

QFP

Ana

log

Cha

nnel

AD

C a

nd C

VD

Tim

ers

PWM

EUSA

RT

MSS

P

Inte

rrup

t

Pull-

Up

Bas

ic

RA0 2 17 19 AN20 — — PWM10 — SS1(1) — — —

RA1 3 18 20 AN10 — — PWM11 — SS2 — — —RA2 4 19 21 AN0 VREF- — PWM12 — — — — —RA3 5 20 22 AN1 VREF+ PWM13 — — — — —RA4 6 21 23 AN2 — T0CKI — — — — — —RA5 7 22 24 AN21 — — — — SS1(1) — — —

RA6 14 29 31 AN22 ADTRIG — — — — — — CLKOUTRA7 13 28 30 AN11 — — — — — — — CLKINRB0 33 8 8 AN16 — — PWM20 — — INT

IOCY —

RB1 34 9 9 AN27 — — PWM21 — — IOC Y —RB2 35 10 10 AN17 — — PWM22 — — IOC Y —RB3 36 11 11 AN28 — — PWM23 — — IOC Y —RB4 37 12 14 AN18 AD1GRDA(1)

AD2GRDA(1)— — — — IOC Y —

RB5 38 13 15 AN29 AD1GRDA(1)AD2GRDA(1)

T1G — — — IOC Y —

RB6 39 14 16 AN19 AD1GRDB(1)AD2GRDB(1)

— — — — IOC Y ICSPCLKICDCLK

RB7 40 15 17 AN40 AD1GRDB(1)AD2GRDB(1)

— — — — IOC Y ICSPDATICDDAT

RC0 15 30 32 AN12 — T1CKI — — SDO2 — — —RC1 16 31 35 AN23 — — PWM2 — SCL2

SCK2— — —

RC2 17 32 36 AN13 — — PWM1 — SDA2SDI2

— — —

RC3 18 33 37 AN24 — — — — SCL1SCK1

— — —

RC4 23 38 42 AN14 — — — — SDA1SDI1

— — —

RC5 24 39 43 AN25 — — — — SDO1I2CLVL

— — —

RC6 25 40 44 AN15 — — — TXCK

— — — —

RC7 26 1 1 AN26 — — — RXDT

— — — —

RD0 19 34 38 AN42 — — — — — — — —


PIC16LF1566/1567

RD1 20 35 39 AN32 — — — — — — — —RD2 21 36 40 AN43 — — — — — — — —RD3 22 37 41 AN33 — — — — — — — —RD4 27 2 2 AN34 — — — — — — — —RD5 28 3 3 AN44 — — — — — — — —RD6 29 4 4 AN35 — — — — — — — —RD7 30 5 5 AN45 — — — — — — — —RE0 8 23 25 AN30 — — — — — — — —RE1 9 24 26 AN41 — — — — — — — —RE2 10 25 27 AN31 — — — — — — — —RE3 1 16 18 — — — — — — — Y MCLR

VPP

VDD 11 7 7 — — — — — — — — VDDVDD — 26 28 — — — — — — — — VDDVSS 12 6 6 — — — — — — — — VSSVSS 31 27 29 — — — — — — — — VSSNote 1: Pin functions can be assigned to one of two pin locations via software.

TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16LF1567) (CONTINUED)

I/O

40-P

in P

DIP

40-P

in U

QFN

44-P

in T

QFP

Ana

log

Cha

nnel

AD

C a

nd C

VD

Tim

ers

PWM

EUSA

RT

MSS

P

Inte

rrup

t

Pull-

Up

Bas

ic


PIC16LF1566/1567

Table of Contents1.0 Device Overview ........................................................................................................................................................................ 112.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 203.0 Memory Organization ................................................................................................................................................................. 224.0 Device Configuration .................................................................................................................................................................. 585.0 Oscillator Module........................................................................................................................................................................ 636.0 Resets ........................................................................................................................................................................................ 717.0 Interrupts .................................................................................................................................................................................... 798.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 899.0 Watchdog Timer (WDT) ............................................................................................................................................................. 9110.0 Flash Program Memory Control ................................................................................................................................................. 9511.0 I/O Ports ................................................................................................................................................................................... 11212.0 Interrupt-on-Change ................................................................................................................................................................. 13113.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 13514.0 Temperature Indicator Module ................................................................................................................................................. 13715.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 13916.0 Hardware Capacitive Voltage Divider (CVD) Module ............................................................................................................... 15317.0 Timer0 Module ......................................................................................................................................................................... 17918.0 Timer1 Module with Gate Control............................................................................................................................................. 18219.0 Timer2/4 Modules..................................................................................................................................................................... 19320.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module .............................................................................................. 19721.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 25522.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................. 28223.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 28924.0 Instruction Set Summary .......................................................................................................................................................... 29125.0 Electrical Specifications............................................................................................................................................................ 30526.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 32827.0 Development Support............................................................................................................................................................... 32928.0 Packaging Information.............................................................................................................................................................. 333Appendix A: Data Sheet Revision History.......................................................................................................................................... 352The Microchip Website....................................................................................................................................................................... 353Customer Change Notification Service .............................................................................................................................................. 353Customer Support .............................................................................................................................................................................. 353Product Identification System............................................................................................................................................................. 354

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PIC16LF1566/1567

1.0 DEVICE OVERVIEWThe PIC16LF1566/1567 devices are described within thisdata sheet. The block diagram of these devices is shownin Figure 1-1, the available peripherals are shown inTable 1-1 and the pinout descriptions are shown inTable 1-2 and Table 1-3. TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC

16LF

1566

PIC

16LF

1567

Analog-to-Digital Converter (ADC)ADC1 ● ●ADC2 ● ●

Hardware Capacitive Voltage Divider (CVD) ● ●Enhanced UniversalSynchronous/Asynchronous Receiver/Transmitter (EUSART)

● ●

Fixed Voltage Reference (FVR) ● ●Temperature Indicator ● ●Master Synchronous Serial Ports

MSSP1 ● ●MSSP2 ● ●

PWM ModulesPWM1 ● ●PWM2 ● ●

TimersTimer0 ● ●Timer1 ● ●Timer2 ● ●Timer4 ● ●


PIC16LF1566/1567

FIGURE 1-1: PIC16LF1566/1567 BLOCK DIAGRAM(1,2)

Note 1: See applicable chapters for more information on peripherals.2: See Table 1-1 for peripherals available on specific devices.3: PIC16LF1567 only.

(See Figure 2-1)

Program Flash Memory

RAM

PORTA

PORTB

PORTC

CPU

TMR2 TMR1 TMR0 Temp Indicator

ADC110-bit

ADC210-bit

FVR

PWM2 PWM1 EUSART

MCLR

OSC1/CLKIN

OSC2/CLKOUT Timing Generation

INTRCOscillator

Hardware CVD

MSSP2 TMR4MSSP1

PORTD(3)

PORTE


PIC16LF1566/1567

TABLE 1-2: PIC16LF1566 PINOUT DESCRIPTION

Name Function Input TypeOutput Type Description

RA0/AN20/PWM10/SS1(1)

RA0 TTL CMOS General Purpose I/O.

AN20 AN — ADC Channel Input for ADC2.

PWM10 — CMOS PWM Output for PWM1.

SS1 ST — Slave Select Input for MSSP1.

RA1/AN10/PWM11/SS2





RA2/AN0/PWM12


AN0 AN — ADC Channel Input for both ADC1 and ADC2.


VREF- AN — ADC Negative Voltage Reference Input.

RA3/AN1/ VREF+/PWM13



VREF+ AN — ADC Positive Voltage Reference Input.


RA4/AN2/T0CKI



T0CKI ST — Timer0 Clock Input.

RA5/AN21/SS1(1)RA5 TTL CMOS General Purpose I/O.



RA6/AN22/ADTRIG/CLKOUT



ADTRIG ST — ADC Conversion Trigger Input.

CLKOUT — CMOS FOSC/4 Output.

RA7/AN11/CLKIN



CLKIN CMOS — External Clock Input (EC mode).

RB0/AN16/PWM20/INT

RB0 TTL CMOS General Purpose I/O with IOC and WPU.



INT ST — External Interrupt.

RB1/AN27/PWM21




RB2/AN17/PWM22





PIC16LF1566/1567

RB3/AN28/PWM23




RB4/AN18/AD1GRDA(1)/AD2GRDA(1)



AD1GRDA — CMOS ADC1 Guard Ring Output A.


RB5/AN29/AD1GRDA(1)/AD2GRDA(1)/T1G





T1G ST — Timer1 Gate Input.

RB6/AN19/AD1GRDB(1)/AD2GRDB(1)/ICSPCLK/ICDCLK



AD1GRDB — CMOS ADC1 Guard Ring Output B.


ICSPCLK ST CMOS ICSP™ Programming Clock.

ICDCLK ST CMOS In-Circuit Debug Clock.

RB7/AN40/AD1GRDB(1)/AD2GRDB(1)/ICSPDAT/ICDDAT





ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST CMOS In-Circuit Debug Data.

RC0/AN12/T1CKI/SDO2

RC0 TTL CMOS General Purpose I/O.



SDO2 — CMOS SPI Data Output for MSSP2.

RC1/AN23/PWM2/SCL2/SCK2




SCL2 I2C OD I2C Clock for MSSP2.

SCK2 ST CMOS SPI Clock for MSSP2.

RC2/AN13/PWM1/SDA2/SDI2




SDA2 I2C OD I2C Data for MSSP2.

SDI2 CMOS — SPI Data Input for MSSP2.

RC3/AN24/SCL1/SCK1





TABLE 1-2: PIC16LF1566 PINOUT DESCRIPTION (CONTINUED)



PIC16LF1566/1567

RC4/AN14/SDA1/SDI1





RC5/AN25/SDO1/I2CLVL




I2CLVL AN — I2C Voltage Level Input.

RC6/AN15/TX/CK

RC6 TTL — General Purpose I/O.


TX — CMOS EUSART Asynchronous Transmit.

CK ST CMOS EUSART Synchronous Clock.

RC7/AN26/RX/DT



RX ST — EUSART Asynchronous Input.

DT ST CMOS EUSART Synchronous Data.

RE3/VPP/MCLR

RE3 TTL — General Purpose Input with WPU.

VPP HV — Programming Voltage.

MCLR ST — Master Clear with Internal Pull-up.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C levelsHV = High Voltage XTAL = Crystal

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

TABLE 1-2: PIC16LF1566 PINOUT DESCRIPTION (CONTINUED)



PIC16LF1566/1567

TABLE 1-3: PIC16LF1567 PINOUT DESCRIPTIONName Function Input Type Output Type Description

RA0/AN20/PWM10/SS1(1)





RA1/AN10/PWM11/SS2





RA2/AN0/PWM12



VREF- AN — ADC Negative Voltage Reference Input.


RA3/AN1/VREF+/PWM13



VREF+ AN — ADC Positive Voltage Reference Input.


RA4/AN2/T0CKI




RA5/AN21/SS1(1)RA5 TTL CMOS General Purpose I/O.



RA6/AN22/ADTRIG/CLKOUT



ADTRIG ST — ADC Conversion Trigger Input.

CLKOUT — CMOS FOSC/4 Output.

RA7/AN11/CLKIN



CLKIN CMOS — External Clock Input (EC mode).

RB0/AN16/PWM20/INT




INT ST — External Interrupt.

RB1/AN27/PWM21




RB2/AN17/PWM22




RB3/AN28/PWM23





PIC16LF1566/1567

RB4/AN18/AD1GRDA(1)/AD2GRDA(1)





RB5/AN29/AD1GRDA(1)/AD2GRDA(1)/T1G





T1G ST — Timer1 Gate Input.

RB6/AN19/AD1GRDB(1)/AD2GRDB(1)/ICSPCLK/ICDCLK





ICSPCLK ST CMOS ICSP™ Programming Clock.

ICDCLK ST CMOS In-Circuit Debug Clock.

RB7/AN40/AD1GRDB(1)/AD2GRDB(1)/ICSPDAT/ICDDAT





ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST CMOS In-Circuit Debug Data.

RC0/AN12/T1CKI/SDO2





RC1/AN23/PWM2/SCL2/SCK2






RC2/AN13/PWM1/SDA2/SDI2






RC3/AN24/SCL1/SCK1





RC4/AN14/SDA1/SDI1





TABLE 1-3: PIC16LF1567 PINOUT DESCRIPTION (CONTINUED)Name Function Input Type Output Type Description


PIC16LF1566/1567

RC5/AN25/SDO1/I2CLVL




I2CLVL AN — I2C Voltage Level Input.

RC6/AN15/TX/CK



TX — CMOS EUSART Asynchronous Transmit.

CK ST CMOS EUSART Synchronous Clock.

RC7/AN26/RX/DT



RX ST — EUSART Asynchronous Input.

DT ST CMOS EUSART Synchronous Data.

RD0/AN42RD0 TTL CMOS General Purpose I/O.
















RE0/AN30RE0 TTL CMOS General Purpose I/O.






RE3/VPP/MCLR

RE3 TTL — General Purpose Input with WPU.

VPP HV — Programming Voltage.

MCLR ST — Master Clear with Internal Pull-up.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C levels HV = High Voltage XTAL = Crystal

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

TABLE 1-3: PIC16LF1567 PINOUT DESCRIPTION (CONTINUED)Name Function Input Type Output Type Description


PIC16LF1566/1567

2.0 ENHANCED MID-RANGE CPUThis family of devices contain an enhanced mid-range8-bit CPU core. The CPU has 49 instructions. Interruptcapability includes automatic context saving. Thehardware stack is 16 levels deep and has Overflow andUnderflow Reset capability. Direct, Indirect, andRelative Addressing modes are available. Two FileSelect Registers (FSRs) provide the ability to readprogram and data memory.

• Automatic Interrupt Context Saving• 16-level Stack with Overflow and Underflow• File Select Registers• Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

1515

15

15

8

8

8

1214

75

3

Program Counter

MUX

Addr MUX

16-Level Stack(15-bit)

Program MemoryRead (PMR)

Instruction Reg

Configuration

FSR0 Reg

FSR1 Reg

BSR Reg

STATUS Reg

RAM

W Reg

Power-upTimer

Power-onReset

WatchdogTimer

Brown-outReset

InstructionDecode and

Control

TimingGeneration

InternalOscillator

Block

ALU

FlashProgramMemoryM

UX

Data Bus

ProgramBus

Direct AddrIndirect

Addr

RAM Addr

CLKIN

CLKOUT

VDD VSS

Rev. 10-000055A7/30/2013

1212


PIC16LF1566/1567

2.1 Automatic Interrupt Context

SavingDuring interrupts, certain registers are automaticallysaved in shadow registers and restored when returningfrom the interrupt. This saves stack space and usercode. See Section 7.5 “Automatic Context Saving”,for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory 15 bitswide and 16 words deep. A Stack Overflow orUnderflow will set the appropriate bit (STKOVF orSTKUNF) in the PCON register, and if enabled, willcause a software Reset. See Section 3.4 “Stack” formore details.

2.3 File Select RegistersThere are two 16-bit File Select Registers (FSR). FSRscan access all file registers and program memory,which allows one data pointer for all memory. When anFSR points to program memory, there is one additionalinstruction cycle in instructions using INDF to allow thedata to be fetched. General purpose memory can nowalso be addressed linearly, providing the ability toaccess contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. SeeSection 3.5 “Indirect Addressing” for more details.

2.4 Instruction SetThere are 49 instructions for the enhanced mid-rangeCPU to support the features of the CPU. SeeSection 24.0 “Instruction Set Summary” for moredetails.


PIC16LF1566/1567

3.0 MEMORY ORGANIZATIONThese devices contain the following types of memory:

• Program Memory- Configuration Words- Device ID- User ID- Flash Program Memory

• Data Memory- Core Registers- Special Function Registers- General Purpose RAM- Common RAM

The following features are associated with access andcontrol of program memory and data memory:

• PCL and PCLATH• Stack• Indirect Addressing

3.1 Program Memory OrganizationThe enhanced mid-range core has a 15-bit ProgramCounter capable of addressing a 32K x 14 programmemory space. Table 3-1 shows the memory sizesimplemented. Accessing a location above theseboundaries will cause a wrap-around within theimplemented memory space. The Reset vector is at0000h and the Interrupt vector is at 0004h (seeFigure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words)Last Program Memory

AddressHigh-Endurance Flash

Memory Address Range (1)

PIC16LF1566 8,192 1FFFh 1F80h-1FFFhPIC16LF1567 8,192 1FFFh 1F80h-1FFFh

Note 1: High-endurance Flash applies to low byte of each address in the range.


PIC16LF1566/1567

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16LF1566/1567

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants inprogram memory. The first method is to use tables ofRETLW instructions. The second method is to set anFSR to point to the program memory.

3.1.1.1 RETLW InstructionThe RETLW instruction can be used to provide accessto tables of constants. The recommended way to createsuch a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table verysimple to implement. If your code must remain portablewith previous generations of microcontrollers, then theBRW instruction is not available so the older table readmethod must be used.

3.1.1.2 Indirect Read with FSRThe program memory can be accessed as data bysetting bit 7 of the FSRxH register and reading thematching INDFx register. The MOVIW instruction willplace the lower eight bits of the addressed word in theW register. Writes to the program memory cannot beperformed via the INDF registers. Instructions thataccess the program memory via the FSR require oneextra instruction cycle to complete. Example 3-2demonstrates accessing the program memory via anFSR.

The HIGH operator will set bit 7 if a label points to alocation in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR

CALL, CALLW RETURN, RETLWInterrupt, RETFIE

On-chipProgramMemory

Stack Level 0

Stack Level 15

Stack Level 1

Reset Vector

PC

Interrupt Vector

Page 1

Page 0

0000h

0004h0005h

07FFh0800h

0FFFh1000h

7FFFh

Rollover to Page 0

Rollover to Page 3

Page 2

Page 3

17FFh1800h

1FFFh2000h

15

Rev. 10-000040B7/30/2013

constantsBRW ;Add Index in W to

;program counter to;select data

RETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function;… LOTS OF CODE…MOVLW DATA_INDEXcall constants;… THE CONSTANT IS IN W

constantsDW DATA0 ; First constantDW DATA1 ; Second constantDW DATA2DW DATA3

my_function;… LOTS OF CODE…MOVLW DATA_INDEXADDLW LOW constantsMOVWF FSR1LMOVLW HIGH constants; MSb is set

automaticallyMOVWF FSR1HBTFSC STATUS,C ; carry from ADDLW?INCF FSR1H,f ; yesMOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W


PIC16LF1566/1567

3.2 Data Memory OrganizationThe data memory is partitioned in 32 memory bankswith 128 bytes in a bank. Each bank consists of (seeFigure 3-2):

• 12 Core Registers• 20 Special Function Registers (SFR)• Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM

The active bank is selected by writing the bank numberinto the Bank Select Register (BSR). Unimplementedmemory will read as ‘0’. All data memory can beaccessed either directly (via instructions that use thefile registers) or indirectly (via the two File SelectRegisters - FSR). See Section 3.5 “IndirectAddressing” for more information.Data memory uses a 12-bit address. The upper five bitsof the address define the Bank Address and the lowerseven bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERSThe core registers contain the registers that directlyaffect the basic operation. The core registers occupythe first 12 addresses of every data memory bank(addresses x00h/x08h through x0Bh/x8Bh). Theseregisters are listed below in Table 3-2. For detailedinformation, see Table 3-10.

3.2.1.1 STATUS RegisterThe STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU• the Reset status

The STATUS register can be the destination for anyinstruction, like any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable. Therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras ‘000u u1uu’ (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect any Status bits. For other instructions notaffecting any Status bits, refer to Section 24.0“Instruction Set Summary”).

TABLE 3-2: CORE REGISTERS

Note: The C and DC bits operate as Borrow andDigit Borrow Out bits, respectively, in sub-traction.

Addresses BANKxx00h or x80h INDF0x01h or x81h INDF1x02h or x82h PCLx03h or x83h STATUSx04h or x84h FSR0Lx05h or x85h FSR0Hx06h or x86h FSR1Lx07h or x87h FSR1Hx08h or x88h BSRx09h or x89h WREGx0Ah or x8Ah PCLATHx0Bh or x8Bh INTCON


PIC16LF1566/1567

3.2.2 SPECIAL FUNCTION REGISTERThe Special Function Registers are registers used bythe application to control the desired operation ofperipheral functions in the device. The Special FunctionRegisters occupy the 20 bytes after the core registers ofevery data memory bank (addresses x0Ch/x8Chthrough x1Fh/x9Fh). The registers associated with theoperation of the peripherals are described in theappropriate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAMThere are up to 80 bytes of GPR in each data memorybank. The Special Function Registers occupy the 20bytes after the core registers of every data memorybank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPRThe general purpose RAM can be accessed in anon-banked method via the FSRs. This can simplifyaccess to large memory structures. See Section 3.5.2“Linear Data Memory” for more information.

3.2.4 COMMON RAMThere are 16 bytes of common RAM accessible from allbanks.

3.2.5 DEVICE MEMORY MAPSThe memory maps for PIC16LF1554/1559 are asshown in Table 3-3 through Table 3-7.

REGISTER 3-1: STATUS: STATUS REGISTERU-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — — TO PD Z DC(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurred

bit 3 PD: Power-Down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the fourth low-order bit of the result occurred0 = No carry-out from the fourth low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.


PIC16LF1566/1567

FIGURE 3-2: BANKED MEMORY

PARTITIONING

Memory Region7-bit Bank Offset

00h

0Bh0Ch

1Fh20h

6Fh

7Fh

70h

Core Registers(12 bytes)

Special Function Registers(20 bytes maximum)

General Purpose RAM(80 bytes maximum)

Common RAM(16 bytes)

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TABANK 6 BANK 7

0000000000000 30Ch — 38Ch —0 30Dh — 38Dh —0 30Eh — 38Eh —0 30Fh — 38Fh —0 310h — 390h —0 311h — 391h —0 312h — 392h —0 313h — 393h —0 314h — 394h IOCBP0 315h — 395h IOCBN0 316h — 396h IOCBF0 317h — 397h —0 318h — 398h —0 319h — 399h —0 31Ah — 39Ah —0 31Bh — 39Bh —0 31Ch — 39Ch —0 31Dh — 39Dh —0 31Eh — 39Eh —0 31Fh — 39Fh —0 320h

GeneralPurposeRegister80 Bytes

3A0h


0 36Fh 3EFh0 370h

Accesses70h – 7Fh

3F0hAccesses70h – 7Fh

0 37Fh 3FFh

LeN

BLE 3-3: PIC16LF1566 MEMORY MAP, BANKS 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

00h

CPU Core Register, see Table 3-2 for specifics

01h02h03h04h05h06h07h08h09h0Ah0Bh0Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch —0Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh —0Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh —0Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh —10h PORTE 090h — 110h — 190h — 210h WPUE 290h —11h PIR1 091h PIE1 111h — 191h PMADRL 211h SSP1BUF 291h —12h PIR2 092h PIE2 112h — 192h PMADRH 212h SSP1ADD 292h —13h — 093h — 113h — 193h PMDATL 213h SSP1MSK 293h —14h — 094h — 114h — 194h PMDATH 214h SSP1STAT 294h —15h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSP1CON1 295h —16h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h —17h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSP1CON3 297h —18h T1CON 098h — 118h — 198h — 218h SSPLVL 298h —19h T1GCON 099h OSCCON 119h — 199h RCREG 219h SSP2BUF 299h —1Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah SSP2ADD 29Ah —1Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRGL 21Bh SSP2MSK 29Bh —1Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch SSP2STAT 29Ch —1Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh SSP2CON1 29Dh —1Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh SSP2CON2 29Eh —1Fh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh SSP2CON3 29Fh —20h


0A0h


120h


1A0h


220h


2A0h


6Fh 0EFh 16Fh 1EFh 26Fh 2EFh70h 0F0h

Accesses70h – 7Fh

170hAccesses70h – 7Fh




7Fh 0FFh 17Fh 1FFh 27Fh 2FFh

gend: = Unimplemented data memory locations, read as ‘0’.ote 1:These ADC registers are the same as the registers in Bank 14.

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BANK 6 BANK 7

30Ch — 38Ch —30Dh — 38Dh —30Eh — 38Eh —30Fh — 38Fh —310h — 390h —311h — 391h —312h — 392h —313h — 393h —314h — 394h IOCBP315h — 395h IOCBN316h — 396h IOCBF317h — 397h —318h — 398h —319h — 399h —31Ah — 39Ah —31Bh — 39Bh —31Ch — 39Ch —31Dh — 39Dh —31Eh — 39Eh —31Fh — 39Fh —320h


3A0h


36Fh 3EFh370h

Accesses70h – 7Fh


37Fh 3FFh

TABLE 3-4: PIC16LF1567 MEMORY MAP, BANKS 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

000h


001h002h003h004h005h006h007h008h009h00Ah00Bh00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch 28Ch —00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh —00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh —00Fh PORTD 08Fh TRISD 10Fh LATD 18Fh ANSELD 20Fh — 28Fh —010h PORTE 090h TRISE 110h LATE 190h ANSELE 210h WPUE 290h —011h PIR1 091h PIE1 111h — 191h PMADRL 211h SSP1BUF 291h —012h PIR2 092h PIE2 112h — 192h PMADRH 212h SSP1ADD 292h —013h — 093h — 113h — 193h PMDATL 213h SSP1MSK 293h —014h — 094h — 114h — 194h PMDATH 214h SSP1STAT 294h —015h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSP1CON1 295h —016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h —017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSP1CON3 297h —018h T1CON 098h — 118h — 198h — 218h SSPLVL 298h —019h T1GCON 099h OSCCON 119h — 199h RCREG 219h SSP2BUF 299h —01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah SSP2ADD 29Ah —01Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRGL 21Bh SSP2MSK 29Bh —01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch SSP2STAT 29Ch —01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh SSP2CON1 29Dh —01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh SSP2CON2 29Eh —01Fh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh SSP2CON3 29Fh —020h


0A0h


120h


1A0h


220h


2A0h


06Fh 0EFh 16Fh 1EFh 26Fh 2EFh070h 0F0h

Accesses70h – 7Fh





07Fh 0FFh 17Fh 1FFh 27Fh 2FFh

Legend: = Unimplemented data memory locations, read as ‘0’.Note 1:These ADC registers are the same as the registers in Bank 14.

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TABANK 14 BANK 15

40404040404040404040404040 — 78Ch —40 — 78Dh —40 — 78Eh —40 — 78Fh —41 — 790h —4 AD1CON0 791h AD2CON041 ADCOMCON 792h —41 AD1CON2 793h AD2CON241 AD1CON3 794h AD2CON341 ADSTAT 795h —41 AD1PRECON 796h AD2PRECON41 AD1ACQCON 797h AD2ACQCON41 AD1GRD 798h AD2GRD41 AD1CAPCON 799h AD2CAPCON41 AAD1RES0L 79Ah AAD2RES0L41 AAD1RES0H 79Bh AAD2RES0H41 AAD1RES1L 79Ch AAD2RES1L41 AAD1RES1H 79Dh AAD2RES1H41 AD1CH0 79Eh AD2CH041 AD1CH1 79Fh AD2CH142

UnimplementedRead as ‘0’

7A0h


46 7EFh47

Accesses70h – 7Fh


47 7FFh

No

BLE 3-5: PIC16LF1566/1567 MEMORY MAP, BANKS 8-15BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13

0h


1h2h3h4h5h6h7h8h9hAhBhCh — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70ChDh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70DhEh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70EhFh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh0h — 490h — 510h — 590h — 610h — 690h — 710h

11h — 491h — 511h — 591h — 611h PWM1DCL 691h ADCTX 711h2h — 492h — 512h — 592h — 612h PWM1DCH 692h AD1TX0 712h3h — 493h — 513h — 593h — 613h PWM1CON 693h AD1TX1 713h4h — 494h — 514h — 594h — 614h PWM2DCL 694h AD2TX0 714h5h TMR4 495h — 515h — 595h — 615h PWM2DCH 695h AD2TX1 715h6h PR4 496h — 516h — 596h — 616h PWM2CON 696h — 716h7h T4CON 497h — 517h — 597h — 617h — 697h — 717h8h — 498h — 518h — 598h — 618h — 698h — 718h9h — 499h — 519h — 599h — 619h — 699h — 719hAh — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71AhBh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71BhCh — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71ChDh — 49Dh — 51Dh — 59Dh — 61Dh PWMTMRS 69Dh — 71DhEh — 49Eh — 51Eh — 59Eh — 61Eh PWM1AOE 69Eh — 71EhFh — 49Fh — 51Fh — 59Fh — 61Fh PWM2AOE 69Fh — 71Fh0h


4A0h


520h


5A0h


620h General Purpose Register 48 Bytes

6A0h


720h64Fh

650h UnimplementedRead as ‘0’

Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh0h

Accesses70h – 7Fh






770h

Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh

te 1:These ADC registers are the same as the registers in Bank 1.

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BANK 22 BANK 23

B0Ch — B8Ch —B0Dh — B8Dh —B0Eh — B8Eh —B0Fh — B8Fh —B10h — B90h —B11h — B91h —B12h — B92h —B13h — B93h —B14h — B94h —B15h — B95h —B16h — B96h —B17h — B97h —B18h — B98h —B19h — B99h —B1Ah — B9Ah —B1Bh — B9Bh —B1Ch — B9Ch —B1Dh — B9Dh —B1Eh — B9Eh —B1Fh — B9Fh —B20h


BA0h


B6Fh BEFhB70h

Accesses70h – 7Fh

BF0hAccesses70h – 7Fh

B7Fh BFFh

TABLE 3-6: PIC16LF1566/1567 MEMORY MAP, BANKS 16-23BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21

800h


801h802h803h804h805h806h807h808h809h80Ah80Bh80Ch — 88Ch — 90Ch — 98Ch — A0Ch — A8Ch —80Dh — 88Dh — 90Dh — 98Dh — A0Dh — A8Dh —80Eh — 88Eh — 90Eh — 98Eh — A0Eh — A8Eh —80Fh — 88Fh — 90Fh — 98Fh — A0Fh — A8Fh —810h — 890h — 910h — 990h — A10h — A90h —811h — 891h — 911h — 991h — A11h — A91h —812h — 892h — 912h — 992h — A12h — A92h —813h — 893h — 913h — 993h — A13h — A93h —814h — 894h — 914h — 994h — A14h — A94h —815h — 895h — 915h — 995h — A15h — A95h —816h — 896h — 916h — 996h — A16h — A96h —817h — 897h — 917h — 997h — A17h — A97h —818h — 898h — 918h — 998h — A18h — A98h —819h — 899h — 919h — 999h — A19h — A99h —81Ah — 89Ah — 91Ah — 99Ah — A1Ah — A9Ah —81Bh — 89Bh — 91Bh — 99Bh — A1Bh — A9Bh —81Ch — 89Ch — 91Ch — 99Ch — A1Ch — A9Ch —81Dh — 89Dh — 91Dh — 99Dh — A1Dh — A9Dh —81Eh — 89Eh — 91Eh — 99Eh — A1Eh — A9Eh —81Fh — 89Fh — 91Fh — 99Fh — A1Fh — A9Fh —820h


8A0h


920h


9A0h


A20h


AA0h


86Fh 8EFh 96Fh 9EFh A6Fh AEFh870h

Accesses70h – 7Fh




A70hAccesses70h – 7Fh

AF0hAccesses70h – 7Fh

87Fh 8FFh 97Fh 9FFh A7Fh AFFh

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TABANK 30 BANK 31

CCCCCCCCCCCCC0 F0Ch — F8Ch

See Table 3-8 and Table 3-9 for

register mapping details

C0 F0Dh — F8DhC F0Eh — F8EhC F0Fh — F8FhC F10h — F90hC F11h — F91hC F12h — F92hC F13h — F93hC F14h — F94hC F15h — F95hC F16h — F96hC F17h — F97hC F18h — F98hC F19h — F99hC F1Ah — F9AhC F1Bh — F9BhC1 F1Ch — F9ChC1 F1Dh — F9DhC F1Eh — F9EhC F1Fh — F9FhC F20h


FA0h

C F6Fh FEFhC F70h

Accesses70h – 7Fh

F0hAccesses70h – 7Fh

CF F7Fh FFFh

BLE 3-7: PIC16LF1566/1567 MEMORY MAP, BANKS 24-31BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29

00h


01h02h03h04h05h06h07h08h09h0Ah0BhCh — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch —Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh —

0Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh —0Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh —10h — C90h — D10h — D90h — E10h — E90h —11h — C91h — D11h — D91h — E11h — E91h —12h — C92h — D12h — D92h — E12h — E92h —13h — C93h — D13h — D93h — E13h — E93h —14h — C94h — D14h — D94h — E14h — E94h —15h — C95h — D15h — D95h — E15h — E95h —16h — C96h — D16h — D96h — E16h — E96h —17h — C97h — D17h — D97h — E17h — E97h —18h — C98h — D18h — D98h — E18h — E98h —19h — C99h — D19h — D99h — E19h — E99h —1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah —1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh —Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch —Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh —

1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh —1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh —20h


CA0h


D20h


DA0h


E20h


EA0h


6Fh CEFh D6Fh DEFh E6Fh EEFh70h

Accesses70h – 7Fh

CF0hAccesses70h – 7Fh

D70hAccesses70h – 7Fh

DF0hAccesses70h – 7Fh

E70hAccesses70h – 7Fh

EF0hAccesses70h – 7Fh

Fh CFFh D7Fh DFFh E7Fh EFFh

PIC16LF1566/1567

TABLE 3-8: PIC16LF1566/1567 MEMORY

MAP, BANK 31TABLE 3-9: PIC16LF1566/1567 MEMORY

MAP, BANK 31

Address Bank 31F80h INDF0

F81h INDF1

F82h PCL

F83h STATUS

F84h FSR0L

F85h FSR0H

F86h FSR1L

F87h FSR1H

F88h BSR

F89h WREG

F8Ah PCLATH

F8Bh INTCON

F8Ch ICDIOF8Dh ICDCON0F8Eh —F8Fh —F90h —F91h ICDSTATF92h —F93h —F94h —F95h —F96h ICDINSTLF97h ICDINSTHF98h —F99h —F9Ah —F9Bh —F9Ch ICDBK0CONF9Dh ICDBK0L

F9Eh ICDBK0H

F9Fh


FE2h

Legend: = Unimplemented data memory locations, read as ‘0’.

Address Bank 31FE3h BSRICDSHAD

FE4h STATUS_SHAD

FE5h WREG_SHAD

FE6h BSR_SHAD

FE7h PCLATH_SHAD

FE8h FSR0L_SHAD

FE9h FSR0H_SHAD

FEAh FSR1L_SHAD

FEBh FSR1H_SHAD

FECh —

FEDh STKPTR

FEEh TOSL

FEFh TOSHFF0h


FFFh

Legend: = Unimplemented data memory locations, read as ‘0’.


PIC16LF1566/1567

3.2.6 CORE FUNCTION REGISTERS

SUMMARYThe core function registers listed in Table 3-10 can beaddressed from any bank.

TABLE 3-10: CORE FUNCTION REGISTERS SUMMARY

Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BOR

Value on all other

Resets

Bank 0-31x00h or x80h INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu

x01h or x81h INDF1

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu

x02h or x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x03h or x83h STATUS — — — TO PD Z DC C ---1 1000 ---q quuu

x04h or x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x05h or x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x06h or x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x07h or x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x08h or x88h BSR — — — BSR ---0 0000 ---0 0000

x09h or x89h WREG Working Register 0000 0000 uuuu uuuu

x0Ah or x8Ah PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

x0Bh or x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’.


PIC16LF1566/1567

Value on all other Resets

uuuu uuuuuuuu uuuu0000 0000---q quuuuuuu uuuu0000 0000uuuu uuuu0000 0000---0 0000uuuu uuuu-000 00000000 0000xxxx xxxxxxxx xxxxxxxx xxxx

xxxx xxxx----x-------xxxx0000 0000-0-- 000-

uuuu uuuuuuuu uuuuuuuu uuuuuuuu -u-u

uuuu ux-u

0000 00001111 1111-000 0000

—

—

—

ad as ‘0’.

TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY

Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:POR, BOR

Bank 0000h INDF0(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx001h INDF1(1) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx002h PCL(1) Program Counter (PC) Least Significant Byte 0000 0000003h STATUS(1) — — — TO PD Z DC C ---1 1000004h FSR0L(1) Indirect Data Memory Address 0 Low Pointer 0000 0000005h FSR0H(1) Indirect Data Memory Address 0 High Pointer 0000 0000006h FSR1L(1) Indirect Data Memory Address 1 Low Pointer 0000 0000007h FSR1H(1) Indirect Data Memory Address 1 High Pointer 0000 0000008h BSR(1) — — — BSR ---0 0000009h WREG(1) Working Register 0000 000000Ah PCLATH(1) — Write Buffer for the upper 7 bits of the Program Counter -000 000000Bh INTCON(1) GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000000Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx00Fh Unimplemented(4)

00Fh PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx010h PORTE — — — — RE3 — — — ----x---010h PORTE(2) RE3 RE2 RE1 RE0 ----xxxx011h PIR1 TMR1GIF AD1IF RCIF TXIF SSP1IF SSP2IF TMR2IF TMR1IF 0000 0000012h PIR2 — AD2IF — — BCL1IF BCL2IF TMR4IF — -0-- 000-013h Unimplemented

014h Unimplemented

015h TMR0 TMR0 xxxx xxxx016h TMR1L TMR1L xxxx xxxx017h TMR1H TMR1H xxxx xxxx018h T1CON TMR1CS T1CKPS — T1SYNC — TMR1ON 0000 -0-0

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL — T1GSS 0000 0x-0

01Ah TMR2 TMR2 0000 000001Bh PR2 PR2 1111 111101Ch T2CON — T2OUTPS TMR2ON T2CKPS -000 000001Dh — Unimplemented —

01Eh — Unimplemented —

01Fh — Unimplemented —

Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, reNote 1: These registers can be accessed from any bank.

2: PIC16LF1567.3: These registers/bits are available at two address locations, in Bank 1 and Bank 14.4: PIC16LF1566 only.5: Unimplemented, read as ‘1’.


PIC16LF1566/1567

uuuu uuuuuuuu uuuu0000 0000---q quuuuuuu uuuu0000 0000uuuu uuuu0000 0000---0 0000uuuu uuuu-000 00000000 00001111 11111111 11111111 1111

1111 1111----11110000 0000-0-- 000-

1111 1111qq-q qquu--01 0110

0011 1-00-q-q --0q

uuuu uuuu

uuuu uuuu

0000 0000

0000 0000

-000 ----


ad as ‘0’.

Bank 1080h INDF0(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx081h INDF1(1) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx082h PCL(1) Program Counter (PC) Least Significant Byte 0000 0000083h STATUS(1) — — — TO PD Z DC C ---1 1000084h FSR0L(1) Indirect Data Memory Address 0 Low Pointer 0000 0000085h FSR0H(1) Indirect Data Memory Address 0 High Pointer 0000 0000086h FSR1L(1) Indirect Data Memory Address 1 Low Pointer 0000 0000087h FSR1H(1) Indirect Data Memory Address 1 High Pointer 0000 0000088h BSR(1) — — — BSR ---0 0000089h WREG(1) Working Register 0000 000008Ah PCLATH(1) — Write Buffer for the upper 7 bits of the Program Counter -000 000008Bh INTCON(1) GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000008Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 111108Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 111108Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 111108Fh Unimplemented

090h Unimplemented

08Fh TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111090h TRISE(2) — — — — —(5) TRISE2 TRISE1 TRISE0 ----1111091h PIE1 TMR1GIE AD1IE RCIE TXIE SSP1IE SSP2IE TMR2IE TMR1IE 0000 0000092h PIE2 — AD2IE — — BCL1IE BCL2IE TMR4IE — -0-- 000-093h Unimplemented

094h Unimplemented

095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 1111 1111096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq097h WDTCON — — WDTPS SWDTEN --01 0110098h Unimplemented

099h OSCCON SPLLEN IRCF — SCS 0011 1-0009Ah OSCSTAT — PLLSR — HFIOFR — — LFIOFR HFIOFS -0-0 --0q

09Bh ADRESL/AD1RES0L(3) ADRESL xxxx xxxx

09Ch ADRESH/AD1RES0H(3) ADRESH xxxx xxxx

09Dh ADCON0/AD1CON0(3)CHS15 CHS14 CHS13 CHS12 CHS11 CHS10 GO/DONE1 AD1ON 0000 0000

09EhADCON1/ADCOM-CON(3)

ADFM ADCS ADNREF GO/DONE_ALL ADPREF 0000 0000

09Fh ADCON2/AD1CON2(3) — TRIGSEL — — — — -000 ----

TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)





PIC16LF1566/1567

uuuu uuuuuuuu uuuu0000 0000---q quuuuuuu uuuu0000 0000uuuu uuuu0000 0000---0 0000uuuu uuuu-000 00000000 0000uuuu uuuuuuuu uuuuuuuu uuuu

uuuu uuuu

---- -uuu—

—

—

—

—

uu-- ---u0q00 --00

—

—

—

—

—

--0---00—

—


ad as ‘0’.

Bank 2100h INDF0(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx101h INDF1(1) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx102h PCL(1) Program Counter (PC) Least Significant Byte 0000 0000103h STATUS(1) — — — TO PD Z DC C ---1 1000104h FSR0L(1) Indirect Data Memory Address 0 Low Pointer 0000 0000105h FSR0H(1) Indirect Data Memory Address 0 High Pointer 0000 0000106h FSR1L(1) Indirect Data Memory Address 1 Low Pointer 0000 0000107h FSR1H(1) Indirect Data Memory Address 1 High Pointer 0000 0000108h BSR(1) — — — BSR ---0 0000109h WREG(1) Working Register 0000 000010Ah PCLATH(1) — Write Buffer for the upper 7 bits of the Program Counter -000 000010Bh INTCON(1) GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000010Ch LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx

10FhUnimplemented

LATD(2) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx

110hUnimplemented

LATE(2) — — — — — LATE2 LATE1 LATE0 -----xxx111h — Unimplemented —

112h — Unimplemented —




116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q117h FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR 0q00 --00118h — Unimplemented —


11Ah — Unimplemented —

11Bh — Unimplemented —

11Ch — Unimplemented —

11Dh APFCON — — SSSEL — — — GRDBSEL GRDASEL --0---0011Eh — Unimplemented —







PIC16LF1566/1567

uuuu uuuuuuuu uuuu0000 0000---q quuuuuuu uuuu0000 0000uuuu uuuu0000 0000---0 0000uuuu uuuu-000 00000000 00001111 11111111 11111111 1111

1111 1111

-----1110000 00001000 0000uuuu uuuu--uu uuuu-000 q0000000 0000

—

—

xxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000x0000 001001-0 0-00


ad as ‘0’.

Bank 3180h INDF0(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx181h INDF1(1) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx182h PCL(1) Program Counter (PC) Least Significant Byte 0000 0000183h STATUS(1) — — — TO PD Z DC C ---1 1000184h FSR0L(1) Indirect Data Memory Address 0 Low Pointer 0000 0000185h FSR0H(1) Indirect Data Memory Address 0 High Pointer 0000 0000186h FSR1L(1) Indirect Data Memory Address 1 Low Pointer 0000 0000187h FSR1H(1) Indirect Data Memory Address 1 High Pointer 0000 0000188h BSR(1) — — — BSR ---0 0000189h WREG(1) Working Register 0000 000018Ah PCLATH(1) — Write Buffer for the upper 7 bits of the Program Counter -000 000018Bh INTCON(1) GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000018Ch ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 111118Dh ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 111118Eh ANSELC(3) ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 1111 1111

18FhUnimplemented

ANSELD(2) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111

190hUnimplemented

ANSELE(2) — — — — — ANSE2 ANSE1 ANSE0 -----111191h PMADRL PMADRL 0000 0000192h PMADRH — PMADRH 1000 0000193h PMDATL PMDATL xxxx xxxx194h PMDATH — — PMDATH --xx xxxx195h PMCON1 — CFGS LWLO FREE WRERR WREN WR RD -000 x000196h PMCON2 Program Memory Control Register 2 0000 0000197h — Unimplemented —


199h RCREG RCREG xxxx xxxx19Ah TXREG TXREG xxxx xxxx19Bh SPBRGL BRG xxxx xxxx19Ch SPBRGH BRG xxxx xxxx19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 001019Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00






PIC16LF1566/1567

uuuu uuuuuuuu uuuu0000 0000---q quuuuuuu uuuu0000 0000uuuu uuuu0000 0000---0 0000uuuu uuuu-000 00000000 0000

—

1111 1111—

—

----1---uuuu uuuu0000 00001111 11110000 00000000 00000000 00000000 0000

—

uuuu uuuu0000 00001111 11110000 00000000 00000000 00000000 0000


ad as ‘0’.

Bank 4200h INDF0(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx201h INDF1(1) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx202h PCL(1) Program Counter (PC) Least Significant Byte 0000 0000203h STATUS(1) — — — TO PD Z DC C ---1 1000204h FSR0L(1) Indirect Data Memory Address 0 Low Pointer 0000 0000205h FSR0H(1) Indirect Data Memory Address 0 High Pointer 0000 0000206h FSR1L(1) Indirect Data Memory Address 1 Low Pointer 0000 0000207h FSR1H(1) Indirect Data Memory Address 1 High Pointer 0000 0000208h BSR(1) — — — BSR ---0 0000209h WREG(1) Working Register 0000 000020Ah PCLATH(1) — Write Buffer for the upper 7 bits of the Program Counter -000 000020Bh INTCON(1) GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000020Ch — Unimplemented —

20Dh WPUB(3) WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 111120Eh — Unimplemented —


210h WPUE(3) — — — — WPUE3 — — — ----1---211h SSP1BUF MSSPx Receive Buffer/Transmit Register xxxx xxxx212h SSP1ADD ADD 0000 0000213h SSP1MSK MSK 1111 1111214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000218h SSPLVL — — — S2ILS — — — S1ILS ---0---0219h SSP2BUF MSSPx Receive Buffer/Transmit Register xxxx xxxx21Ah SSP2ADD ADD 0000 000021Bh SSP2MSK MSK 1111 111121Ch SSP2STAT SMP CKE D/A P S R/W UA BF 0000 000021Dh SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 000021Eh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 000021Fh SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000






PIC16LF1566/1567


—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—


ad as ‘0’.


28Dh — Unimplemented —
























PIC16LF1566/1567


—

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—

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—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—


ad as ‘0’.


























PIC16LF1566/1567


—

—

—

—

—

0000 00000000 00000000 0000

—

—

—

—

—

—

—

—

—

—

—

—


ad as ‘0’.






391h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000392h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000393h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000394h — Unimplemented —

















PIC16LF1566/1567


—

0000 000011111111-000 0000

—


ad as ‘0’.

Bank 8400h INDF0(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx401h INDF1(1) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a p

pic16lf1566/1567 data sheet - microchip...

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