physical/biochemical inspired computing models for reliable nano …... · 2019-02-13 ·...

Physical/Biochemical Inspired Computing Models for

Reliable Nano-technology Systems

A Thesis Presented

by

Xiaojun Ma

to

The Department of Electrical and Computer Engineering

in partial fulfillment of the requirements

for the degree of

Doctor of Philosophy

in the field of

Computer Engineering

Northeastern University

Boston Massachusetts

November 2008

NORTHEASTERN UNIVERSITYGraduate School of Engineering

Thesis Title: Physical/Biochemical Inspired Computing Models for Reliable

Nano-technology Systems.

Author: Xiaojun Ma.

Department: Electrical and Computer Engineering.

Approved for Thesis Requirement for the Doctor of Philosophy Degree

Thesis Advisor: Prof. Fabrizio Lombardi Date

Thesis Committee Member: Prof. Yong-Bin Kim Date

Thesis Committee Member: Prof. Stefano Basagni Date

Department Chair: Prof. Ali Abur Date

Graduate School Notified of Acceptance:

Director of the Graduate School Date

NORTHEASTERN UNIVERSITYGraduate School of Engineering

Thesis Title: Physical/Biochemical Inspired Computing Models for Reliable

Nano-technology Systems.

Author: Xiaojun Ma.

Department: Electrical and Computer Engineering.

Approved for Thesis Requirement for the Doctor of Philosophy Degree

Thesis Advisor: Prof. Fabrizio Lombardi Date

Thesis Committee Member: Prof. Yong-Bin Kim Date

Thesis Committee Member: Prof. Stefano Basagni Date

Department Chair: Prof. Ali Abur Date

Graduate School Notified of Acceptance:

Director of the Graduate School Date

Copy Deposited in Library:

Reference Librarian Date

Abstract

Quantum-Dot Cellular Automata (QCA) and DNA self-assembly are promising

nanotechnologies that are being studied as potential successors to CMOS VLSI

technology. Their information processing principles are inspired by new physical

(for QCA) and biochemical (DNA self-assembly) phenomena. Because they

are radically different from the conventional CMOS based computation, new

modeling, design, test and fault tolerance techniques are required.

For QCA, modeling, design, testing and fault tolerance are studied while

considering the technical background of reversible computing. A mechanical

molecular QCA is proposed and applied to the analysis of logic function and

energy dissipation of QCA circuits. New reversible gates are designed for QCA

implementation. The test of QCA reversible gate array are discussed while test

cases under different fault assumptions and array configurations are considered.

A fault tolerance scheme called majority-multiplexing is investigated for

QCA circuits in terms of fault tolerant capacity, signal restoration speed and

implication on the reversibility of circuits.

The design and error tolerance of DNA self-assembly are also studied in

this dissertation. The logic design of DNA self-assembly system is investigated

for using DNA self-assembly as a promising nanoscale manufacturing approach.

This design problem is formulated as a combinatorial optimization problem and

proven to be NP-complete. Greedy algorithms are proposed for this problem.

DNA self-assembly system designed using the algorithms may generate errors

during assembly and the errors are studied and modeled in this research.

DNA self-assembly suffers from high error rate. A new error tolerant tech-

nique called (2k− 1)× (2k− 1) snake redundant block (also known as snake tile

set) is proposed. The reduction of error by (2k − 1)× (2k − 1) snake redundant

block is modeled and analyzed. Both analysis and simulation show the error

tolerant technique to be effective and efficient.

Acknowledgments

I would like to extend my most heartfelt thanks to my advisor, Prof. Fabrizio

Lombardi, for his guidance in every aspect of my academic pursuit. This work

would not have been possible without him inspiring my research enthusiasm,

giving sound advice and providing good teaching.

I would also like to thank Prof. Cecilia Metra from University of Bologna,

Prof. Yong-bin Kim and Prof. Stefano Basagni from my department for their

help in my research work.

Many thank, to many student colleagues of mine for providing a collabora-

tive, stimulating and enjoyable environment. I am especially grateful to Mas-

soud Hashempour, Mariam Momenzadeh, Marco Ottavi, Luca Schiano, Vamsi

Vankamamidi, Rui Tang, Jueming Zhang and Ping Liu.

I am grateful to all the staff members at the ECE department, the College

of Engineering and NU ISSI for all their kind assistance over the years.

ii

Finally, I want to dedicate this work to my families. I want to thank my

wife Jing Huang for being a great partner in my life and in my research. Words

can not express my gratitude to my parents, Pengnian Ma and Lin Ma, for their

support and love, which I owe all my achievements to.

iii

To my families

iv

Contents

1 Introduction 1

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Review of Reversible QCA 14

2.1 Quantum-dot Cellular Automata (QCA) . . . . . . . . . . . . . 15

2.2 Reversible Computing . . . . . . . . . . . . . . . . . . . . . . . 22

2.2.1 Reversibility Analysis of a General Computing System . 26

3 A Mechanical Based QCA Model 31

3.1 Mechanical Model . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2 Steady State Analysis of QCA Devices . . . . . . . . . . . . . . 37

v

3.3 Entropy and Dissipation Analysis . . . . . . . . . . . . . . . . . 41

3.3.1 Operation of the Mechanical Cell . . . . . . . . . . . . . 41

3.3.2 Validation of Dissipation Analysis . . . . . . . . . . . . . 48

3.3.3 Energy Dissipation Analysis of Circuit Units . . . . . . . 53

3.4 Landauer and Bennett Clocking Schemes . . . . . . . . . . . . . 57

3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4 Reversible and Testable Circuits for QCA 64

4.1 Reversible Gates in QCA . . . . . . . . . . . . . . . . . . . . . . 66

4.2 Defect Analysis and Gate Testing . . . . . . . . . . . . . . . . . 75

4.3 Test Reversible 1D Array with Single Fault . . . . . . . . . . . . 79

4.4 Test Reversible 1D Array with Multiple Fault . . . . . . . . . . 82

4.4.1 Original 1D Array . . . . . . . . . . . . . . . . . . . . . 82

4.4.2 Array with Additional Observability . . . . . . . . . . . 85

4.4.3 Array with Additional Observability and Controllability 90

4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5 Fault Tolerance of Reversible QCA Circuits 99

5.1 Fault Tolerance in QCA Using Majority Multiplexing (Maj-MUX) 100

5.1.1 Hardware Redundancy Techniques in Literature . . . . . 101

5.1.2 Fault Tolerant Capacity of Maj-MUX . . . . . . . . . . . 105

vi

5.1.3 Restoration Speed of Multiplexing . . . . . . . . . . . . . 108

5.1.4 Summary of Comparison . . . . . . . . . . . . . . . . . . 111

5.2 Energy Dissipation of Maj-MUX Systems with Reversible Modules113

5.2.1 System without Fault . . . . . . . . . . . . . . . . . . . . 114

5.2.2 Dissipation in Fault Correction . . . . . . . . . . . . . . 116

5.3 Conclusion and Discussion . . . . . . . . . . . . . . . . . . . . . 121

6 Review on DNA Self-Assembly 122

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.2 Reported DNA Self-Assembly Experiments . . . . . . . . . . . . 125

6.3 Model of DNA Self-assembly System . . . . . . . . . . . . . . . 129

6.3.1 aTAM Model . . . . . . . . . . . . . . . . . . . . . . . . 129

6.3.2 kTAM Model . . . . . . . . . . . . . . . . . . . . . . . . 134

6.3.3 Model with Negative Bonding Strength . . . . . . . . . 137

6.4 Error Modeling of DNA Self-assembly . . . . . . . . . . . . . . . 138

6.4.1 Growth Error . . . . . . . . . . . . . . . . . . . . . . . . 138

6.4.2 Facet Roughening Error . . . . . . . . . . . . . . . . . . 140

6.4.3 Spurious Nucleation Error . . . . . . . . . . . . . . . . . 142

6.4.4 Gross Damage Error . . . . . . . . . . . . . . . . . . . . 143

6.5 Error Tolerant Methods . . . . . . . . . . . . . . . . . . . . . . 144

vii

6.5.1 Change Assembly Environment . . . . . . . . . . . . . . 144

6.5.2 Change Tile Set . . . . . . . . . . . . . . . . . . . . . . . 145

6.5.3 Change Molecular Structure . . . . . . . . . . . . . . . . 156

7 Synthesis of Tile Sets for DNA Self-Assembly 158

7.1 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . 160

7.1.1 Graph Model . . . . . . . . . . . . . . . . . . . . . . . . 160

7.1.2 Tile Set Design from Trivial Tile Set . . . . . . . . . . . 162

7.2 Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . 168

7.3 Greedy Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.3.1 PATS Bond Algorithm . . . . . . . . . . . . . . . . . . . 176

7.3.2 PATS Tile Algorithm . . . . . . . . . . . . . . . . . . . . 180

7.3.3 Complexity of Greedy Algorithms . . . . . . . . . . . . . 182

7.3.4 Simulation Results for Synthesis . . . . . . . . . . . . . . 185

7.4 Errors in Synthesized Tile Sets . . . . . . . . . . . . . . . . . . . 192

7.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8 Error Tolerance in DNA Self-Assembly 196

8.1 (2k − 1) × (2k − 1) Snake Redundant Blocks . . . . . . . . . . . 197

8.2 Modeling Tolerance to Facet Roughening Errors . . . . . . . . . 201

8.2.1 Model for 3 × 3 Snake Redundant Block . . . . . . . . . 203

viii

8.2.2 Model for 4 × 4 Snake Redundant Block . . . . . . . . . 206

8.2.3 Model for 5 × 5 and 6 × 6 Snake Redundant Block . . . 208

8.3 Simulation and Discussion . . . . . . . . . . . . . . . . . . . . . 211

8.3.1 Error Rate in Assembly of Sierpinski Triangle . . . . . . 212

8.3.2 Tolerance of Facet Roughening Error . . . . . . . . . . . 216

8.4 Discussion on Error Rate and Number of Tile Types . . . . . . 220

8.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

9 Conclusion and Future Work 226

Appendix A 230

Bibliography 234

ix

List of Tables

3.1 Steady State Energy of QCA circuits . . . . . . . . . . . . . . . 39

4.1 Comparison Between the Four QCA Reversible Gates . . . . . . 73

4.2 Reversible Gate Implementation of Thirteen Standard Functions 74

4.3 Benchmark synthesis results . . . . . . . . . . . . . . . . . . . . 76

4.4 Fault Patterns of Fredkin Gate and Toffoli Gate . . . . . . . . . 77

4.5 Fault Patterns of QCA1 Gate and QCA2 Gate . . . . . . . . . . 78

4.6 Example for Rule 1 . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.7 Example for Rule 2 . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.8 Benchmark result . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.1 Comparison of the optimum and PATS tile generated tile sets . 188

7.2 Results for known patterns of finite size . . . . . . . . . . . . . . 191

7.3 Results of QCA layout patterns . . . . . . . . . . . . . . . . . . 192

x

8.1 Comparison of Error-Tolerant Redundant Blocks . . . . . . . . . 225

xi

List of Figures

2.1 QCA cell and Basic Devices . . . . . . . . . . . . . . . . . . . . 16

2.2 Four-phased Landauer Clocking . . . . . . . . . . . . . . . . . . 19

2.3 Tri-state model for clocked molecular QCA . . . . . . . . . . . . 19

2.4 A memory cell of a gas molecule . . . . . . . . . . . . . . . . . . 29

3.1 Mechanical model for molecular QCA . . . . . . . . . . . . . . . 35

3.2 Clocking of the proposed model . . . . . . . . . . . . . . . . . . 36

3.3 Steady State Analysis of QCA Circuits . . . . . . . . . . . . . . 38

3.4 Rotation unit with Brownian movement at a small angle . . . . 42

3.5 RELEASE phase for a cell under a driver of different polarization 47

3.6 A signal path with two cells . . . . . . . . . . . . . . . . . . . . 49

3.7 Shift register with one cell per stage (SR1) . . . . . . . . . . . . 52

3.8 Fanout and Reversible Eraser . . . . . . . . . . . . . . . . . . . 55

xii

3.9 One-input one-output inverter as one-to-two fanout and three-cell

inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.10 Damping in Majority Voter causes dissipation . . . . . . . . . . 56

3.11 Landauer and Bennett Clocking Schemes . . . . . . . . . . . . . 59

3.12 Two-to-one MUX Schematic and Layout Diagrams . . . . . . . 61

3.13 Timing Diagrams for the MUX under Landauer and Bennett

Clocking Schemes . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.1 QCA Layout of the Fredkin Gate . . . . . . . . . . . . . . . . . 67

4.2 QCA Layout of the Toffoli Gate . . . . . . . . . . . . . . . . . . 68

4.3 QCA Layout of QCA1 . . . . . . . . . . . . . . . . . . . . . . . 70

4.4 QCA Layout of QCA2 . . . . . . . . . . . . . . . . . . . . . . . 71

4.5 QCA layout of the CNOT gate . . . . . . . . . . . . . . . . . . 75

4.6 1D Array of Modules made of Reversible Logic Gates . . . . . . 80

4.7 One-to-one onto mapping and fault masking . . . . . . . . . . . 84

4.8 1D Array of Reversible Module with Increased Observability . . 85

4.9 SPI (Single Pin Inversion) fault . . . . . . . . . . . . . . . . . . 87

4.10 C-Testability of 1D Fredkin Gate Array (Added Observe and Con-

trol lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.1 A TMR system in QCA . . . . . . . . . . . . . . . . . . . . . . 102

xiii

5.2 Concatenated TMR System . . . . . . . . . . . . . . . . . . . . 103

5.3 A TMR system with MV redundancy . . . . . . . . . . . . . . . 103

5.4 A NAND multiplexing system . . . . . . . . . . . . . . . . . . . 105

5.5 A majority multiplexing system . . . . . . . . . . . . . . . . . . 106

5.6 Range of fault probability improvement for Maj-MUX . . . . . . 107

5.7 Fault in multiplexing connection . . . . . . . . . . . . . . . . . . 109

5.8 Comparison of restoration speed for Maj-MUX and NAND-MUX 110

5.9 A circuit with 3-Fan and 3-MV connected together. . . . . . . . 115

5.10 Example of majority multiplexing system. . . . . . . . . . . . . 116

5.11 Error and dissipation in restorations of different stage number . 119

5.12 Error and dissipation of 6-stage restoration . . . . . . . . . . . . 120

6.1 Assembling of Sierpinski Triangle using DX tile. [92] . . . . . . . 126

6.2 Fully addressable DNA array. Pattern shows letters “D”, “N”

and “A” [86] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.3 The tile model in aTAM . . . . . . . . . . . . . . . . . . . . . . 130

6.4 The Sierpinski Triangle Tile Set . . . . . . . . . . . . . . . . . . 133

6.5 Tile association and dis-association in kTAM . . . . . . . . . . . 136

6.6 Errors in the Sierpinski Tile Set . . . . . . . . . . . . . . . . . . 140

xiv

6.7 Phase diagram: resulted DNA aggregation under different Gse

and Gmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

6.8 The Sierpinski 2×2 Proofreading Redundant Block . . . . . . . 147

6.9 The 4 × 4 Snake Redundant Block . . . . . . . . . . . . . . . . 151

6.10 Avoid the area overhead in snake redundant block error tolerance 154

7.1 Graph model for the Sierpinski triangle tile set . . . . . . . . . . 161

7.2 Illustration of the example that shows the contradiction in assum-

ing that T1 and T2 may generate a partial assembly with same

shape but they are not equivalent. . . . . . . . . . . . . . . . . . 165

7.3 Example of converting the coloring problem to the PATS problem 170

7.4 Simplification is possible if the bond graph is not a complete bi-

partite graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

7.5 Flow chart of the algorithm PATS Bond . . . . . . . . . . . . . 177

7.6 An exemplar pattern to be generated . . . . . . . . . . . . . . . 178

7.7 Execution of PATS Bond for example pattern . . . . . . . . . . 179

7.8 Flow chart of the algorithm PATS Tile . . . . . . . . . . . . . . 180

7.9 Pattern example: assembly and model . . . . . . . . . . . . . . 182

7.10 Execution of PATS Tile for pattern example . . . . . . . . . . . 183

7.11 Examples of execution of the PATS program . . . . . . . . . . . 186

xv

7.12 Simulation results for PATS Tile . . . . . . . . . . . . . . . . . 187

7.13 Simulation results for PATS Bond . . . . . . . . . . . . . . . . . 187

7.14 Sierpinski triangle patterns in experiments . . . . . . . . . . . . 190

7.15 Coplanar crossing layout patterns in QCA . . . . . . . . . . . . 190

7.16 Error rate of tile sets for various patterns . . . . . . . . . . . . . 194

8.1 The 3 × 3 Snake Redundant Block . . . . . . . . . . . . . . . . 198

8.2 Snake Redundant Blocks with Block Size of 5 × 5 and 6 × 6 . . 199

8.3 Xgrow Simulation Results using the 3 × 3 Snake Redundant Block 200

8.4 Generalized Markov Model for Facet Roughening Error Genera-

tion in Snake Redundant Blocks . . . . . . . . . . . . . . . . . . 203

8.5 Markov Chain Model for Facet Roughening Error Generation in

the 3 × 3 Snake Redundant Block . . . . . . . . . . . . . . . . . 205

8.6 Markov Chain Model for Facet Roughening Error Generation in

a 4 × 4 Snake Redundant Block . . . . . . . . . . . . . . . . . . 206

8.7 Generation Rate of Facet Roughening Errors . . . . . . . . . . . 209

8.8 Facet Roughening Error in 5×5 and 6×6 Snake Redundant Blocks210

8.9 Comparison of Error Tolerant Methods for the Sierpinski Triangle

Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

8.10 Facet Roughening Error of 3 × 3 Proofreading Redundant Block 218

xvi

8.11 Facet Roughening Errors in the x-Direction . . . . . . . . . . . 218

8.12 Facet Roughening Errors in the y-Direction . . . . . . . . . . . . 219

8.13 Error Rate versus Null Tile Concentration . . . . . . . . . . . . 222

xvii

Chapter 1

Introduction

1.1 Overview

In the past half century, the computing and information processing technology

have experienced explosive growth driven by the exponential development of

VLSI technology. However, the CMOS based VLSI is scaling down to its limita-

tions as predicted by the end of the technology roadmap [22]. Extensive research

is being done to search for alternative technology to supersede CMOS VLSI and

attain higher computational power. Both fundamental computing paradigms

and implementation technologies are being investigated. Extremely small fea-

ture size, high device density and low power are some of the attributes that

1

CHAPTER 1. INTRODUCTION 2

nanotechnologies must address. At its small feature size, completely new man-

ufacturing approach is needed for the nanotechnology systems. However, any

manufacturing technology in sight is error prone [78] and the nanoscale devices

is sensitive to soft errors due to environment change [39].

Many nanotechnology research aim at novel devices to supersede CMOS tran-

sistor and continue the success of computation using voltage level “high” and

“low” for representing information. Carbon nanotube has been used to build

diodes [35], field-effect transistors (FETs), SETs and programmable switches [8]

and these devices have been proposed or report to build memory [95] and

FPGA [27]. Various electrical elements and devices can also be built with

nanowires [13][24][49][77][25]. Using electrical active molecules, several new

switching devices have been proposed: a tunneling junction [31] behaves a rec-

tifying diode; a single molecular transistor [31] has similar behavior as con-

ventional FET but with better performance [69]; a switch made of a single

molecule [20] work as a programmable switch. Single electron transistor[19][37]

utilizes controlled quantum tunneling of a single electron to act similar to a

FET with smaller dimension and better performance. Resonant tunneling diode

(RTD) [15][67] features a working region with negative differential resistance.

This feature can be used to amplify signals and provide fast switching action.


Several logic blocks based on RTD have been demonstrated in [7].

Another group of research aim at computing using different ways of rep-

resenting and processing information. They employ new physical, biological

or chemical phenomena that have never been used for computation purpose.

Among them, QCA (Quantum-dot Cellular Automata) and DNA self-assembly

are two promising technologies that are getting intensive attention from re-

searchers. Spin transistor also belongs to this class f nanotechnologies. Spin

transistor technology uses the spin of electrons to represent information. A spin

transistor has a channel that behaves “on” or “off” based on the spin state of

the electron entering it.

Quantum-dot Cellular Automata (QCA) [59][100] relies on novel design con-

cepts to exploit new physical phenomena. It uses the angular position of elec-

tric quadrupole to represent information and employs Coulombic interaction to

transfer and process information. A QCA computing system is designed that

its system ground state corresponds to the logic solution of the computational

problem.

QCA is unique in several aspects: it represents information with the position

of electrons instead of voltage level; it processes and transfers information using

only one type of device (called QCA cell); the basic logic gate in QCA is majority


voter (MV) instead of NAND/NOR gate; a QCA cell is intrinsically a sequential

device (latch) and all its operations are controlled by a clocking mechanism.

Because of its unique features, the modeling and design of QCA system are

different from CMOS systems. QCA models usually involve quantum dynamic

calculation thus are computationally expensive and hard for manual analysis.

QCA logic synthesis needs to utilize MV efficiently. Placement and routing in

QCA must take clocking into consideration as a primary constraint. Another

important aspect of QCA is that its manufacturing is different from CMOS VLSI

and expected to have high fault rate [12][78]. Thus, fault model, testing and

fault tolerance for QCA need to be studied before it can be used as a practical

and reliable computation technology.

One of the most pressing hurdles in the development of computing systems

is energy dissipation [57]. With the increasing logic density, the energy became

a issue affects system design as well as devices and circuits. An extensive study

has revealed the relation between the thermodynamic lower bound of energy

dissipation and computing at logic level [11]. Reversible computing has been

proposed to avoid this bound and improve device density without resulting in

an unacceptable energy density. Because of its ultra-low energy dissipation,


QCA has been advocated as a candidate for implementing reversible comput-

ing. However, the analysis of reversible logic in the context of QCA requires

a substantial content of quantum dynamics. Only small circuit units has been

successfully analyzed regarding their reversibility using quantum-based QCA

model [57][106]. More importantly, the basic logic gate of QCA, majority voter,

is not reversible under normal QCA clocking mechanism. New clocking scheme

has been proposed for single majority voter in [57] but further research is needed

to build QCA circuit using the new clocking scheme. The feature of reversible

computing also need to be considered for its implication on the testing and fault

tolerance of QCA circuits.

Self-assembly is the process in which small objects spontaneously assemble

“bottom-up” and form a organized complex structure. DNA is used by na-

ture as the carrier of the genetic information. In DNA self-assembly, special

engineered DNA structures called DNA tiles are used to carry and execute the

instructions of self-assembly. DNA self-assembly exploits the biochemical phe-

nomenon that the unpaired nucleotide segment in DNA bonds selectively to the

other nucleotide segment according to their nucleotide sequences. Combining

the information bearing and selective reacting ability with the research of novel

computing technology, DNA self-assembly has attracted intensive interest as


an promising nanotechnology. Controlled deposition of nano-scale devices on

DNA self-assembled patterns has been proposed as the manufacturing method

beyond the limit of photo-lithography technology and experiment results have

been reported supporting the proposal [41][51][87]. It has also been proven and

shown by example that DNA self-assembly can be used as a novel computing

paradigm [124][53]. The most prominent advantage of DNA self-assembly is that

a large number of assembly instances can be executed in parallel and achieve

high process throughput.

Information in self-assembly is localized and assembly of each building-block

object only responses to its immediate vicinity. Thus, it imposes entirely new

problems to design the assembling behavior of the objects according to the

desired pattern or the required computing task.

It has been shown that the error rate in a DNA self-assembly process is

as high as 10% [128], involving a large number of DNA tiles in the assembled

structure. These errors limit the application of the self-assembly either as a

manufacturing technology or as a computing paradigm. Efficient error toler-

ant techniques must be adopted in DNA self-assembly before it can be put to

practical application.


1.2 Previous Work

The concept of QCA was first proposed by Lent [59]. Since then, different device

structure and implementation has been proposed and reported [109][4][83][56][61][63][112].

Various QCA logic blocks and circuits have been designed [33][79][81][26][116][118].

Design methodologies [30][46][45][6][113] and CAD technology [46][80][133][111]suitable

for QCA circuits have also been studied.

Several quantum dynamics based modeling techniques for QCA has been pro-

posed, including iterative simulation using the Hartree-Fock approximation [110][117],

QBert [82], Fountain-Excel simulation[117] and nonlinear simulation [117]. Sim-

ulation tool such as AQUINAS [110] and QCADesigner [117] have been devel-

oped based these models. A SPICE based model has been proposed and exper-

imentally verified in [104][105], which characterize metal-island based QCA.

The defects generated in QCA manufacturing has been studied in [64]. Fault

characterization of QCA circuits has been pursued for interconnection [103][48]

and logic gates [47][84]. Testing and fault tolerance of QCA circuits have been

studied [38][103][122][43][21].

[58] proposed a clocking scheme to control the operation of QCA circuits

which is later referred to as Landauer clocking. In order to operate the QCA

circuits (especially the QCA majority voters) reversibly, a new clocking scheme


called Bennett clocking has been proposed [57]. The reversibility of QCA under

different operation configurations has been studied using a quantum dynamics

based calculation [106][57]. The quantitative calculation on basic QCA gates

has shown the validity of Bennett clocking.

Several different structure of DNA tiles have been proposed for DNA self-

assembly [99][34][52][132]. 1-dimensional or 2-dimensional DNA assemblies with

controlled patterns have been reported [52][87][86][88][85]. Results of nanoscale

fabrication using DNA self-assembly have been presented in literature [41][87][88][85].

Computing using DNA self-assembly was first proposed in [124], the comput-

ing paradigm has been proven [126] and an example of solving combinatorial

optimization problem has been presented [54].

Various models have been proposed, characterizing DNA self-assembly at

logic level [93][124] and thermodynamic level [128]. A simulation tool named

Xgrow [123] has been developed based on these models.

Logic level model and simulation are used in research of logic design of DNA

self-assembly systems. [124] shed light on the method of converting a comput-

ing problem into the design of DNA self-assembly system, using Wang’s tile

theory [119]. [86] has reported the design of exemplar DNA self-assembly sys-

tems with total control of each pixel in the assembled patterns. However, no


research has been pursued addressing the problem of optimizing the design of

DNA tiles to manufacture a desired pattern with less DNA synthetic effort.

Thermodynamic level models and simulation are used in research regard-

ing assembly speed, errors and error tolerance in DNA self-assembly. Assembly

speed and error rate are effected by several key parameters in the assembly

condition, such as temperature and solution concentration [125][128]. The er-

ror generation in DNA self-assembly has been studied in experiments [92] and

model-based analysis [128]. Different types of errors and their causes have been

reported and modeled in the literature [128][127][18]. Various error tolerant

techniques have been proposed to reduce the error rate in DNA self-assembly,

including changing the chemical structure of DNA tiles [17][36][90][96], control-

ling assembly environment [125][50] and modifying the logic design of DNA

tiles [128][18][98][127][101].

1.3 Contribution

Existing models and tools for QCA analysis and design have very limited capa-

bilities. A new mechanical-based model for computing in QCA is proposed in

this dissertation. The motivation for this new model is that it provides an intu-

itive and classical treatment of energy and heat phenomena in QCA technology.


By avoiding a full quantum-thermodynamical calculation, it offers a classical

view of the principle s of QCA operation and can be used in evaluating energy

dissipation for reversible computing. The proposed model is mechanically based

and is applicable to six-dot (neutrally charged) QCA cells for molecular imple-

mentation. Based on this model, reversibility of QCA is investigated in detail at

both device and circuit levels; Landauer and Bennett clocking scheme [57] are

also analyzed.

As a candidate technology for implementing reversible computing, QCA are

used in this dissertation to design two well-known reversible gates, Toffoli gate

and Fredkin gate. Two new reversible gates (referred to as QCA1 and QCA2) are

proposed for better implementing result using QCA. These gates are compared

in terms of delay, area and logic synthesis and result showed that QCA1 and

QCA2 gate are more suitable for building QCA reversible circuits.

Due to the expected high error rates in nanoscale manufacturing, testing of

QCA has received considerable attention. Self-assembly has been proposed as

the manufacturing technology for QCA and it is likely to result in the array

based manufacturing of QCA gates. Thus, array based testing of QCA gates

is a topic worth studying. Fault model for reversible gates implemented with

molecular QCA is developed base on the single missing/additional cell defect.


Using the fault model, the testability of 1-dimensional arrays made of QCA

reversible gates are studied in this dissertation. It is shown that the array is C-

testable if only single faulty gate is considered in the array. For multiple faulty

gates assumption, testability of different array configurations is investigated and

compared.

QCA is limited by the high fault rate in manufacturing. New fault tolerant

schemes are required to build reliable system with fault-prone QCA technology.

In this dissertation, several fault tolerant schemes are analyzed and compared

for QCA systems. It is shown that majority multiplexing (Maj-MUX) is a

high capacity fault tolerant scheme specially suitable for QCA circuits. Fault

tolerant capability and signal restoration speed of QCA systems using Maj-MUX

is investigated in detail.

DNA self-assembly has been advocated as a promising approach for nanoscale

manufacturing. This dissertation addresses the issues revolving around the logic

design of DNA tile according to the patterns need to be manufactured using

DNA self-assembly. As for a finite pattern, the problem of generating a optimum

set of tiles (referred to as PATS, Pattern Assembly Tile-set Synthesis, problem)

is proven to be NP-complete by showing its equivalence to a minimum graph

coloring problem. Two greedy algorithms for this problem are proposed and


evaluated. In addition, The errors in the DNA self-assembly using the tiles

designed by the algorithms are investigated and modeled.

Error modeling and error tolerance in DNA self-assembly are also studied in

this dissertation. A error tolerance technique called (2k − 1) × (2k − 1) snake

redundant block (also known as snake tile set in literature) is proposed in this

dissertation. Compared with other error tolerant method, the proposed snake

tile sets achieve a considerable reduction in error rate at a very modest reduction

in growth rate. An model is created to characterize the error generation under

this error tolerance technique. This model is used to analyze the error tolerant

capability of (2k − 1) × (2k − 1) snake redundant block and compare it with

other technique of error tolerance.

1.4 Dissertation Outline

In Chapter 2, a review of QCA and reversible computing is provided. The me-

chanical model for QCA is presented in Chapter 3 and used to analyze the logic

operation, energy dissipation and clocking schemes in QCA reversible circuits.

In Chapter 4, new QCA reversible gates are proposed and evaluated. Also,

the test of reversible QCA gate array is discussed. Fault tolerance for QCA


circuit is investigated and evaluated in Chapter 5. The implication of fault tol-

erance on reversible computing is also considered. Chapter 6 provides a review

of DNA self-assembly. In Chapter 7, the logic design of DNA tiles is discussed

for manufacturing required pattern. A discussion of errors generated by the

tiles designed this way is also given in Chapter 7. The fault tolerant technique,

(2k−1)×(2k−1) snake redundant block, is presented in Chapter 8. Conclusion

and future work are addressed in Chapter 9. An index of the chapters and their

associated publications are provided in the Appendix.

Chapter 2

Review of Reversible QCA

Quantum-dot Cellular Automata (QCA) [59][100] is a innovative new computing

paradigm that was inspired by novel physical phenomenon and principle that had

never been used to build computing systems. One of its most attractive features

is the ultra-low power consumption [33][80]. Energy dissipation is an important

fact that limits the increase of logic density in computing system. Despite all the

efforts to decrease the dissipation, there is a lower bound of dissipation imposed

by the nature of computing process [55][10]. One of the possible solutions to

bypass this lower bound is reversible computing. QCA has been deemed as a

promising technology for approaching the thermodynamic limit of computation

and build reversible logic systems. Because the low-power feature of QCA, it

14

CHAPTER 2. REVIEW OF REVERSIBLE QCA 15

is expected that QCA implementation of reversible computing will make the

dissipation benefit of reversible computing observable.

2.1 Quantum-dot Cellular Automata (QCA)

Quantum-dot Cellular Automata (QCA) relies on the Coulombic interaction be-

tween cells to implement novel computational paradigms. In its simplest form,

a QCA cell can be viewed as a set of four charge containers or “dots” (two

dipoles), positioned at the corners of a square [109]. The cell contains two extra

mobile electrons which can quantum mechanically tunnel between dots, but not

cells. The electrons are forced to the corner positions by Coulombic repulsion.

The two possible polarization states represent logic “0” (polarization P = −1)

and logic “1” (polarization P = +1), as shown in Figure 2.1(a). QCA operates

by the Coulombic interaction that connects the state of one cell to the state of

its neighbors. This results in a technology in which information transfer (inter-

connection) is the same as information transformation (logic manipulation).

Manufacturing of QCA falls into three major categories of implementation:

metal, semiconductor and molecular [108]. Metal QCA with size of micrometer

and operates under ultra-low temperature has been reported [4][83]. Recent

developments in manufacturing involve molecular assembly of QCA devices to


B

C

A

(a) QCA Cell

(b) Majority Voter

(c) Inverter

(d) Binary Wire

(e) Inverter Chain

"0" "1"Polarization −1 Polarization +1

dot

quantumcell

Figure 2.1: QCA cell and Basic Devices

supersede metal-based implementations [56][61][62][63]. At very small features

sizes, self-assembly and large scale cell deposition on insulated substrates have

been proposed to manufacture QCA circuits [40]. In QCA, logic gates (such as

the inverter, INV and majority voter, MV) and other devices (such as the binary

wire and the inverter chain) have been proposed as primitives for combinational

circuit design [109]. The basic QCA devices are shown in Figure 2.1(b)-(e).

As a combined methodology for computation and communication [5] [33][79],

different designs of logic circuits have been proposed for QCA implementation

[33][81] [26][116][118]. It has been shown [46] that for QCA, the function with at

most three variables (such as the MV) provides a efficient basis for combinational

design.

Clocking is used to modulate the inter-dot tunneling barrier of QCA cells.


Using an induced electric field mechanism for clocking, true power gain is pos-

sible. A QCA circuit is partitioned into a number of clocking zones and all cells

in the same zone are controlled by a common clock signal. The clock signals

are commonly supplied by CMOS wires buried under the QCA circuitry. The

use of a quasi-adiabatic switching technique for QCA circuits requires a four-

phased clocking signal. The four-phase clocking scheme, also known as Landauer

clocking, was proposed in [58], and is shown in Figure 2.2. The four phases are

RELAX, SWITCH, LOCK and RELEASE. During the RELAX phase, there is

no inter-dot barrier and a cell remains unpolarized. During the SWITCH phase,

the inter-dot barrier is slowly raised and a cell attains a definitive polarity under

the influence of its neighbors. In the LOCK phase, barriers are high and a cell

retains its polarity. Finally in the RELEASE phase, barriers are lowered and a

cell loses its polarity. Clocking zones of a QCA circuit or system are arranged

in this periodic fashion, such that zones in the LOCK phase are followed by

zones in the SWITCH, RELEASE and RELAX phases. A signal is effectively

“latched” when one clocking zone goes into the LOCK phase and acts as input

to the subsequent zone. This clocking mechanism provides inherent pipelining

[6] and allows multi-bit information transfer in QCA through signal latching.


QCA has low power consumption [33][80], so it has been proposed as a tech-

nology to quantitively investigate the relationship between computation and en-

ergy dissipation [57][106]. In QCA, the information stored in the cell is “erased”

when the cell goes from the LOCK phase to the RELAX phase. Two cases are

considered in [106]: logically irreversible “erase” and logically reversible “copy-

then-erase”. Erasure without copying requires an amount of energy dissipation

of at least in the order of kT . However, energy dissipation during a “copy-then-

erase” process (in which a copy of the bit is retained) can be made arbitrarily

small. For a binary wire (such as a QCA shift register), it has also been shown

that the energy dissipated per switching operation can be significantly less than

kT ln2. However, it must be pointed out that as the fundamental operation in

QCA, the majority voting function is logically irreversible, because the informa-

tion in the minority input is lost during computation. A novel scheme referred

to as Bennett clocking has been proposed for QCA in [57]. With this scheme,

it is possible to build reversible logic circuits for making QCA a realistic tech-

nology [57] for reversible computing. It was shown by direct calculation that

energy dissipation per switching event is much less than KTln2 for QCA circuits

containing MV and fan-out [68].

QCA performs computation basing on the fact that the cell configurations


Relax Switch Hold Release

/2 3 /2 2

1

0

-1V

/ V

ma

x

Figure 2.2: Four-phased Landauer Clocking

(a) 3 states

(b) Energy states

Figure 2.3: Tri-state model for clocked molecular QCA


that put the system in the ground state correspond to the correct logic function.

So the analysis of QCA system bases on the correct analysis of the ground

state. The modeling and analysis of QCA requires a substantial content of

quantum dynamics. For example, robustness to thermal effects must consider

the repeated estimates of ground (and preferably near-ground) states, along with

cell polarization for different designs. This evaluation is presently possible only

through a computational expensive quantum-mechanical simulation. Existing

tools such as AQUINAS [110] and the coherence vector simulation engine of

QCADesigner [117] perform an iterative quantum mechanical simulation using

the Hartree-Fock approximation. The simulator factories the joint wave function

over all QCA cells into a product of individual cell wave functions to calculate

the ground state of the system. Other techniques such as QBert [82], Fountain-

Excel simulation, nonlinear simulation [117] only estimate the state of the cells.

Unfortunately, these techniques in some cases may fail to estimate the correct

ground state. A new model based on a SPICE model has been proposed and

experimentally verified in [104][105]. Such model characterizes the behavior of

metal-based QCA by electrical elements. A metal-island QCA cell is modeled as

a network consisting of capacitors, resistors and voltage sources. However, this

model does not fully capture the behavior of a QCA cell, as energy and related


effects (such as dissipation) are not analyzed.

Presently, CAD tools for QCA (such as QCADesigner and AQUINAS) are

inadequate in assessing energy dissipation as related to using QCA for reversible

computation. They are applicable to an evaluation of QCA circuits under spe-

cific conditions in clocking scheme and technology implementation. Moreover,

because of the complex quantum dynamic description of QCA system, it is dif-

ficult to acquire an intuitive understanding of the computational procedure and

related energy dissipation.

Similar to other nanotechnology, QCA manufacturing suffers from high de-

fect rate. Defects generated in the manufacturing of molecular QCA has been

studied [64]. It has been shown that defects can occur in both the chemical

synthesis phase (in which the QCA cells are manufactured) and the deposition

phase (in which the QCA cells are attached to a substrate). Defects are more

likely to occur in the deposition phase than in the chemical synthesis phase,

which result in perfectly manufactured cells being imperfectly placed in the sub-

strate. Defect has been studied. Two types of defects are considered, namely the

missing cell defect and the additional cell defect. The former represents the case

in which a cell fails to attach to the substrate, while the latter represents the

case of unwanted cell deposition. Fault characterization of QCA interconnect


using this defect model have been reported [103][48]. Fault model of logic gates

has also been studied [47][84]. Testing of QCA circuits have been studied [38]

2.2 Reversible Computing

A dynamical system is reversible if from any point of its state set, it is possible

to uniquely trace a trajectory backward as well as forward in time [107]. For any

thermodynamical process involving a system moving from state A into state B,

the change of entropy is defined by the second law of thermodynamics as

S(B) − S(A) ≥∫ B

A

dQ

T

where S(A) and S(B) are the entropy of a system in state A (initial) and B (final)

respectively, and dQ is the infinitesimal amount of heat received by the system at

temperature T during the change (from state A to B). The equality sign holds

for a thermodynamically reversible process. The time reversion (to rewind a

process from the end to the beginning in reverse order) of a thermodynamically

reversible process does not violet the the second law of thermodynamics. For

a process under constant temperature, reversibility means that the total heat

exchange with its environment is T × (S(B) − S(A)). If this process starts and


ends at the same state (i.e. a cycle is said to occur), then the total heat exchange

is 0. If the cycle is not reversible, the system is dissipative.

The relation between computing and energy dissipation was initially inves-

tigated by Landauer [55]. It was shown that a computation process that loses

information cannot be thermodynamically reversible. kBT ln2 joules of energy

are generated for each bit of information lost (where kB is Boltzmann’s constant

and T is the operating temperature). So, a computing system is dissipative if

its working cycle consists of information loss. Reversible computing was pro-

posed in [10] to preserve information. Primitives in reversible computing must

have a one-to-one onto mapping between inputs and outputs. This property

is called the bijective property; primitives with this property are logically re-

versible (or invertible) primitives. The implementations of logically reversible

primitives are called reversible logic gates, but in most cases these two words are

interchangeable, i.e. reversible computing is based on invertible primitives and

composition rules that preserve invertibility [107]. Different theoretical models

of reversible computing have been proposed in the technical literature [11]. It

was proved [10][107][32] that general computation can be accomplished through

a logically reversible process.

Reversibility mentioned so far has two respects:


1. Logic Reversibility: the bijective property (one-to-one onto function) be-

tween the input and output logic states holds. This is independent of the

technology and the internal structure of the circuit.

2. Thermodynamic Reversibility: no energy is dissipated. In this case, the

internal structure of the circuit must satisfy strict reversible primitives in

a given technology as an implementation platform.

Thermodynamic reversibility requires logic reversibility but a system can be

logically reversible, but not thermodynamically reversible. In our study, the term

“reversible” means thermodynamically reversible, unless otherwise specified.

As a thermodynamically reversible system, the irreversible process in com-

putation is avoided. In theory, it is possible build computational systems whose

energy dissipation is only determined by the number of inputs and outputs, not

by the number of gates in the system. For a large system, the amount of energy

per gate can be made infinitely small, so that the high density integration of sys-

tems manufactured in the nano-scale will not be limited by energy dissipation.

[57, 106] showed by quantitative calculation that it’s possible to build reversible

logic circuits using QCA.

As a logically reversible system, circuit-level testing becomes significantly

simpler compared to the conventional computing system. Reversible logic gates


are information lossless so the information output of a reversible circuit is max-

imized. Therefore the probability of fault detection is maximized too [3]. The

one-to-one onto property improves the controllability as well as the observability

of the circuit. It has been proved [89] that any test set that detects all single

stuck-at faults must detect all multiple stuck-at faults. Efficient test generation

algorithms for reversible circuits [89] can be used to obtain a test set of half the

size of that generated by conventional ATPG. A bound presented in [89] shows

that the size of the test set grows at most logarithmically with the size of the

circuit. Testability for a subclass of reversible logic gates, namely the k-CNOT

gates has been investigated in [14]. It was shown that n-wire reversible circuits

have a universal test set of size n2 + 2n + 2. Iterative Logic Arrays (ILAs) built

with reversible logic gates were also considered in [14] under a single module

fault assumption. It was proved that an 1D array with a single faulty module is

C-testable. It was also shown that any d-dimensional array is C-testable under

a single-faulty-module assumption.


2.2.1 Reversibility Analysis of a General Computing Sys-

tem

In a computing system, the degrees of freedom of its components are encoded

to bear information. A thermodynamic model of a single ideal-gas molecule

is presented in this section. Its operation is analyzed in terms of information,

entropy and dissipation. By analogy, the relation between entropy change and

heat dissipation derived in this model can used in the analysis of the operation

and dissipation of the computing model proposed in Chapter 3.

System entropy increases during loss (or destruction) of information. Ac-

cording to thermodynamics [29], the change of system entropy is ∆S = k lnWf

Wi,

where k is Boltzmann’s constant, Wi and Wf are the number of possible sub-

states in the initial and final states, respectively. Q is the heat that the system

absorbs from the environment and W is the work done by the system.

For example, an ideal gas has six degrees of freedom (three dimensions of

space position and three directions of momentum). If a gas with NA molecules

changes its volume from Vi to Vf = 2Vi in an isothermal expansion, then the

change of its entropy is given by ∆S = k ln(V NA

f /V NA

i ) = NAk ln(2). Isothermal

expansion is reversible [29], so this increase in entropy comes from the heat

absorbed from the environment and Q = ∆S × T = NA × kT ln 2 (Q is positive


when the heat goes from the environment to the system). The internal energy of

a gas is constant in an isothermal expansion, so the work W = −Q is done to the

gas (W is positive when work is done to the system). If the change in volume

is achieved by free expansion, then there is no work done in the process, i.e.

W = 0. The internal energy of the system does not change. So, there is no heat

exchange between the system and the environment, Q = ∆Einternal − W = 0.

Free expansion is not reversible, so the change of entropy ∆S is larger than

∫ dQT

= QT

= 0.

In a computing system, some degrees of freedom can be used to encode

information. So, with no loss of generality, a bi-state computing unit divides all

possible states into two sub-spaces, according to the information-bearing degrees

of freedom. Consider again the example of an ideal gas; if a gas molecule in a

cell (container) with volume 2V is utilized as a bi-state unit, then information

can be encoded by defining a first state as 1 if the molecule is in the upper half

of the cell, and a second state as 0 if the molecule is in the lower half of the cell

(shown in Figure 2.4). If there is no separation, the gas can move freely in the

cell, thus changing the cell state between 1 and 0. Entropy in this free state is

denoted by S0. The state can be set to 1 by moving the bottom to the middle

of the cell. Similarly, moving to the top can set the cell to the 0 state. Assume


the movement is slow enough to keep the operation isothermal, this operation

places one bit of information into the cell, and the entropy of the cell becomes

S0 − k ln 2. If the temperature of the system is denoted by T , then W = kT ln 2

of work is done to the cell during the operation, and the heat exchange is given

by Q = −kT ln 2.

By knowing the state of a cell, it is then possible to change it from 1 or 0

to the free expansion state by moving the separating wall to the corresponding

position (bottom or top). This operation increases the entropy back to S0; also,

W = −kT ln 2 and Q = kT ln 2 are needed for this operation. In the cycle of this

process (often referred to as set-then-erase), the total work and heat dissipation

are both 0. This is an erasure with no dissipation and can only be performed

when the cell state is known. Consider all the parts involved in this operation

as a system, rather information is not destroyed in this system. Information

will be erased if the separation wall is broken. A molecule’s free expansion

through the broken wall performs zero work, and the internal energy of the

gas experiences no change. So, there is no heat exchange between the system

and the environment. Meanwhile, the cell entropy increases to S0 during free

expansion. For the working cycle of the set-then-erase operation through free

expansion, the work W = kT ln 2 must be done to the system and Q = −kT ln 2


is transferred between the gas (as computing system) and the environment (a

negative value means that there is heat dissipation from the system).

S=S0Unspecified Unspecified

S=S0−k*ln2+1/−1 state

S=S0

W=kT*ln2Q=−kT*ln2

W=−kT*ln2Q=kT*ln2

W=0Break

Q=0

Figure 2.4: A memory cell of a gas molecule

This example illustrates that loss of information entails dissipation. Storing

information into a logic cell requires heat flow into the environment to decrease

the entropy of the cell from the unspecified state. To recover the cell from the

unspecified state, it is possible to absorb heat from the environment. The lower

limit for the heat generated in the former process is the same as the upper

limit of the heat absorbed in the latter process. Both limits are achieved only

by a quasi-equilibrium process. The key element of Landauer’s claim is that

no quasi-equilibrium process can be applied without knowing the state of the

information in the system. However, knowledge of information means that the

information erased in the cell is not the only copy in the entire computing system,

i.e. the information is not destroyed. If no other copy of information exists in

the computing system, then the above example suggests that the cell can only

be recovered to the specified state by a process like free expansion. This process


does not absorb heat and the heat dissipation that occurs in the information

storage process, is the dissipation of the full work-cycle.

In the above discussion, the base of the logarithm was given by e. The

selection of the logarithm base does not change the applicable physical laws that

the formula use. As in the remainder of the paper, a bi-state system is assumed,

so a base of 2 will be used to simplify notation and presentation (albeit, also in

this case the notation has no implication on the general validity of the presented

analysis).

Chapter 3

A Mechanical Based QCA Model

Dynamic analysis of QCA devices requires a substantial content of quantum

dynamics. Even with approximation adopted in [110][117][108] it is compu-

tationally expensive to investigate the dissipation in QCA reversible logic. An

intuitive understanding of the computational procedure and related energy dis-

sipation is often difficult to acquire due to the unique features of the quantum

effects in QCA. A model inspired by the operational features of molecular QCA,

is proposed to provide an intuitive and classical treatment of energy and heat

phenomena in QCA technology. The model bases on mechanical parts and is

applicable to the six-dot QCA cell model [106] for molecular QCA implementa-

tion.

31

CHAPTER 3. A MECHANICAL BASED QCA MODEL 32

Using this model, different features of QCA devices and circuits are ana-

lyzed. Logic function of QCA circuits are analyzed and the results are validated

against results from quantum-dynamic based simulators. Reversibility of QCA

is investigated in detail at both device and circuit levels. Also, Landauer and

Bennett clocking techniques [57] are briefly analyzed to unify reversibility within

a cohesive framework for different QCA devices (such as the majority voter).

3.1 Mechanical Model

The mechanical model proposed for QCA devices and circuits is shown in Fig-

ure 3.1. In the model, each cell consists of two units: the rotation unit and the

clocking unit (Figure 3.1(a)). A 3D view of the entire mechanical computing cell

is given in Figure 3.1(b).

• Rotation unit: There are four charged balls at the end of a cross with

four equal-length arms. Two balls have positive charge and the other two

have negative charge. The electric charge on the positive balls is q and

the charge on the negative balls is −q. The charged balls form an electric

quadrupole, as shown in the 3D view of rotation unit. A compressible

unbendable stick connects two (neutral) balls. The center of the cross and

the midpoint of the stick are installed on the same axle. The cross and the


stick are tightly fixed to the axle and are always kept aligned as shown in

Figure3.1(a).

The angular position of the rotation unit is used to represent the informa-

tion in the computing system. The charged balls in different cells interact

with each other through a Coulomb force. The quadrupole interaction

between mechanical computing cells models the quadrupole interactions

between cells in molecular QCA, which is usd to transfer and transform

information.

• Clocking unit: The neutral balls in the rotation unit are housed in a spe-

cially shaped sleeve. Figure 3.2(a) illustrates the cross sections generated

by cutting at the five positions (A)-(E) in Figure 3.1(a). The forth-and-

back movement of the sleeve changes the shape that constrains the neutral

balls.

The possible angular position of the rotation unit (denoted by β in Fig-

ure 3.2) is limited by the shape of the cross section of the sleeve. A large

amount of energy will be required for pressing the stick connecting the

neutral balls into the narrow part of the sleeve. Thus, the position of

the sleeve defines the system energy state with respect to β. The plot

of the energy state versus β (at the sleeve position (A)-(E)) is shown in


Figure 3.2(c). The position of the charge-ball quadrupole is the degree

of freedom used to encode information; this is shown under the five dif-

ferent scenarios in Figure 3.2(b). The sleeve interacting with the neutral

balls defines the clocking operation in the computing model, hence it is

referred to as the clocking unit. The clocking unit models the clocking for

molecular QCA.

The model uses a four-phase clock configuration to model the four-phase

clock of QCA. In the LOCK and RELAX phases (corresponding to state (A) and

(E) in Figure 3.2), the model precisely captures the energy state configuration of

a QCA cell. In the LOCK phase, the clock sleeve constrains the angular position

β of the rotation unit into two possible polarizations, 45 and 135. Any other

angular position requires the stick to be compressed to fit in the sleeve. As

shown in Figure 3.2(c) , the energy for compressing the stick causes the energy

for the position to raise rapidly when the angular position deviates from 45 or

135. In the RELAX phase, the rotation unit is allowed to be in a small range

around β = 90. This state represents the “NULL” state in a tri-state molecular

QCA cell.

States (B)-(D) correspond to the SWITCH or RELEASE states in QCA. In

state (C), the rotation unit is free to rotate to any angular position. It represents


axle

neutral ball

negative−charge ball

positive−charge ball

Clocking sleeve movesback and forth

Clocking Unit Rotation Unit

C D EA B

neutral ball

axle

Fit in thesleeve

rotation unit

3−D view of

Cross

Clocking sleeve

positive−charge ball

negative−charge ballpositive−charge ball

negative−charge ball

(a) Diagram of a cell of proposed model

(b) 3D view of a cell

Figure 3.1: Mechanical model for molecular QCA


β

(RELEASE/SWITCH) (RELAX)(LOCK)

β

(A)

(a) Cross−section of the clocking sleeve

(b) Position of charged balls

(c) Energy vs angular position

(D) (E)(C)(B)(A)

(D) (E)(C)(B)(A)

E

−1

35

−9

0

−4

5

45

90

13

50

(E)

E

−9

0

−4

5

45

90

13

5

−1

35 0

(C)

E

−1

35

−4

5

45

13

5

900

E

0

13

5

90

45

−4

5

−1

35

−9

0

E

0

13

5

90

45

−4

5

−9

0

−1

35

(D)

β β

βββ

(B)

−9

0

Figure 3.2: Clocking of the proposed model


the state of a QCA cell in which the electrons can tunnel freely to any position.

The states (B) and (D) are the transitions from (A) to (C) and (C) to (E). The

rotation unit can move within an angle defined by the sleeve’s cross sections.

It is assumed that the movement of the sleeve is slow enough to ensure that

the clock change is quasi-adiabatic switching [55]. The mechanical computing cell

is filled with air, so the air behaves as a damper if the movement of the charged

balls is not sufficiently slow (note that air is just a medium in the model, not

a physical requirement for the molecular QCA). Also, air is a source of thermal

noise that gives the charged balls a random “Brownian” rotation movement.

3.2 Steady State Analysis of QCA Devices

A QCA circuit computes by mapping the ground state to the logic solution

that the circuit is designed to generate [58]. Using the mechanical model, the

steady state energy is calculated for several QCA circuits to analyze their logic

functions.

For a cell of size a × a, the cell center-to-center distance is denoted by b. In

the calculation hereafter, assumption is taken that b = 3a, but the same function

is found for different b value. For a pair of balls (with electrical charge q1 and

q2) at a distance of r, the potential energy is given by E = α× q1q2/r, where α


(b) Inverter Chain

A B

logic "1"logic "0"

a

b

(c) Signal Propagation From

Inverter Chain to Binary Wire

B

A

Fb

b

(d) 2−cell 45 Degrees Inverter

b

B

A

b

(f) Coplaner Crossing

A

C

F2

BF1

b b

(e) 3−cell Inverter

F

A

B

b

b

(a) Binary Wire

A Balogic "0" a

b

Ball with Charge +qBall with Charge −q

A

C

B FD

bb

(g) Majority Voter

Figure 3.3: Steady State Analysis of QCA Circuits

is Coulomb’s constant. It will be shown next that for all QCA devices/circuits,

the lowest energy configuration corresponds to the expected logic function.

Binary Wire: The simplest circuit in QCA is the two-cell binary wire with

input A and output B, as shown in Figure 3.3(a). The two possible energy

states, namely the aligned (B = A) and the anti-aligned states (B = A) are

shown in Table 3.1. The aligned state has the smallest energy and the two cells

in the binary wire tend to have the same polarization. Note that by symmetry,

the energy of state A = B = 1 is the same as the energy of state A = B = 0.

The energy of state that can be easily attained by symmetry are omitted from

Table 3.1 hereafter.


Device Cell State Energy (×αq2/a)A= B=

binary 0 0 −3.87wire 0 1 −3.44

1 0 −3.441 1 −3.87

2-cell A= B=inverter 0 0 −3.33chain 0 1 −3.99

A= B= F=+ to x 1 0 1 −6.093conversion 1 0 0 −5.5362-cell A= B=45 0 0 −3.610inverter 0 1 −3.7023-cell A= B= F=inverter 0 0 0 −5.398

0 0 1 −5.586A= B= C= F1= F2=1 1 0 1 1 −9.8001 1 0 0 1 −9.7861 1 1 1 0 −9.156

coplanar 1 1 1 0 0 −9.144crossing 1 1 1 0 1 −8.470

1 1 0 0 0 −9.1441 1 0 1 0 −9.1561 1 1 1 1 −8.483

A= B= C= D= O=majority 1 0 0 0 0 −9.57voter 1 0 0 1 1 −9.13

1 0 0 0 1 −9.131 0 0 1 0 −8.71

Table 3.1: Steady State Energy of QCA circuits

Inverter Chain: By rotating the cells 45, a binary wire becomes an inverter

chain, as shown in Figure 3.3(b). It can be observed that the lowest energy state

is B = −A.

Signal Propagation From an Inverter Chain to a Binary Wire: Some QCA

circuits use both the inverter chain and binary wire. A circuit block referred

to as “+” to “x” conversion (Figure 3.3(c)) is needed to propagate signal

between an inverter chain to a binary wire. A and B are the inputs (A and


B are part of the inverter chain) and F is the output (F can then be used to

drive a binary wire). According to the possible energy states shown in Table 3.1,

F = A = −B is the ground state.

Inverter: Two QCA cells placed at a 45 orientation is referred to as a

2-cell 45 inverter (Figure 3.3(d)), where A is the input and B is the output.

Essentially, 45 inverter is the same as a 2-cell inverter chain, and the calculation

yields its function of B = −A.

Three-cell INV: As shown in Figure 3.3(e), three-cell INV has output F

and inputs A and B (A should always equal to B). From the results shown in

Table 3.1, F has the opposite polarization of A and B in the ground state.

Coplanar Crossing: The coplanar crossing circuit consists of a a binary wire

that crosses an inverter chain (Figure 3.3(f)). A is the input of the inverter chain

(the vertical wire), while B is the input of the binary wire (the horizontal wire).

When A = 1, B = 0, all possible energy states are shown in Table 3.1. In all

different input combinations, the lowest energy state shows funcion is F1 = A,

F2 = B.

Majority Voter: The MV (majority voter) is the basic logic gate in QCA

circuits. When a MV has inputs A = 1, B = C = 0, as shown in Figure 3.3(g),

its possible state and corresponding energy is shown in Table 3.1. The lowest


energy state is D = 0 and F = 0. In all possible input combinations, the model

founds the output to be the majoriy of the inputs.

To verify the validity of the proposed mechanical model, the same circuits

discussed above have been simulated by QCADesigner [117]. In all the cases

above, the mechanical model yields the same steady state result as the simulation

result of QCADesigner. This shows that the proposed model can be used to

characterize the steady state behavior of all QCA circuit primitives, including

logic gates, interconnect structures and QCA systems that consist of these gates

and interconnections.

3.3 Entropy and Dissipation Analysis

3.3.1 Operation of the Mechanical Cell

Three possible types of physical reversible computing models have been sum-

marized in [11]: (a) Ballistic, (b) Brownian and (c) Clocked Brownian models.

The proposed model is a clocked Brownian model. The dissipation of a clocked

Brownian reversible machine is proportional to the speed of computing [11]. If

the process is slow enough to be quasi-equilibrium, then the machine is capable

to compute with no dissipation.


In molecular QCA, the electrons can only be located within a certain range

but not a specific point, because of the uncertainty principle in quantum physics.

Similarly, in mechanical model, the NULL, 1 and 0 states are defined such that

the rotation unit can have a Brownian movement within a small angle interval

given by [−δ, δ] (Figure 3.4). Also, this small range for Brownian movement is

necessary to analyze the entropy of the three states. The entropy of a cell in the

NULL state is hereafter denoted by S0.

movement Brownian

in small angle

−delta

+delta

(LOCK)

BetaBeta=90

+delta−delta

(RELAX)

Figure 3.4: Rotation unit with Brownian movement at a small angle

The following analysis assumes that the system driving the clocking unit can

store energy (a large, but still finite amount). The driving mechanism of clocking

unit provides or absorbs energy from the computing system during the different

phases of the working-cycle. It is also assumed that the energy exchange between

clocking unit and rotation unit is losses.

• First, in the mechanical model the cell is moved from the NULL state to

either the 1, or 0 state reversibly. With no loss of generality, we consider

the 1 state in this example. Initially, the shape of the cross section of the


sleeve is changed to a circle. During this change, W = −kBT log2γ2δ

of

work is done to the rotation unit and the heat exchange is Q = kBT log2γ2δ

(heat flows from the environment to the rotation unit), where γ is the range

of the possible positions of the rotation unit. The driver must be strong

enough to limit the rotation unit in [0, 90], i.e. γ < 90. Subsequently, the

shape of the cross section of the sleeve is changed to a square. During

this process, W = kBT log2γ2δ

of work is exerted to the rotation unit and

Q = −kBT log2γ2δ

(heat flows from the rotation unit into the environment).

This process is logically reversible: starting from the initial NULL state,

the cell goes into a final state specified by the polarization of the driver.

It is also thermodynamically reversible. The rotation unit performs zero

work. Applying the driver requires energy (given by Ep1) and the energy

is transferred into the clocking unit; Ep1 is the difference between the

potential energy of the driver and a NULL state cell and the potential

energy of the driver and a cell in a polarized (1/0) state. The the total

work by driver, rotation unit and clocking unit is zero. The total heat

exchange between the system and the environment is zero.

• Next, if the polarization of a cell in the LOCK phase is known, then it

is possible to place the cell to the NULL state (when the clock goes to


the RELAX phase) with no dissipation. This process needs an external

driver with the same polarization as the cell. Initially, when the shape

of the cross section of the (clocking unit) sleeve becomes circular, the

external driver keeps the rotation unit in a range smaller than [0, 90].

During this step, W = −kBT log2γ′

2δis exerted to the rotation unit and

Q = kBT log2γ′

2δ(also, γ′ is the range of possible positions of the rotation

unit). The driver must keep γ′ < 90. Subsequently, when the clock is

in the RELAX phase, the state of the cell changes into NULL. During

this process, W = kBT log2γ′

2δand Q = −kBT log2

γ′

2δ. This process is

also reversible and no heat is dissipated. There is an energy (given by

Ep2) that is transferred from the clocking unit to the driver. Ep2 is the

difference between the potential energy of this driver and a NULL cell

and the potential energy of this driver and a polarized cell.

Consider an entire clock period (from the RELAX phase to the LOCK phase

and then back to the RELAX phase), no energy dissipation will occur. From

the RELAX phase to the SWITCH phase, the potential energy Ep1 between

the driver and the charged balls flows into the clocking unit. Then from the

RELEASE to the RELAX phase, Ep2 will flow back from the clocking unit and

it becomes potential energy. Ep1 and Ep2 are established by the strength of the


drivers during these two phases. Thus, it is possible to find a Carnot cycle by

keeping the strength of the driver constant during two phases (i.e. , Ep1 = Ep2).

The reversibility of process discussed above depends on the polarization of

the external driver during the RELEASE phase. If the cell is not RELEASEd

under a driver of same polarization, one of the following scenarios will occur:

1) If there is no driver during the RELEASE phase, then a free expansion will

occur at the moment the cross section of the sleeve changes to a circular shape;

the rotation unit increases its range of possible angular positions from [0, 90] to

[0, 180]. There is no work and heat exchange in free expansion. Prior to free

expansion, W = −kBT log2902δ

is done to the rotation unit and Q = kBT log2902δ

(from the environment to the rotation unit). After the free expansion, W =

kBT log21802δ

and Q = −kBT log21802δ

. So, in the whole RELEASE phase, the

clocking unit exerts∑

W = kBT of work to the rotation unit and the system

dissipates kBT (∑

Q = −kBT ).

2) If the driver’s polarization is different from the cell, then energy dissipation

will occur. As illustrated in Figure 3.5, the driver will turn the rotation unit

to the other polarization state. In the LOCK phase, the polarization change

cannot occur because there is not enough energy overcome the energy barrier

between two polarization states. However, during the SWITCH phase, when


the cross section of the sleeve is changing from a square to a circle, the energy

required for the polarization change is small. When the rotation unit changes

into the new polarization, it will receive a kinetic energy Ek from this change and

vibrate around the new polarization position until damping due to the air slows

it gradually to the average thermal noise level. Damping will cause dissipation

of Ek. Prior to the polarization change, due to the driver, the angle β of the

rotation unit is [90 − γ1, 90) (where 0 < γ1 < 90). During the RELEASE phase

prior to the polarization change, W = −kBT log2γ1

2δand Q = kBT log2

γ1

2δ. Then,

a free expansion increases the possible range of β to γ′ = min(90 + 2γ1, 180).

In free expansion, W = 0 and Q = 0. During damping, Ek is dissipated into

the environment to slow down the rotation unit. Also, the driver finally limits

the range of β at an angle γ2. During this process, W = kBT log2γ′

γ2

and the

rotation unit receives Q = −kBT log2γ′

γ2

from the environment. After damping

till the end of the RELEASE phase, W = kBT log2γ2

2δand Q = −kBT log2

γ2

2δ.

So, in the entire RELEASE phase, the total work is∑

W = kBT log2γ′

γ1

and

Ek + kBT log2γ′

γ1

is dissipated. Ek, γ′ and γ1 are determined by the strength of

the driver. As the driver is strong enough to set a cell to a polarization with

high probability, then it must be in the order of kBT (according to Boltzmann’s

distribution). Approximately, Ek is given by Ek = kBT as γ′ = min(90 +


MovementBrownian

(RELEASE)2

BrownianMovement

Driver

Driver

Driver

Driver

Driver

Driver

Driver

4(RELEASE)−After polarization change

gamma’

3(RELEASE)

polarization change

7

(RELAX)

gamma1

−delta

+delta

−Before

(RELEASE)−After damping

gamma2

(RELEASE)6

51

(LOCK)

+vibration with Ek

−delta

+delta

Figure 3.5: RELEASE phase for a cell under a driver of different polarization


2γ1, 180) and 0 < γ1 < 90, kBT log2γ′

γ1

≥ 2. So, the RELEASE phase dissipates

at least 2kBT .

3) If the polarization of the cell is not known in the LOCK phase, it is

impossible to utilize any reversible process to set it to the NULL state. If a

constant driver is applied, then there is a 50% probability to be in the same

polarization as the cell, thus no energy is dissipated. However, there is also a

50% probability to be in the opposite polarization as the cell, thus at least 2kBT

will be dissipated. The expected dissipation is kBT . If no external driver is

applied, the process still dissipates Q = kBT .

As suggested in Section 2.2.1, the “free expansion” process when resetting a

computing cell with no knowledge of its state, is the source of the dissipation

lower bound for information loss. In the analysis above, the same conclusion is

attained for QCA.

3.3.2 Validation of Dissipation Analysis

In [106] [57], a quantitative calculation of the operation of several QCA circuits

were presented. The dissipation analysis is made on the same set of circuits as

in [106] [57] using the proposed mechanical model.


Erasure of a single cell: [106] has calculated the dissipation of setting and

erasing a single cell and reached the conclusion that when utilizing a so-called

“Demon cell” with same polarization as the cell being erased, the erasure process

has dissipation less than kBT ln 2. When no such “Demon cell” exists, dissipation

is larger than kBT ln 2. This agrees with the results of Section 3.3.1.

Two-cell signal path: Two cells in adjacent clocking zones constitute the sim-

plest circuit under the proposed model (Figure 3.6). Over five clocking phases,

its operation is as follows:

ExternalDriver

Tim

e1 2

Figure 3.6: A signal path with two cells

1) Initially, cells 1 and 2 are both in the NULL state, with clocking in the

RELAX phase. An external driver is applied to cell 1. With no loss of generality,

assume that the driver’s value is 1.


2) Cell 1 goes through the SWITCH phase. As described in Section 3.3.1,

cell 1 has a polarization of 1; the potential energy (Ep) between the driver and

cell 1 (denoted as Ed) and the energy between cell 1 and cell 2 (denoted by E1)

are transferred into the clocking unit.

3) Cell 1 goes into the LOCK phase and the external driver is removed.

Meanwhile, cell 2 acquires the value 1. The potential energy between cell 1 and

cell 2 (Ep = E2) is transferred into the clocking unit.

4) Cell 1 is placed in the RELEASE phase under the bias of cell 2, that is

now in the LOCK phase. As described in Section 3.3.1, cell 1 is under a same

polarization condition of bias, so no explicit dissipation occurs; E2 comes from

the clocking unit and becomes potential energy between cell 1 and cell 2.

5) Cell 2 is placed in the RELEASE phase under no bias, so at least Tk of

energy is drained from the clocking unit and dissipated. The clocking unit also

provides E1 as potential energy between cell 1 and cell 2.

Over the entire cycle of the circuit, the external driver provides Ed energy.

At least kBT of this energy is dissipated and the remaining energy goes into

the clocking unit. A two-cell signal path operates as the “one test cell plus

one demon cell” described in [106]. The mechanical model leads to the same

conclusion as calculated in [106]: the cell 1 works reversibly with cell 2 working


as its demon cell; the erasure of the cell 2 is irreversible because when it is

released there is no demon cell for it.

Shift register with one cell per stage (SR1): The shift register with one cell

per stage (denoted as SR1) can be viewed as the concatenation of the two-cell

signal path analyzed above. As illustrated in Figure 3.7, cell m receives its logic

value from cell m − 1. At the same time when cell m − 1 is in the RELAX

phase, cell m + 1 is in the SWITCH phase with the same value of cell m. While

cell m is in the RELAX phase, the signal propagates to cell m + 2. When a

cell (except for the first and last cells in the line of the shift register) is in the

SWITCH phase, then it is driven by the cell located prior to it. When it is in

the RELAX phase, it is driven by the cell located after it. As shown previously,

this behavior of the cells is reversible.

For a shift register with n stages, its operation consists of n + 2 phases. All

stages except the last one work reversibly. After passing one bit information

through SR1, the circuit receives Ed (as defined in the analysis for a two-cell

signal path) from the driver. From this energy of Ed, kBT is dissipated as the

result of an information loss at cell n and the rest of the energy goes into the

clocking unit. However, if the output of SR1 is connected to another circuit, then

cell n is released under the driving of that circuit. In this case, no dissipation


1 2 i n

Phase 1

Driver

Phase 2

Phase n

Pha

se n

+1

Phase n+2

1 2

21

i−2 i−1 i

Phase i−1

Phase i

n−1 n n−1 n

External

Figure 3.7: Shift register with one cell per stage (SR1)


will occur in SR1. As driver, SR1 provides energy to the next circuit, just as it

receives energy from its driver. The difference of Ed and the energy next circuit

receives flows into clocking unit. If SR1, its driver and the next circuit have

the same design parameters (cell size, distance and charge quantity), then SR1

will provide the next circuit with the same amount of energy of Ed. [106] [57]

treated SR1 as a chain of “demon” cells; their calculation confirmed that the

energy dissipated per cell per clock switching can be much less than kBT ln 2.

3.3.3 Energy Dissipation Analysis of Circuit Units

In this section, the entropy change and energy dissipation of various QCA cir-

cuits are analyzed. For ease of presentation, only negative charged balls in the

cell are presented in the figures in this section.

Shift register with multiple cells per stage (SR2): For a register whose stages

consist of different numbers of cells (SR2), the non-dissipation feature also ap-

plies. When the kth stage is in the SWITCH phase, its cells are driven by the

(k − 1)th stage. When it is in the RELEASE phase, its cells are driven by the

(k+1)th stage. So, as in SR1, the first n−1 stages in a n stage shift register work

reversibly. If SR2 does not drive other circuits, each cell in its last stage will

dissipate kBT energy. If it drives other circuits, the entire SR2 works reversibly


and does not dissipate any energy.

Fanout Circuit: For a fanout (Figure 3.8), every cell inside the circuit is

operated reversibly. However, there are two individual output cells. So, if they

are in the RELEASE phase without driving a subsequent circuit, the dissipation

is 2kBT , twice as much as the dissipation of a single cell. If both outputs transfer

information to subsequent circuits and are in the RELEASE phase while driving

these circuits, then the fanout circuit is reversible. The reversibility of fanout

is evident in the fanout-then-erase circuit in Figure 3.8. The eraser (cells 5 to

8) does not destroy information. Its inputs come from the fanout and can only

take “00” or “11” as values. The cell erases two copies of information into one;

it operates reversibly as discussed in Section 3.3.1.

For cell 2, the driver strengths in SWITCH and RELEASE phases are dif-

ferent. In SWITCH, Ep1 = Ed; in RELEASE, Ep2 = 2Ed. The energy difference

Ep2 − Ep1 = Ed is provided by the clocking driving mechanism. This analysis

shows that the fanout structure by itself does not necessarily result in energy

dissipation. The possible increase of dissipation is associated with the erasure

of an extra output cell.

Inverter: From the steady state energy calculation, it has been shown that

the two input cells of the three-cell inverter are in the RELEASE phase under


3a

a

Driver

External

21I

3

4

5

6

O

7

9

8

10

Figure 3.8: Fanout and Reversible Eraser

a same-polarization driver. So, only the output cell in the three-cell inverter

dissipates an energy of kBT when released and with no transfer of information

to a subsequent circuit. If the three-cell inverter connects to another circuit,

then the output cell operates reversibly, too. The inverter in Figure 3.9 consists

of an 1-to-2 fanout circuit and a three-cell inverter. So, it is also reversible.

3a

a

Driver

External

21I

3

4

O

5

6

7

Figure 3.9: One-input one-output inverter as one-to-two fanout and three-cellinverter

Majority Voter: In the MV, if the inputs are 111 or 000, no free expansion

or damping will occur and all cells operates reversibly. The voter cell erases 2

bit information reversibly and 2kBT of energy goes into the clocking unit. If


the input values are one of the remaining six possible combinations, then the

input cell with the minority input will dissipate kBT + Ed energy when released

under an opposite polarization driving condition (as shown in Figure 3.10). Ed

must be at least kBT to ensure that the model operates reliably, so at least

2kBT energy is dissipated. Assume all inputs of the MV are independent, there

is 25% probability that the MV gets equal valued inputs and does not dissipate

energy directly. But an energy of 2kBT goes into the clocking unit and will be

finally dissipated into the environment to keep a stable clocking. There is 75%

probability that the MV dissipates an energy of 2kBT into the environment.

Hence, the MV dissipates 2kBT heat on average.

2/aqα 2/aqα

(a) Before damping (b) After damping

EE

during RELEASE

during RELEASE

during SWITCH

Changing polarizatoin

Keeping polarization

Accelerated from here

Damped to stable position

Changed polarizatoin

3a

3a

a

=10.209 =10.156

Figure 3.10: Damping in Majority Voter causes dissipation


3.4 Landauer and Bennett Clocking Schemes

The clocking scheme that was assumed in the previous sections, is generally

referred to as Landauer clocking. Landauer clocking is the scheme utilized in

most QCA researches reported in the technical literature. Landauer clocking is

simple, however, it makes some circuits (such as the MV) to be irreversible and

dissipative. In [106][57], a different scheme (i.e. the so-called Bennett clocking)

has been proposed for QCA, under which MV can be non-dissipative. Figure 3.11

illustrates these two types of clocking scheme. The proposed model is used to

analyze and compare the operations of the two clocking schemes.

The basic principle of Bennett clocking is that the bit information is held in

place by the clock until an operation is completed by the circuit [57]. Then, it

is erased in the reverse order of computation, as illustrated in Figure 3.11(b).

Thus, every cell is switched and released when all other cells in the circuit are

in the same configuration. It is evident that every cell has a driver of same-

polarization when it is released. As per the conclusions drawn in Section 3.3.1,

every cell works reversibly. So, the computing process of the whole circuit is

reversible. Quantum-dynamic calculation has shown that energy dissipation per

switching event is much less than kBT ln2 for QCA circuits containing the MV

and fan-out [57]. Adopting Bennett clocking to make circuit reversible does not


require any change in QCA layout.

However, the control of Bennett clocking is more complex compared with

Landauer clocking. Additionally, in Bennett clocking the next operation cannot

begin until the circuit is released from the output to the input. For QCA, the

speed of a Bennett clocked computation is proportional to the timing depth

(number of clocking zones) of the circuit. By comparison, Landauer clocking

releases a cell after four phases (1 clock cycle) of quasi-adiabatic switching,

so that the cell can be used in the next operation. Landauer clocking leads

to a pipeline implementation (Figure 3.11) and an increase in computing speed.

Bennett clocking releases the cells from output to input, so the last cell is locked;

as for the input cells, they are released under no driver. As analyzed in previous

sections, the only energy dissipation in Bennett clocking occurs when the input

cells are released under no driver.

A two-to-one multiplexer (MUX) is used as an example to illustrate the ad-

vantages and disadvantages of Landauer and Bennett clocking schemes. The

schematic diagram and the corresponding layout of the MUX are shown in Fig-

ure 3.12; when Sel = 1, F = A; when Sel = 0, F = B. The clocking zone

assignments are the same for Landauer and Bennett clocking schemes and are

represented by different shaded colors and patterns in the layout. The timing


OperationNext

OutputReady

OutputReady

OperationNext

TIM

E

RELAX phase

SWITCH phase

LOCK phase

RELEASE phase

(a) Landauer Clocking (b) Bennett Clocking

Figure 3.11: Landauer and Bennett Clocking Schemes


diagrams for Laudauer and Bennett clocking schemes are depicted in Figure 3.13.

• If Landauer clocking is used, the delay between the inputs and the outputs

is 10; consecutive inputs can be applied at every clock cycle (4 clocking

zones). So, consecutive outputs are produced every clock cycle.

• With Bennett clocking, the delay between inputs and outputs is again 10

clocking zones. However, consecutive inputs can be applied with a delay

of 22 clocking zones, which is 4 times more than for Landauer clocking.

Bennett clocking results in a longer delay compared with Landauer clocking;

however, the energy dissipation of Bennett clocking occurs only at the input/output

ports and the internal energy dissipation of Bennett clocking can be made arbi-

trarily small. The energy dissipation of Landauer clocking is proportional to the

number of irreversible gates in the circuit. Clearly, there is a trade off between

power (and reversible computing) and delay when choosing the desired clocking

scheme for a QCA implementation.

3.5 Conclusion

A new mechanical-based model has been proposed for manual analysis of logic

operation and dissipation in QCA circuits. The objective of this model is to


A

Sel

B

F

clocking zones

5 6 7 8 94321 10

Fixed polarization cell

A

B

F

Sel

P=1P=0

P=0MV

MV

INV

MV

Figure 3.12: Two-to-one MUX Schematic and Layout Diagrams

provide an intuitive and classical view of the operation and energy in molecular

QCA. By avoiding a full quantum-thermodynamical calculation, it has been

shown that the proposed model is versatile in evaluating different features (such

as energy consumption for reversible computing and clocking schemes) at device

and circuit levels for molecular QCA implementation.

The steady state energies of various QCA devices have been calculated using

the proposed model. It has been shown that the mechanical model agrees with

the QCADesigner simulation regarding all basic QCA devices.

The proposed model has been used to characterize the dynamic behavior of

QCA circuits. It has been shown that this model is very effective in analyzing

different QCA circuits for reversible computing.

• The QCA shift register (irrespective of the number of cells per stage) is a

reversible circuit.


to primary inputFirst data applied

2

3

4

5

6

7

8

9

10

to primary inputSecond data applied

at primary outputFirst data available

to primary inputFirst data applied

2

3

4

5

6

7

8

9

10

at primary outputFirst data available

to primary inputSecond data applied

at primary outputSecond data available

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1

Time

SWIT

CH

LOCK

RELAX

RELEA

SE

(b) Timing of Bennett clocking scheme

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1

Time

17 18 19 20 21 22 23

(a) Timing of Landauer clocking scheme

Figure 3.13: Timing Diagrams for the MUX under Landauer and Bennett Clock-ing Schemes


• The fanout circuit in QCA does not necessarily result in energy dissipation.

The dissipation is associated with the disposal of the extra signals gener-

ated from fanout. Thus, fanout does not necessarily result in dissipation

if the extra signals are erased reversibly.

• The 3-cell inverter is a reversible circuit, though its operation apparently

erases information.

• The majority voter circuit in QCA shows an energy dissipation dependency

on the clocking scheme; MV is irreversible if Landauer clocking is used,

but reversible under Bennett clocking.

• There is a tradeoff between circuit reversibility (and therefore energy con-

sumption) and circuit delay when selecting a clocking scheme for QCA.

Chapter 4

Reversible and Testable Circuits

for QCA

While reversible logic has the advantage of building a system with virtually

zero energy dissipation, there are also benefit of improved testability in logically

reversible systems [14]. This chapter focuses on the testing of reversible QCA

circuits by considering different features such as fault model, test set cardinality,

observability and controllability. Thus, the reversible gates discussed in this

chapter are defined by their reversible logic function; they are not necessarily

thermodynamically reversible.

The design of QCA reversible gates must take into consideration the unique

64

CHAPTER 4. REVERSIBLE AND TESTABLE CIRCUITS FOR QCA 65

features of QCA, such as the majority voter based synthesis. In this chapter,

new reversible logic gates are defined using QCA technology. Figures of merit are

provided evaluating area, delay and synthesis. The testability of 1-D array of the

QCA reversible gates are analyzed under different conditions of controllability,

observability, fault models and test sets.

The following notation and assumptions are valid in this chapter:

1. As applicable to molecular implementations of QCA, missing/additional

QCA cell defects are used as defect model. We only consider defects in the

active devices (MV and INV) because the defects in QCA interconnect

were tackled in previous manuscripts [103][48]. It is assumed that each

gate only have one defect.

2. The function of a reversible gate is denoted in the following way. Let ai

represent the 3 bit pattern whose decimal value is i, e.g. a0 = 000, a5

= 101. A reversible logic gate can be represented by an input/output

mapping ai → aj . Evidently, the number of distinct output patterns can

not be larger than the number of distinct input patterns.

3. In fault characterization, the ith faulty input-output mapping is called

fault pattern FPi. Fault patterns are derived from simulation of defective

gates using QCADesigner v1.4 [115]. All cells used in the simulations have


size of 10nm × 10nm, and dot size of 2.5nm. Distance of adjacent cells is

set to 2.5nm.

4. The four phase clocking is used in all QCA designs and cells in the different

clocking zones are represented by different colors in circuit layout.

4.1 Reversible Gates in QCA

Two new reversible gates (denoted as QCA1 and QCA2) are proposed for QCA

implementation and compared with QCA implementation of other reversible

gates (Toffoli and Fredkin gate [107][76]).

Fredkin Gate: The Fredkin gate [32] has output functions given as follows

(where u, x1 and x2 are inputs of the gate):

v = u

y1 = u′x2 + ux1

y2 = u′x1 + ux2

The QCA implementation of the Fredkin gate is shown in Figure 4.1. The

Fredkin gate uses a two-level MV implementation with 6 MVs.


Clock Zone

1 2 30

v

1

2

3

6

7

8

9

10

11

12

14

15

16

17

18

13

19

21

20

22

23

24

25

26

27

28

29

y

5

4

P=−1

P=−1

P=1

u

x1

x2

P=1

P=−1

P=−1

y1

y2

3456789 12x

AND1

AND3

AND2

AND3

OR1

OR2

Figure 4.1: QCA Layout of the Fredkin Gate


Clock Zone

1 2 30

P=−1

x1

x2

P=+1

x3

y2

y1

y3

1

2

3

5

4

6

7

8

9

10

11

12

14

15

16

17

18

13

19

21

20

22

23

24

25

26

27

28

29

3456789 12

y

x

AND

MV1 MV2

OR

Figure 4.2: QCA Layout of the Toffoli Gate


Toffoli Gate: The output functions of Toffoli gate [107] are (where x1, x2

and x3 are inputs):

y1 = x1x2′ + x1x3′ + x1′x2x3

y2 = x2

y3 = x3

A QCA implementation of the Toffoli gate is presented in Figure 4.2. This is

also a two-level MV implementation with 6 MVs.

QCA1: The first gate designed for QCA implementation is referred to as

QCA1. Its output functions are:

y1 = MV (x1, x2, x3)

y2 = MV (x1, x2, x3′)

y3 = MV (x1′, x2, x3)

A QCA implementation of the QCA1 gate is shown in Figure 4.3. QCA1

requires only one-level MV implementation with 3 MVs.


10

Clock Zone

y2

y1

y3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

17

16

15

19

18

20

21

22

23

12345

x2 x3

x1

Figure 4.3: QCA Layout of QCA1


1

2

3

4

5

6

7

8

9

10

11

12

13

14

17

16

15

19

18

20

21

22

23

12345

10

Clock Zone

x2 x3

x1

y3

y2

y1

Figure 4.4: QCA Layout of QCA2


QCA2: The second gate designed for QCA implementation is referred to as

QCA2. Its output functions are:

y1 = MV (x1, x2, x3)

y2 = MV (x1, x2, x3′)

y3 = MV (x1′, x2, x3′)

QCA2 has similar properties to QCA1. A QCA implementation of QCA2 is

given in Figure 4.4. The implementation also requires one-level logic of 3 MVs.

The implementations of the four reversible logic gates can be compared and

the results are shown in Table 4.1. The number of clocking zones is presented

to quantify the delay between inputs and outputs. The geometric area (with

one QCA cell as unit area) occupied by each gate is provided. This is defined

as the rectangular area occupied by the design. The number of QCA cells used

in each design is also compared. The control cells are the input cells with fixed

polarization, which are used to program the MV as a 2-input OR, or AND gate.

All other cells are referred to as normal cells. As QCA1 and QCA2 have one-

level MV implementations and the Fredkin and Toffoli gates have two-level MV

implementations, the delay is smaller for QCA1 and QCA2 gates. QCA1 and

QCA2 occupy a smaller area with a smaller number of QCA cells so they also

have the advantage of circuit area.


Fredkin Toffoli QCA1 QCA2Clk Zones 4 4 2 2

MVs 6 4 3 3Area 30× 18 31 × 18 27 × 15 27 × 15

Ctrl Cells 6 2 0 0Normal Cells 185 167 146 147non-rotated 122 140 100 100

rotated 63 27 46 47

Table 4.1: Comparison Between the Four QCA Reversible Gates

The thirteen standard combinational functions proposed in [121] are being

built from the QCA reversible gates for comparison purposes. These functions

represent all 256 three-variable Boolean functions. The number of gates and the

number of clocking zones are reported in Table 4.2. An additional clocking zone

is used for interconnection between two gates. For example in Table 4.2, the

function F1 implemented by Fredkin gates requires two gates and has a total

delay of 9 clocking zones. This result is derived as follows: 4 clocking zones

are required for each Fredkin gate; interconnect between two gates requires an

additional clocking zone; so 4+1+4=9 clocking zones are needed.

Synthesis results for three benchmark circuits from [75] (MOD5, rd32 and

3 17) are used to compare the gates. These circuits were synthesized using

QCA1, QCA2 and Toffoli gate respectively, with the addition of CNOT gate [75].

The manual synthesis methods as applicable to reversible logic design (detail

described in [72]) were used. The CNOT gate implements the logic functions

y1 = x1; y2 = x1 ⊕ x2 A QCA implementation of the CNOT gate is shown in


Functions Fredkin + INV Toffoli + INV QCA1 QCA2# of # of clk # of # of clk # of clk # of clkFre. INV zone Tof. INV zone QCA1 zone QCA2 zone

F1 = AB′C 2 0 9 2 0 9 2 5 2 5F2 = AB 1 0 4 1 0 4 1 2 1 2

F3 = A′BC + A′B′C′ 2 1 9 2 1 9 2 5 2 5F4 = A′BC + AB′C′ 2 0 9 3 1 9 3 8 3 8

F5 = A′B + BC′ 2 0 9 2 0 9 2 5 2 5F6 = AB′ + A′BC 2 0 9 3 0 9 3 5 3 5

F7 = A′BC 3 1 9 3 2 9 3 5 3 5+ABC′ + A′B′C′

F8 = A 1 0 4 1 0 4 1 2 1 2F9 = AB + AC + BC 3 1 9 4 0 14 1 2 1 2

F10 = A′B + B′C 1 0 4 3 0 9 3 5 3 5F11 = A′B 3 1 9 1 0 4 4 5 4 5

+BC + AB′C′

F12 = AB + A′B′ 1 1 4 1 0 4 2 5 2 5F13 = ABC′ + A′B′C′ 2 2 9 2 1 9 2 5 2 5

+AB′C + A′BC

Table 4.2: Reversible Gate Implementation of Thirteen Standard Functions

Figure 4.5. This implementation requires an area of 15 × 15 and has a delay of

4 clocking zones.

The synthesis results are given in Table 4.3, showing different figures of merit:

“Gate” identifies the number of gates used in the QCA implementation; “Adevice”

is the rectangular area occupied by the active devices (gates) and “Atotal” is the

rectangular area occupied by the entire layout, including interconnections; “Clk”

shows the number of clocking zone used. Note that INV is not considered as an

active gate, but rather part of the interconnect, because in most cases the INV

function can be achieved as part of the interconnect using an inverter chain.

The benchmark synthesis results confirm the findings established previously for

the thirteen standard functions. QCA1/QCA2 gates with CNOT have similar


Clock Zone

1 2 30

x2

P=1

P=−1

P=−1

AND1

AND3 OR1

x1

y1

y2

3456789 12

1

2

3

6

7

8

9

10

11

12

14

15

13

5

4

y

Figure 4.5: QCA layout of the CNOT gate

figures of merit. QCA1 and QCA2 do not show much improvement in terms of

area, but the number of clocking zones (and therefore operating speed of the

synthesized circuit) is significantly lower synthesis results with Toffoli gate.

4.2 Defect Analysis and Gate Testing

In QCA manufacturing, defects can occur in both the chemical synthesis phase

(in which the QCA cells are manufactured) and the deposition phase (in which

the QCA cells are attached to a substrate). Defects are more likely to occur

in the deposition phase than in the chemical synthesis phase, which result in

perfectly manufactured cells being imperfectly placed in the substrate [64]. In


Bench 3 17 mod5 rd32

MV-based Gate 7 5 2(QCA1+CNOT) Adevice 2835 2035 810

Atotal 62×86 32×35 33×41=5332 =1120 =1353

MV-based Gate 7 5 2(QCA2+CNOT) Adevice 2835 2035 810

Atotal 62×86 32×31 33×41=5332 =992 =1353

clk 18 7 6

clk 18 7 6

Modified [75] Gate 4 3 4(Toff+CNOT) Adevice 1566 1008 1566

Atotal 67×60 37×4 57×51=4020 =1517 =2907

clk 14 9 10

Table 4.3: Benchmark synthesis results

our research, two types of defects are considered, namely the missing cell defect

and the additional cell defect. The former represents the case in which a cell

fails to attach to the substrate, while the latter represents the case of unwanted

cell deposition.

The four reversible gates have been characterized in the presence of a single

missing/additional cell defect. Using QCADesigner, fault simulation is per-

formed with exhaustive test set (consisting of 8 input input patterns) in each

case.

• Fredkin Gate: The results for the defects are shown in Table 4.4. All

possible missing/additional cell defects in MV, INV, fan-out and L-shape


Fredkin Gate

Input Fault FPVector Free 1 2 3 4 5 6 7 8 9 10 11 12 13 14

a0 a0 a0 a1 a1 a0 a1 a0 a1 a2 a2 a0 a0 a2 a2 a0








Toffoli Gate

Input Fault FPVector Free 1 2 3 4 5 6 7 8 9 10 11 12 13

a0 a0 a0 a4 a0 a4 a0 a0 a0 a4 a0 a4 a0 a4 a0








Table 4.4: Fault Patterns of Fredkin Gate and Toffoli Gate

wire have been simulated. From the simulation it can be observed that

some defects result in the same fault pattern. Altogether 14 unique fault

patterns are generated at the outputs.

• Toffoli Gate: For this gate, the results are shown in Table 4.4. For all

the possible missing/additional cell defects, 13 unique fault patterns are

generated at the outputs.

• QCA1: The results are shown in Table 4.5. 7 unique fault patterns are


QCA1 Gate

Input Fault FP1 FP2 FP3 FP4 FP5 FP6 FP7

Vector Freea0 a0 a0 a0 a0 a0 a0 a0 a4

a1 a1 a0 a0 a1 a1 a3 a1 a1

a2 a3 a3 a3 a3 a1 a3 a7 a7

a3 a5 a5 a4 a7 a5 a7 a5 a5

a4 a2 a2 a3 a0 a2 a0 a2 a2

a5 a4 a4 a4 a4 a6 a4 a0 a0

a6 a6 a7 a7 a6 a6 a4 a6 a6

a7 a7 a7 a7 a7 a7 a7 a7 a3

QCA2 Gate

Input Fault FP1 FP2 FP3 FP4 FP5 FP6 FP7

Vector Freea0 a1 a0 a0 a1 a1 a1 a1 a5

a1 a0 a0 a0 a0 a0 a2 a0 a0

a2 a3 a3 a2 a3 a1 a3 a7 a7

a3 a5 a5 a5 a7 a5 a7 a5 a5

a4 a2 a2 a2 a0 a2 a0 a2 a2

a5 a4 a4 a5 a4 a6 a4 a0 a0

a6 a7 a7 a7 a7 a7 a5 a7 a7

a7 a6 a7 a7 a6 a6 a6 a6 a2

Table 4.5: Fault Patterns of QCA1 Gate and QCA2 Gate

observed at the outputs.

• QCA2: The results are shown in Table 4.5. 7 unique fault patterns are

observed at the outputs.

Using the simulation results, the minimal test set that detects a single miss-

ing/additional cell defect with 100% coverage, has been established for each re-

versible gate. For a Fredkin Gate, the test has a cardinality of 3: < a1, a2, a7 >

(< 001, 010, 111 >). For a Toffoli Gate, the test set consists of three vectors:

< a3, a4, a7 >. For QCA1, the test set consists of three vectors: < a1, a3, a5 >

For QCA2, the test set consists of three vectors: < a0, a2, a4 >.


4.3 Test Reversible 1D Array with Single Fault

The testing of a 1D unilateral ILA, that is made of N identical modules is

considered (hereafter, the logic cell in the array is referred to as “module” to

differentiate from the QCA cell in the previous discussion) under a single fault

module assumption. The modules are made of the reversible gates presented in

Section 4.1 and the fault model presented in Section 4.2 is used. In array config-

uration, there is no direct controllability and observability for the intermediate

modules. Test vectors are applied to the primary inputs, results are observed

at the primary outputs. “Single fault” means that there is at most one faulty

module in the array. C-testability refers to the property by which the number

of vectors for testing the 1D array is independent of N .

If a fault-free reversible module is tested by an exhaustive set, then the mod-

ule following this module will receive an exhaustive test set. So, an exhaustive

test set will be applied to the only faulty module if the first module receives an

exhaustive test set from the primary input of the array. The erroneous output of

the faulty module can always be propagated to the primary output of the array,

because all the modules following this module are made of fault free reversible

gates. For the reversible gates discussed in this chapter, a test set of smaller

cardinality than an exhaustive test is found to achieve C-testability.


GateReversible Reversible

Gate Gate Gate

Reversible Reversible

1 2 i N

Primary Input Primary Output

Figure 4.6: 1D Array of Modules made of Reversible Logic Gates

• Fredkin Gate: For array of Fredkin gates as shown in Figure 4.6,

the 100% coverage test set consists of the three vectors: a1, a2 and a7. When

these vectors are applied to a fault free module, the output values are a2, a1

and a7. Therefore, in the 1D array the test vectors at the primary inputs can

be regenerated internally by the fault free modules prior to the faulty module.

So, a1, a2, a7 will be applied to the faulty module. Since this test set has 100%

coverage for a single gate, the faulty module will produce at least an erroneous

output. As every fault free module located after the faulty module has a function

given by a one-to-one onto mapping of the inputs to the outputs, then propa-

gation from the faulty module to the primary outputs is guaranteed. Thus, the

fault is detected.

• Toffoli Gate: Considering the function and the fault patterns in

Table 4.4, the full-coverage test set a3,a4,a7 for Toffoli gate is also sufficient

for detecting a Toffoli gate array. When applying the vectors a3, a4, a7 to a

module, a fault free module regenerates these vectors. So, under a single fault


assumption, this input pattern activates any possible fault in the array. With

all fault free modules following the faulty module, the feature of reversibility

ensures that any change of logic response can be propagated to the primary

output of the array.

• QCA1: The test set a1, a2, a3 can detect any single faulty module

in the array of QCA1 gates. As shown in Table 4.5, a1, a2/a5 and a3/a4 are

sufficient to test all possible faults of QCA1. a1 can be regenerated by the fault

free module. When applying a2 to the primary inputs of the array, a2 or a5

will be applied to odd numbered modules and a3 or a4 to the even numbered

modules. When applying a3 to the array, a2 or a5 will be applied to even

numbered modules and a3 or a4 to the odd numbered modules. Thus, 100%

coverage of a single faulty module can be guaranteed.

• QCA2: An array made of QCA2 gates can be tested by the test

set a0, a1, a2 and a3. As shown in Table 4.5, a0, a2/a5 and a3/a4 can test a

QCA2 gate with 100% coverage. When applying a0 to the primary inputs of the

array, a0 is regenerated at the inputs of all odd numbered modules. When a1 is

provided as input to the array, a0 will be regenerated at the inputs of all even

numbered modules. Similarly for a2 (a3) at the primary inputs of the array, a2

or a5 (a4) will be regenerated for the odd (even) numbered modules and a3 or


a4 (a5) for the even (odd) numbered modules. Therefore, every module in the

array is tested with 100% coverage.

4.4 Test Reversible 1D Array with Multiple Fault

4.4.1 Original 1D Array

If an array has any fault that result in an irreversible logic function (a function

with multiple-to-one mapping from input to output states), the number of dis-

tinctive outputs of the faulty module, under exhaustive test pattern, will be less

than a fault-free module. Thus, under exhaustive test, the number of output

patterns of this faulty array is less than a fault-free array. An exhaustive input

set can detect this type of faulty array, independently of the number of modules

in the array. As shown in Table 4.4, all the fault patterns of a Toffoli gate result

in an irreversible function. So, Toffoli gate array is always C-testable.

Fault masking can occur if a fault pattern is also a reversible function. Con-

sider an array consisting of two subarrays: the first subarray consists of only

modules suffering the same reversible fault pattern, while the second subarray

is fault free. This array can be modeled as equivalent to a fault-free k-module

array and an additional fault-equivalent (FE) module, as shown in Figure 4.7.


Consider the function of the whole array, while increasing the length of the faulty

subarray from 1 to k. The function of the FE module corresponding to the array

with n faulty modules, is denoted by FE(n). As the possible function of the FE

module is finite, for k sufficiently large, there must be a number n (n < k) such

that FE(n) is equal to some FE(m) with m < n. So, the n-module faulty array

has the same function as the m-module faulty array (m < n < k). These are

denoted as “array 1” and “array 2” in the figure. They receive the same input

and produce the same output when the entire k-module array is tested. As the

input test set to the k-module array is exhaustive and the modules in the array

have a one-to-one onto function, then array 1 and array 2 are tested exhaus-

tively. So, array 1 (that is assumed to be faulty-free) cannot be differentiated

from array 2 (that has m−n faulty modules). Fault masking occurs when there

are m − n concatenated faulty modules.

Consider a 3-input reversible gate as module; the number of possible FE

functions in a module is given by (23)! = 40320. If a reversible gate has more

inputs, the lower bound of masking probability is further reduced. However,

masking is not rare for the reversible QCA gates considered in this paper. For

example, FP7 of QCA1 results in a faulty reversible function. An array of 12

modules with FP7 fault behaves the same as an array of 12 fault-free modules.


n

m

array 1

(masked)

array 2

FF array

FF array

FF array

FF arrayModule

Module

Module

(1)FE

(m)FE

(n)FE

k

Fault−free module

Faulty module

Figure 4.7: One-to-one onto mapping and fault masking

So, fault masking occurs. A similar problem occurs for QCA2 with fault pattern

FP5. The Fredkin gate has two fault patterns resulting in reversible functions. If

a module with FP7 is followed by a module with FP13 (or FP13 followed by FP7),

then any test pattern cannot distinguish the faulty case with the concatenation

of two fault free modules. So, in an array made of Fredkin gates as modules,

fault masking occurs when fault patterns FP7 and FP13 appear in adjacent

modules.


Input

Primary Primary

Output

Observation Line

Figure 4.8: 1D Array of Reversible Module with Increased Observability

4.4.2 Array with Additional Observability

The 1D array with added lines for observability is shown in Figure 4.8. Different

fault models can be considered for the modules:

1. The traditional Stuck-At Fault (SAF), or line Bridging Fault (BF) are

irreversible faults, i.e. faults that will result in an irreversible function.

Therefore, they can be detected with a constant number of tests. The

array is C-testable and no additional control, or observable line is required

to the modules. However, these fault models are not sufficient for modeling

the faults in QCA [103].

2. Consider an arbitrary functional fault (AFF) model in which it is assumed

that a fault may cause an arbitrary change in the truth table of the circuit.

If there is any number of modules with irreversible faults, then the number

of possible output combinations of the array will be less than an exhaustive

combination (8 for 3 inputs). This scenario (irrespective of the number of

faulty modules) can be detected at the primary outputs. So, only those


reversible faults must be considered.

3. The most suitable fault model is referred to as the arbitrary reversible fault

model (ARF). In ARF, a fault is assumed to change the truth table of the

gate as long as the resulting function is still reversible. It is desirable to

achieve C-testability provided observability is added such that the outputs

of the intermediate modules are made directly observable. Unfortunately,

it will be shown next through an example that even if just a subset of the

ARF model is considered, the array is not C-testable.

4. Consider the so-called Single Pin Inversion (SPI) model as a subset of the

ARF model. In the SPI model, every module has at most one fault in

one of its input/output pins, such that an inversion of the signal occurs at

that pin. The inversion fault is very common in QCA circuits, because it

can easily result from imperfect deposition of QCA cells [103]. As shown

in Figure 4.9, if a fault appears between the nth output pin of the kth

module and the nth input pin of the (k + 1)th module, then detection can

only be guaranteed by observing directly the internal pins (in this case

pin n) between these two modules. The faulty pin can be any one of the

module pins, so we must observe every internal connection to detect all

SPI faults, i.e. this is a pathological case of an array as a fully observable


N

n

1

N

n

1

SPI Fault

Observe Line

k k+1

Figure 4.9: SPI (Single Pin Inversion) fault

system (i.e., every output of every module is observable).

The general fault model above gives pessimistic result for C-testability of

reversible arrays under multiple faults. A case-by-case study of aforementioned

reversible QCA gates, together with their specific input/output functions and

fault patterns, shows that C-testability is often achievable. All possible reversible

faults in a module must be considered when selecting lines in a module for

observability. Three conditions are proposed for selecting lines for observability

in each module of an array:

• Rule 1: If all reversible faults change some entries of the truth

table of one output signal, then this output signal should be a primary observable

line.

For example, consider a reversible module with fault free and fault patterns

given in Table 4.6. It has two reversible fault patterns: FP1 affects the output

y3, FP2 affects the outputs y2 and y3. By Rule 1, the truth table of y3 is changed


Input Fault-Free FP1 FP2

x1x2x3 y1y2y3 y1y2y3 y1y2y3

0 0 0 0 0 0 0 0 1 0 0 00 0 1 0 0 1 0 0 0 0 0 10 1 0 0 1 0 0 1 0 0 1 00 1 1 0 1 1 0 1 1 0 1 11 0 0 1 0 0 1 0 0 1 1 1

1 0 1 1 0 1 1 0 1 1 0 0

1 1 0 1 1 1 1 1 1 1 0 11 1 1 1 1 0 1 1 0 1 1 0

Table 4.6: Example for Rule 1

by all reversible faults, so if y3 is made a primary observable line in the modules,

then the array is C-testable.

The application of Rule 1 to QCA1 and QCA2 arrays makes them C-testable

with one observable line as primary output in each module. For the QCA1 array,

the only reversible fault pattern is FP7 and it modifies the output y3 of a faulty

module. So by observing this output, detection will occur at the faulty module.

Similarly, the QCA2 array is C-testable by making the output y2 as a primary

observable line in each module.

• Rule 2: If all reversible faults can be propagated to a module

output prior to masking, then such output should be a primary observable line.

In Table 4.7, a reversible module and a fault pattern are shown as an example.

The module has 3 reversible fault patterns: FP1 changes the output y3, FP2

changes the outputs y2 and y3, FP3 changes y2. FP1 and FP2 can be propagated

to y3 of the faulty module. FP3 can be propagated to y3 of the module after


Input Fault-Free FP1 FP2 FP3

x1x2x3 y1y2y3 y1y2y3 y1y2y3 y1y2y3

0 0 0 0 0 0 0 0 1 0 0 0 0 0 00 0 1 0 0 1 0 0 0 0 0 1 0 0 10 1 0 0 1 0 0 1 0 0 1 0 0 1 00 1 1 0 1 1 0 1 1 0 1 1 0 1 11 0 0 1 0 0 1 0 0 1 1 1 1 1 01 0 1 1 0 1 1 0 1 1 0 0 1 0 11 1 0 1 1 1 1 1 1 1 0 1 1 1 11 1 1 1 1 0 1 1 0 1 1 0 1 0 0

Table 4.7: Example for Rule 2

the faulty one, independently of the status (faulty or fault free) of this module.

By Rule 2, the selection of y3 as an observable line for each module makes the

array C-testable.

• Rule 3: If the above conditions cannot be satisfied, two or more

observable lines are needed in each module. Each of these lines serves to observe

part of the possible fault patterns and the union of the covered fault patterns

must be the entire possible fault pattern set.

By applying Rules 1 and 2, it is possible to observe different module outputs

to detect different fault patterns. Let the outputs lines of a reversible mod-

ule be y1, y2....yn. The possible fault patterns of each module are denoted by

FP1, FP2.....FPm. By observing an output line yi, a group of fault patterns can

be detected. Selecting observing lines requires to use minimum number of lines

to “covers” all the fault patterns. In the general case, the problem of selecting

multiple observing lines for observability is a set covering problem.


Consider the Fredkin gate for example; there are 2 reversible fault patterns,

FP7 and FP13. FP7 changes the output y3 and FP13 changes the output y2;

so, Rule 1 cannot establish a primary observable line for both fault patterns.

The output of two adjacent modules with FP7 and FP13 will result in masking;

hence, Rule 2 cannot be used. By applying Rule 3, y1 and y2 are selected

as multiple observable lines, because all posable reversible fault patterns are

detected.

Each of the above three rules gives a sufficient condition for constructing

a C-testable array. Rule 1 requires only one observable line per module and is

relatively easy to apply, so it is the preferable condition. Rule 2 requires also one

observable line, but propagation under different multiple fault patterns must be

established. Therefore, it can be applied if Rule 1 fails. Rule 3 requires more

than one observable lines and may account for a large overhead. Rule 3 should

be applied after Rules 1 and 2 have been unsuccessful.

4.4.3 Array with Additional Observability and Control-

lability

By adding lines for controllability as well as observability, the testability of the

array can be improved. A smaller number of test patterns will be needed to fully


test the array. Unfortunately, there is no technique for systematically building

and testing this type of array. 1D arrays made of Fredkin gate, QCA1 gate and

QCA2 gate are presented as examples.

For the Fredkin gate, fault masking can occur for an 1D array as described in

Figure 4.6. But the 1D array shown in Figure 4.10(a) is C-testable. In the array

of N modules, additional controllability is provided by setting the u input of

each module as a primary (vertical) input; additional observability is obtained

by setting the y2 output of each module as a primary (vertical) output. Let the

primary (horizontal) inputs x1, x2 of the first module in the array be denoted as

PI1, P I2. Let the ith module in the array be Gi, the input u of Gi be denoted

as Ui. The mapping between inputs and outputs of a fault free module as well

as a faulty module is shown in Table 4.4. The fault patterns are categorized into

two types: (1) FP1,FP8, FP9, FP10, FP11, FP12, FP13 and FP14 are type I; (2)

FP2,FP3,FP4,FP5,FP6 and FP7 are type II. The test vector set that detects

multiple faults is as follows:

1. First Test Vector: PI1 = 0, P I2 = 1, Ui = 0 for all i.

If the array is fault free, then all modules in the array will receive input

vector ux1x2 = 001 = a1. The expected (fault free) output at y2 of any

module in the array is “0”.


x1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

u

x1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

u

x1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

u

x1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

u

x1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

u

x1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

ux1

x2

v

y1y2

u

(a)

G1 G2 Gi GN

OutputInputPrimary

PI(1)PI(2)

U(1) U(2) U(i) U(N)

Primary

PI(1)PI(2)

G1 G2 G4G3

(c)

(d)

(e)

PrimaryInput

1

0

0

0

1

0

0

0

1010

1 0 1 0

0 1 0 1

PI(1)PI(2)

PrimaryInput

10(b)

0 1

G1 G2 G3 G4

0

0

1

0

0

0

1

0

U(1) U(2) U(3) U(4)

U(4)U(3)U(2)U(1)

U(i−1) U(i) U(i+1) U(i+2)

Gi0

0

1

0

0

0/1

0 1

Gi+1 Gi+2Gi−11 1

Input

0

1

0

1

0

1

0

00

00 0 0GNG2 GiG1

U(1) U(2) U(i) U(N)

0/1(fault−free/faulty)

0/1(fault−free/faulty)

PrimaryOutputPrimary

U(1) U(2) U(i) U(N)

Gi+1 GNGiG1

PI(2)PI(1) 11

1/01

1

1

1

(fault−free/faulty)11 1/0

11 1 1

PrimaryOutput

Figure 4.10: C-Testability of 1D Fredkin Gate Array (Added Observe and Con-trol lines)


2. Second Test Vector: PI1 = 1, P I2 = 1, Ui = 1 for all i.

If the array is fault free, then all modules in the array will receive as input

ux1x2 = 111 = a7. The expected (fault free) output at y2 of any module

is “1”.

3. Third Test Vector: PI1 = 1, P I2 = 0, Ui = 0 for i = 1, 3, 5, 7.... and Ui = 1

for i = 2, 4, 6...., as shown in Figure 4.10(b).

If the array is fault free, the input vector ux1x2 = 010 = a2 is applied to

all Gi (for i an odd integer). The expected output at y2 of Gi is “1” for

odd i and “0” for even i.

4. Fourth Test Vector: PI1 = 0, P I2 = 0, Ui = 1 for i = 1, 3, 5, 7.... and

Ui = 0 for i = 2, 4, 6...., as shown in Figure 4.10(b).

If the array is fault free, ux1x2 = 010 = a2 is applied as input vector to

all Gi (for i as an even integer). The expected output at y2 of Gi is “0”

for odd i and “1” for even i.

Initially, it will be shown that if the array contains any (single or multiple)

type II fault pattern(s), detection is accomplished by observing y2 as primary

output of the modules using the first and second test vectors. When applying

vector 1, all Ui = 0 and v = u for all modules, every module (either faulty or

fault free) will have as input x1 = 0. Therefore, any module in the array has


ux1 = 00; so, if a module with fault pattern FP2,FP3,FP5 or FP7 is present,

then the y2 output of that module will be “1” instead of the expected “0”. Thus,

these fault patterns will be detected by vector 1. Similarly, when applying vector

2, all Ui = 1 and PI1 = 1, P I2 = 1; therefore, each module in the array will have

input ux1 = 11. If a module with fault pattern FP4 or FP6 is present, the y2

output of that module is “0” (instead of the expected “1”). Thus by applying

vector 1 and vector 2, any number of type II fault patterns can be detected.

Consider next the case in which the array contains faulty modules with only

type I fault patterns. Let the faulty module that is closest to the primary inputs

be Gi, i.e. only fault free modules exist from the primary inputs to Gi. Gi must

have one of the type I fault patterns, i.e. FP1,FP8 ,FP9 ,FP10 ,FP11 ,FP12

,FP13 or FP14. If i is odd, the third vector ux1x2 = 010 to Gi is applied; if

i is even, then the fourth vector ux1x2 = 010 to Gi is applied. In both cases,

Gi will have as inputs ux1x2 = 010 and the expected output is vy1y2 = 001;

therefore, Gi+1 is expected to have as inputs ux1x2 = 100 and generate a “0”

at the output y2, as shown in Figure 4.10(c). If Gi has fault patterns FP8 ,FP9

,FP10,FP12 ,FP13 or FP14, Gi will produce a “1” at the output y1, thus Gi+1

will have as inputs ux1x2 = 101. Since Gi+1 is either fault free, or it generates

one of the type I fault patterns, then Gi+1 will produce a “1” (instead of the


expected “0”) at the output y2 (as shown in Table 4.4), thus, the fault can

be detected. Assume that Gi generates FP1. When the first vector is applied,

Gi will have as inputs ux1x3 = 001, at the y2 output a “1” will be produced

(instead of the expected “0”). So, this fault can also be detected. The only

other case is that Gi has as fault pattern FP11, it will be shown next that the

second vector can detect it. When the second vector is applied, Gi will have

as inputs ux1x2 = 111, the expected value of the y2 output of all modules is

“1”. Since G1 has as fault pattern FP11, then it will a “0” (instead of a “1”)

at the y1 output. So Gi+1 has as inputs ux1x2 = 110. Gi+1 is either fault free

or contains one of the type I fault patterns; so Gi+1 will produce a “0” (instead

of the expected “1”) at the primary output y2 (as shown in Table 4.4), thus

detection is accomplished.

Similarly, the testing of QCA1 array and QCA2 array can be found. (The

detailed proof of the test vectors is presented in [72].) For QCA1, additional

controllability is provided by setting x3 of each module as a primary vertical

input; additional observability is obtained by setting y3 of each module as a

primary vertical output. Let the primary inputs for x1 and x2 of the first

module in the array be denoted as PI1 and PI2; the primary outputs for the

y1 and y2 outputs of the last module be denoted as PO1 and PO2 and the ith


module in the array be denoted by Gi. If x3 of Gi is denoted by Ui The test

vector set that detect any multiple faulty modules, is given as follows:

1. First Test Vector: PI1 = 0, P I2 = 0, Ui = 1 for all i.

2. Second Test Vector: PI1 = 1, P I2 = 0, Ui = 1 for all i


for i = 2, 4, 6....

For QCA2, additional controllability is provided by setting the x2 input of

each module as a primary input; additional observability is obtained by setting

the y2 output of each module as a primary output. Let the primary inputs

at x1, x3 of the first module in the array be denoted as PI1, P I2; the primary

outputs at the y3, y1 outputs of the last module be denoted as PO1, PO2. Let

the ith module in the array be Gi, the input x2 of Gi be Ui. The test vector set

that detect any multiple faulty modules, is given as follows:

1. First Test Vector: PI1 = 0, P I2 = 0, Ui = 0 for all i

2. Second Test Vector: PI1 = 1, P I2 = 0, Ui = 0 for all i


for i = 2, 4, 6....


4. Fourth Test Vector: PI1 = 0, P I2 = 0, Ui = 0 for i = 1, 3, 5, 7.... and

Ui = 1 for i = 2, 4, 6....

4.5 Conclusion

This chapter has presented a comprehensive analysis of reversible and testable

circuits implemented in molecular QCA. Two new reversible gates (denoted

as QCA1 and QCA2) have been proposed. After comparing QCA1, QCA2

gates with Fredkin gate and Toffoli gate, it is shown that QCA1 and QCA2

gates are more preferable for QCA implemetation when considering both circuit

area and circuit speed. Albeit the irreversible logic MV is used in the design

of QCA1 and QCA2 gates, it has been shown in the literature that different

clocking arrangements can be used in QCA to make circuits containing MV

work reversibly [106].

In this chapter, more attention is paid to the testing of one-dimensional QCA

reversible gate arrays under single and multiple faulty modules. This analysis

has encompassed different features as related to the assumed fault model, the

cardinality of the test set and controllability/observability in the intermediate

modules of the one-dimensional array. Table 4.8 shows the C-testability of one-

dimensional arrays made of Toffoli, Fredkin, QCA1 or QCA2. The first column


Module Faults Test Set Type of ArrayS/M Cardinality

Toffoli S 3 1D arrayM 3 1D array

Fredkin S 3 1D arrayM 4 1D array with 1OB, 1COM 8 1D array with 2OB

QCA1 S 3 1D arrayM 3 1D array with 1OB, 1COM 8 1D array with 1OB

QCA2 S 4 1D arrayM 4 1D array with 1OB, 1COM 8 1D array with 1OB

Table 4.8: Benchmark result

of the Table is the type of gate used in the module of the array. The second

column shows the fault assumption: “S” stands for single faulty module and “M”

stands for multiple faulty modules. The third column shows the cardinality of

the test set for detection, i.e. the number of vectors in the test set. The last

column is the type of array. For “1D array”, only the inputs of the first module

can be controlled and only the outputs of the last module can be observed. For

“1D array with 1OB, 1CO”, each module has one controllable input and one

observable output. For “1D array with 1OB”, each module has one observable

output. For “1D array with 2OB”, each module has two observable outputs.

Chapter 5

Fault Tolerance of Reversible

QCA Circuits

The manufacturing of molecular QCA circuits, like other nano-scale technologies,

suffers from the problem of a high fault rate. To assemble a reliable comput-

ing system with QCA, fault tolerant techniques must be adopted. For a QCA

system with a high failure rate, a potential fault tolerance technique consists of

tolerating both high permanent manufacturing and operational (transient) fault

rates. Due to the inability of current nanotechnology, the system is likely to be

unreliable when manufactured (at time 0), so the treatment of transient faults

99

CHAPTER 5. FAULT TOLERANCE OF REVERSIBLE QCA CIRCUITS100

during time [0, t] has not yet been addressed. In our research, only manufactur-

ing faults are considered in fault analysis.

The nature of fault tolerance has intrinsic conflicts with the idea of reversible

logic: fault tolerance techniques require that information generated by faulty

modules be masked and discarded while reversible logic requires no information

loss during computing. Therefore, adopting fault tolerance will effect the dissi-

pation of reversible QCA circuits. In this chapter, a fault tolerance technique

for QCA circuit is presented and its impact on the dissipation of QCA reversible

logic is discussed.

5.1 Fault Tolerance in QCA Using Majority Mul-

tiplexing (Maj-MUX)

Fault tolerant schemes popular in VLSI are not fully adequate to handle the

expected fault rates of QCA. A novel fault tolerant scheme referred to as ma-

jority multiplexing (Maj-MUX) has been proposed in [94]; it combines the nand-

multiplexing scheme originally proposed in [114] with a 3-input majority voter

(MV) to provide good fault tolerant capabilities. This fault tolerance technique

is suitable for QCA because the MV is the basic logic gate in QCA and the


3-input MV requires only 5 QCA cells. An evaluation of this technique and

comparison with other hardware redundancy techniques are presented in this

section.

5.1.1 Hardware Redundancy Techniques in Literature

Different types of redundant scheme have been proposed and used for VLSI;

they are also applicable to QCA.

TMR (Triple Module Redundant) is a widely used fault tolerant technique.

It can be implemented in QCA as illustrated in Figure 5.1. TMRs can be

cascaded to further improve the system’s reliability. If the MV is assumed to

be fault free, then every stage in the cascaded TMR system can improve the

signal reliability to Rout = (Rin)3 + 3(Rin)2(1−Rin) where Rin is the reliability

of the input signal. The reliability of outputs of the TMR stage (Rout) is higher

than the reliability of the inputs (Rin) when Rin > 50%. If this is extended

to the NMR (N-Module-Redundant) scheme, then the reliability is improved to

Rout =∑(N−1)/2

i=0 (Ni )(Rin)N−i(1 − Rin)i, when Rin > 50%. The TMR scheme is

advantageous for QCA because the 3-input MV is also the basic QCA device.

The reliability of a TMR system with a non-perfect MV is Rsys = RMV ×


1

2

m

1

2

m

1

2

m

1

2

m

1

2

m

1

2

m

Module 1

Module 2

Module 3

......

......

......

......

......

......

......

............

............

......

In_1In_2

In_m

Out_1Out_2

Out_m

I

I3

I1

3−MV3−Fan

OI2O2

O1

O3

Figure 5.1: A TMR system in QCA

[(Rm)3+3(Rm)2(1−Rm)], where Rsys is the system reliability, Rm is the reliabil-

ity of a module (where RMV is the reliability of the non-perfect MV). To improve

the system reliability using TMR, it is required that RMV > 89≈ 0.8889. With

RMV > 0.8889, modules with Rm ∈ (3RMV −

√9R2

MV−8RMV

4RMV,

3RMV +√

9R2

MV−8RMV

4RMV)

can have improved reliability using TMR.

If the reliability of each module is too low for TMR, a concatenated TMR

system (Figure 5.2) can be employed. Rm i denotes the reliability of the output

signals of the modules at stage i. By dividing a large module into serially

connected stages, the reliability of each stage (Rm i) is suitable for a TMR


MV

. . .

. . .

. . .

MV MV

Module n

Module n

Module n

n−th stage

ModuleEntire Module1 . . . Module n

Module1

Module1

Module1

1st stage (n−1)th stage

a) Divide executive module into stages

b) Apply TMR to every stage

Figure 5.2: Concatenated TMR System

MV

MV

MV

MVMV

MV

MV

Module

Module

Module. . .

. . .

. . .

Module

Module

Module

Output of1st stage

Output of(n−1)th stage

Output ofn−th stage

Figure 5.3: A TMR system with MV redundancy

scheme. The reliability of a system with n stages is

Rsys1 =n

∏

i=1

RMV × [R3m i + 3R2

m i(1 − Rm i)]

This reliability is limited by the reliability of the MVs (i.e. RMV ). To avoid

this bottleneck, a TMR system can be modified as shown in Figure 5.3. The

reliability of this system is

[R3m 1+3R2

m 1(1−Rm 1)]×RMV ×n

∏

i=2

[(Rm i×RMV )3+3(Rm i×RMV )2(1−Rm i×RMV )]


MV redundancy can improve the reliability of a concatenated TMR system

when Rm i > 32(1+RMV )

.

Dynamic redundancy is used for systems with a high failure rate. A dynami-

cally redundant system can tolerate more faulty modules than an NMR system.

However, dynamic redundancy requires a more complex circuitry than the other

techniques investigated. Thus, it has a higher hardware cost and probability of

failure in the fault tolerant circuit. This is a considerable disadvantage given

the expected high defect rate of QCA.

NAND multiplexing [114] uses NAND gates and random permutation mul-

tiplexing to restore a bundle of faulty copies of the same signal. As shown in

Figure 5.4, there are Nbundle redundant copies of the computing module and its

output signal. The multiplexing unit U randomly permutates the signals. The

NAND gates are used to restore the signals. A probabilistic analysis has shown

that this technique provides better fault tolerance than NMR under a high fault

rate [94], albeit a high redundancy rate is needed.

It has been shown [114] that with an extremely large Nbundle, the tolerance

probability is at least 0.0107 for a NAND multiplexing system with NAND

gates as computing modules. In [28], it has been proven that NAND gates with


U

Nbundle Nbundle

U

Module

Module

Module

...

...

...

...

...

...

N stage restoration

1 restorative stage

Figure 5.4: A NAND multiplexing system

fault rate ǫ smaller than ǫ0 = (3−√

7)4

≈ 0.08856 can restore faulty signals to

a distinguishable level. With multiple levels of restorative stages and a large

amount of redundancy, the restored signal fault probability is a function of ǫ

only.

5.1.2 Fault Tolerant Capacity of Maj-MUX

For QCA, due to the compact implementation of a majority voter, a cascaded

voting scheme is a good basis for a fault tolerant solution. Due to its simple

QCA implementation and its better capability in restoring signals, the use of a

MV in place of a NAND gate in a NAND multiplexing technique is intuitively

appropriate (Figure 5.5). This arrangement was originally proposed in [94] and

is generally referred to as majority multiplexing (Maj-MUX). In this section, the

fault tolerant capabilities as well as signal restoration speed is analyzed.


MV

MV

MVMV

MV

MV

m

m

m

m m

NbundleNbundle

m

U

Module

Module

Module

...

...

...

...

...

...

N stage restoration

U

1 restorative stage

Figure 5.5: A majority multiplexing system

Perfect Multiplexing Unit

First, assume a perfect multiplexing unit. Using the method in [114], [94] has

shown that the tolerable MV fault rate of Maj-MUX scheme must be at least

0.0197. In this paper, the method in [28] is employed to pursue a more accurate

estimate of the tolerable MV fault rate required by Maj-MUX.

Assume the inputs of the MVs have an equal fault probability given by x

and the fault rate of the MVs is ǫ. Then, the probability x1 of the MV outputs

being faulty is:

x1 = 1 − (1 − ǫ)[(1 − x)3 + 3x(1 − x)2] (5.1)

The worst case scenario is analyzed, so fault compensation in masking is not

considered. To have an improved reliability, it must hold that x1 < x. Thus,

(2ǫ− 2)x3 + (3− 3ǫ)x2 + ǫ > x. Since x ≤ 1, then the solution of this inequality


0 0.02 0.04 0.06 0.08 0.1 0.120

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

MV fault rate (ε)

sig

na

l fa

ult p

rob

ab

ility

xa

xb

Figure 5.6: Range of fault probability improvement for Maj-MUX

is

xb < x < xa , where xa =(1 − ǫ) +

√

(9ǫ − 1)(ǫ − 1)

4(1 − ǫ); (5.2)

xb =(1 − ǫ) −

√

(9ǫ − 1)(ǫ − 1)

4(1 − ǫ)

If 19

< ǫ < 1, then (5.2) cannot be satisfied. Only when ǫ ∈ [0, 19], the signals

with x ∈ [xb, xa] can be restored to a fault probability equal to xb (Figure5.6).

Non-Perfect Multiplexing Unit

Next, consider a faulty multiplexing unit. For a Maj-MUX scheme implemented

in QCA, another important source of error is the interconnection, in particular

the random multiplexing unit (given by U in Figure 5.7). The probability that

faults in a multiplexing unit results in a signal error, is denoted by µ. The signal


fault probability after restoration is:

x1 = 1 − (1 − µ)(1 − ǫ)[(1 − x0)3 + 3x0(1 − x0)

2] (5.3)

To improve system reliability, it is required that x1 < x0. By substituting

(1 − µ)(1 − ǫ) with (1 − β), Inequality 5.3 has the same form as (5.1). So the

solution is also in the same form, i.e.

xd < x < xc , where xc =(1 − β) +

√

(9β − 1)(β − 1)

4(1 − β); (5.4)

xd =(1 − β) −

√

(9β − 1)(β − 1)

4(1 − β)

If 19

< β = (µ + ǫ − µǫ) < 1, x1 < x0 cannot be satisfied. Only when β ∈

[0, 19], the output signals from the computing modules with fault probability

x ∈ [xb−µ1−µ

, xa−µ1−µ

] can be restored to a fault probability = xb−µ1−µ

, after the Maj-

MUX.

5.1.3 Restoration Speed of Multiplexing

Restoration speed is defined as the fault probability improvement that can be

achieved with one restorative stage. It is a figure of merit that establishes the

number of restorative stages that are needed to assemble a reliable system.

For a NAND multiplexing system, the reliability (i.e. the probability of being


MV

MV

MVMV

MV

MV

m

m

m

m mm

U

Module

Module

Module

...

...

...

...

...

...

N stage restoration

U

1 restorative stage

0 X1XFault Prob.= Fault Prob.=

Figure 5.7: Fault in multiplexing connection

fault free or correct) of a signal after one restorative stage is given by (where x

is the probability of the signal being faulty prior to restoration):

if input=1:

P [FF after 1 nand] = (1 − ǫ)(1 − x)2

P [FF after 1 stage] = (1 − ǫ)(2 − P [FF after 1 nand]) × P [FF after 1 nand]

if input=0:

P [FF after 1 nand] = (1 − ǫ)(1 − x2)

P [FF after 1 stage] = (1 − ǫ)P [FF after 1 nand]2

For a Maj-MUX system, the faulty probability after one restorative stage is

given by

P [FF after 1 stage] = (1 − ǫ)[(1 − x)3 + 3x(1 − x)2] (5.5)


0.7 0.75 0.8 0.85 0.9 0.95 10.7

0.75

0.8

0.85

0.9

0.95

1

Before restoration

Aft

er

resto

rati

on

Fault−free probability: ε=0.03

1−stage2−stage3−stage4−stage5−stage6−stage

0.7 0.75 0.8 0.85 0.9 0.95 10.7

0.75

0.8

0.85

0.9

0.95

1

Before restoration

Aft

er

resto

rati

on

Fault−free probability: ε=0.03, Input=0


0.7 0.75 0.8 0.85 0.9 0.95 10.7

0.75

0.8

0.85

0.9

0.95

1

Before restoration

Aft

er

resto

rati

on



0.7 0.75 0.8 0.85 0.9 0.95 10.7

0.75

0.8

0.85

0.9

0.95

1

Before restoration

Aft

er

res

tora

tio

n

Fault−free probability: ε=0.05


0.7 0.75 0.8 0.85 0.9 0.95 10.7

0.75

0.8

0.85

0.9

0.95

1

Before restoration

Aft

er

res

tora

tio

n



0.7 0.75 0.8 0.85 0.9 0.95 10.7

0.75

0.8

0.85

0.9

0.95

1

Before restoration

Aft

er

res

tora

tio

n



(a) Maj-MUX (b) NAND-MUX (input=0) (c) NAND-MUX (input=1)

Figure 5.8: Comparison of restoration speed for Maj-MUX and NAND-MUX

Figure 5.8 shows the signal reliability after different numbers of restorative

stages. The NAND multiplexing and Maj-MUX schemes are compared under

different values of ǫ. The Maj-MUX scheme has a faster signal restoration speed

than the NAND-MUX scheme. For example, with the error rate of MV and

NAND both at ǫ = 0.03 and signal reliability before restoration = 0.8, Maj-

MUX needs 4 restorative stages to recover the signal to get a full fault tolerance,

while NAND-MUX needs 6 stages.


5.1.4 Summary of Comparison

The advantages of the Maj-MUX technique can be summarized as follows:

1. A Maj-MUX scheme requires a lower reliability for the majority voter

(0.1111) than nand multiplexing for the nand gate (0.08856). As in QCA

the MV requires a very simple implementation this suggests that Maj-

MUX is suitable for this technology.

2. Given a sufficient number of restorative stages and redundancy rate, the

tolerable fault rate of a executive module is high (for example, the module

can be 0.333 faulty if the fault rate of the MV is 0.1). Evaluation has

shown that the Maj-MUX scheme has a good restoration speed (for the

probability of being fault free).

3. The fault tolerant bound and final fault probability of a restored signal

are set by the reliability of the restorative stages. The restored signal

reliability is(1−ǫ)−

√(9ǫ−1)(ǫ−1)

4(1−ǫ). Using Taylor expansion, the reliability is

ǫ+3∗ǫ2+O(ǫ3). For ǫ < 0.1, the restored signal reliability is approximately

ǫ, as the reliability of restorative gate. In QCA, a MV has a every compact

implementation. As a MV requires only 5 QCA cells, then it is possible

to reach the gate reliability requirement of the Maj-MUX scheme. This


advantage makes the Maj-MUX scheme suitable for QCA implementation.

The following disadvantages are however incurred using the proposed scheme.

1. The redundancy rate considered in this work is very large. Some recent re-

search [94] shows encouraging results for multiplexing fault tolerance with

moderate to small redundancy. Ultimately, the fault tolerant capability of

this scheme will be limited by the redundancy.

2. An implementation of Maj-MUX will require a large amount of wire cross-

ing devices in QCA. The reliable operation of the wire crossing device is

therefore crucial for assessing the applicability of this fault tolerant scheme.

3. A multiplexing scheme (using a MV or a nand gate) can preserve a high

reliability of a system, however its output signals are provided in bundles.

So, for a traditional output signal, there will be a threshold (or voted)

logic to reduce the bundle-signal to a bit-signal. The reliability of these

“final” output gates may affect the system reliability.


5.2 Energy Dissipation of Maj-MUX Systems

with Reversible Modules

In the three parts that constitues a Maj-MUX system, the random permutation

multiplexing has a reversible function, so it can be implemented with a reversible

logic circuitry. The MV has three inputs and one output and is not logically

reversible. However, if there is no fault in the circuit, the use of this MV in a

voting system does not increase dissipation lower bound (as shown in Chapter 3).

The executive module is designed to be reversible disregarding its input pattern.

So a fault-free module will not dissipate energy when receiving faulty inputs. if

each module is reversible, then reversibility could be accomplished at system

level.

If a fault exists in a system, then there are two sources of possible dissipation:

the circuits that produce the fault and the fault tolerant circuits that mask the

fault. The dissipation in faulty module is not caused by fault tolerant technique,

so is not our interest. This work concentrates on the dissipation related with

fault masking.


5.2.1 System without Fault

In Chapter 3, it has been shown that fanout and MV of QCA do not necessarily

dissipate energy under unanimous inputs. So they can be included in reversible

computing circuits. Assume that in a system Ebit energy is used to encode a

bit of information. In order to be distinguished from thermal noise, Ebit must

be at least kT . For an 1-to-n fanout (denoted by n-fan), (n − 1) × Ebit need

to be injected into circuit to encode the extra n − 1 copies of information bit.

For an n-input MV (denoted by n-MV), when all the n inputs are the same,

(n − 1) × Ebit will be sent back to energy source. In both cases, there are no

lower bound of energy dissipation. So, if an 3-fan and an 3-MV are connected

together (Figure 5.9, the energy absorbed by the fanout can be send back to the

energy source when the n copies go through the majority voter and are reduced

to just 1 copy.

For example, a reversible TMR system has 3 reversible circuits modules.

The number of input and output signals of a reversible circuit are the same, and

this number is denoted by m. m 3-fan fanout structures are employed to send

copies of input signals to the three modules. m 3-MV and another m are used to

generate final outputs from modules’ outputs. If there is no fault in the system,

every 3-fan and 3-MV works as described above. So the whole system remains


3−Fan 3−MV

Figure 5.9: A circuit with 3-Fan and 3-MV connected together.

reversible. Energy source provides 2m × Ebit energy for the m 3-fan unit, then

get 2m × Ebit back from the m 3-MV. No dissipation will happen in the fault

tolerance circuit. (See Chapter 3 or [71, 42] for detail)

The above analysis can be applied to the majority multiplexing system shown

in Figure 5.10. Assume there are 9 executive modules in the system. There are

4m 3-fan fanout structures to copy primary input signals to the modules. 18m

3-fan fanouts and 18m 3-MV’s are used in the restorative stages, and 4m 3-MV

are used to generate final output. Energy source provides 44m×Ebit energy for

the 22m 3-fan unit, then get 44m×Ebit back from the 22m 3-MV. No dissipation

will happen in the fault tolerance circuit.


m

m

MV

MV

MV

Nbundle

m

...

...

U9

mo

du

les

Module1

Module1

Module1

MV

MV

MV

Nbundle

m

MV

MV

MV

m

m...

...

U

Module2

Module2

Module2...

...

Figure 5.10: Example of majority multiplexing system.

5.2.2 Dissipation in Fault Correction

Though a fault free reversible majority multiplexing system can have energy

dissipation infinitely close to zero, correcting faulty signals will cause energy

dissipation.

System with Fault in Executive Module

Here, we first assume the MV and multiplexing unit are fault free.

If the inputs of one 3-MV are different, 2Ebit of dissipation will happen for

every minority input. Ebit is defined in section 5.2.1. For a restoration stage,

its dissipation is generated by MVs with either 1 or 2 faulty inputs. Every

one of such MVs dissipates 2Ebit. Given the error rate ǫsig of its input signals,

dissipation of that stage is ED = [3ǫsig(1 − ǫsig)2 + 3ǫ2

sig(1 − ǫsig)] × 2Ebit. So,


for a n-stage restoration, the dissipation is

6Ebit × M ×n

∑

k=1

[ǫsig k − ǫ2sig k] (5.6)

where M is the total number of the restored signals and ǫsig k is the input

signal error rate of the k-th stage and ǫsig 1 is the error rate of initial signal.

ǫsig k can be calculated iteratively as:

ǫsig k = [ǫ3sig k−1 + 3(1 − ǫsig k−1)ǫ

2sig k−1] (5.7)

System with Fault in Module and MV

The fault in majority voter is considered in addition to the faulty signals from

executive modules. Because of the logical fault in MV, the signal error rate of

each restoration stage is higher than Equation 5.7. As shown in Equation 5.1,

the signal error rate with fault in MV is

ǫsig k = 1 − (1 − ǫ) × [(1 − ǫsig k−1)3 + 3(1 − ǫsig k−1)

2ǫsig k−1] (5.8)

where ǫ is the logical fault rate of MV. Since only dissipation in correcting the

error is considered, only fault free MV is included in this dissipation calculation.


The dissipation of an n-stage restoration is

6Ebit × M ×n

∑

k=1

(1 − ǫ)[ǫsig k − ǫ2sig k] (5.9)

System with Fault in Module, MV and Multiplexing Unit

Considering the fault in multiplexing unit, the signal error rate of each restora-

tion stage can be derived from Equation 5.3:

ǫsig k = 1 − (1 − β)(1 − ǫ) × [(1 − ǫsig k−1)3 + 3(1 − ǫsig k−1)

2ǫsig k−1] (5.10)

where β is the logical fault rate of multiplexing units. The input error rate of

MV’s in the restoration stages is 1−(1−β)(1−ǫsig k−1). So the total dissipation

from the fault correction of an n-stage restoration is

6Ebit × M ×n

∑

k=1

(1 − ǫ)[(1 − β)(1 − ǫsig k) − (1 − β)2(1 − ǫsig k)2] (5.11)

Summary

The output signal error rate of every restorative stage is decided by two factors:

the input signal error rate and the reliability of error correction system.

As plotted in Figure 5.11, the output signal error rate and dissipation of


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Input error rate

Resto

red

err

or

rate

Error rate before and after restoration


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.5

1

1.5

Input error rate

Dis

sip

ati

on

(× 6

Eb

it× #

sig

nal)

Dissipation in error correction


a) Fault : module only

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Input error rate

Resto

red

err

or

rate

Error rate before and after restoration, MV error rate=0.05


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.5

1

1.5

Input error rate

Dis

sip

ati

on

(x

6E

bitx

#s

ign

al)

Dissipation in error correction, MV error rate=0.05


b) Fault : module + MV

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Input error rate

Resto

red

err

or

rate

Error rate before and after restoration, ε =0.05,β =0.03


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.5

1

1.5

Input error rate

Dis

sip

ati

on

(x

6E

bitx

#s

ign

al)

Dissipation in error correction, ε =0.05,β =0.03


c) Fault : module + MV + Mux. unit

Figure 5.11: Error and dissipation in restorations of different stage number


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Input error rate

Resto

red

err

or

rate

Error rate before and after 6−stage restoration, β =0.01

ε =0

ε =0.02

ε =0.04

ε =0.06

ε =0.08

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.5

1

1.5

Input error rate

Dis

sip

ati

on

(x

6E

bitx

#s

ign

al)

Dissipation in 6−stage error correction, β =0.01

ε =0

ε =0.02

ε =0.04

ε =0.06

ε =0.08

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Input error rate

Resto

red

err

or

rate

Error rate before and after 6−stage restoration, ε =0.01

β =0

β =0.02

β =0.04

β =0.06

β =0.08

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.40

0.5

1

1.5

Input error rate

Dis

sip

ati

on

(x

6E

bitx

#s

ign

al)

Dissipation in 6−stage errore correction, ε =0.01

β =0

β =0.02

β =0.04

β =0.06

β =0.08

a) Change of MV error rate b) Change of mux. unit error rate

Figure 5.12: Error and dissipation of 6-stage restoration


Maj-MUX with different restorative stage is shown as an example, under the

fault assumptions given above. Figure 5.12 shows the change of output error

rate and dissipation of a 6-stage Maj-MUX restoration, with the change of error

rate of MV or multiplexing unit, respectively.

5.3 Conclusion and Discussion

In this chapter, the fault tolerant capacity and signal recovery speed of Maj-

MUX technology. It has been shown that this technology can improve system

reliability as long as the reliability of majority voter is higher than 0.1111. In

comparison with the nand-multiplexing technology, Maj-MUX has not only bet-

ter fault tolerant capacity but also higher signal restoration speed. In addition,

the compact implementation of MV in QCA makes Maj-MUX technology espe-

cially suitable for QCA circuits.

The energy dissipation in QCA reversible circuits that is caused by Maj-

MUX technology is analyzed. Without fault, this technology does not cause

extra dissipation. When faults exist, the energy dissipation caused by fault

correction has been derived from error rates of different parts of circuit. To

the best of our knowledge, our work is the first one to investigate the energy

dissipation cause by fault tolerance in reversible circuit.

Chapter 6

Review on DNA Self-Assembly

6.1 Overview

Self-assembly is the process in which small building blocks spontaneously as-

semble “bottom-up” and form a organized complex structure. It is a ubiquitous

process in nature. DNA is nature’s choice as the carrier of genetic information.

The information-bearing ability of DNA molecules have been extensively ana-

lyzed using biological self-assembly processes as occurring in living cells. DNA

molecule has been well studied and characterized in biology and chemistry. Be-

cause it is highly versatile and can be engineered, DNA is under intensive re-

search as a promising material for self-assembly.

122

CHAPTER 6. REVIEW ON DNA SELF-ASSEMBLY 123

A DNA molecule is a strand consisting of a chain of nucleotides. The nu-

cleotides in DNA has four types and the different types in the series of nucleotides

are used to encode information. Each type of nucleotide only bond with the nu-

cleotide of its complementary type. This feature enables DNA to behave selec-

tively according to the information contained in the nucleotide sequence. DNA

was first proposed as a material for nano-scale artificial self-assembly in [99].

DNA is most commonly known, as can be found in live cells, in the form of

“double-helix” macro-molecule comprising two DNA strands. The DNA macro

molecule used in DNA self-assembly is called DNA tile. It has a branched struc-

ture fabricated by hybridizing complementary DNA strands. Some segments

on the DNA strands that have unpaired nucleotides become sticky-ends of the

tile. A sticky-end preferentially bonds to another sticky-end with a complemen-

tary sequence of nucleotides. The selective bonding of sticky ends of different

tiles connects tiles into a well organized lattice structure. 1-dimensional or 2-

dimensional DNA assemblies with controlled periodic or aperiodic patterns have

been reported using various DNA tile structures [52][87][86][88][85].

DNA self-assembly can be exploited to manufacture novel nano-scale circuits.

Because DNA molecules do not have good electrical character, it is considered

unlikely to build electronics circuits directly with DNA through self-assembly.


But DNA can be the substrate material to selectively deposit electrical martial

or molecular devices so that the programmable control over the DNA structures

can be transferred to the electrical active structures. Metal wires and tubes have

been reported in [87][132]. Controlled deposition of single-molecule electronic de-

vices, such as transistors or quantum-dot cellular automata (QCA) cells has been

proposed in [41][12]. [87][88][85] have reported the use of DNA self-assembly as

templates for molecular electronics. Protein molecular attachments to specific

sites on DNA scaffolds have been demonstrated in [88][60]. As a “bottom-up”

fabrication technology, DNA self-assembly has the advantage that it can simul-

taneously build the desired structure in parallel [87]. This technique has been

advocated as a viable method for future “bottom-up” nanofabrication. It can

avoid the photolithography technology that is becoming increasingly expensive

and difficult to perform with the decreasing feature size.

The self-assembly of DNA tiles can also be used for executing algorithms. In-

formation is encoded in the spatial arrangement of the different sticky-end types,

as exposed on the crystal’s surface or perimeter [127]. DNA based computing

was first proposed in [2]. Algorithmic DNA self-assembly has been proposed

in [124] as implementation of the mathematical tiling theory presented in [120].

It has been proved that a set of tiles that uniquely fit together, can be used


to reproduce the space-time history of any Turing machine [126]. Thus, algo-

rithmic self-assembly of DNA tiles can theoretically be used for general purpose

computing. As an example, it has been demonstrated that satisfiability as a

combinatorial optimization problem can be solved by algorithmic self-assembly

[54].

6.2 Reported DNA Self-Assembly Experiments

Seeman [99] first proposed using DNA building blocks in self-assembly. Though

1-dimensional (linear) and 3-dimensional self-assembly of DNA have also been

studied, most of the research in literature focus on the self-assembly of 2-

dimensional DNA lattice. Different design of DNA tiles are proposed and ex-

periment results are reported.

Holiday junctions are the first tile structures proposed for DNA self-assembly [99].

DNA track and grid with controlled line spacing has been presented in [74].

DX (Double cross-over) tiles are a group of tile with similar structure pro-

posed in [34]. Winfree et al. used different types of DX tiles to create 2-D DNA

array with programmable periodic patterns [129]. Each DX tile structure can

be built into different “logical” type by engineering nucleotide types on the four

sticky ends. DX tiles has been used to build barcode structures by copying the


(a) Sierpinski Triangle pat-tern

(b) Image of assembled result.The asterisk indicates the toppoint of triangle and crosses in-dicate mismatch errors

Figure 6.1: Assembling of Sierpinski Triangle using DX tile. [92]

on an initial DNA strand through layer of DX tiles [131]. Two computational

operations, copying and binary counting, are demonstrated in [9] using DX tile

2-D assembly. It is proposed in [23] to use the pattern produced by binary

counting operation as template to build demultiplexer circuit. In [130], 1-D

assembly of DX tile is used to calculate the result of bit-wise XOR operation

on two multi-bit binary numbers. XOR operation is also implemented using

2-D DX tile assembly [92]. The the resulted assembly of this operation shows

the pattern called “Sierpinski Triangle”. The “Sierpinski Triangle” as shown

in Figure 6.1(a) is an aperiodic pattern that can potentially extend to infinite

size. Though contain several errors, the pattern is recognizable in the image of

assembled DNA crystal shown in Figure 6.1(b).


TX (Triple cross-over) tile structure has been reported to assembly 2-D DNA

lattices [52]. By engineering the TX tiles used, the lattice can have periodic

stripe pattern of different spacing. In [65], DNA nanotube built from TX tiles

has been reported. Using two different types of TX tiles, the 2-dimensional

assembly of TX tiles curves into a nanotube with uniform diameter ≈ 25nm.

Reported length of created nanotube is up to 20µm. Silver has been deposited on

the created nanotube to produce conductive nanowires [65]. Using TX tiles with

engineered structure, controlled organization of protein nano-spheres has been

reported in [60]. TX tiles are also proposed for DNA self-assembly computing.

In [73] accumulative XOR of an n bit data is computed by assembling a 2 × n

TX tile array. 2-D TX assembly is proposed to solve combinatorial problem,

such as satisfiability [53].

4×4 tile [132] has four equal-length arms forming the shape of a cross. There

are two sticky ends at the end of each arm. By changing the sticky end types

in the 4×4 tile, two different assemblies, nanotube and nano-grid, has been

fabricated [132]. The flat DNA nano-grid consisted of different type of 4×4

tiles. By engineering the center part of 4×4 tiles, protein molecule can only

deposit to some types of tiles. Thus the deposited protein molecules follow the

pattern of DNA grid. In [88], the periodic pattern made of the different tile


Figure 6.2: Fully addressable DNA array. Pattern shows letters “D”, “N” and“A” [86]

types in the grid has been used to build a 2-D protein array with controlled

periodic spacing. In [86], Park et al. have shown full control over every pixel in

the assembled pattern. The center pieces of different 4×4 tiles were engineered

to different thickness so that the cross-points in the grid have different height.

DNA nano-grids showing the letter “D”, “N” and “A” have been presented.

Figure 6.2 is the AFM (Atomic Force Microscope) image of the DNA grids.

This experiment showed that researchers are now able to define every individual

“pixel” in the assembly and generate arbitrary pattern wanted.


6.3 Model of DNA Self-assembly System

While some research on DNA self-assembly focus on the construction of basic

shapes or regular periodic patterns [132, 74, 66, 16], other researches aim at

generating complex pattern using algorithmic assembly. In algorithmic assem-

bly, the information bearing and selective bonding features of DNA are better

utilized. Each DNA tile acts as a computing unit. A constructing algorithm is

defined based on the designed computing behavior of tiles and the information

contained by the initial assembly. When the algorithm is executed in the assem-

bling process, the desired pattern is constructed. In order to characterize and

analyze the algorithmic assembly, various models have been proposed.

6.3.1 aTAM Model

The abstract Tile Assembly Model (aTAM) provides the basis for analysis of

algorithmic self-assembly in ideal cases [93][123]. It was originally proposed for

analyzing DX tile, but it is also applicable to the DNA tiles with 4 pairing ends,

such as the 4×4 tile and TX tile. A DNA tile is represented by a square in aTAM

(Figure 6.3). The four sides of the tile are denoted by east, south, west and south

and each side of a tile has a bond type. Figure 6.3 shows the modeling of a DNA

tile using a square tile in aTAM. The numbers near the sticky ends denote


different nucleotide sequence, in aTAM tile, the same notation is used to denote

the bond types representing the nucleotide sequences. The combination of bond

types determine the uniqueness of the tile. Each bond type has an associated

bond strength of 0 (null bond), 1 (single bond) or 2 (double bond). Two bonds

of the same type stick together with their corresponding bond strength. Two

bonds of different types do not bond together.

DX DNA Tile

Modeling1

42

3

1 4

32

aTAM Tile

sticky end distinguished by its "nucleotide sequence" by its "bond type"

side distinguished

Figure 6.3: The tile model in aTAM

In aTAM, a system parameter, called “temperature” τ , is defined to show

the condition of the environment (such as solution temperature, solution con-

centration, etc.) under which the assembly is performed. In aTAM, τ is defined

to be an non-negative integer. In most of the research τ is set to be 2, it is also

the case in our work unless specified otherwise. The aTAM model assumes an

ideal self-assembly process: a self-assembly always begins with a seed tile and a

tile can only be added to the existing DNA assembly if the total bond strength

on its sides binding it to the assembly is greater than or equal to τ .

A tile set is defined as a finite set of unique types of tiles that are used to


build a DNA assembly. A widely adopted style of tile set design uses three

categories of tile types in a tile set.

1. Seed tile is the first piece of the DNA aggregation. In aTAM model it is

assumed that self-assembly always begins with a seed tile.

2. Boundary tile builds two 1-D array of tiles as the boundary of aggregation

starting from the seed tile.

3. Rule tile builds the aggregation starting from the “L”-shape frame of seed

tile and boundary tiles. In the original design of this kind of tile sets, all

sides of a rule tile should have bond strength of 1.

All the tile sets discussed hereafter are designed with above stated style (named

original style), unless stated otherwise. Rule tiles with bond strength of 0 or 2

will be used as part of error tolerant method in Section 6.5.2 and Chapter 8.

Other style of tile set design have been proposed to generate some specific ag-

gregates such as a square with controlled size of n × n [1] .

This kind of tile sets are designed to self-assemble under τ = 2. As a conven-

tion, the seed tile locates at the southeast (lower right) corner and the direction

of growth is towards the northwest (upper left) corner. An empty location where


the total bond strength of its adjacent sides is ≥ τ is called a growth site. Ac-

cording to the aTAM, new tile can only be attached to a growth site. For the

rule tiles in the original style, a growth site is an empty location where there

are assembled tiles both on its south and east, because such a rule tile only has

single-strength bonds and needs two matched sides to attach to an aggregation.

A tile set of original style generates desired shape or pattern only when τ = 2.

If τ ≥ 3, no aggregation will be assembled; if τ ≤ 1, the aggregation shows an

random accumulation of tiles. A tile is called a matched tile if every one of its

sides matches the bond type of its adjacent side. If one or more sides of a tile

have mismatched bond type to their adjacent sides, the tile is a mismatched tile.

An assembly built from original style tile set consists only matched tiles if the

self-assembly process follow the aTAM model. In order to guarantee that a tile

set has one possible assembly result under aTAM, it is required that no two tile

types in the tile set have the same combination of south and east sides. [102]

Figure 6.4 (a) shows a tile set designed for assembling the Sierpinski triangle

pattern using this style. It consists of seven unique tiles: four rule tiles, two

boundary tiles and one seed tile. In the illustration, a dash line represents a null

bond, while a single line represents a single bond and a double line represents

a double bond. As shown in Figure 6.4(b), the seed tile is illustrated at the


southeast corner as starting point of self-assembly. Boundary tiles are utilized to

define the south and east boundaries of the pattern. Rule tiles fill the assembly

and form the desired Sierpinski triangle pattern (as shown in Figure 6.4(c)).

The direction of the growth for the DNA crystal is illustrated by the arrows in

Figure 6.4(b).

3

3

3

2

3

3 3

2

2

2 3

3

2

2 2

2

1

1 0

0

1

3 0

1

3

1 1

0

Rule Tiles Boundary Tiles

horizontal boundary

verticalboundary

Seed Tile

(a) Sierpinski Triangle Tile Set

1

1 0

0

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

3

1 1

0

3

1 1

0

3

1 1

0

3

1 1

0

3

1 1

0

2

2 3

3

3

3 3

2

3

3

3

2

2

2 3

3

2

2 3

3

2

2 3

3

2

2 2

2

2

2 2

2

2

2 2

2

3

3

3

2

3

3 3

2

1

3 0

1

3

1 1

0

3

3

3

2

3

3 3

2

2

2 3

3

2

2 3

3

EastW

est

North

South

(b) Growth of Tile Set (c) Assembled Pattern

Figure 6.4: The Sierpinski Triangle Tile Set

Using aTAM, Winfree proved in [124] that the two-dimensional DNA self-

assembly process can simulate the operation of a universal Turing Machine.

In [102], based on the aTAM, the complexity of a tile set is related with the

Kolmogorov complexity with the pattern it generates. This result shows that

the information used to present a tile set is asymptotically the same as the the

information necessary to present the pattern directly, in other word, the tile set


is “efficient” in bearing the pattern information.

6.3.2 kTAM Model

The aTAM model shows the ideal situation of DNA self-assembly in which no

error happens: Growth only starts from the seed tile; Tiles attach to the aggrega-

tion only if the total bond strength is larger than τ . Attached tiles never fall off

from the assembly. In practice, a tile may attach to the aggregation if the total

bong strength is not larger than τ . This process is called insufficient attach-

ment. Similarly, an attached tile may detach from the aggregation in a process

named The kinetic Tile Assembly Model (kTAM) [125, 128] is used to model the

dynamics of DNA self-assembly as a stochastic process of tiles attaching to and

falling off from the assembly. kTAM can be used to predict self-assembly with

respect to features such as growth speed and error occurrence. A simulator,

Xgrow has been developed based on kTAM [123].

In kTAM, the definition of tile set, tile and bond are the same as in aTAM.

In kTAM, the association and dis-association of tiles are characterized by two

reaction rates called on-rate ron (for association) and off-rate roff (for dis-

association). It is assumed that the on-rate (attaching) ron is determined only


by the tile concentration, which is represented by the parameter Gmc. The off-

rate roff,b is determined by the total bond strength b and the parameter Gse

representing temperature. These rates are given by:

ron = ka · e−Gmc

roff,b = ka · e−bGse

where ka is a constant, Gmc is the physical parameter measuring the tile concen-

tration, while Gse is the physical parameter measuring the unit bond strength, in

terms of the thermal noise energy under the temperature in which the assembly

grows. b is the total bond strength that holds the tile to the crystal, measured

by multiples of the unit bond strength.

Figure 6.5 shows the stochastic assembly process of Sirepinski tile set as-

sumed by kTAM model. In the figure, the ron for one empty location and the

off-rate for 5 attached tiles (roff |b=x, where x is the total bond strength) are

illustrated. Actually, each attached tile has its off-rate and each empty location

has a on-rate for every tile type that can be attached. Because of the limited

space, the figure can only illustrate a small fraction of the “rates” involved. The

probability of tile association and dis-association over a period of time can be

calculated from these rates.


1

1 0

0

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

3

1 1

0

3

1 1

0

3

1 1

0

2

2 3

3

3

3 3

2

3

3

3

2

2

2 3

3

2

2 3

3

2

2 3

3

2

2 2

2

2

2 2

2

2

2 2

2

3

3

3

2

3

3 3

2

roff| b=2

2

2 3

3

3

3 3

2

3

3

3

2

2

2 2

2

roff| b=1

roff| b=3 r

off| b=4

roff| b=2

3

1 1

0

1

3 0

10

1

1

0

rAll have the same on

Figure 6.5: Tile association and dis-association in kTAM

With the same tile concentration, any type of tile has the same probability to

attach to the aggregation, disregard of the total bond strength it has. However,

an insufficiently attached tile has exponentially higher probability to fall off,

because its total bond strength is smaller than a matched tile. Using these two

rates, the probability of the change of every tile and every empty location can be

determined. Thus, the thermal dynamical behavior of the self-assembly system

can be simulated probabilistically.

Analysis and simulation based on the kTAM provides insight of the growth of

DNA aggregation and the generation of error in self-assembly. Gmc and Gse rep-

resent the physical environment in which self-assembly takes place and therefore,

they have a significant impact on the [128]. It has been shown that a decrease


in Gmc (i.e. increasing the tile concentration) and/or an increase in Gse (i.e. de-

creasing the temperature, thus increasing the relative unit bond strength) will

cause an increase in the growth rate of the aggregation. However, this change

also increases the probability of generating errors. The ratio Gmc

Gseplays a role in

kTAM similar to the parameter τ in aTAM. For a tile set of original style, no

aggregation is assembled if Gmc

Gse> 2 and assembly occurs when Gmc

Gse≤ 2. It has

been shown [125, 128] that assembly with least errors occurs when this ratio is

slightly less than 2 and error rate in the assembled aggregation increases when

this ratio decreases from 2 until it becomes a random accumulation of tiles.

6.3.3 Model with Negative Bonding Strength

In aTAM and kTAM models, only the bond strength cannot only be non-

negative. The possibility of having repulsion between tiles was considered in [91].

The Accretive Graph Assembly Model and Self-Destructible Graph Assembly

Model has expanded the limit of bond strength in aTAM to include negative

value bond strength. With the presence of negative-strength bond, the sequence

of tile attachment will effect the final assembly. This poses new problems in

analyzing the result of self-assembly and designing tile set for desired pattern.


A series of problems related to the analysis of the assembly in these two mod-

els has been presented in [91]. Formal proof has shown which complexity class

each problem belongs to. Roughly speaking, the results in [91] have shown that

deciding the assembly results of tile sets is “computationally hard” under the

setting of these two models.

6.4 Error Modeling of DNA Self-assembly

DNA self-assembly are error prone. Both theoretical analysis and experimental

results have shown that under τ = 2, the error rate of original DNA self-assembly

without any error resilience or correction method is between 1% 10% [92, 128].

This high error rate will severely limit the application of DNA self-assembly.

Thus, study of error and error tolerance are important in the research. The

errors in DNA self-assembly can be classified into 4 major categories: growth

error, facet roughening error, spurious nucleation error and gross damage error.

6.4.1 Growth Error

The growth error refers to the type of error in which a mismatched tile attaches to

a growth site which another tile matches perfectly and should have been attached

to [127]. Figure 6.6 shows the occurrence of a growth error in a Sierpinski tile


set caused by the insufficient attachment of the shaded tile in Figure 6.6(a)(1).

After the initial insufficient attachment, more tiles can attach to growth sites A

and B as matched tile, but these tiles will result in erroneous pattern because

they are different from the tiles that should appear in those locations in a error

free aggregation. As stated in kTAM model, the mismatched tile has higher

probability of falling off, however, it is possible that additional tile matches

and attaches to growth sites A or B before it can fall off. As shown in Figure

6.6(a)(2), both the mismatched tile and the newly added tile has total bond

strength larger than 2. So, it is unlikely for the mismatched tile to fall off.

Growth will continue and erroneous pattern will appear in the final assembled

aggregation.

In [128], a technique called “kinetic trapping theory” was proposed based on

kTAM to model the generation of growth error. It was shown that the error rate

of growth error (ǫ) is ∝ e−Gse . Since the assembly growth rate (r) is ∝ e−Gmc

and Gmc ≈ 2Gse, the error rate and growth rate of the original tile set without

error tolerance have the relation: r ∝ ǫ2.


1

1 0

0

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

3

1 1

0

3

1 1

0

3

1 1

0

3

1 1

0

3

1 1

0

2

2 3

3

3

3 3

2

3

3

3

2

2

2 3

3

2

2 2

2

3

3

3

2

3

3

3

2

2

2 3

3

2

2 3

3

3

1 1

0

3

1 1

0

3

1 1

0

3

3 3

2

2

2 3

3

2

2 3

3

2

2 3

3

2

2 2

2

3

3

3

2

1

1 0

0

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

3

1 1

0

3

1 1

0

2

2 3

3

3

3

3

2

3

1 1

0

3

1 1

0

2

2 3

3

3

3

3

2

1

1 0

0

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

2

2 3

3

A

B

3

1 1

0

3

1 1

0

2

2 3

3

3

3

3

2

1

1 0

0

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

1

3 0

1

3

3 3

2

3

3 3

2

3

3

3

2

3

3

3

2B

A

(1) (2)

Insufficient Attachement

(a) Growth Error in Sierpinski

Insufficient Attachement

2

2 3

3

2

2 3

3

(1) (2)

(b) Facet Roughening Error in Sierpinski

Figure 6.6: Errors in the Sierpinski Tile Set

6.4.2 Facet Roughening Error

The facet roughening error (also called “facet nucleation error” or “nucleation

error” in some literature) refers to the error such that tile attaches to a location

in which no tile should yet be added [127]. In an error-free assembly process,

tiles should only be attached to growth site, empty location with assembled tile

on both its east and south sides. An example is shown in Figure 6.6(b)(1). The

shaded tile is insufficiently attached to an empty location next to a facet (a

smooth edge of tiles), prior to the growth of the tile to its south. The empty

location is adjacent to only one sidle-bond-strength side, so no attachment is


supposed to occur. The facet roughening error on a vertical facet (as shown in

Figure 6.6(b)) is referred to as the y-direction facet roughening error, while the

x-direction facet roughening error grows on a horizontal facet.

Without error tolerance, DNA self-assembly is prone to facet roughening er-

rors because an initial insufficient attachment will cause an uncontrolled spon-

taneous growth on a facet: After the occurrence of an insufficient attachment

(shown in Figure 6.6(b)(1)), more tiles can attach to growth site A or B as

matched tiles (shown in Figure 6.6(b)(2)). If prior to this initial error falling off,

an additional tile attaches to site A or B, then both the initial erroneous tile and

the newly attached tile are bond to the aggregation by a total bond strength of

2 and therefore they are unlikely to fall off again. Thus, a facet roughening error

occurs and it will grow into a new layer. Since the insufficient attachment that

starts the growth of this layer only has one side to match the aggregation, it has

a high probability to be an erroneous tile type (not the type that is designed

to assemble at that position). Thus, the whole layer that starts from that tile

is highly likely to be totally erroneous. After this erroneous layer becomes a

new facet, more facet roughening errors may grow on it. In addition to causing

erroneous pattern in the assembled aggregation, facet roughening error can also

cause infinite growth when a limited size of aggregation is desired.


A Markov chain model was proposed in [18] for facet roughening error. It

was shown that the error generation rate of this error in original tile set without

error tolerance is ∝ e−3Gse .

6.4.3 Spurious Nucleation Error

The spurious nucleation error refers to the error in which a crystal grows without

a seed tile [127]. In a tile set, the boundary tiles have double bonds, so a spurious

nucleation error occurs when the boundary tiles attach to each other with no

seed tile. The result of this error is an 1-D array of boundary tile [97]. If spurious

nucleation error combine with facet roughening error, this array can grow into

an uncontrolled 2-D aggregation.

The spurious nucleation error is hard to tackle because that not all the factors

involved in the generation of spurious nucleation error are presented in the kTAM

model. When growing DNA crystals from a DNA tile solution, because of the

interplay between surface and volume energy terms in a supersaturated solution,

crystals smaller than a critical size will tend to shrink, whereas large crystals will

grow [98]. This influence of surface energy and volume energy is not included in

the kTAM model. An analysis of the free energy of a crystal with the threshold

size separating shrinking and growing (named critical nucleus) is provided as an


augment to the kTAM model in [98]. Based on this augmented model, it was

shown that the rate of generating an aggregation with seed tile is ∝ e(2−k)Gse−Gmc ,

where k is the ratio of critical nucleus size to the rule tile size.

6.4.4 Gross Damage Error

The gross damage error [127] is generated not during the self-assembly process

of the error affected area, but after the area is finished. It features a large chunk

of the aggregation being taken away by some external cause. There are various

of causes for gross damage, such as cosmic ray or ripping or collision. Thus,

the generation of this error depends on the occurrence of these causes, not the

assembly process itself. After the gross damage error occurs, new tiles will attach

to the empty locations caused by the error. However, the newly grown tiles are

almost always imperfect. Instead of following the growth order assumed by the

kTAM or aTAM, these tiles grows from the boundary of the erroneous area into

the center of the area. The tiles match the growth site with sides other than east

and south sides. So the new attached tiles can be different from the error-free

tiles preferred by normal grow order.


6.5 Error Tolerant Methods

The error rate in DNA self-assembly must be reduced before it can become a

practical technology for either manufacturing or computing. Different methods

have been proposed to increase error tolerance in the self-assembly process.

6.5.1 Change Assembly Environment

It was noticed in [125][128] that changing the environment parameter Gse and

Gmc effects the result aggregate of self-assembly. The error rate in the aggrega-

tion under different combination of Gse and Gmc was presented by phase diagram

as shown in Figure 6.7. It was proven that error rate can be reduced by slowing

the speed of the self-assembly process. The growth rate r and the error rate ǫ

satisfy the relation r ∝ ǫ2. By decreasing the value δ = 2Gse − Gmc, any level

of low error rate can be achieved, with the sacrifice of growth rate (as show by

“optimal growth” in Figure 6.7). However, this method cannot achieve both an

acceptable error rate and a fast speed of growth.

[50] proposed concentration control of each type of tiles to decrease the error

rate. The method addressed the fact that the demand of different types of tiles

varies with the progress of assembly process. By increasing the concentration of

the tile that is most demanded at the time, the probability of correct attachment


Figure 6.7: Phase diagram: resulted DNA aggregation under different Gse andGmc

can be increased. An error rate reduction of up to 10% was reported in [50].

A significant advantage of this scheme is that it does not entail any overhead

such as aggregation size increase or growth rate decrease, while still achieve a

significant reduction in error rate.

6.5.2 Change Tile Set

A widely studied error tolerant method is changing the design of tile set to

increase the probability of perfectly matched attachment.

Strand invasion is an important error-correction mechanism in natural self-

assembly system. [17] applied the principle of “invasion” to the self-assembly

of DNA tiles. Proof was given in [17] that assembly system with invadable tile


set can simulate universal Turing machine. However, the mechanism of “tile

invasion” is not included in the commonly used model for DNA self-assembly.

And there is no report of “tile invasion” being observed. More importantly, no

method was given to convert a normal tile set into an invadable tile set and

attain error tolerance.

Different templates, or construction rules, of adding spatial redundancy into

the original tile sets have been proposed. These templates are refereed to as er-

ror tolerant tile sets in the literature. In order to distinguish them from the tile

set defined in Section 6.3, these templates are denoted by redundant blocks in-

stead. By using the error tolerant redundant blocks, research has systematically

pursued the tolerance of all four categories of error.

Proofreading Redundant Block

The proofreading redundant block was proposed to reduce growth errors. By

using 2 × 2 proofreading redundant block, the error rate can be reduced from

ǫ ∝ r1

2 to ǫ ∝ r [128]. The basic principle of a proofreading redundant block is

to replace each rule tile in the original tile set with a block of 2 × 2 tile array

(denoted by 2 × 2 block hereafter) [128]. Accordingly, the boundary tiles are

replaced with 2 × 1 or 1 × 2 blocks to keep the matching size of rule tiles and

boundary tiles. The sides internal to the block have unique bond types, i.e.,


this bond type only appear in the tiles from the same block. Thus, this internal

bond can only bind with the tiles from the same block. As an example, the

proofreading redundant block for Sierpinski triangle pattern is shown in Figure

6.8(a). The tile set has 1 seed tile, 4 boundary tiles and 16 rule tiles. The bond

types denoted starting with letter (such as v1 or a2) are the unique bond types

internal to blocks. The bond types denoted by just numbers are bond types

derived from the original tile set.

1

1 0

0

1

3’ 0

v1

v1

3 0

1

3’

1

0

h1

3

1

0

h1

2’

2’ a4

a3

2

a4 2’

a2

a3

2 a1

2’

a2

a1 2

2

3’

3’

b3

b4

3

b4

b2

2’

b3

3

3’

b1

b2

b1

3

2

3’

3’ c4

c3

3

c4 3’

c2

c3

3 c1

2’

c2

c1 3

2

2’

2’ d4

d3

2

d4 3’

d2

d2

d1 3

3

d3

2 d1

3’

1

1 0

0

v1

3 0

1

1

3’ 0

v1

v1

3 0

1

1

3’ 0

v1

3

1

0

h1

3’

1

0

h1

3

1

0

h1

3

1

0

h1

3’

1

0

h1

3’

1

0

h1

v1

3 0

1

1

3’ 0

v1

d2

d1 3

3

d3

2 d1

3’

2

d4 3’

d2

2’

2’ d4

d3

b2

b1

3

2

b3

3

3’

b1

3

b4

b2

2’

3’

3’

b3

b4

c2

c1 3

2

c3

3 c1

2’

3

c4 3’

c2

3’

3’ c4

c3

3

b4

b2

2’

3

c4 3’

c2

2

d4 3’

d2

Rule Tiles

Seed Tile Boundary Tiles

verticalboundary

horizontal boundary

(a) 2x2 Sierpinski Proofreading Tile Set

b2

b1

3

2

A

(b) Growth Error

Figure 6.8: The Sierpinski 2×2 Proofreading Redundant Block

Proofreading redundant blocks achieve a reduced error rate, because when an


mismatched tile is attached, it is not possible to continue growth without gener-

ating an additional error. This feature is illustrated in the example of Sierpinski

tile set with proofreading redundant block shown in Figure 6.8(b). Assume that

an insufficient attachment occurs as shown by the shaded tile. Then, there is

no matched tile that can attach to site A. All the three partially matched tiles

that can attach at site A are shown by the small tiles beside that growth site.

Any one of them will result in yet another insufficient attachment, i.e. two

insufficient attachments must occur in close proximity for growth to continue.

Analysis from kTAM model shows that having two consecutive insufficient at-

tachment is much less likely to happen than correctly attachment. Assembly

process is stalled because this erroneous growth has a small growth rate. The

initial insufficient attachment stays in an unstable state in which its total bond

strength to the aggregation is 1. Thus, it will have sufficient time to fall off and

give the opportunity to correct the error. Thus, using proofreading redundant

block has a higher probability to produce an error-free pattern as final assem-

bly. [128] showed with an Markov model that the error rate of assembly can be

improved to ǫ ∝ e−2Gse (from the original ǫ ∝ e−Gse).

The proofreading redundant block technology was extended to the general

case of replacing a rule tile with a K×K block and named as K×K proofreading


redundant block [128]. The proofreading redundant block given above is named

2 × 2 proofreading. For a K × K proofreading redundant block, theoretical

analysis predicts a further improvement in growth rate up to r ∝ e−K×Gse .

Using Xgrow simulator, [128] proved its prediction of ǫ for 2 × 2 proofreading

redundant block. However, simulation results for K = 3 and 4, higher error

rates than the predicted expectation. This deviation is mainly caused by the

facet roughening errors. The proofreading redundant block cannot correct facet

roughening error. So, after the error rate of growth error becomes ≤ O(e−3Gse),

the error observed by simulation is dominated by facet roughening error, whose

error rate is ∝ e−3Gse [18].

In the proofreading approach, spatial redundancy is used to achieve error

tolerance. By substituting each of the original tiles with a block of 2×2 tiles, the

area overhead is 300%. The area overhead for a K ×K proofreading redundant

block is K2 − 1 times. Also, with the scaling up from one rule tile to a K × K

block, it is evident that the more tile need to be assembled to reach the same

pattern. Thus require more time for assembling a same pattern. Furthermore,

the number of unique tiles is also increased by a factor of four, thus requiring

a significant amount of laboratory work [128]. The proofreading redundant

block can only correct growth error and no other error category. So other error


tolerance technology is needed to further decrease the error rate.

Snake Redundant Block

An improvement to the proofreading redundant block is the snake redundant

block. As proposed in [18], each original rule tile is replaced by a 4 × 4 block,

as shown in Figure 6.9(a). Also, the boundary tiles need to be replace by 4 × 1

or 1 × 4 blocks. Like the proofreading redundant block, the bonds internal

to the block are assigned unique bond types. The spatial redundancy used

by snake redundant block reduces growth errors with the same mechanism as

in proofreading redundant block. In addition, the snake redundant block also

reduces facet roughening errors. This is accomplished by assigning null and

double bonds inside the block to make a snake-shaped growth direction (as shown

in Figure 6.9(a)) inside the block.

An example illustrated in Figure 6.9(b) shows how the facet roughening

error is reduced by the 4×4 snake redundant block. Assume that an insufficient

attachment occurs at the shaded location and the attached tile is tile T5 in the

snake block. A strongly-binding tile (total binding strength ≥ 2) can attach to

site B, but not to site A due to the null bond on the west side of the shaded

tile. If prior to the mismatched tile falling off, the tile T4 is added, the facet

roughening error become 2 tiles’ wide. But, after that, there is no site to which a


T2T3

T4 T1

T7 T8 T9

T6T15

T16

T13

T14

T11 T10

T5

T12

T5 T4

A T5

A C

T

B

(b) Facet Roughening Error

(a) 4x4 Snake Tile Set

Figure 6.9: The 4 × 4 Snake Redundant Block

strongly-binding tile can be further added. Another insufficient attachment must

occur to continue the growth of this facet roughening error. This requirement of

insufficient attachment stalls the error growth and gives time for the erroneous

tiles to fall off and correct the error. A Markov model was created in [18] to

analyze this error correction mechanism in 4× 4 snake redundant block. It was

proved that the error rate was reduced by this error tolerance technology from

∝ e−3Gse to ∝ e−4Gse . In addition, original tile set or the proofreading redundant

block cannot generate a “stable” aggregation of limited size because extra blocks

keep attached to the completed aggregation as facet roughening errors. Snaked

proof reading system can achieve stable result because of its resilience to facet


roughening errors.

The 4 × 4 snake redundant block has been extended to the general 2k × 2k

snake redundant block in [18]. Two theorems showing guaranteed facet roughen-

ing error reduction by 2k×2k snake redundant block are proven in [18] (“block”

in our work is named “supertile” in [18]) :

1. Theorem about fixed supertile size With a 2k×2k snaked tile system

(for some fixed k), assuming we can set eGse to be Ω(N2

k ), an N×N square

of blocks can be assembled in time O(N1+ 4

k ) and with high probability, no

block errors happen Ω(N1+ 4

k ) time after that.

2. Theorem about adaptive supertile size With a 2k × 2k snaked tile

system, k = Ω(log N), assuming we can set eGse to be Ω(k6), an N × N

square of blocks can be assembled in time O(N) and with high probability,

no block errors happen Ω(N) time after that.

These theorems shows that the snaked proof reading technique can assemble

reliably fast 1 and the result of assembly can remain stable for a long time.

Simulation results from xgrow are also given to support the improvement in

error probability and aggregation stability. The snake redundant block reduces

1Though with the slower speed than proofreading tile, the growth rate of snake redundantblock is not “asymptotically” slower


both facet roughening and growth error rates, thus representing an improvement

over the proofreading redundant block in terms of error tolerance.

However, the snake redundant block incurs in a larger overhead than the

proofreading redundant block. For instance, the snake redundant block has at

least a 1500% area overhead (for k=2). Similar to the proofreading tile, the num-

bers of unique tile types and unique bond types used are significantly increased

too. [70] also showed that the growth speed of snake redundant block is slower

than the proofreading redundant block given the same amount of redundancy.

[101] proposed an improvement to the snake redundant block that can avoid

the area overhead while keeping the same error tolerance capacity. While the

original snake redundant block scales-up the size of aggregation by replacing each

original tile with a k × k block (Figure 6.10(a)), the improved compact snake

redundant block replace each k × k block in original assembly by a k × k snake-

shape constructed block (Figure 6.10(b)). However, this improved snake redun-

dant block cannot be efficiently adopted by all desired pattern. [101] showed

that only the patterns that are “robust” can use the improved snake redundant

block with only a modest increase in the number of bond types. The other

patters are “fragile”, applying compact snake redundant block to these patterns

will increase the number of bond type exponentially.


Snake−shape

Constructed Block

Original

Tile

Scale−up

Constructed BlockSnake−shape

3 1

24

NO Scale−up

4x4Original

Tile

block

block

block

1block

2

3

4

(a) Area overhead in normalsnake redundant block

(b) Snake redundant block withnot area overhead

Figure 6.10: Avoid the area overhead in snake redundant block error tolerance


Zig-zag Redundant Block

a zig-zag redundant block was proposed in [98] to provide error resilience against

spurious nucleation error. The zig-zag redundant block takes advantage of the

feature that the crystal must reach a critical size before growth can become

favorable. By using a seed tile larger than the critical size and all other tiles

smaller than that size, only the assembly with seed tile is favorable. However,

the construction of zig-zag redundant block is only proposed for a special set of

aggregation and does not seem to be of general applicability. Currently, it is not

known how to use this approach for improving the error tolerance of existing

redundant blocks to spurious nucleation errors.

Self-Healing Redundant Block

A self-healing redundant block has been proposed in [127] as the ability of a

self-assembled crystal to heal gross damage errors. It has been pointed out that

the use of a proofreading redundant block or a snake redundant block improves

the healing capability; however, healing is still not perfect. A 3 × 3 redundant

block applicable to a special set of tile sets has been proposed to improve the

healing capability of self-assembly [127]. A 5 × 5 self-healing redundant block

can be applied to a wider class of tile sets. To deal with the scenario in which


growth occurs again in multiple tiles simultaneously, a 7 × 7 redundant block

has been introduced.

6.5.3 Change Molecular Structure

Changing the structure of DNA tile can introduce extra chemical or physical

reaction in the self-assembly process, which may be used to provide error toler-

ance.

In [36], a special protective tile is proposed to check if the DNA tile perfectly

matches the growth site. The protective tile stack on top of the normal tile and

only allow two sides (south and east sides according to the notations adopted in

our work) of the DNA tile to bond with other tiles. The protective tile falls off

only after both of the sides are paired with matched bonds. After the protective

tile falls off, the north and west sides are no longer protected and other tiles

can match and attach to this tile. In this method, self-assembly process cannot

continue unless the all the attachments are perfectly matched or the protective

tile falls off mistakenly. A DNA structure was proposed in [36] to implement

the task of protective tile reliably. The performance of this method relies on the

design and implementation of protective tile. However, there is no report on the

implementation of protective tile in the literature.


Redundancy based compact error resilient scheme was first proposed in [90]

as an improvement to the proofreading redundant block. The compact error

resilience increases the number of bond types on the sides of a tile to contain

redundant information. Every side contains extra copies of information that can

be used to proofread the operation of its neighbor tiles. A case study showed

that this error tolerance technology bases on the same mechanism as proof-

reading redundant block but with no overhead of the assembled pattern size.

Analysis and simulation were provided in [90] that the 2-way overlay compact

error resilient scheme generates similar error improvement to 2× 2 proofreading

redundant block and the 3-way scheme generates similar error improvement to

3×3 proofreading redundant block. However, the compact error resilient scheme

is not applicable to all tile sets.

The compact error resilience was further developed in [96]. The improved 3-

way overlay redundancy can improve error rate of arbitrary tile set to ǫ2o (where

epsilono is the error rate without error tolerance). It was also proved that

compact error resilience cannot improve error rate of any tile set to ǫ4o.

Chapter 7

Synthesis of Tile Sets for DNA

Self-Assembly

For DNA self-assembly to be a viable technology for nanoscale manufacturing,

it is imperative to find a method to design tile sets for generating any finite-size

pattern efficiently. It has been reported in [86] that an arbitrary pattern can

be generated within a DNA self-assembly process. However, the tile set used

in [86] gives every tile in the assembly a unique tile type. So, the number of

tiles in the tile set is equal to the number of pixels in the pattern. We refer to

such tile sets as trivial tile sets. Because the number of tile types in a tile set is

related to the amount of laboratory work to implement the tile set, we define the

158

CHAPTER 7. SYNTHESIS OF TILE SETS FOR DNA SELF-ASSEMBLY159

number of tile types in a tile set as its cardinality. It is desirable to design tile

sets of reduced cardinality compared with trivial sets. The process of creating

a non-trivial tile set for a finite-size pattern is referred to as tile synthesis.

Our current work only considers black-and-white patterns because it is the

simplest case and can serve as a starting point for more complex patterns. More-

over, the black-and-white pattern corresponds to the fabrication template com-

monly used for nano manufacturing. For example, by the method introduced

in [87], it is possible to deposit molecular devices only onto DNA tiles of one

color, thus generating the desired pattern for the device array. The proposed

research focuses on the synthesis of the rule tiles because they are the tiles that

constitute the desired pattern of the DNA crystal.

This chapter addresses the issues revolving around tile synthesis, including

problem definition, complexity analysis and algorithms proposed to automate

the tile synthesis process. Extensive simulation results for finite size patterns

are provided.


7.1 Problem Definition

7.1.1 Graph Model

The presentation and discussion of tile set synthesis are based on the following

definitions.

Definition 7.1.1 If by self-assembly, a tile set T can construct a finite-size pat-

tern P without resorting to any other process, then T is said to be the assembling

tile set of P .

A graph model is used to represent the tile set. An example of a tile set and

its model (consisting of two graphs) are shown in Figure 7.1.

• In the tile graph GT =(V ,E), each tile type is represented by a directed

edge in E. The edge connects two vertices in V , (Be, Bs) and (Bw, Bn),

where Be, Bs, Bw and Bn are the bond types on the tile’s east, south,

west and north, respectively. If the bond types of the four sides of a tile

are denoted by east= e1, south= s1, west= w1, north= n1, then this

tile is represented by a directed edge from vertex v1 = (e1, s1) to vertex

v2 = (w1, n1). Consider the example in Figure 7.1(a), the tile in the lower

right corner has the following bond types: east= 1, south= 1, west= 2,


north= 2. As shown in Figure 7.1(b), it is represented by a directed edge

from vertex (1, 1) to vertex (2, 2).

• The bond graph GB=(XB,YB,EB) is an undirected bipartite graph, in

which bond types are represented by vertices. For any vertex (x, y) in

the tile graph GT , there is an edge connecting the vertex representing the

horizontal bond x in the set XB (referred to as the left side of the bond

graph) and the vertex for the vertical bond y in the set YB (referred to as

the right side of the bond graph). EB is a set of colored edges. For an

edge (x′, y′) in the bond graph, if there exists a tile in the tile set with an

east side of bond type x′ and south side of bond type y′, then the color of

the tile (wh or bl, for white or black) is assigned to this edge. If such a

tile does not exist, then this edge has no color.

wh

2,2

X YBB

(a) Pattern and tile set

(Sierpinski triangle)

2,1 1,2

1,1

(b) Tile graph (c) Bond graph

bl

wh

wh

222

121

2

2

22

2 22

22

21

1

21 11

2

1

11

1

11

12

21

1

21

1

111

22

1

11

2 2

11

22

21

11

2 11

22

11

1

12

21

2

Figure 7.1: Graph model for the Sierpinski triangle tile set

Definition 7.1.2 A tile set is valid iff.

1. The out-degree of any vertex in the tile graph is not greater than 1;


2. No edge in the bond graph is assigned both colors (wh and bl).

In a “trivial” tile set, each bond in the horizontal (east and west) and ver-

tical (north and south) sides has a unique type and every pixel in the pattern

corresponds to a unique tile type. So by definition, it is guaranteed that any

finite-size pattern has at least one trivial tile set as its valid assembling tile set.

Also, as every bond/tile in the pattern corresponds to a unique bond/tile type,

any two trivial tile sets can be converted to each other by simply substituting

their notation. The following Lemma is therefore applicable.

Lemma 7.1.1 All different graph models of a trivial tile set are different rep-

resentations of the same design.

7.1.2 Tile Set Design from Trivial Tile Set

Starting from a trivial tile set of P , tile sets with reduced number of tile types

can be generated by merging bond types. When merging bond types, two nodes

on the same side of the bond graph can be merged each time. If merging of the

nodes results in merging of edges in the bond graph, then each new edge is the

result of merging two edges. The color assigned to the new edge is decided by

the colors of the two edges prior to merging. This is given as follows.


• If both edges have the same color assignment (wh, bl or no color), then

the new edge has the same color assignment.

• If only one of the edges has wh or bl color, then the new edge is assigned

that color.

• If the edges have different colors, then the new edge has both colors (which

will result in an invalid tile set).

The nodes in the tile graph need to be changed accordingly if the edges in the

bond graph are merged.

Definition 7.1.3 Assume that T1 is an assembling tile set for P and T2 is a

valid tile set resulting from a series of bond-type merges in T1. A partial assembly

As1 from T1 and a partial assembly As2 from T2 are said to be equivalent if

1) They have the same shape, i.e., any empty location in As1 is also empty in

As2 and vice versa.

2) For any bond on the assemblies, the bond type B2x found on As2 is the result

of merging bond type B1y (the bond type found at the same location on As1)

with other bond types.

For any bond type B1i in T1,a bond type B2j in T2 can be found such that

B2j is the result of merging B1i with other bond types in T1. B1i is referred


to as the merging source of B2j and B2j is the merging result of B1i. For

any tile in T1 represented by an edge ((Be1, Bs1), (Bw1, Bn1)) in the tile graph,

a tile can be found in T2 that is represented in the tile graph by the edge

((Be2, Bs2), (Bw2, Bn2)) such that Be2, Bs2, Bw2 and Bn2 are the merging results

of Be1, Bs1, Bw1 and Bn1, respectively. Tile ((Be1, Bs1), (Bw1, Bn1)) is referred to

as the merging source of tile ((Be2, Bs2), (Bw2, Bn2)) and ((Be2, Bs2), (Bw2, Bn2))

is the merging result of ((Be1, Bs1), (Bw1, Bn1)).

Theorem 7.1.2 Starting from an assembling tile set T1 for pattern P , if the

result of a series of bond type merging operations is also a valid tile set, then the

new tile set T2 is also an assembling tile set for P .

PROOF: As our research concentrates on rule tiles only, it is assumed that

the design of the seed tile and the boundary tiles for T1 and T2 will guarantee that

the south and east boundaries of the assembly from T1 and T2 are equivalent.

Assume that a partial assembly As1 from T1 and a partial assembly As2 from T2

have the same shape, but they are not equivalent. It follows that there must be

a site in both assemblies such that all tiles to the south and east of this site form

two equivalent assemblies (denoted by As′1 and As′2). However, when the tiles at

this site are included in the partial assemblies (denoted by As′′1 and As′′2), then

they are not equivalent. The partial assemblies being considered are given as


(a) Partial assemblies

Part of G for TPart of G for TB 1 B 2

(b) Partial tile graphs

... ...

...

...

... ...

As’’1

1As’

As’’2

...

...

As’2

Be2 Bs2

Bw2 Bn2Bw2 Bn2w1B Bn1

Bs1Be1

Bn1

w1B

Bn2

Bw2 Be2

B

Be1

Bs1 s2

Figure 7.2: Illustration of the example that shows the contradiction in assumingthat T1 and T2 may generate a partial assembly with same shape but they arenot equivalent.


shown in Figure 7.2(a), with the considered site denoted by the gray color. The

four bonds of the tile at this site in As1 are denoted by east=Be1, south=Bs1,

west=Bw1, north=Bn1 and the four bonds at the same site in As2 are east=Be2,

south=Bs2, west=Bw2, north=Bn2. According to Definition 7.1.3, Be2 and Bs2

are the merging results of Be1 and Bs1. Then it must be valid that either

Bw1 is not the merging source of Bw2 or Bn1 is not the merging source of Bn2.

Thus, in the tile graph for T2, there must be an edge ((Be2, Bs2), (Bw2, Bn2)).

Meanwhile, according to the rules of bond merging, there must also be an edge

((Be2, Bs2), (Bw1′ , Bn1′)), where Bw1′ and Bn1′ are the merging results of Bw1 and

Bn1. Part of the tile graphs of T2 (as described above) is shown in Figure 7.2(b).

This contradicts the condition that T2 is a valid tile set (no node in its tile graph

can have an out-degree greater than 1). This shows that if the assemblies from

T1 and T2 have the same shape, then they must be equivalent. Thus, it is proved

that the final assemblies from T1 and T2 are equivalent.

According to the aforementioned color-assignment rules when merging edges

in the bond graph, if a tile in the valid tile set T2 is the merging result of a tile in

the valid tile set T1, then they must have the same color. As the final assemblies

from T1 and T2 are equivalent, then they must have the same pattern.

2 END OF PROOF


Any non-trivial tile set can be expanded into a trivial tile set by reversing the

merging process and assigning unique types to each tile/bond in the assembly.

From Lemma 7.1.1, it is evident that any non-trivial tile set can be derived by

merging a trivial tile set.

Definition 7.1.4 An optimum tile set for a pattern of finite size is an assem-

bling tile set for that pattern with the minimum number of tile types.

Definition 7.1.5 The Pattern self-Assembly Tile-set Synthesis (PATS) consists

of finding the optimum tile set for a given finite-size pattern.

The objective of PATS problem is characterized as follows.

Theorem 7.1.3 Among all assembling tile sets for P , if the tile graph repre-

senting a tile set has the smallest total out-degree among all tile graphs, then

this tile set is referred to as having the minimum tile graph and is an optimum

tile set for P .

PROOF: In the tile graph, every tile type is represented by an edge from

vertex (Be, Bs) to vertex (Bw, Bn). So, the out-degree of the tile graph is equal

to the number of tile types. If an assembling tile set can be represented by a

smaller tile graph than the optimum tile set, then it violates the definition of


optimum tile set for P . Hence, the theorem is proved.

2 END OF PROOF

So, the objective of PATS is to generate a tile set with a minimum tile graph.

As the process of merging node types can decrease the total out-degree in the

tile graph and any non-trivial tile set can be derived from the trivial tile set by

merging operations, then the PATS problem can be solved by finding a valid

tile graph through a series of bond-merging operations from the trivial tile set.

Hereafter, “synthesis” is used to refer to the process of merging bond types from

a trivial tile set to solve the PATS problem. The graph model representing the

trivial tile set of a PATS problem is also used to represent the PATS problem

itself.

7.2 Complexity Analysis

The complexity of the PATS problem is analyzed and its relation to the minimum

graph coloring problem is established.

Theorem 7.2.1 The PATS problem is equivalent to the coloring problem and

therefore in general, it is NP-complete.


PROOF: The minimum graph coloring problem is known to be NP-complete

in the general case (i.e. no restriction on the number of colors). The following

process converts the minimum graph coloring problem into the PATS problem

in polynomial time. Given a coloring problem with graph Gc = (Vc, Ec), the

corresponding PATS problem with a bond graph GB = (Bl, Br, EB) (Br ∪ Bl is

denoted by B) and a tile graph GT = (T,ET ), can be generated as follows.

For each vertex vi ∈ Vc, generate a pair of vertices bl,i and br,i in GB, with

bl,i ∈ Bl and br,i ∈ Br. bl,i and br,i are connected by an edge ei,ib = (bl,i, br,i) ∈

EB. ei,ib is assigned a color wh (note that this color assignment is defined in

Section 7.1, it is not the color used in the graph coloring problem). A vertex in

the tile graph ti,i ∈ T is also generated corresponding to the edge ei,ib . ti,i has a

self-loop edge ei,it = (ti,i, ti,i) ∈ ET . For each edge ej = (vj1, vj2) ∈ Ec, generate

an edge ej1,j2b = (bl,j1, br,j2) and an edge ej2,j1

b = (bl,j2, br,j1) in the bond graph and

the corresponding vertices tj1,j2 ∈ T and tj2,j1 ∈ T in the tile graph. The colors

of ej1,j2b and ej2,j1

b are bl. The edge ej1,j2t = (tj1,j2, tj2,j1) and ej2,j1

t = (tj2,j1, tj1,j2)

connect the two vertices tj1,j2 and tj2,j1 into a loop.

An example of generating the PATS problem from a coloring problem is

shown in Figure 7.3. Note that the bond and tile graphs generated by the above

process have the following properties:


GB GT

l,1b b r,1

b

5,5e

v1

v2

v3

v4

v5

Gc

b

b

b

b b

b

b

bl,2

l,3

l,4

l,5

r,2

r,3

r,4

r,5

be3,5 t

t

t

t 2,2

3,3

4,4

5,5 t t

t t

t t

t t1,4 4,1

2,3 3,2

2,4 4,2

3,5 5,3

t 1,1 t t1,2 2,1w

w

w

w

w

bb

b

b

b

b b

b

b

b

Coloring problem PATS problem

Figure 7.3: Example of converting the coloring problem to the PATS problem

1) For any vertex bl,i ∈ Bl, there must be a vertex br,i ∈ Br and vice versa.

There must be an edge ei,ib ∈ EB and its color must be wh. The vertex ti,i in

the tile graph is connected and only connected by the edge (ti,i, ti,i).

2) For any edge ei,jb (where i 6= j), there must be an edge ej,i

b in the graph. Both

edges are assigned bl as color. The vertex ti,j in the tile graph is connected and

only connected by edge (ti,j, tj,i) and edge (tj,i, ti,j) .

These properties defines a feature that hereafter it is referred to as the feature-S.

To prove that an optimum solution to the coloring problem can be generated

from an optimum solution to its corresponding PATS problem, the following

lemmas are needed:

Lemma 7.2.2 For the PATS problem generated from the coloring problem, any


optimum solution can be converted into an optimum solution with a complete

bipartite graph as its bond graph.

The optimum solution to the PATS problem can be attained by a series

of node merging operations in the bond graph. As per the construction rules

of the PATS problem from the coloring problem, each edge in the bond graph

corresponds to a tile type. So any node merging in the bond graph that is not

related to edge merging, can be omitted and the solution will have the same

number of tile types. After omitting all bond merges of this type, any optimum

solution for the PATS problem will become a new solution that is also optimum.

The new solution can be attained from the original graph of the PATS problem

through a series of edge merges in the bond graph. This solution is referred to

as the edge merged optimum solution for the PATS problem.

According to the color assignment rule for merging, only edges of the same

color can be merged to get a valid result. If the bond graph prior to edge

merging is colored-symmetric, then merging two wh edges ei,ib and ej,j

b in the tile

graph results in combining the vertices pairs (bl,i, bl,j) and (br,i, br,j) in the bond

graph; the merging operation of two “black” edges ej1,j2b and ej3,j4

b requires edges

ej2,j1b and ej4,j3

b to be also merged, to keep the tile graph valid. So the vertex

pairs (bl,j1, bl,j3), (bl,j1, bl,j3), (bl,j1, bl,j3) and (bl,j1, bl,j3) are combined. As the


bond graph of the original PATS problem generated from the coloring problem

has the feature-S, then the bond graph after each edge merging operation still

satisfies the feature-S. Therefore, after a series of edge merges in the bond graph,

the edge merged optimum solution must have a bond graph with the feature-S.

If the bond graph of an edge merged optimum solution Topt is not a complete

graph, then there is at least one pair of vertices in the bond graph (bl,j5, br,j6)

such that ej5,j6b /∈ EB. Due to the feature-S, it follows that ej6,j5

b /∈ EB. Merging

of the node pairs (bl,j5, bl,j6) and (br,j6, br,j5) does not combine edges of different

color. Moreover, as Topt satisfies the feature-S, then the result of the merging

operation will not have any node in the tile graph with out-degree greater than

1. So, the result of merging the node pair (bl,j5, bl,j6) and (br,j6, br,j5) is also valid

and it has less tile types than Topt. This contradicts the assumption that Topt is

optimum. Thus, an edge merged optimum solution must have a complete bond

graph. The lemma is proved.

Lemma 7.2.3 For the coloring problem and the PATS problem derived from it,

any solution to the PATS problem can be converted into a solution to the coloring

problem and vice versa.

Let the coloring problem be denoted by Pc and the PATS problem by Pp.

Pp is represented by a graph GB = (Bl, Br, EB) and GT = (T,ET ). Given a


GB

l,1b b r,1

b

b b

bl,2

l,3

r,2

r,3

l,1b b r,1

b l,3 b r,3

b

3,1ee

1,3

b ,

b bl,2 r,2

)(( )

can be simplified

into

bipartite graph, this bond graph

has 2 edges missing:

Compared with complete

Figure 7.4: Simplification is possible if the bond graph is not a complete bipartitegraph

solution to Pp, a solution to Pc can be generated. First, the solution of Pp is

changed into a solution with the feature-S. Using the method of generating an

edge merged optimum solution, it is guaranteed that the conversion is possible

and the solution with the feature-S (represented by the graph G′B = (B′

l, B′r, E

′B)

and G′T = (T ′, E ′

T )) has the same number of tile types as prior to conversion.

Then, a solution for Pc is generated as follows:

1) Select a vertex b′l,i ∈ B′l, find its merging sources in Bl.

2) Select all vertices in Gc (the graph for the coloring problem) that correspond

to the merging sources of b′l,i.

3) These vertices are assigned the same color in the solution for Pc.

4) Repeat 1) through 3) to every vertex in B′l, but each time the vertices selected

from Gc are assigned a different color.


The solution generated by the above process guarantees that every vertex in Gc

is assigned a color and no two vertices are assigned the same color if they are

connected by an edge. So, the solution is a valid solution for Pc and |B′l| colors

are used in this solution.

Given a solution to Pc, a solution to Pp can be generated. The solution

to Pc is given by the subsets (S1, S2, . . . , Sk), in which each subset includes all

vertices with the same color. Pp is represented by the bond graph GB and the

tile graph GT . For all vertices (vi1, vi2, . . . , vij) in subset Si ∈ (S1, S2, . . . , Sk),

their corresponding nodes in Gl (denoted by bl,i1, bl,i2, . . . , bl,ij) are merged and

their corresponding nodes in Gr (br,i1, br,i2, . . . , br,ij are merged. After merging all

subsets in (S1, S2, . . . , Sk), the resulting graphs G′B and G′

T represent a solution

to Pp. As per construction of Pp from Pc, the following condition holds for any

vertices vi1, vi2, . . . , vij ∈ Si, i.e. in the corresponding GB, bl,i1, bl,i2, . . . , bl,ij ∈ Gl

and br,i1, br,i2, . . . , br,ij ∈ Gr; an edge (bl,ix, bl,iy) /∈ EB if x 6= y. GB, GT satisfies

the feature-S, so bl,i1, bl,i2, . . . , bl,ij can be merged and br,i1, br,i2, . . . , br,ij can be

merged. The result of the merging process is a valid tile set that also satisfies

the feature-S. Thus, G′B, G′

T is a valid solution to Pc, where |B′l| = |B′

r| = k.

Lemma 7.2.4 The solution to Pc that is generated from the optimum solution

to Pp is optimum.


Let the optimum PATS solution be represented by GB = (Bl, Br, EB), GT =

(T,ET ). According to the method for generating the coloring solution from the

PATS solution, the solution GB, GT is first converted into the solution G′B, G′

T ,

which is also optimum and satisfies the feature-S. Then, the coloring solution is

generated from G′B, G′

T . The coloring solution is denoted by S. If S is not the

optimum solution to Pc, then there must be an optimum solution (denoted by S′)

with a smaller number of colors. From S′, the other PATS solution (represented

by G′′B = (B′′

l , B′′r , E ′′

B), G′′T = (T ′′, E ′′

T ) ) can be generated. It follows that

B′′l < B′

l and B′′r < B′

r. As G′B is a complete graph in the optimum PATS

solution, then |E ′′B| must be smaller than |E ′

B|. Every edge in E ′B corresponds

to a tile type and the number of tile types in G′′B, G′′

T is no larger than |E ′′B|.

Therefore, the number of tile types in the solution G′′B, G′′

T must be smaller

than the solution G′B, G′

T . This contradicts the assumption that G′B, G′

T is an

optimum solution for Pp.

Based on Lemmas 7.2.2 and 7.2.4, it is proved that the minimum coloring

problem can be reduced to the PATS problem. In general, the minimum coloring

problem is known to be NP-complete. Thus, the PATS problem is also NP-

complete.

2 END OF PROOF


7.3 Greedy Algorithms

The previous section has shown that the PATS problem is NP complete, hence

requiring a non-polynomial (exponential) execution complexity for its solution.

This section proposes two new greedy algorithms that can be used for the syn-

thesis of tile sets in DNA self-assembly.

7.3.1 PATS Bond Algorithm

PATS Bond is a greedy algorithm aiming at combining as many vertices in the

bond graph as possible. The The flow chart of this algorithm is illustrated in

Figure 7.5.

An example is shown in Figure 7.6 to illustrate the execution of PATS Bond

algorithm. The desired assembly is a square pattern of 4 tiles; the two tiles on

the left are black, while the two tiles on the right are white. Each algorithm

starts with the trivial tile set of 4 different types of tiles, as shown in the same

figure. The graph model representation of the trivial solution is also shown in

Figure 7.6.

The execution of PATS Bond is illustrated in Figure 7.7. In every step, two

bond types are selected and combined into the same bond type.

• The first step combines bonds 1 and 6 on the horizontal boundary (left


Correct illegal tile set bycombining conflicting

vertices recursively

Correct illegal tile set bycombining conflicting

vertices recursively

Generate trivial tile set

1

Record simplified tile setrecorded tile setRecover to last

Is the tile set legal?

Y

N

Randomly combine apair of vertices in the

Is the tileset legal?

NY

Y N

Combiningfailed more than

N times?

recorded tile setRecover to last


Y

N

left half of Bond Graph

Randomly combine apair of vertices in the


NY

Y N

Combiningfailed more than

N times?

Record simplified tile set

right half of Bond Graph

K times without successfulLoop repeated forN

Y

combing?

2

Outer

Loop

Figure 7.5: Flow chart of the algorithm PATS Bond


1

2

3

4

5

6

1

2

3

4

5

6

3,4 4,52,2

4,3 5,63,2

w

w

6,6

b

Desired

b

Tile graphBond graph

Pattern

65

Trivial tile set

6

4

4

23 2

3

12

43

1

5

1,1

5

Figure 7.6: An exemplar pattern to be generated

side of GB) and the result is shown in Figure 7.7(a).

• Step two combines bonds 1 and 2 on the vertical boundary (right side of

GB). Step three combines bonds horizontal bonds 3 and 4. (Figure 7.7(b))

• Step four combines vertical bonds 4 and 5. Step five combines horizontal

bonds 1 and 3. (Figure 7.7(c))

• Step six combines vertical bonds 1 and 3. The resulting graph, as shown

in Figure 7.7(d), has a vertex (1,1) with an out-degree equal to 2. This

violates the correctness rule of the graph model as defined previously.

• To correct the error from step 4, two vertex pairs ((1, 2) and (4, 5), (4, 1)

and (6, 6)) must be combined.

Thus the final graph is shown in Figure 7.7(e) and no further simplification


B

B T TB

GGGG

G G G G

GGGG

(6) Synthesized tile set and assembly:

(5)

(3) (4)

(2)(1)

Synthesis of boundaryand seed tiles is not considered

from the solution of PATSTwo types of rule tile,

1,1

1,2

1 1

2

1,1

4,56,6

4,1

1,2

1

4

6

1

2

5

6

1

3

4

5

6

1

2

3

5

6

1

3

4

6

1

2

5

6

1,1 4,5

6,6

1,1

6,6

4

5

6

1

2

3

4

5

6

1

3

1,1 4,5

6,6

1

3

4

6

1

2

3

5

6

1,1

6,6

(4)(6) b

w(6)

(5)

b

w

b

(3)

1,2=4,5

4,1=6,6

w

b

b

(4)

w

(3)b

w

w

b

3,2 4,3

1,2 3,3

5,5

3,2

1,2

4,1 4,5

3,1

w

w

b

b(2)

3,2 4,3

1,2 3,4

5,5

w

b

b(5)

w

3,2 4,3

1,2 3,3

4,5

TBTB

TBT

1

111

1

1

1

1

1

1

1

11

11

122

22

1

1

Figure 7.7: Execution of PATS Bond for example pattern


vertices pair

Discard theselection of the

Randomly select a pairof non−leaf vertices

in Tile Graph

The vertices’

corresponding edges

same color?in Bond Graph have

Combine the vertices in

Bond Graph accordinglyin Tile Graph. Change

N Y

Generate trivial tile set


NY

set by combiningCorrect illegal tile

conflict vertices

recorded tile set.Recover to last


N

Y

NCombining

process failed in all the lastN trials?

Y

simplified tile set.Record the

Figure 7.8: Flow chart of the algorithm PATS Tile

is possible. The resulting tile set generated by PATS Bond is shown in Fig-

ure 7.7(f), i.e. no tile set with fewer than 2 types of tile can build the desired

pattern. In this case, the algorithm finds an optimal solution.

7.3.2 PATS Tile Algorithm

A second greedy algorithm (referred to as PATS Tile) is proposed for reducing

tile types; this algorithm combines as many vertices in the tile graph as possible.

Its flow chart is illustrated in Figure 7.8.


PATS Tile is explained using the example shown in Figure 7.9. Starting from

the trivial tile set, the execution of PATS Tile is illustrated in Figure 7.10(a). In

every step, two nodes in the tile graph are combined. This proceeds as follows.

• Step 1 combines nodes (1, 1) and (7, 6). Note that this operation not only

combines these two nodes, but it also changes nodes (4, 6) and (7, 8) to

(4, 1) and (1, 8), respectively. By combining (1, 1) and (7, 6), this results

in a conflict in the tile graph, i.e. node (1, 1) has two children, nodes (2, 4)

and (8, 9). It needs to be corrected by combining (2, 4) and (8, 9).

• Step 2 combines (2, 2) and (5, 4) and results in a conflict in the tile graph

again. To resolve this conflict (3, 5) and (6, 7) are combined.

• Step 3 combines (1, 1) and (3, 5) and the conflict is resolved by combining

(1, 2) and (2, 8).

• Step 4 tries to combine (1, 1) and (1, 3). The resulting conflict can only be

resolved by combining (1, 2) and (4, 1). However, the combining process

of (1, 2) and (4, 1) requires that (1, 1) and (1, 2) are combined; this is not

allowed due to the different colors assigned to the corresponding edges in

the bond graph. Step 4 fails to produce a valid tile set so the algorithm

falls back to the result of step 3. No more combining operation is possible


wh 2,2 5,43,3 6,5 7,6

2,4 3,5 4,6 6,7 7,8 8,9

(b) Graph model

(a) Assembly

bl

7

8

7

8

9

whwh

bl

wh 3

4 4

3

G

B

TG

2

1,1

5

6

1

2

5

6

1

878

77

9

3

566 5

3

6 5 4

6 5

34

43 22

2

2 11

1

1

Figure 7.9: Pattern example: assembly and model

from that point, thus PATS Tile ends and uses the result from step 3 as

the synthesized tile set.

The resulting tile set generated by PATS Tile is shown in Figure 7.10(b).

7.3.3 Complexity of Greedy Algorithms

In the worst case of execution time, the tile set is simplified to one tile (for

PATS Tile) or two bond types (for PATS Bond).

By successfully combining each tile type, it is possible to decrease the number


11

4,1

bl

wh(3)

4

TG

2,2

BG

2

1

Step 4 failed, go back to

BG

Alrogithm ends with resultof step 3No other optimization is possible.

the result of Step 3.

(6)

(7)

bl

3,5

2,2wh

wh

step 2

bl

6,7 3,5

4,1

3,3

2,2

1,8

6,5

wh

(5) (4)

wh

wh

bl

bl(8)

(9)

wh

(b) Synthesized tile set and assembly

cannot mergeDifferent colorswh?bl

(2)(4)

3,5=6,7conflicts:Correct

(5)

blwh

(3) 2,2wh


wh

bl(8)

(2) wh

(a) Algorithm execution

step 3

2,4

wh

wh

wh

bl

step 1

2,4=8,9conflicts:Correct4,13,5

1,86,7

6,55,4

8,92,4

3,32,2(6)(7)wh

wh

bl

wh

6,7

6,55,4

3,32,2

4 4

3

7

8

GB

1,8

3

4

3

5

6 7

8

3,5 4,1

GT

1,11

2

1

2

8

7

3

44

3

2

1,1

5

1

2

5

6

1 1

2

5

6

1

2

3

5

9

8

GB GT

GB GT

1,1

1,1

3

2

1

2

1 1,1

TG

1,3

4,12,2

4

1 1,1


TGBG

1,3

4,11,88

1,8

3,3

4,1

GB GT

1,11 1

2

1

2

1

2

3

4

3

5

8

BG

4 3

4

21

1

21 1

1

21 1

31

1

1

1

1

1

1

2

2

12

111

3

11

Figure 7.10: Execution of PATS Tile for pattern example


of tile types by at least 1. The execution time for each successful tile type has

an upper bound as set by the fact that its loop cannot be repeated for more

than a specified number of iterations (N in figure 7.8). In the worst case, it has

run-time linear to the number of tile types to correct an illegal tile set because

combining conflict vertices may have to traverse the whole tile graph. Therefore

the execution time of PATS Tile to decrease the tile set to just one tile type is

O(x2), where x is the number of tile types in the trivial tile set. In a trivial tile

set, the number of tile types is the same as the number of tiles, i.e. x = l × w,

where l is the length of the pattern and w is the width of the pattern. Thus,

the complexity of PATS Tile is O(l2 × w2). If the pattern is a l × l square, the

complexity is O(l4).

For PATS Bond, the number of bond types are decreased by at least one

every K times the outer loop is repeated (as shown in its flow chart). The

upper bound for the execution time of the outer loop is reached if both Loop 1

and Loop 2 are repeated N times. In Loop 1 and Loop 2, all procedures have

constant execution time except the one to correct an illegal tile set by combining

conflict vertices. The correcting procedure has a complexity of O(x). So, the

upper bound for the time to decrease the number of bond types by 1 is O(x);

the worst case complexity of PATS Bond is O(x2) = O(l2 ×w2) for a pattern of


l × w pixels. If the pattern is a l × l square, then the complexity is O(l4).

7.3.4 Simulation Results for Synthesis

In all simulation cases in this section, the algorithm generates the tile set from

the bitmap file of a pattern; then, self-assembly of the tile set is simulated by

Xgrow.

First, the greedy algorithms PATS Tile and PATS Bond have been compared

by simulation using randomly generated patterns. Figure 7.11 shows two exam-

ples from the random patterns (seed and boundary tiles are blue colored). The

first example is a 6 × 6-pixel pattern (Figure 7.11(a)). The tile set synthesized

by PATS Tile generates by simulation the assembly shown in Figure 7.11(b).

The second example is a 14× 14-pixel pattern (Figure 7.11(c)). The simulation

result of its synthesized tile set is shown in Figure 7.11(d). Both simulation

results correctly generate the desired patterns.

Seventy random patterns of different size were used and the number of tile

and bond types were recorded for each generated tile set. The PATS Bond algo-

rithm generates a tile set that on average achieves a 90.4% decrease in bond types

and 3.0% in tile types (as compared with the trivial tile set). The PATS Tile al-

gorithm results on average in a decrease of 75.6% in bond types and 43.5%in tile


(a) A 6 × 6 Pattern (b) Self-assembly in Xgrow: 6 × 6

(c) A 14 × 14 Pattern (d) Self-assembly in Xgrow: 14 × 14

Figure 7.11: Examples of execution of the PATS program

types. Figures 7.12 and 7.13 show the decrease in percentage of tile and bond

types for the random patterns with respect to size. The PATS Tile algorithm

results in less tile types in the synthesized tile set, while the PATS Bond results

in less bond types. If the number of tile types is more important in self-assembly,

then the PATS Tile algorithm should be preferred for tile synthesis.

PATS Bond achieves the highest reduction in bond types, while PATS Tile

achieves the highest reduction in tile types. Because PATS Tile has a superior

performance, the PATS Tile is used hereafter. For small patterns, optimum tile

sets were found using an exhaustive search. The optimum results are compared


0 1000 2000 3000 4000 5000 6000 7000 8000 9000 100000

10

20

30

40

50

60

70

80

90

Pattern Size

Reduction in P

erc

enta

ge (

%)

PATS_Tile

Tile ReductionBond Reduction

Figure 7.12: Simulation results for PATS Tile

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 100000

10

20

30

40

50

60

70

80

90

100

Pattern Size

Re

du

ctio

n in

Pe

rce

nta

ge

(%

)

PATS_Bond

Tile ReductionBond Reduction

Figure 7.13: Simulation results for PATS Bond


Pattern Area Size Number of Rule Tiles in Tile SetName (Pixel) Trivial PATS Tile Optimum

2x3 1 2 × 3 6 2 2

2x3 2 2 × 3 6 3 3

3x3 1 3 × 3 9 6 4

3x3 2 3 × 3 9 5 5

4x3 1 4 × 3 12 7 5

4x3 2 4 × 3 12 6 6

4x4 1 4 × 4 16 2 2

4x4 2 4 × 4 16 10 6

5x5 2 5 × 5 25 2 2

Table 7.1: Comparison of the optimum and PATS tile generated tile sets

with the results of the PATS Tile algorithm as given in Table 7.1. In most

cases, the results of PATS Tile are close or equal to the optimal results, hence

confirming the efficiency of the proposed algorithms for patterns of finite size.

The PATS Tile algorithm was further evaluated by simulation using two sets

of finite size patterns.

• In the first set, the patterns generated from known tile sets (such as the

Sierpinski triangle, binary counter, etc.) are used.

• The second set of patterns include the layouts of various QCA (Quantum-

dot Cellular Automata) circuits [59]. QCA is one of the emerging tech-

nologies that have the potential to supersede CMOS and implement novel

computational paradigms. DNA self-assembly can be utilized to generate

layouts on which QCA cells can be deposited for nano scale manufacturing.


Specific patterns such as the Sierpinski triangle and binary counter, can be

assembled efficiently by a small tile set. The self-assembly of these types of

pattern has been extensively studied as examples of DNA self-assembly. By

comparing the synthesized tile sets with the small tile sets known to assemble

patterns, the performance of synthesized tile sets can be assessed. In the first

set of experiments, the Sierpinski triangle, bar code (including line1 and line2),

chess-board and binary counter have been selected as patterns. These patterns

were originally defined as of infinite size (hence of limited practical use). As the

proposed synthesis process can only be applied to a finite pattern, in this set

of experiments, a limited area of the original pattern is selected for synthesis

and can be periodically replicated on the plane. For example, the Sierpinski

triangle (Figure 7.14(a)) has been evaluated with areas of different pixel size

(Figures 7.14(b), (c) (d)).

Table 7.2 shows the results, including the selected pixel area size, the number

of tiles in the trivial tile set, the number of tiles in the valid tile set (as obtained

by synthesis) and the percentage reduction in tile types. For the pattern line1,

the program produces the optimal tile set. However, for most of the patterns,

the reduction in tile types is similar to the experiments of random tiles.

The second set of experiments provide an insight of patterns that are required


(a) The Sierpinski triangle pattern of infinite size

(b)6×6 pixel area

(c)17×17 pixel

area

(d)32×32 pixel

area

Figure 7.14: Sierpinski triangle patterns in experiments

(a) Layout of Coplanar crossing (b) Simulated pattern

Figure 7.15: Coplanar crossing layout patterns in QCA


Pattern Area Size # of Tile Types ReductionName (Pixel) Trivial Set Synthesized Set Percentage

Sierpinski 6 × 6 36 21 42%8 × 8 64 37 43%

12 × 12 144 80 45%17 × 17 289 172 41%32 × 32 1024 595 42%

Line1 6 × 6 36 2 95%15 × 15 225 2 99%

Line2 6 × 6 36 19 47%15 × 15 225 133 41%

Binary 6 × 6 36 19 47%Counter 15 × 15 225 121 46%

Chess- 6 × 6 36 19 47%Board 15 × 15 225 119 47%

Table 7.2: Results for known patterns of finite size

by DNA self-assembly and could be adopted for manufacturing of circuits in

emerging technologies. The patterns include layouts for the coplanar crossing

(Coplanar) [109], a 2-to-1 multiplexer (MUX2) [113], a two-input XOR gate

(XOR) [84], a 2-to-4 decoder (Dec24) [118], a 3-to-8 decoder (Dec38) [112], a

memory cell (Mem) [112], a full adder (FA) [84], an ALU [79] and the sequential

circuit S27 from the benchmark ISCAS89 suite (S27) [44]. Figure 7.15 shows

the pattern and the self-assembled outcome for the coplanar crossing layout.

Table 7.3 gives the results for these QCA layout patterns. PATS Tile achieves

on average a tile type reduction of 39% from the trivial tile set.


Pattern Area Size # of Tiles Types ReductionName (Pixel) Trivial Synthesized Percentage

Coplanar 14 × 22 308 189 39%

MUX2 64 × 56 3584 2192 39%

XOR 32 × 62 2232 1344 40%

Dec24 24 × 80 1920 1122 42%

Dec38 98 × 60 5880 3613 39%

Mem 28 × 72 2016 1209 40%

FA 58 × 68 3944 2468 37%

ALU 106 × 120 12720 7686 40%

S27 112 × 96 10752 6613 38%

Table 7.3: Results of QCA layout patterns

7.4 Errors in Synthesized Tile Sets

Because DNA self-assembly is error prone, we investigated the errors found in

the assembly of the tile sets synthesized using PATS Tile algorithm.

Because the tiles in the trivial tile set have bonds of unique type on every

side, an insufficient attachment will not result in any error in the final assembly.

For a pattern assembled from a trivial tile set, none of the processes introduced

in section 6.4 that are the usual cause of errors is applicable. In the synthesized

tile set, the bond types are not unique, so there is a higher probability of error

occurrence. Simulation using Xgrow has been employed to investigate the error

rate of synthesized tile sets. It has been shown that the error rate in the trivial

tile set is at least 2 orders of magnitude smaller than in the synthesized tile set.

The simulation parameters were set as follows: Gse = 10, Gmc varied from


18.0 to 19.5. The simulation window had 128× 128 growth sites for tile attach-

ment and the simulation time was set to 80, 000 seconds. The error rates of

the synthesized tile sets were compared with those of the known tile sets given

in [126] generating the same patterns. As shown in Figure 7.16(a), the two tile

sets generated by PATS (PATS BC and PATS Sier) have a similar error rate

and the two known tile sets (Known BC and Known Sier) have similar error

rates. The PATS-generated tile sets have a higher error rate under small values

of Gmc. However, when Gmc is large (corresponding to the scenario of growth

at low error rate), a synthesized tile set has a lower error rate. Figure 7.16(b)

shows the comparison of PATS generated tile sets and known tile sets for other

two patterns (line1 and line2) and similar results are observed.

7.5 Conclusion

The synthesis problem for generating a tile set for a finite pattern has been

presented as a combinatorial optimization problem referred to as the Pattern

self-Assembly Tile-set Synthesis (PATS) problem. A graph model has been

proposed for analyzing the tile sets assembling a specified patterns. The PATS

problem has been analyzed by utilizing the proposed graph model; it has been

proved that the PATS problem is equivalent to the minimum graph coloring


Known tile set vs. PATS generated tile set

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

18 18.5 19 19.5

Gmc

Err

or

rate

PATS BC

PATS Sier

Known BC

Known Sier

(a) “Sierpinski” and “Binary Counter”

Known tile set vs. PATS generated tile set

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

18 18.5 19 19.5

Gmc

Err

or

rate

PATS line1

PATS line2

Known line1

Known line2

(b) “line1” and “line2”

Figure 7.16: Error rate of tile sets for various patterns


problem, hence it is NP-complete.

Two greedy algorithms (referred to as PATS Tile and PATS Bond) have been

proposed for synthesis of tile sets for self-assembly. Both algorithms are O(l4)

complexity for a square pattern of size l × l. Different patterns were used to

verify and evaluate the algorithms and PATS Tile was found to have superior

performance.

Self-assembly from the tile sets synthesized by the proposed algorithms was

simulated using Xgrow. Compared with tile sets found in the technical literature,

patterns by synthesized tile sets have a higher error rate at low Gmc, but a lower

error rate at large Gmc.

Chapter 8

Error Tolerance in DNA

Self-Assembly

Among various error resilient techniques for DNA self-assembly (Section 6.5),

error tolerant blocks have received intensive research because they only change

logic design of tile sets and can be used in combination with other error re-

silient techniques that change the chemical reaction in DNA self-assembly. In

comparison with the 2k × 2k snake redundant blocks, the (2k − 1) × (2k − 1)

snake redundant blocks reported in this chapter use odd-sized square block. A

case study on both types of snake redundant blocks are pursued in this chap-

ter. 3 × 3, 4 × 4, 5 × 5 and 6 × 6 snake redundant blocks are studied. Markov

196

CHAPTER 8. ERROR TOLERANCE IN DNA SELF-ASSEMBLY 197

models are used to analyze the error occurrence in DNA self-assembly under

these error tolerant techniques. The models show analytically that an odd-sized

snake redundant block has a smaller error rate for facet roughening errors than

an even-sized snake redundant block. The results from the model are supported

by simulation results using Xgrow [123].

8.1 (2k − 1) × (2k − 1) Snake Redundant Blocks

The (2k-1)×(2k-1) snake redundant block follows the same construction rule

as the 2k × 2k redundant block proposed by Chen [18], though each tile in

the original design is replaced by a block with (2k-1)×(2k-1) tiles. The bonds

internal to the block are assigned unique bond types thus reducing growth errors.

Null bonds (with zero bonding strength) and double bonds (with twice the

bonding strength as normal bonds) are placed inside the block, so that the

growth direction inside the block is snake-shaped, as shown in Figure 8.1(a).

The case k=2 (i.e. a 3× 3 snake redundant block) is presented as an example in

Figure 8.1(a). Each tile in the original DNA assembly is substituted by a 3 × 3

block (9 tiles per block). By construction, the 3 × 3 block is a strict subset of

the 4 × 4 block by removing the north and west edges. 5 × 5 and 6 × 6 snake

redundant blocks (Figure 8.2) can also be built following the same rule, and


they are also studied as examples with k = 3.

T1

T2T3

T4

T6

T7 T8 T9

T5

T

B

A

A

(a) 3x3 Snake Tile Set

T1

(b) Facet Roughening Error

T4T1 CT5

Figure 8.1: The 3 × 3 Snake Redundant Block

The error tolerance of the 3× 3 snake redundant block is related to the null

bonds in the block. Figure 8.1(b) shows the approach by which a facet rough-

ening error can be handled. Assume that an insufficient attachment occurs (the

shaded tile, tile T1 in the snake block). A strongly-binding tile can attach to

site B, but not to site A due to the null bond on the west side of the shaded

tile. Even if this error grows with the attachment of tile T5 and then T4 (as

shown in the figure), neither site A nor site C will allow a strongly-binding tile

to attach. Thus, another insufficient attachment must occur for the growth to


T1

T2T3

T4

T6

T7 T8 T9T14

T15

T16

T13 T12 T11 T10

T5

(a) A block in 5x5 Snake Tile Set

T17

T18

T19

T20

T21 T22 T23 T24 T25

T1

T2T3

T4

T6

T7 T8 T9T14

T15

T16

T13 T12 T11 T10

T5T17

T18

T19

T20

T21 T22 T23 T24 T25

T26T27T28T29T30T31

T32

T33

T34

T35

T36

(b) A block in 6x6 Snake Tile Set

Figure 8.2: Snake Redundant Blocks with Block Size of 5 × 5 and 6 × 6

continue. [128] has shown that growth including adjacent insufficient attach-

ments is significantly less probable to occur in DNA self-assembly than a single

insufficient attachment. With a similar mechanism for tolerance to growth and

facet roughening errors, the proposed snake redundant block incurs in a smaller

area overhead than the 2k × 2k snake redundant block, for a fixed k. As an

example, the area overhead of the 3× 3 snake redundant block is 800% and less

than the 4 × 4 snake redundant block (i.e. an overhead of 1500%).

Figure 8.3 shows the Xgrow simulation results of the Sierpinski triangle as-

sembled by a 3 × 3 snake redundant block. The following features must be

considered for the proposed 3 × 3 redundant block compared with the 4 × 4

snake redundant block.

• The size and therefore the information redundancy of the blocks in the

3× 3 snake redundant block is less than the 4× 4 snake redundant block.


Figure 8.3: Xgrow Simulation Results using the 3 × 3 Snake Redundant Block

• In the 3 × 3 snake redundant block, a facet roughening error can grow up

to three tiles, until it is stalled by the null bonds on both ends (as shown

in Figure 8.1b). A facet roughening error in the 4 × 4 snake redundant

block can grow up to two tiles (in the x-direction) or four tiles (in the

y-direction).

So, compared with the 4 × 4 snake redundant block, tolerance to growth

errors of the 3 × 3 snake redundant block is expected to be worse; tolerance to

facet roughening errors of the 3 × 3 snake redundant block should be better in

the y-direction and worse in the x-direction. However, the interactions present

in a tile growth process for self-assembly are numerous and make it complicated

to give an analytical comparison of the snake redundant blocks. A simplified

analysis of the tolerance to facet roughening errors will be presented to compare


the error tolerance of four redundant blocks (3 × 3, 4 × 4, 5 × 5 and 6 × 6

redundant blocks), followed by simulation results verifying the analysis.

8.2 Modeling Tolerance to Facet Roughening

Errors

An exact model of facet roughening errors under the snake redundant block

technique is extremely complicated due to the large number of possible paths of

occurrence in the association and d’s-association of tiles. We model the genera-

tion of a facet roughening error using an approximation that only considers the

most likely generation path of errors. As shown in Figure 8.4, the most likely

occurrence path for generating a facet roughening error in a generalized snake

redundant block can be divided into four stages (some stage may consist of more

than one step).

1. Initially in the first stage, a tile is attached to a “smooth” facet (from

the error-free State FF to State 1). The rate of attachment (association)

is given by f = N × ron = N × ka × e−Gmc , where N is the number

of tiles in the smooth facet, ron, ka and Gmc are parameters as defined

in Chapter 6. As the bonds inside the blocks are unique, an insufficient


attachment with matched internal bounds will just add a correct tile. So

only the bonds at the boundary of the blocks are considered as relevant

to a facet roughening error. Thus, the initial error must be in the lowest

row (rightmost column) for the x-direction (y-direction) facet roughening

error. The initial erroneous tile has total bond strength of 1. The rate for

this single erroneous tile to fall off is ka × e−Gse

2. In the second stage (State 1 to State P), new tiles attach around the single

tile until growth is stalled by the null bonds in the block. Depending on

k, there can be many states between State 1 and State P.

3. In the third stage, a weakly-binding tile attaches to the top of the exist-

ing facet roughening error tiles (from State P to State NL). The rate of

attachment is given by f = 3ka×e−Gmc , while the fall-off rate is ka×e−Gse .

4. Finally in the fourth stage, new tiles attach around the tile added in stage

3. Thereafter, the facet roughening error can grow in a snake-shape and

will not be stalled by the null bonds in the tile blocks (reaching State F).


FF

C C CCC C C CCC

E E E

CC

E

C CC ...

...

Ffaulty

E

E E

CC

E

C CC

E

E E

CCC C

E

E

C

E E

C C

1 NL F

Stage 3 Stage 4

P... ...

Stage 2Stage 1

(fault free)

FF 1

(1 tile)

P

(pause by)

(null bonds)

NL(new layer)

...

...

...

...

Figure 8.4: Generalized Markov Model for Facet Roughening Error Generationin Snake Redundant Blocks

8.2.1 Model for 3 × 3 Snake Redundant Block

The generalized model above is applied to the snake redundant blocks inves-

tigated. Markov models with slight modification to the generalized model are

created. The model for 3 × 3 snake redundant block is shown in Figure 8.5(a).

In this model, there are 6 states in the four stages.

This model changes the Stage 2 of the generalized model to characterize the

3 × 3 snake redundant block. The second stage consists of two steps, State P

in Figure 8.4 is now labeled as State 3 and a new state (i.e., State 2) is added.

In each step from State 1 to State 2 and from State 2 to State 3, only one

tile is added. The fall-off rate in both steps in Stage 2 is 2ka · e−2Gse . If the

erroneous tile in State 1 has a null bond, then there is only one growth site for


the second tile (Figure 8.5(b)). If that tile has no null bond, then there are two

growth sites (Figure 8.5(c)). So, the attachment rate from State 1 to State 2 is

13× 2f + 2

3× f = 4

3f . The attachment rate from State 2 to State 3 is f .

In stage 3 (from State 3 to State NL), there are three sites that a new

tile can be attached to, so the attachment rate is now 3f . The fall-off rate is

ka · eGse . If this new tile is located at the edge of the three tiles of the lower

layer (Figure 8.5(d)), then there is only one growth site in stage 4 (from State

NL to State F)1. If the new tile is on top of the middle tile of the lower three

tiles (Figure 8.5(e)), then there are two growth sites in stage 4. Thus, the tile

attachment rate in stage 4 is 43f and the fall-off rate is 2ka · e−2Gse .

The Markov model is solved and the generation rate of a facet roughening

error in a 3×3 snake redundant block is given by (8.1), where A denotes ka·e−Gse ,

B denotes 2ka · e−2Gse .

r3×3 = PNL × 4

3f =

16N · f5 · PFF

3A2B2 + 4AB2f + 12ABf2 + 12Af3 + 16f4(8.1)

1Although it is possible to grow a so-called dangling tile at the edge of the lower layer, thetwo tiles of the upper layer much likely will fall off because they only have a bond strength ofone to connect them to the crystal.


FF 3 F

k e−Gse

N f

21−2Gse2k e

4f/3

−2Gse2k e

f

−Gsek e

3f

C C CCC

E EE

C C CCC

E E

E

E

C C CCC

C C CCC

E E

E E

E

C C CCC

E E

C C CCC

E

NL

C C CCC

EE

C C CCC C C CCC

E E

E

E

C C CCC

E E

E

E

Stage 1 Stage 2 Stage 3 Stage 4

3(3 tiles)

NL(new layer)

Ffaulty

(fault free)

FF 1

(1 tile)

2

(2 tiles)

4f/3

(b) (c) (d) (e)

(a)

a a a a

Figure 8.5: Markov Chain Model for Facet Roughening Error Generation in the3 × 3 Snake Redundant Block


8.2.2 Model for 4 × 4 Snake Redundant Block

A similar model can be built for the 4×4 snake redundant block. The 4×4 snake

redundant block has a directional dependency for facet roughening errors, so two

different models are proposed respectively for both x-direction and y-direction

errors. For the y-direction, its second stage has three steps (four states). Figure

8.6(a) shows the Markov model.

FF 3

k e−Gse

N f

21

(fault free)

FF

C

C

C

C

C

E

1

(1 tile)

E C

C

C

C

C

C

C

C

C

C

C C C

E

2

(2 tiles)

4

(1 tile)

3

(1 tile)

4

E C

C

C

C

C

C

E

E

E C

C

C

C

C

C

E

E

E

E C

C

C

C

C

C

E

E

E

NL(new layer)

E C

C

C

C

C

C

E

E

E

Ffaulty

E E

E

−2Gse2k e

3f/2

−2Gse2k e

5f/4

−2Gse2k e

f

FNL−Gsek e

4f 3f/2


(a) 4x4 snake y−direction

C C CCC C C CCC

E

C C CCC

E

C C CCC

E

E EE

E E

NL(new layer)

Ffaulty

C C CCC

E E

2

(2 tiles)

FF

k e−Gse

N f

1 FNL−2Gse2k e

f

−Gsek e

2f

2


f

(fault free)

FF 1

(1 tile)

(b) 4x4 snake x−direction

a a a a a

a

aaa

Figure 8.6: Markov Chain Model for Facet Roughening Error Generation in a4 × 4 Snake Redundant Block


So, the generation rate of the y-direction facet roughening error is

r4×4 y = PNL×3

2f =

45N · f6 · PFF

4A2B3 + 6AB3f + 24AB2f2 + 24ABf3 + 30Af4 + 45f5(8.2)

For the x-direction, the Markov model has only one step in its second stage.

This is shown in Figure 8.6(b). The generation rate of a steady facet roughening

error in the x-direction is

r4×4 x = PNL × f =2N · f4 · PFF

A2B + ABf + 2Af2 + 2f3(8.3)

As f = ka · e−Gmc and Gmc ≈ 2Gse (as usually set in a DNA self-assembly

process), it follows that B = ka · e−2Gse ≈ f and A = ka · e−Gse >> f . So,

(8.1)-(8.3) can be compared as

r4×4 x : r3×3 : r4×4 y ≈ 2

A2B:

16f

3A2B2:

45f2

4A2B3

= 2 :16

3e2Gse−Gmc :

45

4e4Gse−2Gmc ≈ 2 :

16

3:45

4(8.4)


Figure 8.7 shows the error rates for Gse = 10 and Gmc ∈ [18.2 : 19.0]. The

above analysis is based on a Markov model with approximations in the gener-

ation of facet roughening errors, nevertheless analytical data show agreement

with simulated data (Section 8.3) with respect to a qualitative rather than an

exact quantitative measure. The Markov model analysis successfully shows that

the facet roughening error rate in the 4 × 4 snake redundant block for the x-

direction is the lowest of the three rates, while the rate for the 4 × 4 snake

redundant block in the y-direction is the highest. Let the facet roughening error

rate of the 4 × 4 snake redundant block be given by the average of the rates in

both directions. Then, this analysis also shows that the 3 × 3 snake redundant

block exhibits a facet roughening error rate that is considerably less than the

4×4 snake redundant block. This conclusion is also confirmed by the simulation

results in Section 8.3.

8.2.3 Model for 5 × 5 and 6 × 6 Snake Redundant Block

Consider next the redundant blocks with k=3. For the 5 × 5 and 6 × 6 snake

redundant blocks, growth of a facet roughening error depends on the position

of the initial erroneous tile (as shown in Figure 8.8). The error can start from

one of the following cases and the error growth rate of each case is known from


18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 19

10−15

10−14

10−13

Gmc

Err

or

ge

ne

rati

on

ra

te (

× k

)

Error generation rate of facet roughening error

3x3snake4x4snake−x4x4snake−y4x4snake−avg5x5snake6x6snake−x6x6snake−y6x6snake−avg

Figure 8.7: Generation Rate of Facet Roughening Errors

previous analysis of the 3 × 3 and 4 × 4 snake redundant blocks.

1. If the first tile attached is one of those marked as “A” in this figure, then

growth will be stalled by the null bonds after two tiles are attached. The

growth rate is r2t = 2N ·f4·PFF

A2B+ABf+2Af2+2f3 .

2. If the first tiles is a “B” tile in the figure, then growth will be stalled after

three tiles. The growth rate is r3t = 16N ·f5·PFF

3A2B2+4AB2f+12ABf2+12Af3+16f4 .

3. If the first tile is a “C” tile in this figure, growth will be stalled after four

tiles. The growth rate is r4t = 45N ·f6·PFF

4A2B3+6AB3f+24AB2f2+24ABf3+30Af4+45f5 .

It is assumed that every tile at the bottom or right boundaries of a block

has the same probability to be the first tile in a facet roughening error. For the


A A

A

A

B

B

B

BB A A A AA

A

A

C

C

C

CA

(b) 6x6 Snake Tile Set(a) 5x5 Snake Tile Set

A tile in x−directionC tile in y−direction

Figure 8.8: Facet Roughening Error in 5× 5 and 6× 6 Snake Redundant Blocks

5 × 5 snake redundant block, independently of the direction, 40% of the facet

roughening errors starts with a “A” tile and 60% starts with a “B” tile. For

x-direction facet roughening errors in a 6×6 snake redundant block, all of them

start with a “A” tile. For the y-direction in a 6 × 6 snake redundant block, it

will start with 13

probability from “A” and with 23

probability from “C”. So the

respective facet roughening error generation rates are:

r5×5

=2

5

2N · f4 · PFF

A2B + ABf + 2Af2 + 2f3+

3

5

16N · f5 · PFF

3A2B2 + 4AB2f + 12ABf2 + 12Af3 + 16f4

r6×6 x =2N · f4 · PFF

A2B + ABf + 2Af2 + 2f3(8.5)


r6×6 y

=1

3

2N · f4 · PFF

A2B + ABf + 2Af2 + 2f3

+2

3× 45N · f6 · PFF

4A2B3 + 6AB3f + 24AB2f2 + 24ABf3 + 30Af4 + 45f5(8.6)

Figure 8.7 shows the facet roughening error generation rates for Gse = 10

and Gmc ∈ [18.2 : 19.0]. This Markov analysis is based on an approximation

that only considers the most likely generation path of facet roughening errors.

Therefore, only a qualitative comparison is possible. This analysis shows that

the facet roughening error rates of the 4 × 4 and 6 × 6 snake redundant blocks

in the x-direction are the lowest. The 4 × 4 y-direction has the highest error

generation rate. The average rates have been calculated for the 4× 4 and 6× 6

snake redundant blocks; their average error generation rates are higher than the

error generation rates of the proposed 3 × 3 and 5 × 5 snake redundant blocks.

8.3 Simulation and Discussion

To verify the analysis of the Markov models in last section, different scenarios

of self-assembly and errors are evaluated by simulation in Xgrow. The growth

of a single crystal is simulated. The simulated assembly area contains 256× 256


growth sites for potential tile attachment. The results reported by Xgrow include

the total number of tiles in the crystal, the number of mismatched tiles, and the

total simulation time. The simulation time does not refer to the CPU or machine

time, it is the simulated time of the crystal growth as measured by Xgrow.

8.3.1 Error Rate in Assembly of Sierpinski Triangle

The self-assembly of the Sierpinski triangle pattern was simulated using the

3 × 3 proofreading redundant block, the 4 × 4 proofreading redundant block,

the proposed (2k-1)×(2k-1) snake redundant block (for k=2 and 3) and 2k× 2k

snake redundant block (for k=2 and 3). Gse = 10 and Gmc was varied from 18.0

to 19.5. The simulation time was set to 80, 000 seconds. The speed of growth and

the error rate of the different error tolerant methods were compared. Simulation

was repeated 50 times for each case to obtain the average value. The speed of

growth is shown in Figure 8.9(a) and is measured as√

Ntile/T , where Ntile is

the number of tiles assembled in the DNA crystal and T is the simulation time.

Since all simulations give a roughly triangular shaped assembly at the end of

the 80, 000 seconds simulation time,√

Ntile gives the dimension (not the area) of

the assembly. The growth speed in terms of the one dimensional size is constant

through the self-assembly process, while the growth speed in terms of area (or


Ntile) increases when the total area of the DNA assembly increases. So√

Ntile/T

(referred to as the 1-dimension tile growth rate) is used to compare the growth

speed. As shown in Figure 8.9(a), every plot shows two distinct parts. (1) At

a higher Gmc value, the tile growth rate decreases smoothly as a function of

Gmc. (2) At a lower Gmc value, it does not always show a smooth trend and

the growth rate does not increase with a decrease of Gmc as fast as in the first

part of the curve. It is because when the number of errors in the assembly is

large, an error tolerant method for preventing an erroneous growth may affect

the speed of the assembly.

Approximately the same growth rate is encountered for the 3 × 3 and 4 × 4

proofreading tiles. Due to the snake-shaped serial growth within the blocks

(instead of the parallel growth in the proofreading redundant block), snake re-

dundant blocks have a lower growth rate. The larger the block size of the snake

redundant block is, the slower it grows. This occurs because with a larger block

size, more serial growth is needed inside the blocks to assemble a crystal. The

transition between the two parts in the plots occurs for the snake redundant

blocks at a lower value of Gmc compared with proofreading redundant blocks;

this is caused by the lower error rate in the snake redundant blocks.

The outcome of self-assembly is the produced pattern, in which the basic


1 dimensional tile growth rate

0.00E+00

5.00E-04

1.00E-03

1.50E-03

2.00E-03

2.50E-03

3.00E-03

18.0

18.2

18.4

18.6

18.8

19.0

19.2

19.4

Gmc

tile

/se

c.

proof3

proof4

snake3

snake4

snake5

snake6

1 dimensional pattern growth rate

0.00E+00

1.00E-04

2.00E-04

3.00E-04

4.00E-04

5.00E-04

6.00E-04

7.00E-04

8.00E-04

9.00E-04

1.00E-03

18.0

18.2

18.4

18.6

18.8

19.0

19.2

19.4

Gmc

blo

ck

/se

c.

proof3

proof4

snake3

snake4

snake5

snake6

(a) (b)

Tile error rate

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

18.0

18.2

18.4

18.6

18.8

19.0

19.2

19.4

Gmc

err

or/

tile

proof3

proof4

snake3

snake4

snake5

snake6

Growth speed vs.error rate

0.00E+00

1.00E-04

2.00E-04

3.00E-04

4.00E-04

5.00E-04

6.00E-04

7.00E-04

8.00E-04

9.00E-04

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

2.5E-04

3.0E-04

3.5E-04

4.0E-04

4.5E-04

5.0E-04

error/tile

blo

ck

/se

c. proof3

proof4

snake3

snake4

snake5

snake6

(c) (d)

Figure 8.9: Comparison of Error Tolerant Methods for the Sierpinski TriangleAssembly


pixel is the block, not the tile. Hence, it is appropriate to measure the growth

rate in terms of blocks. This growth rate is referred to as the 1-dimensional

pattern growth rate and is given by√

Ntile/Sblock/T , where Sblock is the number

of tiles assembled in a block. As shown in Figure 8.9(b), a small block size

shows an advantage in terms of pattern growth speed, because it requires a

smaller number of tiles to assemble a block and eventually a pattern.

The tile error rate is the ratio of the number of mismatched (erroneous) tiles

and the total number of assembled tiles, as shown in Figure 8.9(c). The error

rates of all error tolerant methods are close to 0 when Gmc is large. However, the

Gmc threshold for error-free growth is 19.0 for proofreading redundant blocks,

while it is around 18.5 for snake redundant blocks. When errors occur, the error

rate is lower for snake redundant blocks than for proofreading redundant blocks

(this reduction is in orders of magnitude). Simulation results show that the

overhead of a large block size does not always bring the benefit of an increased

error tolerance. The error rate is roughly the same in the 3 × 3 and 4 × 4

proofreading tiles. The error rate of the snake redundant blocks is such that

snake4 > snake3 > snake6 > snake5 (where snakeI denotes the I × I snake

redundant block). It shows that for a snake redundant block with block size of

2k × 2k (k = 2, 3, . . .), an increase of k results in an increase in error tolerance.


The same result is applicable to the snake redundant block with block size (2k-

1)×(2k-1) (k = 2, 3, . . .). However, for the same k, the (2k − 1)-sized snake

redundant block has a lower error rate than the 2k-sized snake redundant block,

i.e. an odd-sized block is better that an even-sized block.

The error rate is plotted against the pattern growth speed for each error

tolerant method in Figure 8.9(d). This shows the error rate that can be achieved

for a pattern growth speed. The 3× 3 snake redundant block has the least error

rate given the same pattern growth speed. In summary, the proposed 3×3 snake

redundant block has the best performance in error tolerance. Its pattern growth

rate ranks second together with the 4 × 4 proofreading redundant block among

the six error tolerance methods simulated. For the same level of error rate, the

proposed 3 × 3 snake redundant block can achieve the highest pattern growth

rate.

8.3.2 Tolerance of Facet Roughening Error

Simulation has also been performed regarding the tolerance to facet roughening

errors. As pointed out in Section 8.2, the 4 × 4 snake redundant block has an

error tolerance to facet roughening error that is direction dependent, i.e. in the

x-direction or in the y-direction. The same analysis is applicable to the 6 × 6


snake redundant block. So, x-direction and y-direction facet roughening errors

are considered separately for these two redundant blocks. In the simulation for

facet roughening in the x-direction, the vertical boundary tiles are removed from

the tile set, so the resulting crystal should contain only the horizontal boundary.

However, in the presence of a facet roughening error, the rule tiles will attach

to the horizontal boundary on a layer by layer basis. In the simulation for facet

roughening in the y-direction, the horizontal boundary tiles are removed from

the tile set and facet roughening therefore occurs on the vertical boundary. An

example of a facet roughening error in the y-direction is shown in Figure 8.10.

This is the Xgrow simulation result of the Sierpinski 3×3 proofreading redundant

block. The total simulation time is given by 278, 220 seconds for Gse = 10 and

Gmc = 18.5. The facet roughening error along the vertical boundary can be

clearly observed.

Simulation has been performed using Gse = 10 for different values of Gmc.

In each simulated case, the crystal is allowed to grow for a simulation time

of Tmax = 400, 000 seconds. The following figures report the number of error

tiles, i.e the number of rule tiles in the final crystal, representing the extent of

the facet roughening error. More rule tiles exist in the final crystal, then more

severe is the facet roughening error. For each pair of Gse and Gmc, simulation


Figure 8.10: Facet Roughening Error of 3 × 3 Proofreading Redundant Block

Figure 8.11: Facet Roughening Errors in the x-Direction

has been repeated 20 times. The average of the total number of error tiles has

been computed and reported in Figure 8.11 and Figure 8.12. The vertical error

line shows the standard deviation for each case.

It can be seen that for all redundant blocks, the facet roughening error is

more severe at a smaller value of Gmc. Moreover. snake redundant blocks are


Figure 8.12: Facet Roughening Errors in the y-Direction

more tolerant to facet roughening errors in both the x-direction and y-direction

than proofreading redundant blocks, this is as expected. For instance, for snake

redundant blocks when Gmc = 19 there is virtually no facet roughening error,

while there is still a roughening error for the proofreading redundant blocks.

In both the x and y direction, the 4 × 4 proofreading tiles have slightly better

tolerance to roughening than the 3×3 proofreading tiles. For 4×4 and 6×6 snake

redundant blocks, facet roughening errors have a much more severe impact in

the y-direction than the x-direction. For the y-direction facet roughening error,

the 3×3 snake redundant block is better than the 4×4 snake, and the 5×5 snake

is better than the 6 × 6 snake. For the x-direction, the 3 × 3 snake redundant

block and the 5 × 5 snake redundant block have more facet roughening errors

than the 4 × 4 and 6 × 6 snake redundant block. This agrees with the estimate


in Section 8.2 using an analytical Markov model.

8.4 Discussion on Error Rate and Number of

Tile Types

As shown previously, although the 4×4 snake redundant block has a higher block

redundancy than the 3 × 3 snake redundant block, the 3 × 3 snake redundant

block has a lower error rate. At first, one may explain this as there are more

types of tiles in the 4×4 snake redundant block, then any growth location has a

higher probability of attaching a mismatched tile. Simulation has been pursued

to verify this possible explanation. A so-called “null” tile type has been added

to the tile set, i.e. this tile has no matched bond with any other type of tiles

in the set. This null tile acts as a mismatched “competitor” to any correct tile

in the assembly process; therefore, its appearance emulates the scenario of an

increase in the number of tile types. For example, if the concentration of the

null tile is 30 times as much as the normal tile (based on the assumption that all

other tiles have the same concentration), its effect on the error rate is equivalent

to having 30 more tile types in the tile set. Simulation has been performed for

all error tolerant redundant block techniques. In the simulation, Gse = 10 and


the simulation time has been set to 80, 000 seconds. The concentration of the

null tile has been varied from 5 to 200 times the concentration of the normal

tiles. The cases with Gmc = 18.3 and Gmc = 18.8 have been simulated. Every

simulation has been repeated 30 times to obtain the average value.

The error rate is plotted against the concentration of the null tile in Fig-

ure 8.13 for each tile set using error tolerant redundant block technique. Fig-

ure 8.13(a) shows the scenario when Gmc = 18.3, while in (b) Gmc = 18.8. The

error rate in both cases shows no definitive trend (i.e., either increasing or de-

creasing) with an increase of null tile concentration. This result shows that the

lower error rate of the proposed 3 × 3 (5 × 5) snake redundant block compared

with the 4 × 4 snake redundant block (6 × 6) is not caused by the increased

number of tile types in the tile set.

The removal of the west and north edges (7 tiles in total) from the block of

a 4× 4 snake redundant block forms the block of a 3× 3 snake redundant block.

This change may contribute to the error rate reduction: the removed tiles are

effectively a “wrapper” to the internal 9 tiles and do not contribute to error

tolerance. The directional dependency of the error tolerance for an even-sized

tile block to facet roughening errors may also contribute to a higher error rate.

These facts need to be investigated in future work to find an explanation to the


better error tolerance ability of odd-size snake redundant blocks.

(a)

(b)

Figure 8.13: Error Rate versus Null Tile Concentration


8.5 Conclusion

(2k-1)×(2k-1) snake redundant block has been proposed for DNA self-assembly.

Analysis and simulation have been performed to evaluate this technique.

Markov models have been presented for facet roughening errors in snake

redundant blocks, including the proposed (2k-1)×(2k-1) snake redundant blocks

and 2k × 2k snake redundant blocks. A detailed analysis based on this model

has been presented for facet roughening errors. Although the Markov models

include an approximation, simulation results have confirmed the validity of this

analysis for both k = 2 and k = 3.

A comparison of different fault tolerant techniques have been summarized in

Table 8.1.

• As expected, snake redundant blocks are more tolerant to facet roughening

errors in both the x-direction and y-direction than proofreading redundant

blocks. For y-direction facet roughening errors, the 3× 3 snake redundant

block is better than the 4× 4 snake, and the 5× 5 snake is better than the

6× 6 snake. For the the x-direction, 3× 3 snake redundant block has less

(more) facet roughening errors compared with the 4 × 4 snake redundant

block in the y-direction (x-direction).


• The growth speeds of different error tolerant methods have been evaluated

by simulation. Given the same Gse and Gmc, the 3×3 and 4×4 proofreading

tiles have almost the same tile growth rate. Snake redundant blocks have

a lower tile growth rate. The snake redundant block with larger block

size has slower tile growth rate due to the serial growth needed in the

block to assemble a crystal. In terms of pattern growth speed, small block

size shows an advantage because it requires a smaller number of tiles to

assemble a block and eventually a pattern.

Overall, the proposed (2k-1)×(2k-1) snake redundant blocks have better er-

ror tolerance, less area overhead and faster growth speed. Especially for 3 × 3

snake redundant block, it has the least error rate given the same pattern growth

speed. Its growth rate ranks second overall and first among all snake redundant

blocks studied. This comparison result shows that the overhead of a large block

size does not always bring the benefit of an increased error tolerance. The error

rate is roughly the same for the 3×3 and 4×4 proofreading tiles. The error rate

of the snake redundant blocks is such that snake4 > snake3 > snake6 > snake5

(where snakeI denotes the I × I snake redundant block). So, for 2k × 2k snake

redundant blocks, an increase of k results in an increase in error tolerance. The

same result is applicable to the (2k-1)×(2k-1) snake redundant blocks. However,


Redundant Area Growth Pattern Error rate Facet rougheningblock over- speed growth Under same Under same error tolerance

head speed Gm growth rate x-dir y-dir Avg.Proof3 800 1 1 5 2 5 5 5Proof4 1500 1 2 5 3 5 5 5Snake3 800 2 2 3 1 3 2 2Snake4 1500 3 3 4 3 1 4 4Snake5 2400 4 4 1 3 2 1 1Snake6 3500 5 5 2 4 1 3 3

(%) 1-fastest,5-slowest 1-lowest,5-highest 1-best,5-worst

Table 8.1: Comparison of Error-Tolerant Redundant Blocks

for the same k, the odd-sized snake redundant block has a better error tolerance

than the even-sized snake redundant block.

Simulation with “null” tiles has shown that it is incorrect to assume that

the presence of more tile types in self-assembly may cause a higher error rate.

Further work is needed to understand the effect of k in odd-size and even-size

snake redundant blocks, given the same redundancy level (i.e. k).

Chapter 9

Conclusion and Future Work

Innovative nanotechnologies emerge from the intersection of science (such as

physics, biology, material science) and information technology. The topics in-

vestigated in this dissertation, QCA and DNA self-assembly are two examples of

the promising technologies generated from this interdisciplinary research method

that have the potential to supersede CMOS based VLSI.

QCA encodes information with the location of electrons in a set of quantum

dots and computes with Coulomb interaction. It boasts the advantage of ultra-

low energy dissipation and has been proposed to implement reversible logic.

DNA self-assembly uses specially engineered DNA tiles to carry information

and perform algorithmic operation. By selective reaction of sticky ends, DNA

226

CHAPTER 9. CONCLUSION AND FUTURE WORK 227

tiles bond together and form a organized assembly according to the information

entailed in the tiles. The tile arrangement in the assembly can be the time-space

trace of a Turing machine so DNA self-assembly can be a computing method.

Or, the assembly can be a substrate bearing predesigned patterns so DNA self-

assembly can be a nano-scale manufacturing technology.

The operation of the emerging technologies base on a totally different set of

physical/biochemical phenomena. Moreover, because the error rate in nanotech-

nology is much higher than CMOS technology it is especially a great challenge

to build a reliable system with the nanotechnologies. With these new features, it

is necessary to investigate the principles of the modeling, design, test and fault

tolerance in QCA and DNA self-assembly. Various aspects of the technologies

are analyzed in this dissertation.

The operation of QCA circuits entails quantum tunneling and Coulomb in-

teraction of electric quadrupoles. Its modeling is different from the modeling of

CMOS devices. A new mechanical-based model has been proposed for analyzing

the computing and the reversibility in QCA. By avoiding a full quantum-thermo-

dynamical calculation, its simplicity enables this model to be used as a versatile

tool for manual evaluation of different features (such as energy consumption

for reversible computing and clocking schemes) at device and circuit levels for


molecular QCA implementation. In particular, the reversibility of several basic

QCA circuit blocks has been studied.

New reversible gates have been proposed targeting efficient implementation

using QCA. It has been shown that the proposed QCA gates has smaller area

and faster speed in comparison with the well-studied Toffoli gate and Fredkin

gate. Testing of reversible QCA gate array has been studied considering the

fault characterization of QCA gates and the feature of reversible gates. Testa-

bility of different array configuration has been analyzed and test cases have

been presented showing the test methods for different gates and different array

configurations.

Fault tolerance by voting is suitable for QCA circuit because majority voter

has a compact implementation in QCA. NAND multiplexing is inspiring for QCA

circuits because it can be expanded to deal with high fault rate. Combining the

two technology, Maj-MUX has been studied in terms of fault tolerant capability

and signal recovery speed. The implication of this fault tolerant technique on

the reversibility of the QCA reversible circuit has also been investigated.

The design of a DNA self-assembly tile set for fabricating a finite-size pattern

from “bottom-up” is a topic that has not been addressed in the literature. This

problem has been formalized as a combinatorial optimization problem with the


help of a graph model. The problem has been proven to be NP-complete and

greedy algorithms for the problem have been presented.

Although they share the principle of spatial redundancy, error tolerance in

DNA self-assembly is very different from fault tolerance in CMOS circuits. A

new error tolerant technique called (2k-1)×(2k-1) snake redundant block has

been proposed. It adopts spatial redundancy by replacing each tile in the original

self-assembly tile set with a block of (2k-1)×(2k-1) tiles. It has been shown that

this snake redundant block is superior than the similar error redundant technique

in the literature, in terms of area overhead, growth speed overhead and error

tolerant capacity.

QCA and DNA self-assembly, similar to many other nanotechnologies, are

facing many challenges. The reliability of the technologies are one of the biggest

challenges. With error rate has high as 10% at device level, the error tolerant

techniques must be further improved to build a reliable system with a acceptable

amount of redundant overhead. New design methodology as well as CAD frame-

work are necessary to improve the design capability of QCA reversible circuit.

It is essential to improve the algorithm solving DNA tile set synthesis problem

in order to manufacture a nano-electronic circuit using this technology.

Appendix A

An index of the chapter numbers and the associated publications (either fully

or partially used) is provided as follows:

Chapter 2 (Review of Reversible QCA):

Partial: X. Ma, J. Huang and F. Lombardi, “A Model for Computing

and Energy Dissipation of Molecular QCA Devices and Circuits”,

accepted and to appear in ACM Journal on Emerging Technologies

in Computing Systems(JETC)

Partial: X. Ma, J. Huang, C. Metra and F. Lombardi, “Testing Reversible

1D Arrays of Molecular QCA”, accepted and to appear in Journal of

Electronic Testing: Theory and Applications (JETTA)

Chapter 3 (A Mechanical Based QCA Model):

230

APPENDIX A. 231

Full: X. Ma, J. Huang and F. Lombardi, “A Model for Computing and En-

ergy Dissipation of Molecular QCA Devices and Circuits”, accepted

and to appear in ACM Journal on Emerging Technologies in Com-

puting Systems(JETC)

Full: J. Huang, X. Ma and F. Lombardi, “Energy Analysis of QCA Cir-

cuits for Reversible Computing”, Proc. IEEE Conf. Nano-technology

’06, Vol. 1, pp.39-42, 2006 Jun

Chapter 4 (Reversible and Testable Circuits for QCA):

Full: X. Ma, J. Huang, C. Metra and F. Lombardi, “Testing Reversible

1D Arrays of Molecular QCA”, accepted and to appear in Journal of

Electronic Testing: Theory and Applications (JETTA)

Full: J. Huang, X. Ma, C. Metra and F. Lombardi, “Testing Reversible

One-Dimensional QCA Arrays for Multiple Faults”, Proc. 22nd IEEE

Intl. Sym. Defect and Fault Tolerance in VLSI Systems (DFT ’07),

pp. 469-477, 2007 Sep

Full: X. Ma, J. Huang, C. Metra and F. Lombardi, “Testing Reversible

1D Arrays of Molecular QCA”, Proc. 21st IEEE Intl. Sym. Defect

and Fault Tolerance in VLSI Systems (DFT ’06), pp .71-79, 2006

APPENDIX A. 232

Oct.

Chapter 5 (Fault Tolerance of Reversible QCA Circuits):

Full: X. Ma, J. Huang and F. Lombardi, “Fault Tolerant Schemes for

QCA Systems”, Proc. 23rd IEEE Intl. Sym. Defect and Fault Toler-

ance in VLSI Systems (DFT ’08), 2008 Oct

Chapter 6 (Review on DNA Self-Assembly):

Partial: X. Ma and F. Lombardi, “Synthesis of Tile Sets for DNA Self-

Assembly”, accepted and to appear in IEEE Tran. Computer Aided

Design (TCAD)

Partial: X. Ma, J. Huang and F. Lombardi, “Error Tolerant DNA Self-

Assembly Using (2k-1)×(2k-1) Snake Tile Sets”, accepted and to ap-

pear in IEEE Tran. NanoBioscience

Chapter 7 (Synthesis of Tile Sets for DNA Self-Assembly):

Full: X. Ma and F. Lombardi, “Synthesis of Tile Sets for DNA Self-

Assembly”, accepted and to appear in IEEE Tran. Computer Aided

Design (TCAD)

Full: X. Ma and F. Lombardi, “On the Computational Complexity of

APPENDIX A. 233

Tile Set Synthesis for DNA Self-assembly”, accepted and to appear

in IEEE Tran. Computer Aided Design (TCASII)

Chapter 8 (Error Tolerance in DNA Self-Assembly):

Full: X. Ma, J. Huang and F. Lombardi, “Error Tolerant DNA Self-

Assembly Using (2k-1)×(2k-1) Snake Tile Sets”, accepted and to

appear in IEEE Tran. NanoBioscience

Full: X. Ma, J. Huang and F. Lombardi, “Modeling Facet Roughening

Errors in Self-Assembly by Snake Tile Sets”, Intl. Test Conference

2007 (ITC ’07), Paper 27.3, 2007 Oct

Full: X. Ma, J. Huang and F. Lombardi, “Error Tolerance in DNA Self-

Assembly by (2k-1)×(2k-1) Snake Tile Sets”, Proc. 25th IEEE VLSI

Test Symposium (VTS ’07), pp. 131-140, 2007 May

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