physical design challenges beyond the 22nm nodephysical design challenges beyond the 22nm node kevin...
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Physical DesignChallenges Beyondthe 22nm Node
Kevin NowkaIBM Research - AustinIEEE International Symposium on Physical Design15 April 2010
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Outline
Background How have we gotten to where we are? What lies at 22nm and beyondChallenges in achieving something better than the path we are on Image fidelity Defectivity Accounting for multi-scale pheneomena Variability and “resilience” failuresSummary
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λ = 365nm
λ = 248nm
λ = 193nm
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'8 6 '8 8 '9 0 '9 2 '9 4 '9 6 '9 8 '0 0 '0 2 '0 4 '0 6 '0 8 '1 0
λ = 365nm
λ = 248nm
λ = 193nm
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Technology Resiliency -- PastDefects were the major yield detractors for technology in the early days, yield and area were the major tradeoffs.
Defect driven groundrules
Relative cell independence => Composable design
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Past: Rules for shorts and opensExtra conducting material Photolithographic printing
error Conductive particle
contamination Incomplete etch Incomplete metal polish
Missing conducting material
Electromigration Fast electrons transfer
momentum tometal atoms at grain boundaries,causing diffusive movement, thinning, open failure
Bridging short
EMfail
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Technology Rules (History)Resulting wire rules
S W
Wmin
WminWidth
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Two rules suffice to define the design space!
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Technology Resiliency – 22nm
Serious lithography challengesNow in a régime where atomistic effects are significant – gate oxide variation, random dopant variation, line edge roughness…No silver bullets -difficult engineering problems
Cell youplace heredetermines behavior of this cell
λ = 365nm
λ = 248nm
λ = 193nm
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'8 6 '8 8 '9 0 '9 2 '9 4 '9 6 '9 8 '0 0 '0 2 '0 4 '0 6 '0 8 '1 0
λ = 365nm
λ = 248nm
λ = 193nm
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'8 6 '8 8 '9 0 '9 2 '9 4 '9 6 '9 8 '0 0 '0 2 '0 4 '0 6 '0 8 '1 0
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Technology Rule ExplosionImpact of CMP, Dishing, Erosion as well as lithography...
S W
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Four or more rules for the same situation in order to accommodate technology complexity!
Wmin Wmax
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Technology ComplexityTechnology has become so complex that it is not well represented by “rules”.
Design / Technology interface information bandwidth needs are skyrocketing!
Expressing complex non-linear realities via rules is becoming difficult.
Technology
# Design Rules
100
300
500
700
900
1100
500nm 350nm 250nm 180nm 130nm 90nm 65nm 45nm
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Basics of Optical Lithography
Three major componentslight source
condenser
mask
lens
wafer
photo-resist
illumination
diffraction
lens trans-mission
source: Liu, CASS 2010
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Optical Lithography at 22nmGet painting!
Using 193nm wavelength to image sub-20nm features ~=
Using a 1 inch brush to create 2mm strokes
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Litho Progression NAk λ
1Resolution =
source: Liebmann, Semicon West ‘08
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Zeiss Starlith® 1700i lens
source: zeiss.com
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65nm M1 litho simulation
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32nm M1 litho simulation – no assist
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Improving Litho Variation with RETs
Simple shapes aren’t so simple!
Sub-ResolutionAssist Feature Optical Proximity Correction source: Liu, CASS 2010
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Improving Litho with Double Exposure
A pattern (interconnect metal level) is broken into two segments Optimized exposure conditions are used for each segment,
overcoming “corner effects” with single exposure
Double Exposure (DE) extends the use of current exposure technology to tighter pitch structures
1. Layout Design
3. X-dipole Exposure
2. Y-dipole Exposure
Split-X
Split-Y4. Single Developed
Image in ResistX-DipoleSource
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Improving Litho with Double Patterning
Frequency doubling through assignment of shapes into two phases
Pitch Split
Phase assignment problem can be exceptionally difficultsource: Wiaux, et al., “Split and Design Guidelines for Double Patterning”, SPIE 2008Liebmann, Semicon West ‘08
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What designers can do: Restrict Design
The technology cannot guarantee the outcome of a free form layout. Thus more restrictions are imposed on the layout.Usually driven by the technology limitationsStarted from FEOL, gradually migrate to BEOLTypical examples: Only allow uni-directional shapes
(at least for critical portion which defines the gate)
Only allow discrete width and spacing
Use Dummy shapes Avoid jogsCan’t come for free => AREA
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What designers can do: Regularity
Restricted Design Rules shows ~3x improvement in variability.
Source: L. Liebman, SPIE 04
RDR
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PD Challenges for 22nm and beyond
One: What can PD do to help balance the desire for density and the need for image fidelity?
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Is this the right abstraction for PD tools?
At/beyond 22nm …. Only at significant cost Means to maintaining arbitrary composability are
costly … probably too costly
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Is this the right abstraction?
No – PD shouldn’t need to go to PV band level
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Why does abstraction matter?
Visibility into / effect on the library Poly/contact/M1 within cell influence
performance, power, routability PD needs to be a partner in the tradeoffs
made within cell Placement clearly has effects within 22nm
“range of litho influence” for performance critical Poly and yield critical M1
Low level routing can have same effect for yield-critical M1
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Learning from SRAMs
M1 target M1 mask
Poly regularity is a done dealM1 is the 22nm design/manufacturing battleground: If litho range of influence is avoided in placement/routing, we
can envision preanalysis and library optimization for improved density, robustness…
Library avoidance of M1 – cost?Future: Just reapply at each level up the stack?
ApproxLithoRange ofInfluencein 22nm
Shapes can be preoptimized
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PD Challenges for 22nm and beyond
Two: What can PD do to help balance the requirements of density and defectivity?
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Critical Area Improvement
ISQED ’03, Dan Maynard, “Productivity Optimization Techniques for the Proactive Semiconductor Manufacturer”
Improved robustness to particle contamination!
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Critical Area Improvement
ISQED ’03, Dan Maynard, “Productivity Optimization Techniques for the Proactive Semiconductor Manufacturer”
Litho $&!*Net: Better or worse?
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Improving Yield with Via RedundancyLess yield loss due to via
redundancyM1 litho more difficult
M1 litho much easierMore yield loss due to via
coverage
How do we manage this tradeoff?What about performance?
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Measuring via resistance distributions key. Placement and redundancy
systematically effect resistance
We created a special structure to measure resistance of individual vias for various configurations.
Steps toward DfM for redundant vias
Wire 1
Via
~100,000Vias in an addressablearray
Wire 2
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Quantifying via resistance distributions
Via ResistanceUse in area vs yield tradeoff analysis
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Balancing density with defectivity
Need better models of yield vs area/power/performance for library designer, placement, routing, buffer insertion, …Manufacturing / Design / Automation all affected
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PD Challenges for 22nm and beyond
Three: How can PD affect multiscale phenomena?
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Long Range (mm-scale) Effects - CMP
Chemical-mechanical polishing (CMP) is used to planarize the wafer surfaceRoutinely used in dual damascene copper interconnect definition steps
source: horibalab.com
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CMP Dishing
source: D. Boning
Different metal wire density can cause changes in the height of ILD and metal layers Change of wire resistance and capacitanceCan further affect the up metal layer shape due to the tight photolithography latitudeCMP awareness showing up in tools flow
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Long Range (mm-scale) Effects - RTA
Rapid thermal anneal (RTA)Length scale: ~mm; layout pattern density dependentApproach: Joint TCAD-compact modeling effortsCan we do something better than fill?
VCO &Logic Data paths
0 200 400 600-10
0
10
20
Vth S
hift (m
V)
X Direction (µm)
Logic & Registers
test chip
Source: Y. Ye
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PD Challenges for 22nm and beyond
Final: Variability and “resilience” failures
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Confluence of variability effects -> SRAM “resilience” fail exposure
On-die arrays Need ~5 σ
effective cell yield for Mb arrays
Vmin issuesSymmetry/regularity allow Precharacterization
/ litho optimization Higher array
supplies/assist Row/column
redundancy ECC
0 1 2 3 4 5 6 7
x 10-8
0
1000
2000
3000
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800010s0 Pull Down historgram
Current [A]
Bin
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1.0
1.05
31.
105
1.15
81.
211
1.26
51.
318
1.37
11.
423
1.47
61.
529
1.58
21.
635
1.68
8M
ore
Bitline Cap Variation
NFETTunneling
Access devicethreshold
Q0.0 0.2 0.4 0.6 0.8 1.00.0
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Confluence of variability effects: future of “resilience” fail exposure
Latch, adder, mux, AOI, buffer, wire … resilience?Lack of symmetry/regularity What topological, functional analogs do we
have to: Precharacterization/litho optimization Higher array supplies/assist Row/column redundancy ECC
…. and how would they be supported in our design flows?
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Summary
Skills and expertise that surround silicon implementation at the technology, circuit, system and CAD levels all will play significant role in continued scaling at 22nm and beyond.Isolation of skills, however, will be increasingly less possible. eg. Effective routing algorithms will need to leverage
knowledge of how wires are created, and how router decisions will impact the resulting electrical parameters of the wire.
Simple technology abstractions that have worked for many generations like rectangular shapes, Boolean design rules, and constant parameters will not suffice to enable us to push designs to the ultimate levels of performance. Physical design must become more technology aware to fully contribute to solving challenging scaling problems.