22nm & 16nm node junction scaling
TRANSCRIPT
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22nm & 15nm Node Junction
Scaling Options
John Borland
J.O.B. Technologies, Aiea, HI
July 15, 2010
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Outline• Introduction
– Technology Roadmap Options
• USJ Technology:
– p+ USJ 22nm node and beyond
– n+ USJ 22nm node and beyond
• Strain Technology
– pMOS 22nm node and beyond
– nMOS 22nm node and beyond
• Summary
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Summary of Planar CMOS –vs-FinFET• VLSI Sym 2008: Planar CMOS to 22nm Node
– Intel said SRAM needs Bulk FinFET/Trigate at 16nm or Floating Body
Cell FD-SOI (Mark Bohr)
• IEDM 2008:
– Intel: Stated that FinFET not ready for 22nm node manufacturing (K.
Kuhn).
• VLSI Sym 2009:
– IBM: TC Chen stated at 16nm node body controlled devices (FD-SOI or
FinFET) will be required to extended CMOS to 11nm CMOS
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Intel, VLSI Sym 2008
short course
Toshiba, VLSI Sym
2006, paper 9.2
-TSMC April 2010: Planar bulk at 20nm node 5th gen SiGe & 2nd gen Hik/MG, 14nm
node maybe FinFET (S.Y. Chiang)
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FD/SOI With Dielectrically Isolated Back
Gates
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IBM/YH, VLSI Sym 2010, paper, 4.4
G. Shahidi, IBM, VLSI Sym
2010, paper 13.5
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Hybrid Localized SOI/Bulk Technology
Using Buried SiGe Layer/Channel
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ST/LETI, VLSI Sym 2010, paper 6.2
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Ultra-Thin-Body & Box (UTBB) FD-SOI
And Localized SOI (LSOI)
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IBM Alliance, VLSI Sym 2010, paper 6.3
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Intel’s 15nm
Node Floating
Body Cell
(FBC) FD-SOI
With Back
Gate Doping
Intel’s Silicon
on Replacemet
Insulator (SRI)
FBC Using
SiGe Etching
For LSOI
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Intel, VLSI Sym 2010, paper
15.1
Intel, VLSI Sym 2010, paper
15.4
Tip implant before spacer
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IEDM-2009: Intel 32nm
Node Low Leakage
Junctions
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Outline• Introduction
– Technology Roadmap Options
• USJ Technology:
– p+ USJ 22nm node and beyond
– n+ USJ 22nm node and beyond
• Strain Technology
– pMOS 22nm node and beyond
– nMOS 22nm node and beyond
• Summary
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Implant Energy Versus Xj
0
100
200
300
400
500
600
700
800
900
1000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Xj (nm)
Imp
lan
t E
ne
rgy
(e
V)
B
BF2
BF3
B
BF3
BF2
32nm Node
45nm Node
Borland, Semiconductor International, Dec. 2006, p.49
22nm Node15nm Node Intel FBC/SOI 22nm
IBM ET-SOI
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B, B18 & B36 Total Retained Dose (2nm oxide)
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B36
B18
B18/2E15
B
55%
70%
64%
78%84%
60%
70%
85%
Borland et al., JOB
2nm
surf
ace
oxid
e
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PCOR-SIMS Analysis
12Boron Xj (nm)
B %
In
2n
m S
urf
ace
Oxid
e
B
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Proof Of Surface Reflectance/Backscatter On
Retained Dose Limit & Implant Oxide Growth
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Ge Ox Xj R.Dose
H2 6.9nm 0.2nm
B 7.0nm 0.57nm 8.3nm 8.89E14
B18 6.9nm 0.45nm 7.7nm 8.44E14
B36 6.9nm 0.46nm 8.6nm 8.35E14
Ox 6.9nm 1.8nm
B 7.0nm 2.05nm 7.7nm 8.0E14
B18 6.7nm 2.18nm 7.6nm 6.09E14
B36 6.9nm 2.3nm 9.6nm 5.96E14
Ge shift due to oxide growth
Implant oxide growth
Renesas/JOB/EAG, SSDM-2010
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PCOR-SIMS Analysis Of Surface Oxide &
Retained Dose
14
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 10 20 30 40 50 60 70 80 90 100
B Retained Dose %
Su
rfac
e O
xid
e T
hic
kn
ess
(nm
)
B36(R)
B18(R) B(R)
B(R)
B18 & B36(R)
Borland et al., JOB
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Lower Residual Implant Damage &
Improve Device Leakage• Improve self-amorphization to reduce residual implant damage
with MSA
– Lower implant wafer temperature (cold or cryo-implantation) -10oC to
-160oC using chilled water of liquid nitrogen wafer cooling
– Use molecular dopants (B18H22, B36H44, As4 or P4) improves self-
amorphization
– Use heavier ions low dose for PAI & optimize amorphous depth (In, Sb
or Xe) at <5E13/cm2
• Stable defects and reduction in residual implant damage
thereby improving junction leakage
– Higher MSA peak temperature >1300oC
– Pre/post MSA diffusion-less spike/RTA 850-900oC
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PLi Of Flash And 900C Spike+Flash
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16Borland et al., JOB/Selete, IWJT 2007
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J.P. Lu, SMIC/KT, IWJT-2010 paper 1.5
Radiance spike/RTA signature
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Extension Results (Leakage)
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
900C spike Spike+FLA FLA+Spike Flash SPE SPE+FLA FLA+SPE
B200eV
5keVGe+B
890eVBF2
5keVGe+BF2
4keVB18H22
RsL Junction Leakage Current (A/cm2)
F effect: Noda (MRS 2008), Yamamoto
(IWJT 2008), England (IIT 2008 P41)
Yamamoto et al., IWJT 2008,
MSA pins F in substitutional
site and degrades leakage!
>1200C?Borland & Kiyama, JOB/DNS, IIT-2008
5keV Ge-PAI=9nm
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Poly & USJ Activation Roadmap
Spike/RTA
+
Flash or Laser-poly dopant diffusion & activation
-improved Tox(inversion)
-USJ diffusion
65nm & 45nm NodeLower Temperature
Spike/RTA-poly dopant diffusion
Flash or Laser-improved poly dopant activation
-improved Tox(inversion)
-USJ diffusion-less activation
Flash, Laser or SPE-USJ diffusion-less activation
45nm 28nm Node
22nm Node
Borland, Semiconductor International,
Dec. 2006, p.49
IBM VLSI 2007 45nm
1000C Spike
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Timans, Mattson, Semicon/West WCJUG July 2008
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Kato, Selete, IWJT-2010 paper 1.7
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EOR>9nm
EOR>32nm
EOR>16nm
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1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1175C
1225C
1275C
1325C
Laser Annealing Temperature
RsL
Ju
nct
ion
Lea
kag
e C
urr
ent
(A/c
m2)
24
Borland et al., IEEE-RTP-2009
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50 10010Xj (nm)
RS
(ohms/sq.)
100
1000
500
5000
5005
50Boron solid solubility:
B <1225C (Bss=5E19/cm3) RD=1E15/cm2
B 1325C (Bss=1E20/cm3)
Ge+B 1325C (Bss=1.3E20/cm3)
Xe+B 1325C (Bss=3.5E20/cm3)
BF2 1175C (Bss=3E19/cm3) RD=5.5E14/cm2
BF2 1325C (Bss=4E19/cm3)
Ge+BF2 1175C (Bss=6E19/cm3)
Ge+BF2 1225C (Bss=6E19/cm3)
Ge+BF2 1275C (Bss=7E19/cm3)
Ge+BF2 1325C (Bss=8E19/cm3)
B36 1325C (Bss=1.2E20/cm3) RD=6.7E14/cm2
Ge+B36 1325C (Bss=1E20/cm3)
In+B36 1325C (Bss=1E20/cm3)
Xe+B36 1325C (Bss=1.2E20/cm3)
Borland et al., RTP-2009
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Boron Dopant Activation With Laser Melt
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K. Kuhn, Intel, IWJT-2010 paper K2
1E15 dose: Rs=205 Bss=1.7E20/cm3
2E15 dose: Rs=132 Bss=3E20/cm3
4E15 dose: Rs=91 Bss=4E20/cm3
1E16 does: Rs=73 Bss=5E20/cm3
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22nm Node Dopant Options: Enhanced SDE &
HALO Dopant Activation/Amorphization• pMOS
– pSDE (1-3E15/cm2 dose limited by Bss?)• B: 100eV/1E15 (need PAI?)
• BF2: 500eV/1E15 (dose lose!)
• B18: 2keV/5E13 (self-amorphization)
• B36H44: 4keV/2.5E13 (self-amorphization)
– HALO (3E13/cm2 dose)• As: 20keV/3E13
• As2: 40keV/1.5E13
• As4: 80keV/7.5E12
• Sb: 35keV/3E13 (self-amorphization)
• nMOS – nSDE (1E15/cm2 or > dose)
• As: 1keV/1E15
• As2: 2keV/5E14
• As4: 4keV/2.5E14
• P: 500eV/1E15
• P2: 1keV/5E14
• P4: 2keV/2.5E14
• Sb: 1.7keV/1E15 (self-amorphization)
– HALO (3E13/cm2 dose)• BF2: 20keV/3E13
• In: 45keV/3E13 dose (self-amorphization but limited by Inss?) In+B!
• B18: 80keV/1.5E12
<850C Spike/RTA
>1350C Flash or Laser
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Mineji et al., NEC/JOBTech/Nissin, IWJT-2007
Borland et al.,
IEEE/RTP-
2009
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For 22nm Node p+ USJ
Formation Using PAI & HALO
Implantation With Laser
AnnealingJohn O. Borland, J.O.B. Technologies, Aiea, HI
John Marino, EAG, East Windsor, NJ
Michael Current, Frontier Semiconductor, San Jose, CA
B.L. Darby, University of Florida, Gainesville, FL
IIT June 8, 2010
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Experimental Matrix Split Conditions
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20keV/3E13 35keV/3E13
No HALO As-HALO Sb-HALO
•B (200eV/1E15) X X X
•With Ge-PAI (3keV/5E14) X X X
•With Ge-PAI (10keV/5E14) X X X
•With Xe-PAI (5keV/5E13) X X X
•With Xe-PAI (14keV/5E13) X X X
•With In-PAI (5keV/5E13) X X X
•With In-PAI (14keV/5E13) X X X
•With B36 (100eV/1E15) X X X
•With B36 (500eV/5E13) X X X
Laser Anneal Pattern
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X-TEM Results For As-HALO & Sb-HALO
Showing No Amorphization
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Surface
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No PAI: B, As & Sb HALO
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Condition Native oxide Xj B-Diffusion
B 2.4nm 8.7nm 3.0nm
As-HALO 2.2nm 10.0nm 3.5nm
Sb-HALO 2.0nm 9.8nm 2.4nm
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Ge-PAI: B, As & Sb HALO
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Condition Native oxide Xj B-Diffusion
B 1.9nm 8.3nm 6.1nm
As-HALO 2.2nm 9.0nm 5.0nm
Sb-HALO 2.1nm 8.5nm 5.5nm
HALO reduces Ge-PAI TED
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No HALO Rs & Junction Leakage
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Leakage (uA/cm2)Leakage (uA/cm2)
Leakage (uA/cm2) Leakage (uA/cm2)
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As & Sb HALO Rs & Junction Leakage
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Leakage (uA/cm2) Leakage (uA/cm2)
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Nagayama, Nissin, IWJT-2010 paper 3.4
Box-like
profile for P
when C dose
increases
between 1-
2E15/cm2
Pss=1.5E20/cm3 what is leakage values!
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Dopant Solid Solubility Limits In Silicon
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Higher n+ Phos. Dopant Activation
>1.8E21/cm3!
H. Kennel et al., Intel, NIST meeting, March 2006
How to get Pss=>1.8E21/cm3?
Compare 1350C to Melt (>1407C)
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Mineji et al., NEC/JOB/Nissin, IWJT-2007
Borland, IIT-2008
In-Temp?
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IEEE/RTP 2009
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Ni Silicide Improvements With By
Shallow Room Temp Si-PAI, Xe-PAI or
Cold C-PAI
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T. Renau, VSEA, IWJT-2010 paper K1 S. Deshpande, IBM, IWJT-2010 paper 4.1
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Outline• Introduction
– Technology Roadmap Options
• USJ Technology
– p+ USJ 22nm node and beyond
– n+ USJ 22nm node and beyond
• Strain Technology
– pMOS 22nm node and beyond
– nMOS 22nm node and beyond
• Next
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Heated 300C HALO Implantation
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S. Deshpande, IBM, IWJT-2010 paper 4.1
Issue for eSiGe-
SDE or disposable
spacer process
flow!
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eSiGe Strain
Relaxation By p+ SDE
Implant
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AMD/Dresden, Insights-2009
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AMD RTP 2007 Paper
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April 2010 ECS Meeting Vancouver,
Canada
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S. Govindaraju et al., Intel, ECS Transactions, vol. 28, no.1, p.81, 2010.
Issue for
disposable
spacer process
flow!
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Intel’s 32nm Node Low Power RF CMOS
SOC Technology
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Intel, VLSI Sym 2010, paper 13.2
Looks like 45nm eSiGe Looks like 65nm eSiGe
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April 2010 ECS Meeting Vancouver,
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Dube et al., IBM/GF, ECS Transactions, vol.28, no.1, p.63, 2010.
In-situ SiCP=3E20/cm3 at C=1.7% Also, 1-2wph!
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22nm Node n+ SiC Stressor
Using Deep PAI+C7H7+P4 With
Laser Annealing
John Borland1, Masayasu Tanjyo2, Nariaki Hamamoto2, Tsutomu Nagayama2, Shankar
Muthukrishnan3, Jeremy Zelenko3, Iad Mirshad4, Walt Johnson4, Temel Buyuklimanli5, Steve
Robie5, Hiroshi Itokawa6, Ichiro Mizushima6 and Kyoichi Suguro6
1) J.O.B. Technologies, Aiea, HI
2) Nissin Ion Equipment, Kyoto, Japan
3) Applied Materials, Sunnyvale, CA
4) KLA-Tencor, San Jose, CA
5) EAG, Sunnyvale, CA
6) Toshiba Corporation, Yokohama, Japan
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IEEE/RTP-2009
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Itokawa, Toshiba/IBM, IWJT-
2010 papers 3.2 & 6.14
Keep Csub to
<1.3% and use
850C SPE+MSA
OK to have 1% C in channel
under the gate stack (mid-
E19/cm3)?
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SUMMARY• 22nm Node (2011-2012)
– Planar Bulk CMOS by Intel & IBM/Alliance Foundry
– Planar PD-SOI by IBM/Alliance
– USJ <10nm using MSA+spike/RTA diffusion-less annealing
• p+(B, B10 or B18/36)
• n+(As or P+C)
– Channel mobility enhancement
• pMOS: eSiGe or SiGe-channel
• nMOS: eSiC by Epi or C+P implant
• 15nm Node (2013-2015) & 11nm Node (2015-2017)
– Planar CMOS:
• Hybrid bulk and localized FD-SOI with back-gate (Intel &
IBM/Alliance Foundry)
• FD-SOI with back-gate: IBM/Alliance
– FinFET CMOS?J.O.B. Technologies (Strategic
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