pd flow document

8/10/2019 PD Flow Document

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###### This document is to give a idea about the PD Flow #####

DATA PREPARATION:

Make a setup file which contains all the files mentioned below:

.vg (generally DFT Inserted netlist) .sdc (timing constraint file) .libs .lefs (tech lef, macro lef and std. cell lefs) .io (pin assignment file if any) .cdbs (celtic libraries for cross talk analysis) Libgens

AUDIT CHECKS

Check the design for the type of cells, IO Pin, Physical infocheckDesign all outDir

Check the design for check timing loops, combo loops

check_timing

Utilization Memory aspect ratio wrt core aspect ratio Check for preplace timing

timeDesign prePlace outDir

FLOORPLAN

Define global net connectivityglobalNetConnect VDD -type pgpin -pin VDD* -inst * -module {} -override -verboseglobalNetConnect VSS -type pgpin -pin VSS* -inst * -module {} -override -verbose

Fix Io pin status Add endCaps (at both the ends of each std. cell row)

addEndCap -postCap -preCap

Place macros Add soft blockages around macros Spacing between macros (based on no. of pins, making sure enough space is left

between macros for timing fixes) Add tapCells

addWellTap -cell -cellInterval 50.00 -checkerBoard -fixedGap -startRowNum 1


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Add endCaps (along the edges of the macros)addEndCap -postCap -preCap

Check the placementcheckPlace

Save the designsaveDesign DBS/init.enc

PG PLAN

Draw the PG StripesFor vertical layer

addStripe -block_ring_top_layer_limit -max_same_layer_jog_length -padcore_ring_bottom_layer_limit -set_to_set_distance -ybottom_offset -stacked_via_top_layer -padcore_ring_top_layer_limit -spacing -merge_stripes_value

-direction horizontal -layer -block_ring_bottom_layer_limit -width -nets {VSS VDD } -stacked_via_bottom_layer -allow_jog_block_ring

For horizontal layeraddStripe -block_ring_top_layer_limit -max_same_layer_jog_length -padcore_ring_bottom_layer_limit -set_to_set_distance -stacked_via_top_layer -padcore_ring_top_layer_limit -spacing -xleft_offset -allow_jog_padcore_ring -xright_offset -layer -block_ring_bottom_layer_limit -width -nets {VSS VDD } -stacked_via_bottom_layer

-allow_jog_block_ring add viaseditPowerVia -skip_via_on_wire_shape {Ring Followpin Corewire Blockwire IowirePadring Fillwire Noshape} -bottom_layer -add_vias 1 -top_layer

SRoutesroute -connect { corePin floatingStripe} -layerChangeRange { lower_layer_nametop_layer_name } -blockPinTarget { nearestTarget } -deleteExistingRoutes -checkAlignedSecondaryPin 1 -allowJogging 0 -crossoverViaBottomLayer -allowLayerChange 0 -targetViaTopLayer -

crossoverViaTopLayer -targetViaBottomLayer -viaConnectToShape { stripe } -corePinMaxViaWidth -corePinLayer 2 -targetPenetration { stripe }

Check for opens and shorts Save the design

saveDesign DBS/init.enc


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PLACE

Attach the IO BuffersattachIOBuffer -in -out -port -markFixed -excludeClockNet -baseName MPIN_BUF -excNetFile

Set the attributes for placementTo specify the tool to perform placement based on timing driven, congestion driven,module aware placement, so on.

Place the std. CellsplaceDesign

Check the placementcheckPlace

Tool generally performs trial route automatically. Check for congestion (make sure there

are no local hotspots and the congestion value is in the specified limit) Save the designsaveDesign DBS/place.enc

PRE CTS OPT

This is the 1 st optimization in the design The optimization can be done by giving priority to the specific path groups, we can use

the creatPathGroup option to create the path groups.optDesign preCTS outDir -numPaths

Save the designsaveDesign DBS/prects.enc

CTS

Before creating the clock tree spec, we must enable the all modes (func,scan,mbist,bscan) in which the design is being run

Generate the clock tree speccreateClockTreeSpec file -buffer_list

Set the skew value, insertion delay, leaf and non leaf transition, list of inverters andbuffers to be used.

Clock group, leaf pins, exclude pins, Specify the NDR (non default rules) Macro models Analyze the clock tree and check the coverage of the clock tree network

ckSynthesis check -forceReconvergent


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Build the clockckSynthesis -forceReconvergent

Save the designsaveDesign DBS/cts.enc

POST CTS OPT

In postCTS stage, we can perform the optimization for both setup and hold.

Optimize the design by propagating the clocks To propagate the clocks use set_propagated_clocks [all_clocks]

optDesign postCTS outDir -numPaths to optimize for holdoptDesign postCTS hold outDir -numPaths

Save the designsaveDesign DBS/postcts.enc

DETAIL ROUTE

Perform the detail route Make sure the attributes for SI aware route is set

globalDetailRoute Save the design

saveDesign DBS/route.enc

POSTROUTE OPT

Optimize the design if any timing violations are thereoptDesign postRoute

Save the designsaveDesign DBS/postroute.enc

PDV Check the design for shorts, opens Perform LVS, LPC, DRC, Antenna Checks

pd flow document

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