pattern unit for the muon barrel design proposal

MUON Barrel Workshop - Oct 13, 2011

Pattern Unit for the Muon BarrelDesign Proposal

Artur JutmanDepartment of Computer Engineering

Tallinn University of TechnologyESTONIA


Outline

• Shortly about Tallinn Univ. of Technology

• Specifications of the Pattern Unit (PU)

• PU prototype proposal

• Final implementation of PU

• Questions and open issues


Tallinn University of Technology


Tallinn University of Technology

• Second biggest Estonian university with ~12 000 students.

• Established in 1918, university status in 1936• A campus university with 3 main

cores (organized in 8 faculties): Technology Natural Sciences Social Sciences

• A three-lingual university (Estonian-Russian-English)


Department of Computer Engineering

• Staff (32 employees): 5 professors 7 ass. professors 10 researchers 15 PhD students

• Collaboration with academia industry (R&D, EDA, EMS)

• High-tech. environment Test & measurement equipment from Agilent, NI,

SAAB, Goepel, etc. CAD tools from major vendors In-house developed CAD and hardware


Designfor

Dependability

Verification and Debug

Diagnostic Modeling

System Modeling and Synthesis

Test

Test GenerationTest Generation

Fault DiagnosisFault Diagnosis

Fault SimulationFault Simulation

Board TestingBoard Testing

Design-for-TestabilitySelf-Test

Embedded Diagnosis

DES

IGN

VER

IFIC

ATIO

N, T

ES

TThe scope of research in DCE


CEBE - Estonian Centre of Excellence

• CEBE – Centre of Integrated Electronic Systems and Biomedical Engineering: cebe.ttu.ee

• CEBE is one of the seven research excellence centres in Estonia, and is based on three departments of Tallinn University of Technology: Computer Engineering Electronics Technomedicum

• The staff includes 80 researchers and PhD students (10 full professors)

• Participates currently in 7 EU projects• Extensive experience with various EU programs

(CEBE researchers have participated in more than 30 EU-funded projects since 1992)


Est. in 2005 Activities:

• Engineering services • Products for EMS companies• R&D, technologies

Focus:• Electronics test: boards and

systems• JTAG - Boundary scan• FPGA-based JTAG test

instrumentation• Processor emulation based

JTAG test• Verification and debug of ICs• Software development

TUT Spin-off Testonica Lab

http://dev.docs.ee/


Specifications of the Pattern Unit


Main objective (from specification)

• Build an electronic module (Pattern Unit) for testing LVDS/Fiber links of the Muon Barrel Simple and user-friendly Capable to act both as a transmitter and receiver Be configurable (default value, clock speed, number of words

to transmit, etc)• Work modes of Pattern Unit (PU):

Serializer mode: test trigger chain, test readout chain Two PU for testing fiber link

• PU consist of: FPGA board with parallel I/O 2-types of mezzanine board (serializer or deserializer) VHDL design for FPGA Software for pattern load / runtime control


PU block scheme (from specification)


Requirements (from specification)

• FPGA with at-least 32KB of internal memory

• 96 parallel single-ended I/O lines (FPGA mezzanine)

• 8 A/C coupled serial LVDS links on mezzanine board

SERDES based on DS92LV1021A/ DS92LV1212A chips

2 RJ45 connectors

• Clock (40MHz) is generated external or internally

• Auxiliary I/O: CLOCK input (up to 40MHz), asynchronous START input, SPARE output for synchronizing

LEMO-type connectors (which type?)

Configurable voltage support: LVDS, TTL, NIM (support of NIM is required or preferred?)

• Slow control bus to load test patterns

VMEBus (if needed), USB/Ethernet


Missing Requirements ;)

• What is the target of testing? Specific defects or faults? Reliability issues? Signal integrity problems? Conformity tests? Stress or soak testing?

• Test quality requirements Measurable test coverage needed? What is the target test coverage? Automated diagnostics needed?

• Test pattern generation Offline (who generates)? Online (pseudo-random patterns)?


PU prototype proposal


Proposed development plan

• Split-up the implementation of Pattern Unit into several stages: Step 1: Making prototype Step 2: Prototype evaluation at CERN Step 3: Final implementation

• We need to define the schedule/deadlines


Purpose of the prototype• Provides proof-of-concept

First version purpose: establishing communication PUtx+serializer mezz-> CuOF -> Fibers –> OFCu -> PUrx + Deserializer mezz

• Reduces initial costs Parts of the system could be off the shelf

components• Speeds-up development

Modules of the PU (e.g. SW, VHDL, mezzanine) can be tested verified separately before final implementation

Working solution is available quickly• Secures the success of development

Helps to avoid potential bugs in the final version of PU


Proposed prototype• Do not use custom FPGA board in prototype

Design of complex FPGA board with many high-speed I/O requires a lot of time and efforts

TUT has no in-house facilities for PCB manufacturing PU modules (VHDL, Mezzanine, SW) cannot be tested

until FPGA PCB is ready (risk not to meet deadlines)

• Use off-the-shelf FPGA development board instead Off-the-shelf board can be

immediately used for prototyping May be also re-used in final

implementation• Mezzanine boards should be designed upfront

Mezzanine boards can be designed much faster Specific I/O standards/connectors can be implemented

on mezzanine instead of FPGA board (or skipped in prototype)

• Design of VHDL code and corresponding SW


FPGA board requirements

•FPGA development board for prototype: External power supply 12V Link I/O – as stated in the specification Clock, Start and Spare I/O support LVDS/TTL:

• NIM is skipped in the first prototype

• SMA connectors are used instead of LEMO-connectors

No special mechanics No VMEBus support Pattern load (slow control) via on-board

USB/LAN Capable for firmware updates (via USB or

JTAG)


FPGA development board example

• Avnet Spartan 6 LX150T development board XC6SLX150 FPGA (>500 I/O, 4Mbit memory) Two FMC LPC connectors with 136 single-

ended I/O (can also be configured as LVDS), power and ground

Buttons, LEDs, DIP switch, SMA connectors (can be used for START, CLOCK, SPARE)

12V power supply PCI express x4 compatible Price $995 mezzanine

FMCFMC

…..

SERDES SERDES

SERDES


Mezzanine board• Custom designed mezzanine PCB

2 types of mezzanine (serializer/deserializer) 8 SERDES chips RJ45 connectors

• Specific connectors and support of I/O voltage can be placed onto mezzanine (instead of FPGA board) Possibility to use NIM standard and LEMO

connectors CLOCK/START/SPARE signals will be routed into

mezzanine via FMC LPC connector on FPGA board

LEMO connectors and voltage translator (for NIM) can be placed on mezzanine


Firmware and software• Firmware: FPGA design in VHDL

May also contain embedded pattern generator (to avoid pattern loading)

Can be designed to allow standalone operation of PU after power-up (without host PC)

• Runtime software Communicates with PU using USB cable (no

additional modules/cables needed) Loads test patterns, can initiate test

operation (start) Will be written in C Target execution environment

(Windows?/Linux?)


Final implementation of PU


Final implementation• Option 1: Continue with off-the-shelf FPGA board

VMEBus can unlikely be supported (is this strongly required?)

USB instead of VMEBus Auxiliary I/O can be placed on mezzanine (if

support of specific connectors/voltages is needed)

• Option 2: Custom FPGA board Should be designed and manufactured Can support VMEBus Can contain any type of auxiliary I/O

signals / connectors Longer lead time, lower reliability More expensive in low volume production


General questions

• Schedule, time-frames, deadline, etc

• Any special requirements for HW of PU, e.g. ability to work in strong electromagnetic

enviroment? • Mechanics: PU is used in a rack or as a

standalone box?• What number of PUs (FPGA boards, mezzanines)

are planned to be manufactured / used?• Compatibility with any existing HW that should be

preserved?


Questions on the specification

• Clock input / Spare output have LEMO-type connector More info about LEMO-connectors (which type

of LEMO?) Can we replace them with SMA in prototype? Can we route these signals to mezzanine and

place the connectors there?

• What is the connector-type for START input?• NIM (Nuclear Instrumentation Module?)

More info about NIM How strongly the support of NIM is required?


Questions on the specification (2)

• FPGA re-configuration Is it OK to use Xilinx cable (or other JTAG

cable) for reconfiguration?

• VME32 We have no experience with VMEBus Can it be replaced with USB?

• VHDL design Is there any benefit in generation of patterns

inside FPGA?• Software design:

Which OS (Windows/Linux/other) is targeted?


Questions on the specification (3)

•The following needs to be clarified (quote from specification):

“be able to modify the phase for the serializer and deserializer clock lines in steps of 1ns with respect to the data lines”

Which data lines (parallel I/O or serial LVDS) are referred here?

Limits of phase modification (i.e. what is the maximal phase shift needed)?

pattern unit for the muon barrel design proposal

Documents

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