dt muon sorter - istituto nazionale di fisica nuclearetridas_nov04).pdf · a.montanari-infn bologna...

Tridas week, 09-Nov-04A.Montanari-INFN Bologna 1

DT Muon Sorter

DT front endBarrel

DT Track Finder

DT Sorter

GLOBAL MUON TRIGGER

Detector in UXC

Countingroom in USC

LVDS copper link

Opto link

Towers in UXC

DT station (minicrate)

CCB

Trigger Boards(BTI,TRACO,TSS)

Sector Collector

Server Board

12xWedge Sorter

In: max 12 tracks from 6 f Track-Finder of a wedge

Out: 2 “best” tracks

1xBarrel Sorter

In: max 24 tracks from 12 Wedge Sorters

Out: 4 “best” tracks

Main news:

-Trigger chain from front-end upto Wedge Sorter tested at bunchedtestbeam at beginning of October

- All final boards, but Sector Collector..

Tridas week, 09-Nov-04F.Odorici-INFN Bologna 2

DT Sector Collector

LVDS link:

- 2 Ethernet cables/minicrate FTP cat.6

- TX rate @ 480 Mbps (< 50 m), with National

Semicond. chipset:

a) serializer 10-1 DS92LV1021 (8 IC/link)

b) cable equalizer CLC014 (8 IC/link)

c) deserial. 1-10 DS92LV1212A (8 IC/link)

Opto link:

- 6 multimodal fibers (Ericsson)/SC (< 100 m)

- TX rate @ 1.6 Gbps, with GOL serializer

(32 bits @ 40 MHz), and Honeywell opto-ICs:

a) VCSEL trasmitter HFE4190-541

b) Pin Diode receiver HFD3180-102

DT front endBarrel

DT Track Finder

DT Sorter

GLOBAL MUON TRIGGER

Detector in UXC

Countingroom in USC

LVDS copper link

Opto link

Towers in UXC

DT station (minicrate)

CCB

Trigger Boards(BTI,TRACO,TSS)

Sector Collector

Server Board

Main functionalities:

- a SC board serves a sector (4/5 stations)

- track sorting (1 out of 2 tcks/station)

- DT trigger path syncronization (compensate forTime-Of-Fligth, TTC fibers and LVDS cables) via clock delay and pipe lines.

Tridas week, 09-Nov-04F.Odorici-INFN Bologna 3

Sector Collector to Track Finder opto-link

ETTF(η view)

1 board/wedge

PHTF(φ view)

6 board/wedge

2 Opto Rx (5 ch) board / ETTF

1 Opto RX (4 ch) board / PHTF

Opto Tx (4 ch) piggy board

Sameboards

TF crate backplane

MB1

MB2

MB3

MB4

Clock

Vcc

Control

LVDS Rx piggy boards

SC

Virtex-II FPGA used as:

- Deserializer (Rocket IO)

- RX parity checker

- I/O Router


Combined test with PHTF in preparation of testbeam (1)

Combined test with emulated track segments @ 40 MHz with new PHTF was ok!

In Sep04 the SC-to-TF interface and Wedge Sorter, were tested togheterthe new PHTF in Vienna setup at CERN

I/O was tested at 40 MHz by using 2 Pattern Unit board in a portable VME crate

The WS processor was programmed in a simplified way, in order to pass the tracksfound by only one PHTF

Read back the outputthrough WS

Emulation of inputsfrom 2 MB stations

Pattern Unit Pattern Unit


Combined test with PHTF in preparation of testbeam (2)

Portable VMEw/ 2 Pattern Units

Track Finder crate

LVDS-to-TTL

PHTF

WS

SC-to-TF

Vienna lab at CERN

Front

Back


Setup at bunched testbeam

Copper link, 40 m(2 cables for redundancy) Data reduction

(Actel ProAsic)

LVDS deserializer(1:10) + equalizer

Record data at IN (Track segments from chambers) andOUT (Reconstructed muons) of PHTF

(max rate determined by VME bandwidth)Pattern Unit 1 Pattern Unit 2

CENTRAL_DAQ VME crate

2.5 m

Chambers syncronization, SC functionalities, PHTF, WS tested in real environment!First look at data in Jorge’s talk

SPY_DAQ through JTAG


Wedge Sorter production- Start production submitted mid Oct 04- First evaluation board expected on 22 Nov 04- If the evaluation board is ok, confirm full production (18 boards)- Production start expected by Jan 05 (as scheduled)

- Each board will be tested with our test jig

TTLGTL+

TTLGTL+

LVDSTTL

Shielded flat cables (VME)VME

TTL 128 I/Oup to 100 MHz

Pattern Unit


Barrel Sorter requirements and design approach

TASKS: BS algorithm is similar to WS one BUT– 24 input tracks à much bigger I/O ( ~ 870 )

à complex ghost bustingà sorting 4 out of 24 (heavy task)

Design approach similar to WS:– All functionalities on one big FPGA:

Altera StratixII EP2S130, 1508 fBGA (new device!!)– 9U, 400 mm VME board– Latency: 3 BX for ghost-busting + sorting&multiplexing

with some main different features:– Inputs from cable (LVDS) through connectors on board top– Main FPGA on mezzanine board


Barrel Sorter board layout

Mother board prototype expected by mid of December 04


BS main chip design

Sorter 1 Sorter 2 Sorter 3 Sorter 4

MUXs

Ghost Busting

75 ns

• Notice that (sorting 4 out of 24) >> 2 x (sorting 2 out of 12) !!!– In the fully-parallel sorting algorithm used in WS, logic usage and routing

congestion increase as very steep functions of the number of input words

• New FPGAs work better with fine segmented pipelines:– BS uses sequentially 4 x (1-out-of-24) sorters in pipeline

StratixII floorplan


Milestones update

DT Sector Collector Prod start Jun-03 Delay: Sep-04DT Barrel Sorter Proto done Nov-03 DoneDT Sector Collector Prod done Dec-03 Delay: Mar-05DT Wedge Sorter Prod done Jul-04DT Barrel Sorter Prod done Jul-04

DT Sector Collector Proto done Jan-05DT Sector Collector Prod start Jun-03 Delay: May-05DT Barrel Sorter Proto done Nov-03 Delay: Jan-05DT Sector Collector Prod done Dec-03 Delay: Jul-05DT Wedge Sorter Prod done Jul-04 Delay: Jan-05DT Barrel Sorter Prod done Jul-04 Delay: Mar-05

Changes into:


Boards status file

Aug-05May-050Jul-050May-05Jul-05May-05PPP-Jan-05

70Bologna

60SectorCollector

SCDT

Apr-05Mar-050Mar-050Feb-05Mar-05Feb-05PPP-

Jan-053

Bologna1

DTBarrelSorter

BSDT

Mar-05Feb-050Feb-050Dec-04Jan-05Dec-04PPP-

Nov-0415

Bologna12

DTWedgeSorter

WSDT

Sep-05May-050Aug-050May-05Jul-05May-05PPP-

Jan-05110

Bologna96

DTTFGigabitOptical

Rx

OpticalInputDT

Readyfor

USC55

Readyfor904

ProdTest %Compl

ProdTestFinish

Prod %Compl

Prodtest start

ProdFinish

ProdStart

StatusTotal-respNeededExplanItemSubsys

In red, modified/new items:

dt muon sorter - istituto nazionale di fisica nuclearetridas_nov04).pdf · a.montanari-infn bologna...

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