2020

PEMICBGU

Digital Lock-In Controller IC for Data-Centers 48V-12V ZCS-STC

• This work introduces a lock-in integrated controller for

48V-12V ZCS switched-tank converters (STC)

• The controller identifies the resonant period of each sub-

circuit on-the-fly and locks-in on the correct switching time

• Key building blocks of the system: two independent ZCD

sensors, digital HR-DPWM, Sigma-Delta ADC and a

programmable dead-time module

• Two approaches have been developed for the sensors’ data

acquisition, taking into account the inherent delay between

the gating-command and the actual turn-off of the switches

• All units of the digital controller have been designed through

asynchronous architecture, eliminating the need of high-

speed clock

Introduction STC Operation IC Controller

• Effective silicon area of 0.64mm2

• The IC has been designed and fabricated on a

0.18μm 5V process by pure digital means

• All synchronization and calculations are based

on an internal 20MHz clock

Experimental Verification

EXPERIMENTAL PROTOTYPE

VALUES AND PARAMETERS

Simplified schematic diagram of a 4:1

STC with digital lock-in controller

Mismatched resonators

steady-state current waveform

Equivalent circuits of the 4:1 STC

Tom Urkin, Guy Sovik, Erez Masandilov, and Mor Mordechai PeretzThe Center for Power Electronics and Mixed-Signal IC

Department of Electrical and Computer Engineering, Ben-Gurion University of the Negev, Israel

ZCD Sensor

Tank 1

ZCD Sensor

Tank 2

Vin

Q2 Q3 Q4Q1

Lr1

Cr1

Cf

Q6Q5 Q8Q7 Q10Q9

Lr2

Cr2Cout RL

Vout

Error

Calculator

Tank1

Error

Calculator

Tank 2

Compensator

Synchronous

Sampling Unit

Asynchronous

Sampling Unit

Tuning

Registers

Digital Self-Tuned STC Controller

Drive Logic

Tank 1

Drive Logic

Tank 2

Q1

Q10

Samp1

Samp2

Sel2

Sel1

SM

SM

Samp1 Samp2

Mux

Mux

System

GovernorDelay

Estimation

Logic

OP

DT

DT

Ton1

Ton2

SM Sel1

Sel2

Ts

Se1 Se2

Se1 Se2

Cout RL

Vout

Vin Cr1

Lr1

Cr2

Lr2

Cout RL

Vout

Vin Cr1

Lr1

Cr2

Lr2

Vsw1 Vsw2

Vsw1 Vsw2

(a)

(b)

Cf

Cf

Q1 Q2 Q3 Q4

Q5 Q6 Q7 Q8 Q9 Q10

Q1 Q2 Q3 Q4

Q5 Q6 Q7 Q8 Q9 Q10

clkΣ Δ

Digital

Lock-In

Controller

HR

Drive

selN

QN

Mux

Counterclk

Computational

Blcok

sel1

Q1

Mux

Single delay element based drive circuitry

ICr1,ICr2

Vsw1

t

Vsw1

t

Vsw2

Vsw2

t

Vsw1

Vsw2

(b)

(a)

(c)

ICr1,ICr2

ICr1,ICr2

t

t

t

t

t

t

ZCD sensor

Sensors’ data acquisition procedures

Block diagram of the auto-tuner module

S1

S2

Vth1

Vth2

VSe nsed

Vout

RA

RC

VCC

VCC

R2

R1Vsw

RB

CMP

CMP

Condition S1 S2

VSensed>Vth1 1’b1 1’b1

VSensed <Vth2 1’b0 1’b0

Vth2< VSensed <Vth1 1’b0 1’b1

Digital Lock-In Controller IC

System

Governor

Sequencer

HR-Timer

Units

Tune

RegistersAuto-Tuner

Locked

Tpul se_1

Tpul se_N

Locked

ZCD1

ZCDN

OP

QN

Q1

Q1

Q2

QN

Sampling

Block

ZCDNZCD1

Samp1

Samp2

t

ZCD

Qx

t

clk

Delay

Dead-Time

Invalid Valid Invalid

Δs

t

ZCD

Qx

t

clk

Delay

Dead-Time

Invalid Valid Invalid

(a)

(b)

(c)

Vout

ICr1

ICr2

ICr2

VSW2

ICr1

VSW1

ICr2

VSW2

ICr1

VSW1

200µsController Enable

Command

10.57V

11.75V

Zoom-in

(a)

(b)

(a)

(b)

Component Value

Input voltage Vin 48V

Output power 650W

Resonant capacitor Cr1, Cr2 2.35µF

Resonant inductor Lr1, Lr2 70nH

Flying capacitor Cf 40µF

Q1-Q4 40V/2.5mΩ

Q5-Q10 25V/1.3mΩ