ovm video slides

8/14/2019 OVM Video Slides

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macros automate housekeeping (inline substitution of systemverilog code)


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Tom Fitzpatrick, Mentor Graphics Verification Technologist


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Circles = exports

Squares = portsDiamonds = analysis ports

Know when to stop running useless cycles or when coverage is not increasing.Try to figure out how to run in half-the-time.

Simulation cycles are non-renewal resource. Once its used its gone.


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u1 = red, u2 = red


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set_type_override (u1= blue, u2 = blue)set_inst_override (u1=green, u2= blue)

set_config_string (u1=green, u2 = green)


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messages


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add a fork join to wait for all child processes to complete


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tests are components from the factory

Kathleen Meade, Application Engineer, Systemverilog, Cadence


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Vi = virtual interface


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aka UVM


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See ovm-1.0/examples/xbus/sv/xbus_env.sv


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one sequencer on a driver at a time


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Easy to deply all key randomization concepts !


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everytime do is executed the sequence is randomized


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Doug Smith, Senior Engineer & Trainer at Doulos


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test is hard instantied but only used for example


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use packages to avoid scoping issues

run_test kicks off the simulation


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random is not good enough


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should one use OVM transaction or OVM sequence?It depends upon the situation.


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to add more drivers : AHB, PCIE, add more ovm_sequencers


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not an OVM sequencer

Use virtual sequencer


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can have multiple scoreboards


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check to see iterations. If none set then use default

wrap up objects, structures and then use factory or virtual interface

downside of using strings, is that systemverilog has to do searching for objects and OVMplans to add checking for mistyped strings.


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can run test by itself


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ovm video slides

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