overview of vlsi manufacturing technologysresa.org.in/l1-anil-kottantharayil.pdf · 3 overview of...

1

Overview of VLSI Manufacturing Technology

Anil Kottantharayil, Ph. D. Associate Professor

Department of Electrical Engineering IIT Bombay

[email protected]

Overview of VLSI Manufacturing Technology, BARC, 6th December 2012 Anil Kottantharayil, IIT-B 2

Acknowledgements

•  This being an overview of the technology, literature data including those from web have been cited liberally

•  Former Colleagues at IMEC, Belgium for teaching me semiconductor processing

2


A Typical VLSI Circuit

metal2

metal3

metal4

metal5

metal1

silicide contact

via1

via2

via3

via4

metal6

via5

Thompson et al., Intel technology journal, vol. 6, no. 2, 2002


Introduction to ULSI Technology

Part 1: How is a circuit made on Silicon – integration Part 2: Packaging and assembly Part 3: Wafer Manufacture and Unit Processes Resources

3


STI : basic process flow

Si

Si3N4

SiO2

Pad oxide growth + nitride deposition

Si SiO2

Si3N4

Si

Si3N4

SiO2 SiO2

Sidewall oxidation, corner rounding

Si3N4

Pattern and etch Si3N4, SiO2 and the trench etch into Si

Si3N4

Si

SiO2

SiO2

Deposition of trench filling oxide

Si SiO2

Si3N4

Oxide CMP polish step with stop on nitride

Si SiO2

Field oxide recess (HF) Removal of nitride layer (H3PO4)



Si

SiO2

Agnello, IBM Journal of research and development, no. 2/3 2002

4


The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have n

well & channel doping module

Photo nwell N-type implants Strip resist

The image cannot be displayed. Your computer may not have enough memory

to open the image, or the image may have n

p

Photo pwell P-type implants Strip resist Oxidation / Anneal

(optional)


gate module

remove implant oxide gate oxidation LPCVD poly/a-Si layer remove backside layers


to open the image, or the image may have n p

photo poly



dry etch poly strip resist re-oxidation

5


photo nplus p-type HALO implant n-type ext. implant strip resist RT anneal

source/drain extensions



The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have n p

photo pplus n-type HALO implant p-type ext. implant strip resist RT anneal


spacer module

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have

n p


n p

Deposition dielectric layer(s) : oxide and nitride

remove backside layers

anisotropic dry etching polymer removal

6


photo nplus n-type implant strip resist anneal (opt.)

HDD junction module


n p


photo pplus p-type implant strip resist anneal


wet/dry etch oxide metal sputter :

Ti, Co/Ti, Ni silicidation

1st RTP treatment selective etch 2nd RTP treatment

salicide module



n p

7


Pre-Metal Dielectric Module

nitride (SiON/SiC)

•  Step 1: •  Plasma Enhanced Chemical Vapor

Deposition (PECVD) of thin nitride layer (PMD liner )

•  Pre-Metal Dielectric (PMD) is insulating layer between silicide and 1st metallisation layer (metal1)



HDP PSG

•  Step 2: High Density Plasma (HDP) deposition of Phospho-Silicate Glass (PSG) for gapfill

•  HDP gapfill is achieved by a deposition - sputter process D/S ~ 4 (Deposition to Sputter ratio)

8



PSG CMP

•  Step 3: •  Chemical Mechanical Polishing

(CMP) of PSG layer



oxide

•  Step 4: •  PECVD of thin oxide layer (PMD

cap )

9


Contact Module

•  Step 1: •  contact lithography @193nm

Contact module makes electrical contact between silicide and 1st metallisation layer (Al or Cu metal1)


Contact Module •  Step 2: •  contact etch

– selective towards nitride liner

STI AA

nitride etch stop layer

shallow contact deep contact

10


Contact Module •  Step 3: •  nitride liner opening

– selective towards silicide – selective towards STI isolation oxide

STI AA


STI AA

Contact Module •  Step 4: •  resist strip of contact photo

11


Contact Module •  Step 5: •  in situ degas step •  Ar preclean (sputter etch) •  Ti deposition by sputtering •  TiN deposition by CVD

Ti/TiN


Contact Module •  Step 6: •  W CVD

W

12


Contact Module •  Step 7: •  CMP of W layer

– + Ti/TiN barrier – + oxide cap layer PMD

W CMP


SD IMD1 BD Module

•  Step 1: PECVD SiC •  Step 2: PECVD Black Diamond •  Step 3: PECVD Oxide

BD SiC

Oxide

Embedding Inter Metal Dielectric (IMD) for Cu Single Damascene (SD) metal1

13


SD Metal1 Patterning Module •  Step 1: •  193 nm metal1 trench lithography


SD Metal1 Patterning Module •  Step 2: •  single damascene dry etching •  → bottom SiC layer is etch stop layer

14


SD Metal1 Patterning Module •  Step 3: •  SiC opening


SD Metal1 Patterning Module •  Step 4: •  single damascene dry/wet strip •  (compatible with W and Ti/TiN in contact

plug)

15


SD Cu Metal1 Module •  Step 1: degas / Ar preclean •  Step 2: TaN/Ta bilayer barrier (Sputter) •  Step 3: Cu seed layer (Sputter)

TaN/Ta barrier Cu seed


SD Cu Metal1 Module

electroplated Cu

•  Step 4: Cu electroplating •  Step 5: Forming gas anneal @250°C

16


SD Cu Metal1 Module •  Step 6: Cu CMP •  Step 7: TaN/Ta CMP

Cu CMP TaN/Ta CMP


7 Interconnection Levels

contact metal1 via1 metal2 via2 metal3 via3 metal4 via4 metal5 via5 metal6 via6 metal7

PMD

IMD1

IMD2

IMD3

IMD4

IMD5

IMD6

IMD7

17


A Typical VLSI Circuit

metal2

metal3

metal4

metal5

metal1

silicide contact

via1

via2

via3

via4

metal6

via5


Source Drain

Spacer

Gate dielectric

Gate


Passivation Module wire bonding

package

SiCN

TaN oxide/nitride

Al

18





Assembly and Packaging

Objectives: •  Signal distribution

•  Power (electrical) and ground distribution

•  Heat dissipation

•  Electromagnetic protection/shielding

•  Mechanical protection

•  Environmental protection

19


Packaging Process

•  Wafer preparation – thinning of the wafer, wafer scribing or slicing •  Chip bonding •  Wire bonding •  Encapsulation •  Package seal or mould •  Burn-in •  Test


Packaging Options

20


Some of the popular packages




21


Wafer Manufacture and Unit Processes

•  Wafer manufacturing •  Wafer cleaning •  Oxidation •  Thin film deposition

•  CVD processes •  Physical vapor deposition (PVD)

•  Photolithography •  Etch processes

•  Reactive ion etch or dry etch •  Wet etch

•  Chemical mechanical polish •  Ion Implantation


Si Wafer Manufacture •  Si – 2nd most abundant material on earth s crest (~25%)

•  But in the form of SiO2 – quartz – sand (SiO2 + impurities)

•  VLSI grade: impurity levels typically ppb or 1013 cm-3 (~1015 cm-3 C

& 1018 cm-3 oxygen OK)

•  Single crystal

•  Desired resistivity (doping) and orientation

•  Required in the shape of circular wafers

•  Mechanical properties

•  smooth mirror finish top surface (lithography)

•  minimal bow and taper

•  thickness of the wafer to give mechanical strength

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Si Wafer Manufacture (2)

SiO2 + 2 C Si + 2CO

quartzite coke Metallurgical grade 98% purity + Al + Fe + other

~ 2000C & 13 kWh/kg

Metallurgical grade (MGS) to electronic grade (EGS) Si + HCl SiH4 + Cl2

SiH3Cl + Cl2 SiH2Cl2 SiHCl3 + H2 SiCl4 + H2

Sand to metallurgical grade Si (MGS)

MGS, powder Typical process

High temperature catalysts


Si Wafer Manufacture (3) Metallurgical grade (MGS) to electronic grade (EGS) SiHCl3 is a liquid at RT purify further by fractional distillation Purified SiHCl3 is used for deposition of poly-Si on a poly-Si rod by chemical vapor deposition (CVD) SiHCl3 (gas) + 2H2 (gas) 2 Si (solid) + 6 HCl (gas)

Poly-Si •  Impurity levels of ppb or 1013 to 1014 cm-3 •  But we need single crystal wafers for ULSI •  SiHCl3 or poly-Si can be used as raw material for solar cell

23


Si Wafer Manufacture (4) •  Two techniques for fabrication of single crystal Si ingots

•  Czochralski method •  Large ingot diameter possible •  High Oxygen (~1018 cm-3) and Carbon (~1015 cm-3) content •  Most widely used technique

•  Float-Zone method •  Smaller ingots •  Less issues with contamination •  High resistivity wafers

•  Detectors (dark current in photodiodes) •  Power semiconductor devices (breakdown strength)

•  Purification by concentration change by segregation during the liquid – solid transition



http://www.processpecialties.com/siliconp.htm http://www.memc.com/co-as-description-crystal-growth.asp

Czochralski Method

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Si Wafer Manufacture (6) Float-Zone Method

http://www.topsil.com/410

Si crystal Seed

RF coils

Molten Si

Poly-Si

•  EGS rods •  No crucibles •  Heating by Eddy currents •  Low contamination



Grinding the ingot Wafer slicing Edge profiling

Wafer lapping Al2O3 + water + glycerine

Removes bow & taper Flat wafer

Wafer polish NaOH + SiO2

CMP Mirror finish

Epitaxy High quality Si

on top for devices

Si etch HNO3 + HF + acetic acid Removes

mechanical damage

http://www.memc.com/co-as-process-animation.asp

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Si

Si3N4

SiO2


Si SiO2

Si3N4

Si

Si3N4

SiO2 SiO2


Si3N4


Si3N4

Si

SiO2

SiO2


Si SiO2

Si3N4


Si SiO2


26


Wafer Cleaning •  Part of contamination control during processing

•  Alkali ions like Na+ and K+ •  Mobile: Vt instabilities, lower breakdown fields,…. •  levels below 1010 cm-2 •  Unavoidable: Used in slurries used for wafer polish •  Unintentional: handling by humans

•  Other metallic contamination: Cu, Au, Ag,…. •  Carrier lifetime, breakdown fields,…. •  levels below 1010 cm-2 •  Unavoidable: Equipment, process materials, …. •  Unintentional: Handling

•  Organic contamination •  Breakdown fields, defects,…. •  Unavoidable: Photo resist •  Unintentional: handling

•  Clean the wafers before and between critical process


Wafer Cleaning (2)

Silicon VLSI Technology, J. D. Plummer, M. D. Deal, P. B. Griffin

0 50 100 150 2000

20

40

60

80

100

120

140

SPM APM No clean

Oxi

de th

ickn

ess

(nm

)

Oxidation time (min)

27


Wafer Cleaning (3) •  Front end of line

•  High temperature processes & hence higher risk of diffusion •  Metals not used intentionally

•  Backend of line •  Low process temperatures •  Metals (Ti, Ta, W, Cu, Al,….) used for interconnects

•  Different cleaning strategies •  FEOL

•  Wet cleaning using acids and alkalis •  Resist ashing using oxygen plasma

•  BEOL •  Resist ashing using oxygen plasma •  Phenol based organic strippers


Wafer Cleaning (4) •  RCA cleaning

!  H2SO4 + H2O2 1:1 to 4:1 at 120 – 150 C for 10 minutes •  Also called SPM (Sulphuric Peroxide Mixture) •  Strips organics especially photo resist

!  HF 2% at RT •  Strips chemical oxide

!  DI H2O rinse at RT !  NH4OH + H2O2 + DI H2O 1:1:5 at 80-90 C for 10 minutes

•  Also called APM (Ammonia Peroxide Mixture) or SC-1 •  Strips organics, metals and particles

!  DI H2O rinse at RT !  HCl + H2O2 + DI H2O 1:1:5 at 80-90C for 10 minutes

•  Also called SC-2 •  Strips alkali ions and metals

!  DI H2O rinse at RT

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Wafer Cleaning (5) •  RCA cleaning – latest trends

"  Every chemical is expensive and not so environment friendly "  Can be used only once "  Reduce the amount of chemical used – batch versus single wafer "  Alternative chemistries

"  A modified RCA clean replacing H2O2 by ozone introduced by IMEC

"  H2O2 is used in RCA clean for oxidizing the contaminants and the Silicon wafer surface "  A localized ozone generator is used instead and O3 is bubbled through the bath








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Si

Si3N4

SiO2


Si SiO2

Si3N4

Si

Si3N4

SiO2 SiO2


Si3N4


Si3N4

Si

SiO2

SiO2


Si SiO2

Si3N4


Si SiO2



Thermal oxidation Success of Si in electronic applications is attributed to the availability of SiO2, which:

•  Can be easily grown thermally on Si •  has an excellent interface with Si: the best in terms of electrical and mechanical properties. Low density of defects and stable with time. •  SiO2 blocks diffusion of most of the dopants and other impurities •  Si can be etched selective to the oxide •  SiO2 is resistant to most chemicals used in fabrication but can be easily etched using HF

30


Thermal oxidation (2)


Dry/wet

Wet




•  Temperature ~ 800C to 1100C •  dry oxide => oxygen •  wet oxide => bubbling O2 through H2O or H2 + O2

31



Deal-Grove model Silicon VLSI Technology, J. D. Plummer, M. D. Deal, P. B. Griffin

Reaction limited Diffusion limited

tABxx

Bxx ii =

−+

−

/0

220

Parabolic rate constant Linear rate constant



Deal-Grove model Silicon VLSI Technology, J. D. Plummer, M. D. Deal, P. B. Griffin

32




•  Dry versus wet oxidation •  Wet process is faster due to higher solubility of water and related species in SiO2 •  Wet oxidation is used for thick oxides and dry for thinner in which case, the thickness control is more critical

•  Orientation dependence •  growth rate (111) > (110) > (100) •  more surface density of atoms on the (111) plane than (100) •  reaction limited regime (thin oxide growth) is faster

•  2D and 3D structures •  Different orientations with different growth rates •  Stress due to volume expansion => modifies growth kinetics




33



Compiled from ITRS roadmap

Ultra thin oxides for ULSI gate applications on large wafers

2000 2005 2010 20150

15

30

45

60

75

oxid

e th

ickn

ess,

t OX

(nm

)

chan

nel l

engt

h, L

(nm

)

Year

0.3

0.6

0.9

1.2

1.5

Lo et al., IEEE Electron Dev. Lett., p. 209, 1997


Thermal oxidation (9) Ultra thin oxides for ULSI gate applications on large wafers (2)


Nitrided oxide for ULSI Rapid thermal process chamber

Applied Materials Inc.

34










Si

Si3N4

SiO2


Si SiO2

Si3N4

Si

Si3N4

SiO2 SiO2


Si3N4


Si3N4

Si

SiO2

SiO2


Si SiO2

Si3N4


Si SiO2


35


Thin film deposition •  Materials deposited

•  dielectrics: SiO2, Si3N4, high-k (metal oxides & silicates) •  semiconductors: crystalline Si or Ge (epitaxy), poly-Si, a-Si •  metals/metallic compounds: Ni, W, Ti, TiN, Ta, TaN, Al, Cu

•  Techniques •  atmospheric CVD •  low pressure CVD •  plasma enhanced CVD •  physical sputtering •  Atomic Layer Deposition (ALD)

•  Desirable properties •  Uniform composition •  Uniform thickness •  low level of contaminants incorporated in the film •  low defect density


Thin film deposition (2) •  Desirable properties (continued)

•  step coverage

•  void formation to be avoided

Ohshita et al., Thin Solid Films, 1 March 2002, pp. 215

36


Thin film deposition (3) Atmospheric Pressure Chemical vapor deposition (APCVD)



Thin film deposition (4)


NC

hkhkv

CkFCChF

G

GS

GS

SS

SGG

+=

=

−=

2)(1

Atmospheric Pressure Chemical vapor deposition (APCVD)

37




Large quantities of reactants available on surface than consumed by the reaction.

Transport through the boundary layer is slower than the reaction.




Wafers placed on susceptors in a furnace. Boundary layer width changes leading to changes in hG along the length of the tube. Special susceptor design required for mass transfer limited regime.

Batch process, cannot be done in mass transfer limit with thickness uniformity.

38


Thin film deposition (7) Atmospheric Pressure Chemical vapor deposition (APCVD) •  Mass transfer limited regime

•  High temperature process and hence better quality films and high deposition rates •  special reactor and susceptor designs •  batch process with good thickness uniformity is difficult and hence low throughput

•  Reaction limited •  low temperature of deposition and hence poorer quality films •  low deposition rate •  batch process possible and hence high throughput



Thin film deposition (8) Low Pressure Chemical vapor deposition (LPCVD)


39


Thin film deposition (9) Low Pressure Chemical vapor deposition (LPCVD) •  Reaction limited regime

•  High temperature process and hence better quality films and high deposition rates •  Batch process with good thickness uniformity is possible and hence high throughput •  Low pressure => low gas flow rates and hence safer

•  Almost all thermal CVD processes used in VLSI (c-S, poly-Si, a-Si, SiO2, Si3N4) are LPCVD processes •  SiGe and Ge deposition are done only using low pressure processes



Thin film deposition (10) Low Pressure Chemical vapor deposition (LPCVD)


40


Thin film deposition (11) Plasma Enhanced Chemical Vapor Deposition (PECVD) •  Sometimes it is desirable to do the depositions at low T

•  e.g.: Al melts at 660C, all depositions on Al below 450C •  But thermal CVD

•  becomes slow as the temperature is decreased •  poor film quality



Thin film deposition (12) Plasma Enhanced Chemical Vapor Deposition (PECVD)


41


Thin film deposition (13) Sputter Deposition



Thin film deposition (14) Sputter Deposition


42


Thin film deposition (15)

Au nanocrystals on SiO2, formed by metal sputtering + anneal Abhishek Misra, IIT Bombay


Thin film deposition (16) Sputter Deposition Variants •  Reactive sputtering

•  compounds like TiN can be deposited by passing nitrogen through the chamber during Ti sputtering

•  RF sputtering •  Used for dielectrics •  A dielectric target can get charged by Ar+ ions in DC sputtering, which reduces the net negative charge on the target and the plasma shuts off after a short time ~ micro seconds

Applications •  Inter metal and passivation dielectrics •  Metals like Ti, Co, Ni, Al, Cu, Ta, TaN and TiN


43

Overview of VLSI Manufacturing Technology, BARC, 6th December 2012 Anil Kottantharayil, IIT-B

ALD cycle: Al2O3 example

Courtesy: Dr. Mrinalini, CEN, IIT-B

85

Overview of VLSI Manufacturing Technology, BARC, 6th December 2012 Anil Kottantharayil, IIT-B

ALD System: Schematic

Angus Rockett, “Material Science of Semiconductors”, Springer Verlag, 2008

86

44




•  CVD processes •  Physical vapor deposition (PVD) •  ALD






Si

Si3N4

SiO2


Si SiO2

Si3N4

Si

Si3N4

SiO2 SiO2


Si3N4


Si3N4

Si

SiO2

SiO2


Si SiO2

Si3N4


Si SiO2


45


Photolithography

Ability to selectively process parts of a wafer is key to making devices and circuits on Silicon, which is enabled by lithography •  Selective etch •  Selective implants



Photolithography (2)

VLSI Technology, Edited by S. M. Sze, 1983

46



Important specifications: •  Resolution: the smallest feature that can be printed •  Overlay: the alignment accuracy of a layer to the previous layer •  Throughput: wafers that can be processed per hour •  Defect density: Defects generated on the wafer per unit area by the lithographic process





Critical dimension The smallest that can be printed.

overlay Layer 1

Layer 2

Major components of design rules.

47




- Defects + Low cost + No diffraction effects

- Defects - Diffraction effects - higher cost

+ No defects - Diffraction effects - highest cost



αλ

sin6.0

nR =


2)sin(5.0αλ

nDOF =

48



αλ

sin6.0

nR = 2)sin(

5.0αλ

nDOF =


•  i-line 365nm Hg arc lamp •  248nm KrF Laser •  193nm ArF Laser •  193nm/immersion ArF Laser water (n=1.33)

•  E-beam lithography

Ehc

=λ



Raith 150 EBL system at IIT-Bombay CD = 25nm

49




Positive resist Negative resist








50



Si

Si3N4

SiO2


Si SiO2

Si3N4

Si

Si3N4

SiO2 SiO2


Si3N4


Si3N4

Si

SiO2

SiO2


Si SiO2

Si3N4


Si SiO2



Etch Processes Wafer immersed in etchant

Etchant is in solution Etchant is in plasma

Reaction by products are soluble Etching by chemical

reaction Usually isotropic High selectivity

Etching by sputtering

Reaction by products are volatile

Isotropic Highly selective

Anisotropic Poor selectivity

Anisotropic Good selectivity

Wet etch Dry etch

51


Etch Processes (2)



Etch Processes (3): Wet etch Etch rate and selectivity: •  Concentration •  Temperature •  Stirring of solution Some of the common wet etch processes used in VLSI •  HF for etching SiO2 selective to Si •  BHF (HF: NH4F = 1:5) for etching SiO2 selective to photo resist and Si

SiO2 + 6HF H2SiF6 + 2H2O •  Boiling H3PO4 for etching Si3N4 selective to SiO2 and Si

Williams et al., IEEE Journal of MEMS, Dec. 1996 & Dec. 2003

52


Etch Processes (4): Dry Etch



Etch Processes (5): Dry Etch


53


Etch Processes (6): Dry etch Classification •  Chemical etch:

•  caused by chemical reaction of the free radicals like F, CF3, … with materials on the wafer surface •  isotropic, highly selective

•  Physical etch: •  caused by bombardment of high energy ions on the wafer surface •  anisotropic, not selective

•  Ion enhanced etch: •  ions and free radicals acting together •  anisotropic and selective


Etch Processes (7): Dry etch


Chemical etching process

54




Chemical etch Physical etch




Ion enhanced etch

55


Etch Processes (10): Dry etch Typical chemistries for Si etch •  CF4

•  isotropic or near isotropic •  no selectivity to SiO2

•  HBr/Cl2/O2 •  anisotropic •  high selectivity to SiO2 (>1000)








56



Si

Si3N4

SiO2


Si SiO2

Si3N4

Si

Si3N4

SiO2 SiO2


Si3N4


Si3N4

Si

SiO2

SiO2


Si SiO2

Si3N4


Si SiO2



Chemical Mechanical Polish •  Global planarization (wafer level) •  Local planarity better than depth of focus

Si

LOCOS

57


Chemical Mechanical Polish (2)

Ceramic Engineering, Hanyang University, Korea.


Chemical Mechanical Polish (3)

•  Slurry contains chemicals which would convert the layer to be etched into a softer material. e. g.: NaOH for Si polishing •  This material is then removed by the abrasives present in the slurry •  Chemical part provides the selectivity

Ceramic Engineering, Hanyang University, Korea.

58









The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have n

well & channel doping module

Photo nwell N-type implants Strip resist


to open the image, or the image may have n

p

Photo pwell P-type implants Strip resist Oxidation / Anneal

(optional)

59


Ion Implantation

What distinguishes semiconductors from metals and insulators?

•  Resistivity can be changed over many orders of magnitude •  Type of current carriers can be chosen to be electrons or holes

Both these are achieved by a process called doping. Means of doping: •  Diffusion •  Ion implantation


Ion Implantation (2)

)(2

BvqRmv

×=Silicon VLSI Technology, J. D. Plummer, M. D. Deal, P. B. Griffin

60


Ion Implantation (3) Ion implantation: •  Allows good control of the doping profile

•  Example: a retrograde profile is possible with ion implant •  Precise control of total dopants incorporated •  Efficient masking of implants possible using photoresist •  Important parameters

•  species •  energy •  dose •  range •  straggle •  lateral straggle

2011 Monsoon EE669: Ion Implantation: Anil Kottantharayil 120

Visualization of ion implantation

SRIM simulations B, 100 keV www.srim.org

61

2011 Monsoon EE669: Ion Implantation: Anil Kottantharayil 121

Ion implantation profiles

•  The traces of 99999 ions of Boron implanted into Si at 100 keV

SRIM simulations B, 100 keV, 99999 ions



Target: Si, energy = 100 keV Monte Carlo simulations using SRIM

Implantation of 9999 Boron ions

62



STM image of Si atoms on (111) plane http://materials.usask.ca/photos/

Channeling

Channeling of implanted ions

Channeling


Ion Implantation (7) Implant activation and diffusion •  The dopants should be in lattice sites for them to modify the conductivity

•  As implanted they may not be in lattice sites •  Implantation can damage the host crystal

•  Example: Medium to high doses of Arsenic can cause amorphization of crystalline Si

•  Dopants are activated and damages are repaired by thermal anneal

•  Typical anneal process: Rapid thermal anneal at 1050C for 1sec •  Diffusion is an inevitable part of the anneal process, but is avoided as much as possible in state of the art technologies

63











64



Resources Resources References Thompson et al., Intel technology journal, vol. 6, no. 2, 2002 Agnello, IBM Journal of research and development, no. 2/3 2002 http://www.processpecialties.com/siliconp.htm http://www.memc.com/co-as-description-crystal-growth.asp http://www.topsil.com/410 http://www.memc.com/co-as-process-animation.asp http://www.itrs.net Lo et al., IEEE Electron Dev. Lett., p. 209, 1997 Ceramic Engineering, Hanyang University, Korea. http://materials.usask.ca/photos/ Williams et al., IEEE Journal of MEMS, Dec. 1996 & Dec. 2003

65


Resources (2) Resources Books J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI technology : fundamentals, practice and modeling , Prentice-Hall, 2000 S. M. Sze, Very Large Scale Integration Technology , Mc.Grawhill, 1998


Resources (3) Resources Simulation software Srim for Monte Carlo simulation of ion implantation www.srim.org Device modeling PISCES and process modeling: http://www-tcad.stanford.edu/tcad/programs/oldftpable.html

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