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Overview of the Xilinx ISE (Integrated Software Environment) ver. 10.1 1. Xilinx ISE GUI:

The GUI (Graphical User Interface) is called Project Navigator and it can be invoked by:

1. Double clicking the Xilinx ISE 10.1 shortcut icon on your desktop 2. Clicking on All Programs Xilinx ISE Tool Suite 10.1 ISE Project Navigator 3. Running the command ise through a terminal window. To invoke ise successfully through a

command window you have to make sure that your path environmental variable contains the location where the ise program is installed or invokes the command using its complete path. On Windows XP Xilinx’s default path for ise is: c/Xilinx/10.1/ISE/bin/nt

Figure 1. The Terminal Window

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Figure 2. Xilinx’s default installation of ise on Windows XP 2. ISE Window Structure:

The ISE is divided in 4 main windows:

1. Sources Window 2. Processes Window 3. Transcript (Log) Window 4. Workplace Window

Figure 3 Typical ISE Window

Workspace Window

Sources Window

Processes Window

Transcripts Window

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Designing an FPGA based digital system: A simple four step development methodology

1. Create the Logic Design a. Create a project

• workspace selection • device selection • tools selection (XST/Synopsys, VHDL/Verilog, etc.)

b. Create or add HDL files c. Check HDL syntax

2. Create a Testbench and Perform RTL Simulation 3. Synthesis and Implementation

a. Add a constraint file (.ucf file) b. Synthesis and Implementation c. Check the design Summary (Synthesis and Implementation Reports)

4. Generate and Download the “configuration” file into the FPGA Device a. Generate the configuration file (a.k.a. bit file) b. Connect the download cable c. Download the configuration file

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Summary of the “Development” Methodology

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Xilinx ISE ver. 10.1 QuickStart Tutorial (and useful tricks) 1. Introduction The goal of this document is to bring you up to speed in using the Xilinx ISE Software and the Spartan 3E Starter Kit board as painlessly as possible. For a more complete and detailed description of the Xilinx software and the Spartan 3E starter kit board you can read the extensive documentation provided by Xilinx. The most relevant documentation is also posted on the class website. 2. A word of caution The Starter Kit boards are quite robust but not indestructible. Handle them with care:

1. Before laying the board on your desk makes sure there are no conductive objects underneath. 2. Unless differently advised please make sure the configuration jumpers are set as shown in figure 4

(you should have eight caps for the jumpers on the board).

Figure 4 – Spartan 3E Starter-Kit Board

3. If you plan to plug-in or plug-off any of the cables make sure to first switch the power off. There

is a power switch on the board: use it. Do not pull off or plug-in the power cord with the power switch on. Anytime the power supply is turned on (or off) the voltage across its terminals looks like a rising (or falling) voltage step.

Power Switch

J11

J30

JP9

JP6

JP7

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Since the load provided by the board is essentially capacitive, applying a voltage step to the board causes (at least theoretically) a Dirac’s pulse of current (i.e. an infinite current) through the board’s capacitance. This is not a very “gentle” experience for the board. The role of the power-on switch is to smooth the peak current flowing into the board by modifying the original circuit with the addition of a resistor along the path from the power supply to the board’s capacitive load.

Figure 5. Surge currents at power on and power off

4. When the power is on, there is no need for you to touch any part of the board besides the various switches and buttons.

5. Get familiar with the content of the Starter Kit board User Guide 3. ISE Tutorial During this tutorial we will:

1. invoke Xilinx’s project navigator 2. create a new project 3. design a very simple digital system using VHDL 4. add the design to the project 5. check the VHDL syntax of the project 6. create a VHDL test bench 7. add the VHDL test bench the project 8. check the VHDL syntax of the test bench and simulate the behavior of the VHDL design 9. synthesize the VHDL design into a logic circuit 10. analyze the synthesis report 11. create a constraint file 12. add the constraint file to the project and implement the logic circuit into the FPGA 13. analyze the implementation reports 14. generate a configuration file 15. connect the download cable and download the configuration file into the FPGA

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3.1 Invoke Xilinx’s Project Navigator (and change the ISE General Preferences) To invoke the Xilinx’s Project Navigator double click on the Xilinx ISE 10.1 icon on your desktop or click on Start All Programs Xilinx ISE Design Suite 10.1 ISE Design Navigator

Figure 6. Xilinx ISE desktop icon

The project navigator window will open:

Figure 7. Project Navigator window To change the ISE General Preferences first click on Edit Preferences, then click on the ISE General tab and modify the preferences as shown in Figure 8. Finally click on Apply and then Close.

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Figure 8. ISE General Preferences 3.2 Create a Project Click of File New Project… First enter the directory where you want to place all project’s files into the “Project location” field:

Figure 9. Project location

or better: C:\tutorial\VHDL\simple

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Second enter the logical name you want to assign the project (notice that as a result also the Project location field will be automatically modified) and then click on Next.

Figure 10. Project name Third, fill all fields on the Device Properties dialog as shown in Figure 11 and then click on Next:

Figure 11. Device Properties dialog

or better: C:\tutorial\VHDL\simple\simple

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Forth, click Next on the Create New Source dialog (or you can click on New Source and use the wizard to help you create a number of different types of source files; but I like better to create my source files with a text editor such as vi, emacs or textedit). It is always possible to create new source files later in the development.

Figure 12. Create New Source dialog Forth, click Next on the Add New Source dialog (or if you have already created your source files click on Add Source and use the wizard to help you browse and select the source files you have). It is always possible to add source files later in the development.

Figure 13. Add New Source dialog

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Last, click Finish on the Project Summary dialog:

Figure 14. Project Summary dialog At this point the Navigator analyzes all source files created/added and tries to figure out what kind of purpose they serve (Implementation, Behavioral Simulation, Post-Route Simulation, All). In our case we did not create/add any file so no file (Design Unit) or file association (Association) will show in the dialog. Just click OK.

Figure 15. Adding Source Files dialog

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The Project navigator window will now looks as follows:

Figure 16. Project Navigator window 3.3 Design a very simple digital system using VHDL The digital system we will design performs the function illustrated in figure 17.

Figure 17. Simple digital system

Using your favorite text editor code the design of Figure 17 in VHDL. Call the VHDL file you just created slogic.vhdl and place it in the directory: C:\Claudio\EWU\Courses\ee360\VHDL\simple\ or better in:

C:\tutorial\VHDL\simple

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If you do not feel comfortable coding in VHDL download slogic.vhdl from the class web page and place it in the directory suggested above. -- -- slogic.vhdl -- simple logic design -- by C. Talarico -- library ieee; use ieee.std_logic_1164.all; entity simple_logic is port ( a : in std_logic; b : in std_logic; clk : in std_logic; rst : in std_logic; andreg : out std_logic; orreg : out std_logic; xorreg : out std_logic ); end simple_logic; architecture rtl of simple_logic is signal andreg_d : std_logic; signal orreg_d : std_logic; signal xorreg_d : std_logic; begin combinational: process (a,b) begin andreg_d <= a and b; orreg_d <= a or b; xorreg_d <= a xor b; end process combinational; sequential: process(rst, clk) begin if (rst = '1') then andreg <= '0'; orreg <= '0'; xorreg <= '0'; elsif (clk='1' and clk'event) then andreg <= andreg_d; orreg <= orreg_d; xorreg <= xorreg_d; end if; end process sequential; end rtl;

Figure 18. slogic,vhdl file 3.4 Add the design to the project To add the source file slogic.vhdl to the project go through the following steps First, select “simple” in the source window.

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Figure 19. Select the project simple in the Source Window Second right click on simple and then click on Add Source…:

Figure 20. Add Source … Third, browse the Add Existing Source dialog until you find slogic.vhdl. Once you find slogic.vhdl select it and click on open (Figure 21). At this point the Navigator analyzes the source file added and it figures out that the design unit corresponding to the source file can be used for implementation purposes (Figure 22). If by any chance the Navigator doesn’t provide the correct association for the design unit added you can change the association manually. If the association is correct (as usually is) just click OK. Finally, at this point the file is successfully added to the project. The navigator window will look like Figure 23. Now the source window shows slogic.vhdl as being part of the project and the process windows shows many more tasks than it used to.

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Figure 21. Add the source file slogic.vhdl to the project.

Figure 22. Adding Source Files dialog

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Figure 23. Project Navigator window after successfully adding the source file slogic.vhdl 3.5 Check the VHDL syntax of the design In order to check the VHDL syntax of the design: first make sure to select the simple_logic-rtl unit in the Source Window, and second expand the Synthesize - XST “task“ in the Process Window and double click check syntax.

Figure 24. Sources window and Processes window

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Figure 25. Successful syntax check

If the syntax if correct a green check will show up besides the check Syntax task” in the processes windows, and a “completed successfully” message will appear in the console tab of the transcripts window (see Figure 25). If you feel you deserve to celebrate your success and would like to take a break, in order to close the Navigator just click on: File Exit. 3.6 Create a VHDL test bench To re-open the project just invoke Xilinx Project Navigator, click on File Open Project, and double click on the simple.ise icon as shown in Figure 26.

Figure 26. Open an existing Project (simple.ise)

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At this point open a text editor of your choice and write the VHDL testbench. The VHDL testbench file is shown in Figure 27, and can be downloaded from the course web site. -- -- tb-slogic.vhdl -- testbench for slogic.vhdl -- by Claudio Talarico -- library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity tb_slogic is --empty end tb_slogic; architecture beh of tb_slogic is component simple_logic port( a : in std_logic; b : in std_logic; clk : in std_logic; rst : in std_logic; andreg : out std_logic; orreg : out std_logic; xorreg : out std_logic ); end component simple_logic; --constant declaration constant period_c : time := 20 ns; constant tb_skew_c : time := 1 ns; constant severity_c : severity_level := failure; --signal declaration signal clk : std_logic; signal rst : std_logic; signal a : std_logic; signal b : std_logic; signal andreg : std_logic; signal orreg : std_logic; signal xorreg : std_logic; signal tb_clk : std_logic; begin inst_uut: simple_logic port map( a => a, b => b, clk => clk, rst => rst, andreg => andreg, orreg => orreg, xorreg => xorreg );

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-- testbench clock generator tb_clk_gen : process begin tb_clk <= '0'; wait for period_c/2; tb_clk <= '1'; wait for period_c/2; end process; -- system clock generator clock_gen : process (tb_clk) begin clk <= transport tb_clk after tb_skew_c; end process; test_bench : process -- -- this procedure writes out the current time and a string. -- (the current time modulo 10) -- procedure write_message(s : string; delay : time := 0 ns) is variable l :line; variable cycle: integer; begin write(l, string'(" ")); write(l, (now - delay)); write(l, string'(" ")); write(l, s); writeline(output, l); end write_message; -- -- wait for the rising edge of tb_ck -- procedure wait_tb_clk(num_cyc : integer := 1) is begin for i in 1 to num_cyc loop wait until tb_clk'event and tb_clk = '1'; end loop; end wait_tb_clk; -- -- wait for the rising edge of clk -- procedure wait_clk(num_cyc : integer := 1) is begin for i in 1 to num_cyc loop wait until clk'event and clk = '1'; end loop; end wait_clk;

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begin write_message("Start of simulation"); a <= '0'; b <= '0'; rst <= '1'; wait for 1 ns; rst <= '0'; -- Let's waste some time wait_tb_clk(10); write_message("Start Testing all possible Input Patterns"); a <= '0'; b <= '0'; wait_tb_clk(2); a <= '0'; b <= '1'; wait_tb_clk(2); a <= '1'; b <= '0'; wait_tb_clk(2); a <= '1'; b <= '1'; wait_tb_clk(2); write_message("Done Testing all possible Input Patterns"); a <= '0'; b <= '0'; -- Let's waste some time wait_tb_clk(10); assert false report "End of Simulation" severity severity_c; end process test_bench; end beh;

Figure 27. VHDL Testbench file: tb-slogic.vhd 3.7 Add the VHDL test bench the project Go to the “Sources window” make sure xc3s500e-5fg320 is selected (i.e. make sure it is gray), right click on it and select Add Source (Figure 28). In the Add Existing Source dialog select the file tb-slogic.vhdl and click on Open (Figure 29). At this point the navigator will analyze the project and associate the VHDL testbench to the simulator. If the association is correct (as usually is) just click OK (Figure 30). Finally, at this point the testbench is successfully added to the project and the source and process windows will look as shown in Figure 31.

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Figure 28. Add a the Testbench Source File to the project

Figure 29. Select the name of the testbench source file

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Figure 30. Association of the test bench file to the Simulator

Figure 31. Sources and Processes windows after successfully adding the source file tb-slogic.vhdl

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3.8 Check the VHDL syntax of the test bench and simulate the behavior of the VHDL design In order to check the VHDL syntax go through the following three steps. First, make sure the “Source for:” field of the Sources window says Behavioral Simulation. Second select the testbench unit in the Sources window (i.e. make sure tb_slogic – beh is gray). Finally, double click on Behavioral Check Syntax in Processes window.

Fig 32. Double check the VHDL syntax of the testbench file. If the syntax if correct a green check will show up besides the check Syntax task” in the processes windows, and a “completed successfully” message will appear in the console tab of the transcripts window (see Figure 33).

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Figure 33. Successful syntax Check At this point to run the simulation all we have to do is to double click on Simulate Behavioral Model in the processes window (Figure 34) and the simulation waveforms will automatically pop up in the Workspace window of the navigator (Figure 35)

Figure 34. Invoking the Simulator

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Figure 35. Simulation waveforms If you’d like to look at the waveforms without having them docked in the Workspace window you can right click on the Simulation Tab and click on Float.

Figure 36. Taking the simulation waveforms off the Workspace window

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Figure 37. Simulation Waveforms

If you do not like the order in which the waveforms are displayed you can move a waveform by simply left clicking on it and then dragging it to your favorite spot. If you feel some of the waveforms are of no interest to you can remove them. To remove a waveform you have to first select it by left clicking on it, then right click on it and select delete. If for any reason your want to monitor more waveforms besides the ones displayed by default you can do so as follows (Figure 38). First browse the hierarchy of your design through the Sim Instance Tab of the Sources Window and select design unit select you’d like to monitor more closely. Second, select All in the Type field of the Sim Objects Tab of the Processes Window and finally drag the waveform you’d like to add from the Processes Window to the Simulation waveforms Window (alternatively you can left click on the name of the object you want to add, and then right click on it and select add to Waveform). Once you are done with adding waveforms (Figure 39) before you can really see them you need to re-run the simulation. To rerun the simulation go to the Simulation waveforms window and first select Simulation

Restart and then Simulation Run All (Figure 40).

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Figure 38. Browsing the design hierarchy to monitor additional object

Figure 39. Added additional simulation object to the Simulation waveforms window

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Figure 40. Re-run the simulation

Figure 41. Successful simulation re-run

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NOTE: occasionally it happens that the simulation window doesn’t get refreshed as it should. If this is the case the easiest way to solve the problem is first to go to the Sources window and make sure the design unit selected is the top level of the hierarchy, and then go to the Processes window and double click on Simulate Behavioral Model.

NOTE: occasionally under Window XP, when re-running a simulation the new simulation process starts

its execution before the old simulation process has been completely killed. In this case the following error message (Figure 42) will be issued in the transcript windows: ERROR: Simulator - Failed to link the design. Check to see if any previous simulation executables are still running. In order to solve the problem invoke Windows XP Task manager and kill the process (Figure 43).

Figure 42. Transcript window

Figure 43 Killing the simulation process

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3.9 Synthesize the VHDL design into a logic circuit First, make sure the “Source for:” field of the Sources window says Implementation, and that the design unit is selected (i.e. simple_logic-rtl must be gray). Second, go to the processes window and double click on Synthesize – XST.

Figure 44. Synthesize the design slogic.vhdl If the synthesis process completes successfully a green check will appear next to the Synthesize-XST task, and success message will appear in the transcript window (Figure 45).

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Figure 45. Successful Synthesis 3.10 Analyze the synthesis report Before moving on with the physical implementation of the design you have to make sure to analyze thoroughly the results of the synthesis process. To access the synthesis report make sure to expand the Synthesize – XST task in the Processes window and double click on View Synthesis Report (Figure 46).

Figure 46. Analyzing the Synthesis Report The synthesis report will open in the Workspace window. The more interesting sections of the report are: Section 4 (HDL Analysis), Section 5 (HDL Synthesis) and Section 9.3 (Timing Report). Here are few golden rules that you should follow:

1. Make sure the HDL Analysis report does not contains any Warnings about incomplete sensitivity lists

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2. Make sure the HDL Synthesis report does not list the use of any undesired Latch 3. Make sure the Timing Report does list any timing violation

In general the synthesis report should not contain any error, warning or info. Do not overlook warning and info. Make sure you fully understand the meaning of any warning and info and whenever possible (which is most of the times) eliminate them. Ideally the last three lines of the synthesis report should look as follows: Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) In addition to analyzing the synthesis report it is possible to gain further inside by looking at the RTL logic schematic generated. To access the RTL schematic double click on the “View RTL Schematic” task in the processes window. The RTL schematic opens in the workspace window (Figure 47). To push down one into a schematic’s instance just double click on it (figure 48)

Figure 47. RTL schematic (top level)

Figure 48. RTL schematic (one level down into the hierarchy)

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Right clicking on the schematic window and selecting “Pop to the Calling Schematic” allows go back one level in the hierarchy 3.11 Create a constraint file To implement the synthesized logic into the FPGA we need to provide a number of physical constraints. The physical constraints the user is able to provide include timing specifications, area specifications, and the location of the FPGA input/output pins. A comprehensive discussion of user constraints is beyond the scope of this tutorial. Please refer to the Xilinx documentation for more information For the simple digital system we designed the only constraints we need to worry are the once concerning the I/O location of the FPGA pins. The system inputs A and B will be provided through the board slide switches SW3 and SW2. The slide switches SW3 and SW2 are connected to the FPGA through the pins N17 and H18 (see page 15 of Starter Kit Board User Guide)

The system outputs ANDREG, ORREG, and XORREG will be “passed” to the board LED7, LED6, and LED5. LED7, LED6, and LED5 are connected to the FPGA through the pins F9, E9 and D11 (see page 19 of Starter Kit Board User Guide)

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The system input CLK will be provided through the on board 50 MHz Oscillator and is connected to the pin C9 of the FPGA (see page 21 of Starter Kit Board User Guide).

The system input RST will be provided through the EAST push button BTN_EAST and is connected to the pin H13 of the FPGA (see page 16 of Starter Kit Board User Guide).

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At this point all it remains to do is to edit the user constraint file according to the information provided in the Starter Kit board User Guide. Create the file slogic.ucf (Figure 49) using your favorite text editor and place it in the directory: C:\Claudio\EWU\Courses\ee360\VHDL\simple\ #I/O Pin Assignments NET "CLK" LOC = "C9" | IOSTANDARD = LVCMOS33 ; NET "RST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; NET "A" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; NET "B" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; NET "ANDREG" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "ORREG" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "XORREG" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; #Area Constraints #Timing Constraints

Figure 49. slogic.ucf The file slogic.ucf can be download from the course webpage. 3.12 Add the constraint file to the project and implement the logic circuit into the FPGA By now you should probably know how to add a source file to the project. If you don’t remember see Figures 50 to 53.

Figure 50. Add the user constraints file to the project

or better: C:\tutorial\VHDL\simple\

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Figure 51. Browse the project directory structure and select the user constraints file slogic.ucf

Figure 52. Associate the user constraints file to the implementation process

Figure 53. Sources window after the ucf has been added to the project

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Finally, to implement the design’s logic circuit double click on the Implement Design task in the Processes window.

Figure 54. Implement the Design As usual if everything goes right a green check will appear close to the task you just run and a success message will appear in the Transcripts window.

Figure 55. Navigator after the successful implementation of the design

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3.13 Analyze the implementation reports To analyze the various implementation reports 1) go to the Processes window, 2) expand the Implementation Design task and all its sub-tasks and 3) double click on the associated reports.

Figure 56. Implementation reports

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3.14 Generate the configuration file To generate the configuration file (a.k.a. programming file or bit file) go to the Processes window and double click on the Generate Programming File process. As usual if the process runs successfully a green check mark will appear next to the process name.

Figure 57. Generate the programming file (a.k.a. bit file)

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3.15 Connect the download cable and download the configuration file into the FPGA It is now time to power on the Starter kit board and to connect it to the computer through the USB cable provided. The first time you connect the board and the computer through the USB cable you will need to install a couple of software drivers. To install the drivers just follow the wizard and reply YES or OK to any question prompted.

Figure 57. Spartan 3E starter kit Board

ON

OFF

Power Switch

USB’s LED

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When the USB cable driver is successfully installed and the board is correctly connected to the computer, a green LED lights up, indicating a good connection. Finally, once a good connection between the board and the computer is established we can configure the target device (i.e. download the bit file into the FPGA). To configure the target device go to the processes window and double click on the Configure Target Device process.

Figure 58. Configure Target Device

Click OK on the Project Navigator dialog (Figure 59) to use the iMPACT software for downloading the bit file into the device (i.e. the FPGA). Click Finish on the iMPACT dialog (Figure 60) to program the device using the boundary scan chain.

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Figure 59. Project Navigator dialog

Figure 60. Program the device through the Boundary Scan Chain. Download the bit file (simple_logic,bit) into the xc3s500e device (Figure 61), and by-pass the xcf04s and xc2c64a devices (Figure 62 and 63). As shown in Figure 64, use the default values provided as device programming properties (click on apply and then OK on the Device Programming Properties dialog).

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Figure 61. Download simple_logic.bit into the xc3s500e device.

Figure 62. By-pass the device the xcf04s

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Figure 63. By-pass the device xc2c64a

Figure 64 Default device programming properties

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Now, go to the workspace window, right click on the xcs500e device, and choose Program (Figure 65).

Figure 65. Program the target device

Finally we are done !!! The design has been successfully implemented and downloaded into the FPGA (Figure 66)

Figure 66. The FPGA has been successfully programmed

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This document has been developed using MS word and MWSnap screen capture utility. The utility can be downloaded for free at http://www.mirekw.com/winfreeware/mwsnap.html.

overview of the xilinx ise (integrated software ... · overview of the xilinx ise (integrated...

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